Power supply control circuit

Abstract

The invention discloses a power supply control circuit which comprises a first control circuit, a second control circuit, an intermediate circuit, a first detection module, a clamping module and a second detection module. The first control circuit is connected with a first power supply voltage and a first reference voltage to form a first node. The first transistor and the second transistor in the second control circuit are connected to form a second node. The intermediate circuit is connected with the first node and the second node. The first detection module is used for generating a detection signal based on the second reference voltage and the first reference voltage. The clamping module is used for clamping the voltage of the second node based on the detection signal. The second detection module is used for adjusting the detection signal based on the change of the second power supply voltage to turn off the clamping module. According to the power supply control circuit, the voltage on the second node can be clamped, the conduction problem of a parasitic triode is avoided, and backward current between power supplies is eliminated. And the clamping module is turned off when the low-voltage domain power supply is normally powered on, so that the normal work of the circuit is ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a power supply control circuit. Background Art

[0002] In some AFE chips for industrial applications, there is often a need to input low-voltage signals for communication or detect low-voltage signals, and control the output to generate high positive voltage or high negative voltage signals to drive loads. At this time, the chip requires several different power supplies to supply power to the low-voltage part and the high-voltage part of the chip respectively. In a board-level system, these power supplies are often generated by other power supply chips (such as LDO, DC-DC, etc.). Due to the different power-on speeds of different power supplies and the different start-up timings of different systems, it is difficult to ensure that the chip is powered on in a certain fixed power-on sequence in actual applications.

[0003] Due to the functional requirements of controlling the high-voltage domain circuit or detecting high-voltage nodes through the low-voltage domain circuit, there must be a circuit bridging between the low-voltage domain and the high-voltage domain. This part of the circuit is very prone to overvoltage problems in the scenario where only the high-voltage power supply is powered on while the low-voltage power supply is not yet powered on, which may cause damage to low-voltage devices.

[0004] As Figure 1 shown, in a design scenario, VCC is the positive power supply voltage of the high-voltage domain, VSS is the negative power supply voltage of the high-voltage domain, VDD is the positive power supply voltage of the low-voltage domain, and GND is the ground voltage of the low-voltage domain. MOS transistor PM1 and MOS transistor NM1 are low-voltage devices, working within the low-voltage domain GND~VDD. MOS transistor PM2 and MOS transistor NM2 are high-voltage devices, working within the high-voltage domain VSS~VCC. Q1 is a parasitic triode between node Y, GND, and VDD. The drains of MOS transistor PM1 and MOS transistor NM1 are connected to the drains of MOS transistor PM2 and MOS transistor NM2 through a voltage-dividing circuit.

[0005] After normal power-on is completed, node X is a high-voltage node. After being driven by the voltage-dividing circuit and MOS transistor PM1 and MOS transistor NM1, the voltage at node Y changes to the low-voltage domain, and MOS transistor PM1 and MOS transistor NM1 will not be overvoltage. The parasitic diodes and parasitic triode Q1 on MOS transistor PM1 and MOS transistor NM1 are all in the reverse bias state.

[0006] When the power supply VCC~VSS of the high-voltage domain is powered on, but the power supply VDD~GND of the low-voltage domain is not yet powered on, the driving circuit of the low-voltage domain for driving MOS transistor PM1 and MOS transistor NM1 cannot work properly, and there is no current on the voltage-dividing circuit from node X to node Y. If node X is in the negative high-voltage domain, node Y may also be in the negative high-voltage domain, resulting in overvoltage of the low-voltage devices connected to this node.

[0007] The conventional method is to add a clamping diode D1 to the ground voltage GND at node Y or directly utilize the forward conduction of the body diode of MOS transistor NM1 to provide a current from GND to VSS to the voltage division resistor network, thereby clamping node Y at about -0.7V to avoid the overvoltage risk of the subsequent circuit. However, at this time, the VBE of parasitic transistor Q1 is 0.7V and the BE junction is forward-conducted. Therefore, in addition to the current path between GND and VSS, there will also be a current path of VDD - Y - VSS. At this time, the positive power supply voltage VDD in the low voltage domain has not been powered on and has no current-carrying capacity, so it will be pulled to an intermediate potential, which is jointly determined by the internal parasitic path of the chip and the external power supply output impedance, and sometimes exceeds the normal operating range of this power supply voltage, which may pose a reliability risk. This phenomenon is not desired at the application side.

[0008] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of implication that this information constitutes the prior art already known to those of ordinary skill in the art. Summary of the Invention

[0009] An object of the present invention is to provide a power supply control circuit, which can solve the problems of overvoltage and current backflow in the circuit when the high-voltage power supply is powered on but the low-voltage power supply is not powered on.

[0010] To achieve the above object, the technical solution provided by a specific embodiment of the present invention is as follows:

[0011] The power supply control circuit includes: a first control circuit connected to a first power supply voltage and a first reference voltage, the first control circuit having a first node, and the first power supply voltage and the first reference voltage are in a high voltage domain; a second control circuit including a first transistor and a second transistor, a first end of the first transistor is connected to a second power supply voltage, a second end of the first transistor is connected to a second end of the second transistor to form a second node, a first end of the second transistor is connected to a second reference voltage, and the second power supply voltage and the second reference voltage are in a low voltage domain; an intermediate circuit connected to the first node and the second node; a first detection module connected to the first reference voltage and the second reference voltage for generating a detection signal based on the second reference voltage and the first reference voltage; a clamping module connected to the first detection module to form a third node for receiving the detection signal, and the clamping module is connected to the second node to clamp the voltage of the second node based on the control of the detection signal; a second detection module connected to the third node and the second power supply voltage for adjusting the signal on the third node based on the change of the second power supply voltage.

[0012] In one or more embodiments of the present invention, the first detection module includes a first voltage dividing unit connected to a first reference voltage and a second reference voltage. The first voltage dividing unit is configured to divide the voltage difference between the first reference voltage and the second reference voltage to generate a detection signal. Alternatively, the first detection module includes a resistance unit and a self-biased current source. The self-biased current source is connected to the first reference voltage and the second reference voltage to generate a first current based on the first reference voltage and the second reference voltage. The resistance unit is connected to the self-biased current source to generate a detection signal based on the first current.

[0013] In one or more embodiments of the present invention, the clamping module includes a third transistor. A first end of the third transistor is connected to the second reference voltage. A second end of the third transistor is connected to the second node. A control end of the third transistor is connected to the first detection module to form a third node for receiving the detection signal.

[0014] In one or more embodiments of the present invention, the second detection module includes a fourth transistor. A first end of the fourth transistor is connected to a second power supply voltage. A second end of the fourth transistor is connected to the third node. A control end of the fourth transistor is connected to the second reference voltage or a characterization signal indicating the power-on of the second power supply voltage. Alternatively, the second detection module includes a fourth transistor and a first resistor. A first end of the fourth transistor is connected to the second power supply voltage. A second end of the fourth transistor is connected to the third node. A control end of the fourth transistor is connected to a first end of the first resistor. A second end of the first resistor is connected to the second reference voltage.

[0015] In one or more embodiments of the present invention, the intermediate circuit includes a second voltage dividing unit and a switching unit. A first end of the second voltage dividing unit is connected to the first node. A second end of the second voltage dividing unit is connected to the switching unit. A voltage dividing end of the second voltage dividing unit is connected to the second node. The switching unit is connected to the second power supply voltage and the second reference voltage. The switching unit is configured to control the connection and disconnection between the second end of the second voltage dividing unit and the second power supply voltage and the second reference voltage.

[0016] In one or more embodiments of the present invention, the switching unit includes a fifth transistor and a sixth transistor. A first end of the fifth transistor is connected to the second power supply voltage. A second end of the fifth transistor and a second end of the sixth transistor are connected to the second end of the second voltage dividing unit. A first end of the sixth transistor is connected to the second reference voltage.

[0017] In one or more embodiments of the present invention, the intermediate circuit further includes a clamping unit. The clamping unit is connected to the third node to receive a detection signal, and the clamping unit is connected to the second end of the second voltage dividing unit to clamp the voltage at the second end of the second voltage dividing unit based on the detection signal.

[0018] In one or more embodiments of the present invention, the clamping unit includes a seventh transistor. A first end of the seventh transistor is connected to a second reference voltage, a second end of the seventh transistor is connected to the second end of the second voltage dividing unit, and a control end of the seventh transistor is connected to the first detection module to receive the detection signal.

[0019] In one or more embodiments of the present invention, the first control circuit includes a pull-up unit and a pull-down unit. The pull-up unit is connected to a first power supply voltage, the pull-down unit is connected to a first reference voltage, and the pull-up unit and the pull-down unit are connected to form a first node.

[0020] In one or more embodiments of the present invention, the pull-up unit includes an eighth transistor. A first end of the eighth transistor is connected to the first power supply voltage, and a second end of the eighth transistor is connected to the pull-down unit; or the pull-up unit includes a second resistor. A first end of the second resistor is connected to the first power supply voltage, and a second end of the second resistor is connected to the pull-down unit; and / or, the pull-down unit includes a ninth transistor. A first end of the ninth transistor is connected to the first reference voltage, and a second end of the ninth transistor is connected to the pull-up unit; or the pull-down unit includes a third resistor. A first end of the third resistor is connected to the first reference voltage, and a second end of the third resistor is connected to the pull-up unit.

[0021] Compared with the prior art, by providing the first detection module and the clamping module, when the high-voltage domain power supply is powered on but the low-voltage domain power supply is not powered on, the power supply control circuit of the present invention can clamp the voltage at the second node, thereby avoiding the problem of parasitic triode conduction in the prior art and eliminating the reverse current between the power supplies. When the low-voltage domain power supply is normally powered on, the clamping module can be turned off through the second detection module to ensure the normal operation of the circuit. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1It is a circuit connection diagram between the high-voltage domain and the ground-voltage domain in the prior art.

[0024] Figure 2 It is the circuit schematic diagram of the power supply control circuit in an embodiment of the present invention.

[0025] Figure 3 It is the circuit schematic diagram of the first detection module in another embodiment of the present invention. Detailed implementation manners

[0026] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0027] "Coupled" or "connected" or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through a circuit or component such as a switch, a follower circuit, etc. In addition, in the invention, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0028] In the detailed description of the specification, reference is made to the accompanying drawings that form a part of it, in which the same reference numerals always represent the same components, and which are shown by way of exemplary embodiments that can be implemented. It should be understood that other embodiments can be utilized without departing from the scope of the present application, and structural or logical changes can be made. Therefore, the following detailed description should not be construed as limiting.

[0029] The various operations in the specification can be described as a plurality of discrete actions or operations in the order that is most helpful for understanding the claimed subject matter. However, the described order should not be construed as implying that these operations must be order-related. Specifically, these operations may not be performed in the order presented. The described operations can be performed in an order different from the described embodiments. Various additional operations can be performed in additional embodiments and / or the described operations can be omitted.

[0030] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0031] Various components and devices may be referred to or shown herein in the singular form (e.g., "MOS transistor", "transistor", "switch", etc.), but this is merely for convenience of discussion, and any element referred to in the singular form may include a plurality of such elements in accordance with the teachings herein.

[0032] The specification describes the use of the phrases "in one embodiment", "in other embodiments", or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "comprising", "including", "having", etc. used with respect to the embodiments of this application are synonymous.

[0033] Embodiment 1

[0034] As Figure 2 shown, the power supply control circuit in one embodiment of the present invention includes a first control circuit 10, a second control circuit 20, an intermediate circuit 30, a first detection module 40, a clamping module 50, and a second detection module 60.

[0035] Among them, the first control circuit 10 is connected to a first power supply voltage VCC and a first reference voltage VSS. The first control circuit 10 has a first node X, and the first power supply voltage VCC and the first reference voltage VSS are in a high voltage domain.

[0036] The second control circuit 20 includes a first transistor M1 and a second transistor M2. The first end of the first transistor M1 is connected to a second power supply voltage VDD. The second end of the first transistor M1 is connected to the second end of the second transistor M2 to form a second node Y. The first end of the second transistor M2 is connected to a second reference voltage GND. The second power supply voltage VDD and the second reference voltage GND are in a low voltage domain.

[0037] The second control circuit 20 may further include a drive control circuit for controlling the first transistor M1 and the second transistor M2. In other embodiments, the second control circuit 20 may further include other circuit structures. In addition, the first transistor M1 and the second transistor M2 may also be equivalent devices in the second control circuit 20, that is, the second control circuit 20 may be divided into one or more modules to be equivalent to the first transistor M1 and the second transistor M2 (each module may include various devices such as transistors, resistors, capacitors, inductors, etc.).

[0038] The control terminals of the first transistor M1 and the second transistor M2 receive corresponding driving signals, which are provided by the corresponding driving control circuits.

[0039] The intermediate circuit 30 is connected to the first node X and the second node Y. In other embodiments, the intermediate circuit 30 may also be other circuits for current transmission.

[0040] The first detection module 40 is connected to the first reference voltage VSS and the second reference voltage GND, and is configured to generate a detection signal V_Ctrl based on the second reference voltage GND and the first reference voltage VSS.

[0041] The clamping module 50 is connected to the first detection module 40 to form a third node Z to receive the detection signal V_Ctrl. The clamping module 50 is connected to the second node Y and the second reference voltage GND to clamp the voltage of the second node Y based on the detection signal V_Ctrl and the second reference voltage GND.

[0042] The second detection module 60 is connected to the third node Z and the second power supply voltage VDD, and is configured to adjust the signal on the third node Z based on the change of the second power supply voltage VDD. In one embodiment, when the second power supply voltage VDD is powered on or reaches a preset value, the second detection module 60 is turned on to adjust the signal on the third node Z to turn off the clamping module 50.

[0043] In one embodiment, the first power supply voltage VCC is a high positive voltage power supply, and the first reference voltage VSS is a high negative voltage power supply. The second power supply voltage VDD is a low positive voltage power supply, and the second reference voltage GND is the ground voltage of the low voltage domain.

[0044] The first control circuit 10 includes a pull-up unit and a pull-down unit. The pull-up unit is connected to the first power supply voltage VCC, the pull-down unit is connected to the first reference voltage VSS, and the pull-up unit and the pull-down unit are connected to form a first node X.

[0045] Specifically, as Figure 2 shown, the pull-up unit includes an eighth transistor M8. The first end of the eighth transistor M8 is connected to the first power supply voltage VCC, and the second end of the eighth transistor M8 is connected to the pull-down unit.

[0046] The pull-down unit includes a ninth transistor M9. The first end of the ninth transistor M9 is connected to the first reference voltage VSS, and the second end of the ninth transistor M9 is connected to the second end of the eighth transistor M8.

[0047] The first control circuit 10 may further include a driving control circuit for controlling the eighth transistor M8 and the ninth transistor M9. The control terminals of the eighth transistor M8 and the ninth transistor M9 receive corresponding driving signals, which are provided by the corresponding driving control circuits.

[0048] In other embodiments, the eighth transistor M8 can also be replaced by a second resistor. The first end of the second resistor is connected to the first power supply voltage VCC, and the second end of the second resistor is connected to the pull-down unit. The ninth transistor M9 can also be replaced by a third resistor. The first end of the third resistor is connected to the first reference voltage VSS, and the second end of the third resistor is connected to the pull-up unit.

[0049] In addition, whether it is the eighth transistor M8 and the ninth transistor M9, or the second resistor and the third resistor, they can all be equivalent devices in the first control circuit 10. That is, the first control circuit 10 can be divided into one or more modules to be equivalent to the eighth transistor M8, the ninth transistor M9, the second resistor, and the third resistor (each module can include various devices such as transistors, resistors, capacitors, and inductors).

[0050] The intermediate circuit 30 includes a second voltage dividing unit 31, a switching unit 32, and a clamping unit 33.

[0051] Among them, the first end of the second voltage dividing unit 31 is connected to the first node X, the second end of the second voltage dividing unit 31 is connected to the switching unit 32, and the voltage dividing end of the second voltage dividing unit 31 is connected to the second node Y. The switching unit 32 is connected to the second power supply voltage VDD and the second reference voltage GND. The switching unit 32 is used to control the on-off between the second end of the second voltage dividing unit 31, the second power supply voltage VDD, and the second reference voltage GND. The clamping unit 33 is connected to the third node Z to receive the detection signal V_Ctrl, and the clamping unit 33 is connected to the second end of the second voltage dividing unit 31 to clamp the voltage at the second end of the second voltage dividing unit 31 based on the detection signal V_Ctrl.

[0052] In one embodiment, as Figure 2 shown, the second voltage dividing unit 31 includes a fourth resistor R4 and a fifth resistor R5. The first end of the fourth resistor R4 is connected to the first node X, the second end of the fourth resistor R4 and the first end of the fifth resistor R5 are connected to the second node Y, and the second end of the fifth resistor R5 is connected to the switching unit 32.

[0053] The switching unit 32 includes a fifth transistor M5 and a sixth transistor M6. The first end of the fifth transistor M5 is connected to the second power supply voltage VDD, the second end of the fifth transistor M5 and the second end of the sixth transistor M6 are connected to the second end of the fifth resistor R5, and the first end of the sixth transistor M6 is connected to the second reference voltage GND.

[0054] The control ends of the fifth transistor M5 and the sixth transistor M6 receive corresponding driving signals, and the driving signals can be provided by the corresponding driving control circuit according to the actual requirements of the circuit.

[0055] The clamping unit 33 includes a seventh transistor M7. The first end of the seventh transistor M7 is connected to the second reference voltage GND. The second end of the seventh transistor M7 is connected to the second end of a fifth resistor R5. The control end of the seventh transistor M7 is connected to the first detection module 40 to receive a detection signal V_Ctrl.

[0056] In other embodiments, the second voltage dividing unit 31, the switching unit 32, and the clamping unit 33 may be other circuit structures, or the clamping unit 33 may not be provided either.

[0057] As Figure 2 shown, the first detection module 40 includes a first voltage dividing unit connected to the first reference voltage VSS and the second reference voltage GND. The first voltage dividing unit is used to divide the voltage difference between the first reference voltage VSS and the second reference voltage GND to generate a detection signal V_Ctrl.

[0058] Specifically, the first voltage dividing unit includes a sixth resistor R6 and a seventh resistor R7. The first end of the sixth resistor R6 is connected to the second reference voltage GND. The second end of the sixth resistor R6, the first end of the seventh resistor R7, the control end of the seventh transistor M7, and the clamping module 50 are connected to generate a detection signal V_Ctrl. The second end of the seventh resistor R7 is connected to the first reference voltage VSS.

[0059] As Figure 2 shown, the clamping module 50 includes a third transistor M3. The first end of the third transistor M3 is connected to the second reference voltage GND. The second end of the third transistor M3 is connected to the second node Y. The control end of the third transistor M3 is connected to the second end of the sixth resistor R6 and the first end of the seventh resistor R7 to receive a detection signal V_Ctrl.

[0060] As Figure 2 shown, the second detection module 60 includes a fourth transistor M4 and a first resistor R1. The first end of the fourth transistor M4 is connected to the second power supply voltage VDD. The second end of the fourth transistor M4 is connected to the second end of the sixth resistor R6 and the first end of the seventh resistor R7. The control end of the fourth transistor M4 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the second reference voltage GND.

[0061] By providing the first resistor R1, the electrostatic protection ability between the second reference voltage GND and the second power supply voltage VDD can be improved. In other embodiments, the first resistor R1 may not be provided either. Then, the control end of the fourth transistor M4 may be directly connected to the second reference voltage GND, or the control end of the fourth transistor M4 may also be connected to a characterization signal indicating the power-on of the second power supply voltage VDD, such as a POR (power-on reset) signal, a UVLO (under-voltage lockout) signal, or other control signals in the low voltage domain.

[0062] In other embodiments, the second detection module 60 can also be set as a current source with other structures. Then, this current source is connected to the second terminal of the sixth resistor R6, the first terminal of the seventh resistor R7, and the second power supply voltage VDD. After the second power supply voltage VDD is powered on, the detection signal V_Ctrl can be pulled high through this current source.

[0063] In one embodiment, the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 are P-channel MOS transistors, and the second transistor M2, the sixth transistor M6, and the ninth transistor M9 are N-channel MOS transistors.

[0064] The first terminals of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are source electrodes; the second terminals of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are drain electrodes; the control terminals of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are gate electrodes.

[0065] In other embodiments, the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 can also be N-channel MOS transistors or other devices, and the second transistor M2, the sixth transistor M6, and the ninth transistor M9 can also be P-channel MOS transistors or other devices. Then, their connection methods and control methods are adjusted adaptively.

[0066] As Figure 2 shown, when the first reference voltage VSS and the first power supply voltage VCC are powered on, but the second power supply voltage VDD is not powered on, the magnitude of the detection signal V_Ctrl is where R6 and R7 are the resistances of the sixth resistor R6 and the seventh resistor R7 respectively, and the voltages VGS between the control terminal and the first terminal of the third transistor M3 and the voltage VGS between the control terminal and the first terminal of the seventh transistor M7 are both The third transistor M3 and the seventh transistor M7 are turned on, and the voltage on the second node Y and the second end of the second voltage dividing unit 31 is clamped near the second reference voltage GND (i.e., near 0V).

[0067] At this time, the parasitic diodes on the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6, and the parasitic triodes between the second power supply voltage VDD and the second reference voltage GND will not conduct. Therefore, when the second power supply voltage VDD is not powered on, there will be no current path from the second power supply voltage VDD to the first reference voltage VSS, and thus there will be no backflow problem.

[0068] After the second power supply voltage VDD is powered on, the fourth transistor M4 is turned on, pulling up the signal on the third node Z (i.e., the detection signal V_Ctrl), turning off the third transistor M3 and the seventh transistor M7, so that the voltage on the second node Y and the second end of the second voltage dividing unit 31 is no longer clamped, ensuring that the circuit can work normally after power-on. At the same time, it avoids the overvoltage problem between the control end and the second end of the third transistor M3 and between the control end and the second end of the seventh transistor M7 after the second power supply voltage VDD is powered on.

[0069] Embodiment 2

[0070] As Figure 3 shown, the difference between the power supply control circuit in this embodiment and that in Embodiment 1 lies in the specific structure of the first detection module 40, and the structures and working principles of other circuit parts are the same as those in Embodiment 1.

[0071] Specifically, the first detection module 40 includes a resistance unit and a self-biased current source. The self-biased current source is connected to the first reference voltage VSS and the second reference voltage GND to generate a first current based on the first reference voltage VSS and the second reference voltage GND. The first end of the resistance unit is connected to the second reference voltage GND, and the second end of the resistance unit is connected to the self-biased current source to generate the detection signal V_Ctrl based on the first current.

[0072] Among them, the resistance unit includes an eighth resistor R8. The first end of the eighth resistor R8 is connected to the second reference voltage GND, and the second end of the eighth resistor R8 is connected to the self-biased current source.

[0073] The self-biased current source includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and a ninth resistor R9.

[0074] In one embodiment, the eleventh transistor M11 and the twelfth transistor M12 form a current mirror, and the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 also form a current mirror.

[0075] Specifically, the first ends of the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are connected to the second reference voltage GND. The first ends of the fourteenth transistor M14, the fifteenth transistor M15, the seventeenth transistor M17, and the first end of the ninth resistor R9 are connected to the first reference voltage VSS. The first end of the sixteenth transistor M16 is connected to the second end of the ninth resistor R9. The second end of the tenth transistor M10, the control end of the tenth transistor M10, and the control end of the thirteenth transistor M13 are connected to the second end of the fourteenth transistor M14. The control end of the fourteenth transistor M14, the first end of the thirteenth transistor M13, the control end of the fifteenth transistor M15, the second end of the fifteenth transistor M15, the control end of the sixteenth transistor M16, and the control end of the seventeenth transistor M17 are connected to the second end of the eleventh transistor M11. The control end of the eleventh transistor M11, the control end of the twelfth transistor M12, the second end of the twelfth transistor M12, and the second end of the thirteenth transistor M13 are connected to the second end of the sixteenth transistor M16. The second end of the seventeenth transistor M17 is connected to the second end of the eighth resistor R8 to output a detection signal V_Ctrl.

[0076] In one embodiment, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are PMOS transistors, and the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 are NMOS transistors.

[0077] The first terminals of the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 are source electrodes. The second terminals of the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 are drain electrodes. The control terminals of the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 are gate electrodes.

[0078] In other embodiments, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 may also be NMOS transistors or other devices, and the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 may also be PMOS transistors or other devices. Then, their connection methods and control methods are adjusted adaptively. The self-biased current source may also adopt other current source circuit structures.

[0079] After the first reference voltage VSS is powered on, the self-biased current source can generate a first current. The eighth resistor R8 generates a voltage of the detection signal V_Ctrl based on the first current, which is lower than the second bias voltage GND, so that the third transistor M3 and the seventh transistor M7 can be turned on, realizing the clamping effect on the second node Y and the second end of the second voltage dividing unit 31.

[0080] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0081] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment contains only one independent technical solution. This narrative style of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A power supply control circuit, characterized in that: include: A first control circuit is connected to a first power supply voltage and a first reference voltage, the first control circuit has a first node, and the first power supply voltage and the first reference voltage are located in a high voltage domain; A second control circuit includes a first transistor and a second transistor, wherein a first end of the first transistor is connected to a second power supply voltage, a second end of the first transistor is connected to a second end of the second transistor to form a second node, a first end of the second transistor is connected to a second reference voltage, and the second power supply voltage and the second reference voltage are located in a low voltage domain; an intermediate circuit connected to the first node and the second node; A first detection module, connected to the first reference voltage and the second reference voltage, and configured to generate a detection signal based on the second reference voltage and the first reference voltage; A clamping module connected to the first detection module to form a third node to receive a detection signal, wherein the clamping module is connected to the second node to clamp the voltage of the second node based on the control of the detection signal; The second detection module is connected to the third node and the second power supply voltage, and is used to adjust the signal on the third node based on the change of the second power supply voltage.

2. The power supply control circuit according to claim 1, characterized in that: The first detection module includes a first voltage dividing unit connected to the first reference voltage and the second reference voltage, and the first voltage dividing unit is used to divide the voltage difference between the first reference voltage and the second reference voltage to generate a detection signal; or The first detection module includes a resistance unit and a self-bias current source, the self-bias current source is connected to a first reference voltage and a second reference voltage to generate a first current based on the first reference voltage and the second reference voltage, and the resistance unit is connected to the self-bias current source to generate a detection signal based on the first current.

3. The power supply control circuit according to claim 1, characterized in that: The clamping module includes a third transistor, a first end of the third transistor is connected to the second reference voltage, a second end of the third transistor is connected to the second node, and a control end of the third transistor is connected to the first detection module to form a third node to receive a detection signal.

4. The power supply control circuit according to claim 1, characterized in that: The second detection module includes a fourth transistor, a first end of the fourth transistor is connected to the second power supply voltage, a second end of the fourth transistor is connected to the third node, and a control end of the fourth transistor is connected to the second reference voltage or to a characterization signal characterizing that the second power supply voltage is powered on; or The second detection module includes a fourth transistor and a first resistor, the first end of the fourth transistor is connected to the second power supply voltage, the second end of the fourth transistor is connected to the third node, the control end of the fourth transistor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the second reference voltage.

5. The power supply control circuit according to claim 1, characterized in that: The intermediate circuit includes a second voltage divider unit and a switch unit, wherein the first end of the second voltage divider unit is connected to the first node, the second end of the second voltage divider unit is connected to the switch unit, the voltage divider end of the second voltage divider unit is connected to the second node, the switch unit is connected to the second power supply voltage and the second reference voltage, and the switch unit is used to control the on and off between the second end of the second voltage divider unit and the second power supply voltage and the second reference voltage.

6. The power supply control circuit according to claim 5, characterized in that: The switch unit includes a fifth transistor and a sixth transistor, the first end of the fifth transistor is connected to the second power supply voltage, the second end of the fifth transistor and the second end of the sixth transistor are connected to the second end of the second voltage divider unit, and the first end of the sixth transistor is connected to the second reference voltage.

7. The power supply control circuit according to claim 5, characterized in that: The intermediate circuit further includes a clamping unit connected to the third node to receive the detection signal and connected to the second end of the second voltage dividing unit to clamp the voltage of the second end of the second voltage dividing unit based on the detection signal.

8. The power supply control circuit according to claim 7, characterized in that: The clamping unit includes a seventh transistor, a first end of the seventh transistor is connected to the second reference voltage, a second end of the seventh transistor is connected to the second end of the second voltage divider unit, and a control end of the seventh transistor is connected to the first detection module to receive a detection signal.

9. The power supply control circuit according to claim 1, characterized in that: The first control circuit includes a pull-up unit and a pull-down unit, the pull-up unit is connected to a first power supply voltage, the pull-down unit is connected to a first reference voltage, and the pull-up unit and the pull-down unit are connected to form a first node.

10. The power supply control circuit according to claim 9, characterized in that: The pull-up unit includes an eighth transistor, a first end of the eighth transistor is connected to the first power supply voltage, and a second end of the eighth transistor is connected to the pull-down unit; or the pull-up unit includes a second resistor, a first end of the second resistor is connected to the first power supply voltage, and a second end of the second resistor is connected to the pull-down unit; and / or, The pull-down unit includes a ninth transistor, a first end of the ninth transistor is connected to the first reference voltage, and a second end of the ninth transistor is connected to the pull-up unit; or the pull-down unit includes a third resistor, a first end of the third resistor is connected to the first reference voltage, and a second end of the third resistor is connected to the pull-up unit.

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