Switching circuit and clock pulse supply circuit

Abstract

The invention provides a switching circuit and a clock pulse supply circuit, and the switching circuit is coupled with a first oscillation circuit and a second oscillation circuit. The first oscillation circuit generates a first clock pulse signal according to a first enable signal. The second oscillation circuit generates a second clock pulse signal according to a second enable signal. The switching circuit takes the first clock signal or the second clock signal as an output clock according to a selection signal. The switching circuit comprises a first D-type flip-flop and a second D-type flip-flop. The reset end of the first D-type flip-flop receives the first enable signal. The reset end of the second D-type flip-flop receives the second enable signal.

Description

Technical Field

[0001] The present invention relates to a switching circuit, and more particularly to a switching circuit for switching clock signals. Background Art

[0002] With the progress of technology, the functions and types of electronic devices are increasing. There are many digital circuits inside electronic devices. The driving signals of digital circuits are mostly clock signals. Sometimes, the clock signal needs to be switched to different frequencies according to different application scenarios. Therefore, an electronic device has at least two clock sources for generating at least two clock signals with different frequencies. However, when switching the clock signal, it is easy to form glitches on the clock signal, which will affect the stability of the system. Summary of the Invention

[0003] An embodiment of the present invention provides a switching circuit, which is coupled to a first oscillation circuit and a second oscillation circuit. The first oscillation circuit generates a first clock signal according to a first enable signal. The second oscillation circuit generates a second clock signal according to a second enable signal. The switching circuit of the present invention includes a detection circuit, an inverter, a first judgment circuit, a first D flip-flop, a second judgment circuit, a second D flip-flop, and a clock gating circuit. The detection circuit detects a third enable signal and a fourth enable signal to generate a detection signal. The inverter inverts a selection signal to generate an inverted signal. When the detection signal is a specific voltage, the first judgment circuit outputs the inverted signal. The first D flip-flop receives the inverted signal and uses the inverted signal as the third enable signal according to the first clock signal. When the detection signal is the specific voltage, the second judgment circuit outputs the selection signal. The second D flip-flop receives the selection signal and uses the selection signal as the fourth enable signal according to the second clock signal. The clock gating circuit uses the third and fourth enable signals to use the first or second clock signal as an output clock. The first D flip-flop has a first reset terminal. The first reset terminal receives the first enable signal. The second D flip-flop has a second reset terminal. The second reset terminal receives the second enable signal.

[0004] The present invention further provides a clock supply circuit, which provides an output clock according to a selection signal, and includes a first oscillation circuit, a second oscillation circuit, and a switching circuit. The first oscillation circuit generates a first clock signal according to a first enable signal. The second oscillation circuit generates a second clock signal according to a second enable signal. The switching circuit takes the first or second clock signal as the output clock according to the selection signal, and includes a detection circuit, an inverter, a first judgment circuit, a first D flip-flop, a second judgment circuit, a second D flip-flop, and a clock gating circuit. The detection circuit detects a third enable signal and a fourth enable signal to generate a detection signal. The inverter inverts the selection signal to generate a first inverted signal. When the detection signal is a specific voltage, the first judgment circuit outputs the first inverted signal. The first D flip-flop receives the first inverted signal and takes the first inverted signal as the third enable signal according to the first clock signal. When the detection signal is a specific voltage, the second judgment circuit outputs the selection signal. The second D flip-flop receives the selection signal and takes the selection signal as the fourth enable signal according to the second clock signal. The clock gating circuit takes the first or second clock signal as the output clock according to the third and fourth enable signals. The first D flip-flop has a first reset terminal. The first reset terminal receives the first enable signal. The second D flip-flop has a second reset terminal. The second reset terminal receives the second enable signal.

[0005] The present invention provides a switching circuit and a clock supply circuit, which eliminate the glitches formed on the clock signal during the clock signal switching, and improve the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of the clock supply circuit of the present invention.

[0007] Figure 2A is a schematic diagram of the switching circuit of the present invention.

[0008] Figure 2B is another schematic diagram of the switching circuit of the present invention.

[0009] Figure 3 is a timing control schematic diagram of the switching circuit of the present invention.

[0010] Figure 4 is another schematic diagram of the switching circuit of the present invention.

[0011] SYMBOL DESCRIPTION

[0012] 100: Clock supply circuit

[0013] 110, 120: Oscillation circuit

[0014] 130, 200A, 200B: Switching circuit

[0015] clk_sel: Selection signal

[0016] clk_out, SO_1 ~ SO_6: Output clock

[0017] osc0_en, osc1_en, clk0_en, clk1_en: Enable signal

[0018] clk0, clk1: Clock signal

[0019] 210: Detection circuit

[0020] INV_1 ~ INV_5: Inverter

[0021] 220A, 220B: Judgment circuit

[0022] DFF_1 ~ DFF_4: D-type flip-flop

[0023] 230: Clock gating circuit

[0024] 240: Synchronization circuit

[0025] 211: NOR gate

[0026] SD: Detection signal

[0027] SI_1 ~ SI_3: Inverted signal

[0028] SP_1, SP_2: Processing signal

[0029] AD_1 ~ AD_4: AND gate

[0030] OR_1 ~ OR_3: OR gate

[0031] MX_1, MX_2: Multiplexer

[0032] SC_1, SC_2: Control signal

[0033] clk0_en_d, clk1_en_d: Delay signal

[0034] 300: Time point

[0035] 310: Falling edge

[0036] 400: Switching circuit

[0037] 250A, 250B: Logic gate

[0038] SPOR: Power-on reset signal

[0039] SR_1, SR_2: Reset signals Detailed implementation manners

[0040] To make the objectives, features, and advantages of the present invention more apparent and understandable, embodiments are specifically given below and detailed descriptions are made in conjunction with the accompanying drawings. The specification of the present invention provides different embodiments to illustrate the technical features of different implementation manners of the present invention. Among them, the configurations of the components in the embodiments are for illustrative purposes only and are not intended to limit the present invention. In addition, the partial repetition of the reference numerals in the drawings of the embodiments is for simplifying the description and does not imply the relevance between different embodiments.

[0041] Figure 1 FIG. is a schematic diagram of a clock supply circuit of the present invention. As shown in the figure, the clock supply circuit 100 provides an output clock clk_out to a load (not shown) according to a selection signal clk_sel. In this embodiment, the clock supply circuit 100 includes oscillator circuits 110, 120 and a switching circuit 130. In some embodiments, the oscillator circuits 110, 120 and the switching circuit 130 are integrated in a system on a chip (SOC).

[0042] The oscillator circuit 110 generates a clock signal clk0 according to an enable signal osc0_en. In a possible embodiment, when the enable signal osc0_en is enabled, the enable signal osc0_en is a specific voltage, such as a low voltage. At this time, the oscillator circuit 110 generates the clock signal clk0. When the enable signal osc0_en is disabled, the enable signal osc0_en is not a specific voltage. Therefore, the oscillator circuit 110 stops generating the clock signal clk0. In a possible embodiment, when the enable signal osc0_en is disabled, the enable signal osc0_en is a high voltage. The present invention does not limit the architecture of the oscillator circuit 110. Any circuit that can generate a clock signal can be used as the oscillator circuit 110.

[0043] The oscillator circuit 120 generates a clock signal clk1 according to an enable signal osc1_en. Since the characteristics of the oscillator circuit 120 are similar to those of the oscillator circuit 110, they will not be described in detail. In a possible embodiment, the frequency of the clock signal clk1 is different from the frequency of the clock signal clk0.

[0044] The switching circuit 130 takes the clock signal clk0 or clk1 as the output clock clk_out according to the selection signal clk_sel. For example, when the selection signal clk_sel is a first voltage (such as a low voltage), the switching circuit 130 takes the clock signal clk0 as the output clock clk_out. When the selection signal clk_sel is a second voltage (such as a high voltage), the switching circuit 130 takes the clock signal clk1 as the output clock clk_out.

[0045] Figure 2A This is a schematic diagram of the switching circuit of the present invention. As shown in the figure, the switching circuit 200A includes a detection circuit 210, an inverter INV_1, judgment circuits 220A, 220B, D-type flip-flops DFF_1, DFF_2, and a clockgate circuit 230.

[0046] The detection circuit 210 generates a detection signal SD according to the enable signals clk0_en and clk1_en. In this embodiment, when the enable signals clk0_en and clk1_en are both a first specific voltage (such as a high voltage), the detection circuit 210 sets the detection signal SD to a second specific voltage (such as a low voltage). When the enable signals clk0_en and clk1_en are both a second specific voltage (such as a low voltage), the detection circuit 210 sets the detection signal SD to a first specific voltage (such as a high voltage). The present invention does not limit the architecture of the detection circuit 210. In a possible embodiment, the detection circuit 210 is a NOR gate 211. The NOR gate 211 receives the enable signals clk0_en and clk1_en and provides the detection signal SD.

[0047] The inverter INV_1 inverts the selection signal clk_sel to generate an inverted signal SI_1.

[0048] The judgment circuit 220A provides an output signal SO_5 to the D-type flip-flop DFF_1 according to the detection signal SD, the inverted signal SI_1, and the enable signal clk0_en. In a possible embodiment, when the detection signal SD is a first specific voltage (such as a high voltage), it means that the enable signals clk0_en and clk1_en are both a second specific voltage (such as a low voltage). Therefore, the judgment circuit 220A sets the output signal SO_5 equal to the inverted signal SI_1. In another possible embodiment, when the detection signal SD is a second specific voltage, it means that at least one of the enable signals clk0_en and clk1_en is not the second specific voltage. Therefore, the judgment circuit 220A sets the output signal SO_5 equal to the enable signal clk0_en or a low voltage according to the inverted signal SI_1.

[0049] The architecture of the determination circuit 220A is not limited by the present invention. In a possible embodiment, the determination circuit 220A includes an AND gate AD_3, an OR gate OR_2, and a multiplexer MX_1. The AND gate AD_3 generates an output signal SO_3 according to the detection signal SD and the inverted signal SI_1. The OR gate OR_2 generates a control signal SC_1 according to the output signal SO_3 and a processing signal SP_1.

[0050] In a possible embodiment, the processing signal SP_1 is the same as the selection signal clk_sel. Therefore, an input terminal of the OR gate OR_2 may be directly coupled to the input terminal of the inverter INV_1. The multiplexer MX_1 sets the output signal SO_5 equal to the enable signal clk0_en or the output signal SO_3 according to the control signal SC_1. In some embodiments, the determination circuit 220A further includes an inverter INV_4. The inverter INV_4 inverts the inverted signal SI_1 to generate the processing signal SP_1.

[0051] The D-type flip-flop DFF_1 receives the output signal SO_5 and provides the enable signal clk0_en according to the clock signal clk0. In a possible embodiment, the D-type flip-flop DFF_1 uses the inverted signal SI_1 as the enable signal clk0_en. In this embodiment, the input terminal D of the D-type flip-flop DFF_1 receives the output signal SO_5. The clock terminal of the D-type flip-flop DFF_1 receives the clock signal clk0. The output terminal Q of the D-type flip-flop DFF_1 provides the enable signal clk0_en. The reset terminal R of the D-type flip-flop DFF_1 receives the enable signal osc0_en. In a possible embodiment, when the enable signal osc0_en is a low voltage (or a second specific voltage), the D-type flip-flop DFF_1 sets the enable signal clk0_en to a low voltage.

[0052] The determination circuit 220B provides an output signal SO_6 to the D-type flip-flop DFF_2 according to the detection signal SD, the selection signal clk_sel, and the enable signal clk1_en. In a possible embodiment, when the detection signal SD is a first specific voltage, it means that both the enable signals clk0_en and clk1_en are a second specific voltage. Therefore, the determination circuit 220B sets the output signal SO_6 equal to the selection signal clk_sel. In another possible embodiment, when the detection signal SD is a second specific voltage, it means that at least one of the enable signals clk0_en and clk1_en is not the second specific voltage. Therefore, the determination circuit 220B sets the output signal SO_6 equal to a low voltage or the enable signal clk1_en according to the selection signal clk_sel.

[0053] The present invention does not limit the architecture of the determination circuit 220B. In a possible embodiment, the determination circuit 220B includes an AND gate AD_4, an OR gate OR_3, and a multiplexer MX_2. The AND gate AD_4 generates an output signal SO_4 according to the detection signal SD and the selection signal clk_sel. The OR gate OR_3 generates a control signal SC_2 according to the output signal SO_4 and a processing signal SP_2.

[0054] In a possible embodiment, the processing signal SP_2 is the same as the inverted signal SI_1. Therefore, one input terminal of the OR gate OR_3 may be directly coupled to the output terminal of the inverter INV_1. The multiplexer MX_2 sets the output signal SO_6 to be equal to the enable signal clk1_en or the output signal SO_4 according to the control signal SC_2. In some embodiments, the determination circuit 220B further includes an inverter INV_5. The inverter INV_5 inverts the selection signal clk_sel to generate the processing signal SP_2.

[0055] The D flip-flop DFF_2 receives the output signal SO_6 and provides the enable signal clk1_en according to the clock signal clk1. In a possible embodiment, the D flip-flop DFF_2 uses the selection signal clk_sel as the enable signal clk1_en. In this embodiment, the input terminal D of the D flip-flop DFF_2 receives the output signal SO_6. The clock terminal of the D flip-flop DFF_2 receives the clock signal clk1. The output terminal Q of the D flip-flop DFF_2 provides the enable signal clk1_en. The reset terminal R of the D flip-flop DFF_2 receives the enable signal osc1_en. In a possible embodiment, when the enable signal osc1_en is a low voltage, the D flip-flop DFF_2 sets the enable signal clk1_en to be a low voltage.

[0056] The clock gating circuit 230 uses the enable signals clk0_en and clk1_en to select the clock signal clk0 or clk1 as the output clock clk_out. For example, when the enable signal clk0_en is a first specific voltage, it means that the enable signal clk0_en is enabled. Therefore, the clock gating circuit 230 uses the clock signal clk0 as the output clock clk_out. When the enable signal clk1_en is a first specific voltage, it means that the enable signal clk1_en is enabled. Therefore, the clock gating circuit 230 uses the clock signal clk1 as the output clock clk_out. The present invention does not limit the architecture of the clock gating circuit 230. In a possible embodiment, the clock gating circuit 230 includes AND gates AD_1, AD_2, and an OR gate OR_1.

[0057] The AND gate AD_1 determines whether to use the clock signal clk0 as an output signal SO_1 according to the enable signal clk0_en. For example, when the enable signal clk0_en is a high voltage (or a first specific voltage), the AND gate AD_1 uses the clock signal clk0 as the output signal SO_1. When the enable signal clk0_en is a low voltage (or a second specific voltage), the AND gate AD_1 stops using the clock signal clk0 as the output signal SO_1. At this time, the AND gate AD_1 may set the output signal SO_1 to a low voltage.

[0058] The AND gate AD_2 determines whether to use the clock signal clk1 as an output signal SO_2 according to the enable signal clk1_en. Since the operation of the AND gate AD_2 is similar to that of the AND gate AD_1, it will not be elaborated here. The OR gate OR_1 generates the output clock clk_out according to the output signals SO_1 and SO_2. For example, when the AND gate AD_1 uses the clock signal clk0 as the output signal SO_1, the OR gate OR_1 uses the clock signal clk0 as the output clock clk_out. When the AND gate AD_2 uses the clock signal clk1 as the output signal SO_2, the OR gate OR_1 uses the clock signal clk1 as the output clock clk_out.

[0059] In this embodiment, the detection circuit 210 detects the enable signals clk0_en and clk1_en, so that the judgment circuits 220A and 220B require the clock gating circuit 230 to switch the output clock clk_out under a specific condition (such as when the enable signals clk0_en and clk1_en are both low voltages), thus avoiding glitches in the output clock clk_out.

[0060] Figure 2B This is another schematic diagram of the switching circuit of the present invention. Figure 2B Similar Figure 2A , except that Figure 2B the switching circuit 200B further includes a synchronization circuit 240. The synchronization circuit 240 is used to compensate for the metastable state caused by the asynchronization between signals in different clock domains.

[0061] For example, when the time domain of the selection signal clk_sel is different from the time domains of the clock signals clk0 and clk1, the voltage change time point of the selection signal clk_sel may just be very close to the rising edge or the falling edge of the clock signal clk0 or clk1. As a result, the output clock clk_out is in a metastable state, causing abnormal operation of the circuit that receives the output clock clk_out at the back end.

[0062] However, by means of the synchronization circuit 240, when the selection signal clk_sel changes state, it can be avoided that the clock gating circuit 230 immediately uses the clock signal clk0 or clk1 as the output clock clk_out. In a possible embodiment, after waiting for a period of time, the synchronization circuit 240 requests the clock gating circuit 230 to use the clock signal clk0 or clk1 as the output clock clk_out.

[0063] In this embodiment, the synchronization circuit 240 includes inverters INV_2, INV_3, D flip-flops DFF_3 and DFF_4. The inverter INV_2 inverts the clock signal clk0 to generate an inverted signal SI_2. The inverter INV_3 inverts the clock signal clk1 to generate an inverted signal SI_3.

[0064] The D flip-flop DFF_3 is coupled between the D flip-flop DFF_1 and the clock gating circuit 230, and according to the inverted signal SI_2, uses the enable signal clk0_en as a delayed signal clk0_en_d. In this embodiment, the input terminal D of the D flip-flop DFF_3 receives the enable signal clk0_en. The clock terminal of the D flip-flop DFF_3 receives the inverted signal SI_2. The output terminal Q of the D flip-flop DFF_3 provides the delayed signal clk0_en_d. The reset terminal R of the D flip-flop DFF_3 receives the enable signal osc0_en. In a possible embodiment, when the enable signal osc0_en is a low voltage, the D flip-flop DFF_3 sets the delayed signal clk0_en_d to a low voltage.

[0065] The D flip-flop DFF_4 is coupled between the D flip-flop DFF_2 and the clock gating circuit 230, and according to the inverted signal SI_3, uses the enable signal clk1_en as a delayed signal clk1_en_d. In this embodiment, the input terminal D of the D flip-flop DFF_4 receives the enable signal clk1_en. The clock terminal of the D flip-flop DFF_4 receives the inverted signal SI_3. The output terminal Q of the D flip-flop DFF_4 provides the delayed signal clk1_en_d. The reset terminal R of the D flip-flop DFF_4 receives the enable signal osc1_en. In a possible embodiment, when the enable signal osc1_en is a low voltage, the D flip-flop DFF_4 sets the delayed signal clk1_en_d to a low voltage.

[0066] In this embodiment, the AND gate AD_1 of the clock gate control circuit 230 receives the delay signal clk0_en_d, and determines whether to use the clock signal clk0 as the output signal SO_1 according to the delay signal clk0_en_d. For example, when the delay signal clk0_en_d is a first specific voltage (such as a high voltage), the AND gate AD_1 uses the clock signal clk0 as the output signal SO_1. When the delay signal clk0_en_d is a second specific voltage (such as a low voltage), the AND gate AD_1 stops using the clock signal clk0 as the output signal SO_1. At this time, the AND gate AD_1 may set the output signal SO_1 to the second specific voltage.

[0067] The AND gate AD_2 of the clock gate control circuit 230 receives the delay signal clk1_en_d, and determines whether to use the clock signal clk1 as the output signal SO_2 according to the delay signal clk1_en_d. For example, when the delay signal clk1_en_d is a first specific voltage, the AND gate AD_2 uses the clock signal clk1 as the output signal SO_2. When the delay signal clk1_en_d is a second specific voltage, the AND gate AD_2 stops using the clock signal clk1 as the output signal SO_2. At this time, the AND gate AD_2 may set the output signal SO_2 to the second specific voltage.

[0068] In this embodiment, the detection circuit 210 detects the delay signals clk0_en_d and clk1_en_d to generate a detection signal SD. In this example, when both the delay signals clk0_en_d and clk1_en_d are a first specific voltage (such as a high voltage), the detection circuit 210 sets the detection signal SD to a second specific voltage (such as a low voltage). When both the delay signals clk0_en_d and clk1_en_d are a second specific voltage (such as a low voltage), the detection circuit 210 sets the detection signal SD to a first specific voltage (such as a high voltage).

[0069] Figure 3 This is a timing control schematic diagram of the switching circuit 200B of the present invention. Before time point 300, a specific event does not occur. Therefore, a reset signal rstn is a high voltage. At this time, a selection signal clk_sel is a high voltage, indicating that the output clock clk_out provided by the switching circuit 200B needs to be equal to the clock signal clk1.

[0070] Before time point 300, an enable signal osc0_en is a low voltage, and an enable signal osc1_en is a high voltage. Therefore, the oscillation circuit 110 stops generating the clock signal clk0, and the oscillation circuit 120 generates the clock signal clk1. In this example, since the oscillation circuit 110 does not need to continuously generate the clock signal clk0, power consumption can be saved.

[0071] In addition, since the enable signal clk0_en is a low voltage, the delayed signal clk0_en_d is also a low voltage. Therefore, the AND gate AD_1 of the clock gating circuit 230 does not output the clock signal clk0. At this time, since the enable signal clk1_en is a high voltage, the delayed signal clk1_en_d is also a high voltage. Therefore, the AND gate AD_2 of the clock gating circuit 230 outputs the clock signal clk1. The OR gate OR_1 outputs the clock signal clk1 as the output clock clk_out.

[0072] At time point 300, a specific event occurs. Therefore, the reset signal rstn is enabled, changing from a high voltage to a low voltage and then back to a high voltage. When the reset signal rstn is enabled, the select signal clk_sel is reset to a first preset voltage, such as a low voltage. At this time, the enable signal osc0_en is reset to a first preset voltage, such as a high voltage, and the enable signal osc1_en is reset to a second preset voltage, such as a low voltage. In some embodiments, the enable signal osc1_en returns to the second preset voltage after the falling edge 310 of the clock signal clk1.

[0073] Since the enable signal osc0_en is a high voltage, the oscillator circuit 110 generates the clock signal clk0. The enable signal osc1_en is a low voltage, so the oscillator circuit 120 does not generate the clock signal clk1. At this time, since the enable signal osc1_en is a low voltage, the D-type flip-flops DFF_2 and DFF_4 enable the signals clk1_en and the delayed signal clk1_en_d, making the enable signal clk1_en and the delayed signal clk1_en_d low voltages.

[0074] To avoid generating glitches, the enable signal clk0_en changes from a low voltage to a high voltage after a period of delay. Then, to avoid metastability, after a period of time when the enable signal clk0_en changes from a low voltage to a high voltage, the delayed signal clk0_en_d also changes from a low voltage to a high voltage. Since the delayed signal clk0_en_d is a high voltage, the AND gate AD_1 of the clock gating circuit 230 outputs the clock signal clk0, and the OR gate OR_1 of the clock gating circuit 230 outputs the clock signal clk0 as the output clock clk_out.

[0075] In this embodiment, since the enable signal clk0_en is a low voltage, after half a cycle of the clock signal clk0, the delayed signal clk0_en_d is a low voltage, so the AND gate AD_1 of the clock gating circuit 230 does not output the clock signal clk0. At this time, since the delayed signal clk1_en_d is a high voltage, the AND gate AD_2 of the clock gating circuit 230 outputs the clock signal clk1. Since the enable signal osc1_en is a high voltage, the oscillation circuit 120 generates the clock signal clk1, and the OR gate OR_1 of the clock gating circuit 230 uses the clock signal clk1 as the output clock clk_out. Before time point 300, since the enable signal osc0_en is a low voltage, the oscillation circuit 110 pauses generating the clock signal clk0.

[0076] Figure 4 Another schematic diagram of the switching circuit of the present invention. Figure 4 Similar to Figure 2B , the difference is that, Figure 4 the switching circuit 400 of Figure 4 further includes logic gates 250A and 250B. In other embodiments, Figure 2A the logic gates 250A and 250B of

[0077] The logic gate 250A provides a reset signal SR_1 to the reset terminals R of the D-type flip-flops DFF_1 and DFF_3 according to the enable signal osc0_en and a power-on reset signal SPOR. In a possible embodiment, when the power-on reset signal SPOR is not a specific voltage (such as a high voltage), the logic gate 250A uses the power-on reset signal SPOR as the reset signal SR_1.

[0078] The logic gate 250B provides a reset signal SR_2 to the reset terminals R of the D-type flip-flops DFF_2 and DFF_4 according to the enable signal osc1_en and the power-on reset signal SPOR. In a possible embodiment, when the power-on reset signal SPOR is not a specific voltage (such as a high voltage), the logic gate 250B uses the power-on reset signal SPOR as the reset signal SR_2.

[0079] In this embodiment, the power-on reset signal SPOR is used to reset the D-type flip-flops DFF_1 to DFF_4 before the switching circuit 400 starts to operate, so as to set the enable signals clk0_en, clk1_en, and the delayed signals clk0_en_d and clk1_en_d to a low voltage. The present invention does not limit the types of the logic gates 250A and 250B. In this embodiment, both the logic gates 250A and 250B are AND gates.

[0080] When the power-on reset signal SPOR is enabled to be a low voltage, both the reset signals SR_1 and SR_2 are low voltages. Since the reset signal SR_1 is a low voltage, the D-type flip-flop DFF_1 sets the enable signal clk0_en to a low voltage, and the D-type flip-flop DFF_3 sets the delay signal clk0_en_d to a low voltage. Additionally, since the reset signal SR_2 is a low voltage, the D-type flip-flop DFF_2 sets the enable signal clk1_en to a low voltage, and the D-type flip-flop DFF_4 sets the delay signal clk1_en_d to a low voltage. At this time, both the delay signals clk0_en_d and clk1_en_d are low voltages, so the detection signal SD is a high voltage. Therefore, the determination circuit 220A provides the inverted signal SI_1 to the D-type flip-flop DFF_1 and the determination circuit 220B provides the selection signal clk_sel to the D-type flip-flop DFF_2.

[0081] When the selection signal clk_sel is a low voltage, the D-type flip-flop DFF_1 sets the enable signal clk0_en to a high voltage. When the voltage of the clock signal clk0 changes from a high voltage to a low voltage, the D-type flip-flop DFF_3 sets the delay signal clk0_en_d to a high voltage. Therefore, the AND gate AD_1 outputs the clock signal clk0 as the output signal SO_1. At this time, the D-type flip-flop DFF_2 sets the enable signal clk1_en to a low voltage. When the voltage of the clock signal clk1 changes from a high voltage to a low voltage, the D-type flip-flop DFF_4 sets the delay signal clk1_en_d to a low voltage. Therefore, the AND gate AD_2 does not output the clock signal clk1 as the output signal SO_2. Therefore, the OR gate OR_1 outputs the clock signal clk0 as the output clock clk_out.

[0082] When the selection signal clk_sel is a high voltage, the D-type flip-flop DFF_2 sets the enable signal clk1_en to a high voltage. When the voltage of the clock signal clk1 changes from a high voltage to a low voltage, the D-type flip-flop DFF_4 sets the delay signal clk1_en_d to a high voltage. Therefore, the AND gate AD_2 outputs the clock signal clk1 as the output signal SO_2. At this time, the D-type flip-flop DFF_1 sets the enable signal clk0_en to a low voltage. When the voltage of the clock signal clk0 changes from a high voltage to a low voltage, the D-type flip-flop DFF_3 sets the delay signal clk1_en_d to a low voltage. Therefore, the AND gate AD_1 does not output the clock signal clk0 as the output signal SO_1. Therefore, the OR gate OR_1 outputs the clock signal clk1 as the output clock clk_out.

[0083] It must be understood that when a device is referred to as being "coupled" to another device, it can be directly coupled or connected to the other device, or there can be other devices in between. Conversely, when a device is "connected" to another device, there are no other devices in between. Additionally, "enable" shall mean changing the state of a Boolean signal. The Boolean signal can be enabled to be high or have a higher voltage, and the Boolean signal can be enabled to be low or have a lower voltage at the discretion of the circuit designer. Similarly, "disable" shall mean changing the state of the Boolean signal to a voltage opposite to the enabled state.

[0084] Unless otherwise defined, all terms herein (including technical and scientific terms) shall have the ordinary meaning as understood by those of ordinary skill in the art to which this invention pertains. In addition, unless explicitly stated, the definitions of terms in a general dictionary shall be interpreted as being consistent with their meanings in the context of the relevant technical field, and shall not be interpreted in an idealized or overly formal sense. Although terms such as "first", "second", etc. may be used to describe various devices, these devices should not be limited by these terms. These terms are only used to distinguish one device from another.

[0085] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. For example, the systems, devices, or methods described in the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be determined by the scope defined in the patent application.

Claims

1. A switching circuit, characterized in that: A first oscillating circuit and a second oscillating circuit are coupled, the first oscillating circuit generates a first clock signal according to a first enable signal, and the second oscillating circuit generates a second clock signal according to a second enable signal, and the switching circuit includes: a detection circuit, detecting a third enable signal and a fourth enable signal to generate a detection signal; a first inverter, inverting a selection signal to generate a first inverted signal; a first judgment circuit, which outputs the first inverted signal when the detection signal is a specific voltage; a first D-type flip-flop, receiving the first inverted signal, and using the first inverted signal as the third enable signal according to the first clock signal; a second judgment circuit, which outputs the selection signal when the detection signal is the specific voltage; a second D-type flip-flop, receiving the selection signal and using the selection signal as the fourth enable signal according to the second clock signal; and a clock gating circuit, which uses the first clock signal or the second clock signal as an output clock according to the third enable signal and the fourth enable signal, The first D-type flip-flop has a first reset terminal, and the first reset terminal receives the first enable signal. The second D-type flip-flop has a second reset terminal, and the second reset terminal receives the second enable signal.

2. The switching circuit according to claim 1, characterized in that: Also includes: a second inverter, inverting the first clock signal to generate a second inverted signal; a third D-type flip-flop coupled between the first D-type flip-flop and the clock gate control circuit, and using the third enable signal as a first delay signal according to the second inverted signal; a third inverter, inverting the second clock signal to generate a third inverted signal; A fourth D-type flip-flop is coupled between the second D-type flip-flop and the clock gate control circuit, and uses the fourth enable signal as a second delay signal according to the third inverted signal.

3. The switching circuit according to claim 2, characterized in that: The third D-type flip-flop has a third reset terminal, and the third reset terminal receives the first enable signal. The fourth D-type flip-flop has a fourth reset terminal, and the fourth reset terminal receives the second enable signal.

4. The switching circuit according to claim 2, characterized in that: The clock gate control circuit comprises: a first AND gate, determining whether to use the first clock signal as a first output signal according to the first delay signal; A second AND gate determines whether to use the second clock signal as a second output signal according to the second delay signal; and a first OR gate generates the output clock according to the first output signal and the second output signal.

5. The switching circuit according to claim 1, wherein: The detection circuit includes: A NOR gate generates the detection signal according to the third enable signal and the fourth enable signal.

6. The switching circuit according to claim 5, characterized in that: The first judgment circuit comprises: a third AND gate, generating a third output signal according to the detection signal and the first inverted signal; a second OR gate, generating a first control signal according to the third output signal and a first processing signal; and a first multiplexer, providing the third enable signal or the third output signal to the first D-type flip-flop according to the first control signal, The first processing signal is the same as the selection signal.

7. A clock supply circuit, characterized in that: According to a selection signal, an output clock is provided, and the method includes: a first oscillating circuit, generating a first clock signal according to a first enabling signal; a second oscillating circuit, generating a second clock signal according to a second enabling signal; and A switching circuit, which uses the first clock signal or the second clock signal as the output clock according to the selection signal, and includes: a detection circuit, detecting a third enable signal and a fourth enable signal to generate a detection signal; an inverter, inverting the selection signal to generate a first inverted signal; a first judgment circuit, which outputs the first inverted signal when the detection signal is a specific voltage; a first D-type flip-flop, receiving the first inverted signal, and using the first inverted signal as the third enable signal according to the first clock signal; a second judgment circuit, which outputs the selection signal when the detection signal is the specific voltage; a second D-type flip-flop, receiving the selection signal and using the selection signal as the fourth enable signal according to the second clock signal; and a clock gating circuit, which uses the first clock signal or the second clock signal as the output clock according to the third enable signal and the fourth enable signal, The first D-type flip-flop has a first reset terminal, and the first reset terminal receives the first enable signal. The second D-type flip-flop has a second reset terminal, and the second reset terminal receives the second enable signal.

8. The clock supply circuit according to claim 7, wherein: When the first enable signal is the specific voltage, the first oscillating circuit generates the first clock signal. When the first enable signal is not the specific voltage, the first oscillating circuit stops generating the first clock signal.

9. The clock supply circuit according to claim 7, wherein: Also includes: a first logic gate, providing a first reset signal to the first reset terminal according to the first enable signal and a power-on reset signal; A second logic gate provides a second reset signal to the second reset terminal according to the second enable signal and the power-on reset signal.

10. The clock supply circuit according to claim 9, wherein: When the power-on reset signal is not the specific voltage, the first logic gate uses the power-on reset signal as the first reset signal, and the second logic gate uses the power-on reset signal as the second reset signal.

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