Delay-locked loop system and memory

Abstract

The application provides a DLL system and a memory, which adds a clock loss detection circuit to the circuit structure of the original DLL system to detect whether there is a clock loss at the clock feedback node of the DLL loop, the scheme is simple and easy to implement, and when the clock loss detection circuit detects the clock loss, the DLL loop freezes the current delay line length (i.e. temporarily does not adjust the delay line length), and the DCC loop adjusts the duty cycle of the output clock signal of the DLL loop to a set value, until the clock loss detection circuit detects that there is no clock loss, then the DLL loop resumes work and releases the freezing of the delay line length (i.e. unfreezes the delay line length), so as to continue to adjust the delay line length to complete the DLL loop locking, thereby ensuring that the DLL loop can successfully complete the locking when the working condition of the memory is very poor.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory, and in particular to a delay-locked loop system and a memory. BACKGROUND

[0002] A memory chip such as a DRAM (Dynamic Random Access Memory) usually has a delay-locked loop (DLL) inside to synchronize (i.e. align the phase of) the internal and external clock signals.

[0003] However, when the chip of the memory works in a poor condition (e.g. works in an extreme condition such as low voltage, ss process corner where both NMOS and PMOS work slowly, etc.), if the duty cycle of the external clock signal received by the DLL is poor (e.g. deviates from 50%), clock loss may occur in the DLL loop at the initial stage of the locking work of the DLL, thus causing the DLL to fail to align the phase of the internal and external clock signals. SUMMARY

[0004] The present application aims to provide a delay-locked loop system and a memory, which can detect whether clock loss occurs at the clock feedback node of the DLL loop, and ensure that the DLL loop can complete locking smoothly.

[0005] To achieve the above-mentioned purpose, the present application provides a delay-locked loop system, which comprises:

[0006] a DLL loop, which is used to align the phase of the input clock signal received by the DLL loop and the output clock signal output by the DLL loop;

[0007] a DCC loop, which is coupled to the DLL loop and is used to adjust the duty cycle of the output clock signal;

[0008] a clock loss detection circuit, which is coupled to the clock feedback node of the DLL loop and is used to detect whether clock loss occurs at the clock feedback node during the locking process of the DLL loop, and when it is detected that clock loss occurs at the clock feedback node, the DLL loop is caused to freeze the current delay line length thereof, the DCC loop is caused to adjust the duty cycle of the output clock signal to a set value, and after it is detected that clock loss no longer occurs at the clock feedback node, the DLL loop is caused to unfreeze the delay line length thereof to adjust the delay line length and complete locking.

[0009] Optionally, the DLL loop comprises a DLL controller configured to generate a corresponding state signal according to a period of the input clock signal, and the clock loss detection circuit comprises:

[0010] a reset signal generation circuit coupled to the DLL controller and configured to generate a corresponding reset signal according to the state signal;

[0011] a clock edge detection circuit coupled to an output terminal of the reset signal generation circuit and the clock feedback node, and configured to reset according to the reset signal, and detect a number of rising edges or falling edges of a feedback clock signal output by the clock feedback node during a period from the end of the reset to a next active period of the state signal, and output a corresponding indication signal according to a detection result, wherein the indication signal is active when the clock feedback node has a clock loss;

[0012] a thaw signal generation circuit coupled to the DLL controller and the clock edge detection circuit, and configured to generate an active thaw signal to the DLL controller when the indication signal and the state signal are both active, so that the DLL controller releases a freeze on a delay line length of the DLL loop to adjust the delay line length to complete a lock of the DLL loop.

[0013] Optionally, the state signal is active once every N Tck, and each active period has a length of 1 Tck, wherein Tck is a period of the input clock signal, and N is a set value determined by a mode register or a trim setting determined according to a pre-shipment test.

[0014] Optionally, the DLL controller is internally provided with a state machine, and the N value is stored in the state machine, and the state machine outputs the state signal based on the N value and the Tck.

[0015] Optionally, the reset signal is delayed relative to the state signal.

[0016] Optionally, the reset signal generation circuit comprises a delay, an inverter and an NOR logic circuit, an input terminal of the delay and a first input terminal of the NOR logic circuit both receive the state signal, an output terminal of the delay is coupled to an input terminal of the inverter, an output terminal of the inverter is coupled to a second input terminal of the NOR logic circuit, and an output terminal of the NOR logic circuit outputs the reset signal.

[0017] Optionally, the clock edge detection circuit comprises a flip-flop chain formed by cascading a plurality of flip-flops, the clock terminal of each flip-flop is coupled to the clock feedback node, the reset terminal of each flip-flop is coupled to the output terminal of the reset signal generation circuit, the input terminal of the flip-flop in the first stage is coupled to a power voltage, and the output terminal of the flip-flop in the last stage outputs the indication signal; the flip-flop chain is configured to detect whether the number of rising edges or falling edges of the feedback clock signal output by the clock feedback node is greater than or equal to a set threshold during a period from the end of the reset to the next time when the state signal is active, and output the active indication signal if the number of rising edges or falling edges is greater than or equal to the set threshold.

[0018] Optionally, the thaw signal generation circuit comprises an AND logic circuit, the first input terminal of the AND logic circuit receives the state signal, the second input terminal of the AND logic circuit is coupled to the output terminal of the clock edge detection circuit to receive the indication signal, and the AND logic circuit is configured to perform AND logic operation on the state signal and the indication signal to output the active thaw signal if both the state signal and the indication signal are active.

[0019] Optionally, the DLL loop comprises:

[0020] a delay line configured to output the input clock signal after delay, and the length of the delay line determines the delay amount of the DLL loop to the external clock signal;

[0021] a replica delay circuit, the input terminal of which is coupled to the output terminal of the DCC loop, and the output terminal of which is the clock feedback node, and the replica delay circuit is configured to feedback output the clock signal output by the DCC loop;

[0022] a phase detector, the output terminal of which is coupled to the output terminal of the replica delay circuit, and the phase detector is configured to compare the phase between the input clock signal and the feedback clock signal output by the replica delay circuit;

[0023] wherein the DLL controller is further coupled to the phase detector and the delay line, and is configured to adjust the delay amount of the delay line according to the comparison result of the phase detector during the locking process of the DLL loop to complete the locking of the DLL loop.

[0024] Optionally, the DCC loop comprises:

[0025] a DCC adjustment circuit configured to adjust the duty cycle of the output clock signal;

[0026] a DCC detection circuit configured to detect the duty cycle of the clock signal output by the DCC adjustment circuit;

[0027] A DCC controller is coupled to the DCC detection circuit and is configured to control a duty cycle adjustment amount of the DCC adjustment circuit according to a detection result of the DCC detection circuit.

[0028] Optionally, the DLL system further comprises:

[0029] An input buffer is coupled to an output end of the DLL loop and is configured to receive an externally input clock signal and output the clock signal as the input clock signal and provide the input clock signal to the DLL loop.

[0030] A clock tree is coupled to an output end of the DLL loop and is configured to distribute the output clock signal to other circuits inside the DLL system.

[0031] An output buffer is coupled to an output end of the clock tree and is configured to output the clock signal output by the clock tree after delaying the clock signal.

[0032] Based on the same inventive concept, the application further provides a memory comprising the DLL system according to the application.

[0033] Compared with the prior art, the technical scheme of the application adds a clock loss detection circuit to the circuit structure of the original DLL system to detect whether there is a clock loss at the clock feedback node of the DLL loop, and the scheme is simple and easy to implement. When the clock loss detection circuit detects a clock loss, the DLL loop freezes the current delay line length (i.e., temporarily does not adjust the delay line length), and the DCC loop adjusts the duty cycle of the output clock signal of the DLL loop to a set value. Until the clock loss detection circuit detects no clock loss, the DLL loop resumes operation and unfreezes the delay line length, thereby continuing to adjust the delay line length to complete DLL loop locking. Thus, even when the working condition of the memory (or the system chip of the memory) is very poor, the DLL loop can still successfully complete locking. BRIEF DESCRIPTION OF DRAWINGS

[0034] Those skilled in the art will understand that the provided drawings are for the purpose of better illustrating the application and do not constitute any limitation on the scope of the application. Among them:

[0035] Figure 1 is a structural schematic diagram of an original DLL system.

[0036] Figure 2 is a structural schematic diagram of a DLL system according to an embodiment of the application.

[0037] Figure 3is a schematic diagram of an architecture of a replica delay circuit in a delay-locked loop system according to an embodiment of the present invention.

[0038] Figure 4 is a schematic diagram of an architecture of a clock loss detection circuit in a delay-locked loop system according to an embodiment of the present invention.

[0039] Figure 5 is a schematic diagram of an example architecture of a reset signal generation circuit in a clock loss detection circuit in a delay-locked loop system according to an embodiment of the present invention.

[0040] Figure 6 is a schematic diagram of an example architecture of a clock edge detection circuit in a clock loss detection circuit in a delay-locked loop system according to an embodiment of the present invention.

[0041] Figure 7 is a schematic diagram of an example architecture of a phase sampling trigger circuit in a clock loss detection circuit in a delay-locked loop system according to an embodiment of the present invention.

[0042] Figure 8 is a schematic diagram of signal timing in a clock loss detection circuit in a delay-locked loop system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention can be practiced without one or more of the specific details. In other instances, well-known features are not described in order to avoid obscuring the conception of the invention. It will be understood that the invention can be practiced with different arrangements of components, and that the scope of the invention is not limited to the embodiments presented herein. Rather, the present embodiments are presented by way of example only and are not limiting as to the scope of the invention. Throughout this disclosure, like reference numerals in the figures shall refer to similar features unless otherwise described in the text. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, the term "includes" means includes but not limited to, but equivalents.

[0044] A circuit architecture of a delay-locked loop system according to an embodiment of the present invention is shown in FIG. 1. Figure 1As shown, it comprises a clock receiving end 10, an input buffer 11, a DLL loop 12, a DCC (Duty Cycle Corrector) loop 13, a clock tree 14, an output buffer 15 and a clock output end 16. The DLL loop 12 comprises a delay line 121, a phase detector 123, a DLL controller 122 and a replica delay circuit 124. The DCC loop 13 comprises a DCC adjustment circuit 131, a DCC detection circuit 132 and a DCC controller 133.

[0045] The input end of the input buffer 11 is coupled to the clock receiving end 10 to receive an external clock signal Clk and output it as a clock signal Clk_rcv after delay. The input end of the delay line 121 receives the clock signal Clk_rcv and outputs it as a clock signal Clk_out after delay, which is provided to the DCC adjustment circuit 131. The DCC adjustment circuit 131 adjusts the clock signal Clk_out under the control of the DCC controller 133 and outputs it as a clock signal Lf_clk. The DCC detection circuit 132 detects the duty cycle of the clock signal Lf_clk, and the DCC controller 133 generates a corresponding control signal DCC_ctrl (also referred to as a control code Dcc code) to control the duty cycle adjustment amount of the DCC adjustment circuit 131 according to the duty cycle detection result of the DCC detection circuit 132. The replica delay circuit 124 feeds back the clock signal Lf_clk output by the DCC adjustment circuit 131 to the phase detector 123 (the output end of the replica delay circuit 124 is a clock feedback node of the DLL loop). The phase detector 123 compares the phase of the clock signal Clk_rcv output by the input buffer 11 with that of the feedback clock signal Clk_fb output by the replica delay circuit 124, and the DLL controller 122 generates a control signal DLL Ctrl (also referred to as a control code Dll code) to control the delay amount of the delay line 121 according to the phase comparison result of the phase detector 123. When the phase detector 123 detects that the phases of Clk_rcv and Clk_fb are the same and the duty cycle of Clk_fb reaches a set value (50%), the phase of the external clock signal Clk input at the clock input end 10 is aligned with that of the internal clock signal DQS output at the clock output end 16, and the duty cycle of the internal clock signal DQS reaches a set value (50%), at which time the DLL loop 12 is locked.

[0046] When the duty cycle of the external clock signal Clk input at the clock input end 10 deviates from 50% due to extreme working conditions or the like (which can also be referred to as poor chip working conditions), the above-mentioned scheme has the following problems:

[0047] 1、In the initial stage of DLL loop 12 locking, due to the long transmission path of the clock signal in DLL loop 12, the problem of duty cycle loss is prone to occur after the transmission through DLL loop 12. If the DCC adjustment circuit 131 has not started to adjust the duty cycle or the adjustment amount of the duty cycle is small, the duty cycle of the clock signal Lf_clk output by the DCC adjustment circuit 131 will deviate from 50%. For example, the duty of the external clock signal Clk input at the clock input end 10 is 45%, and the duty of the clock signal Lf_clk output by the DCC adjustment circuit 131 is 40%. When the clock signal Lf_clk output by the DCC adjustment circuit 131 is further transmitted to the replica delay circuit 124 and output as the feedback clock signal Clk_fb, due to the longer clock transmission path, the duty loss is more, and thus the feedback clock signal Clk_fb output by the replica delay circuit 124 can be a high level or a low level for a period of time, that is, the feedback clock signal Clk_fb output by the replica delay circuit 124 has the problem of clock loss.

[0048] 2、When the feedback clock signal Clk_fb output by the replica delay circuit 124 has the problem of clock loss, the phase detector 123 will still compare the phase of the clock signal Clk_rcv output by the input buffer 11 and the feedback clock signal Clk_fb output by the replica delay circuit 124 and output the comparison result "0" or "1". Since the feedback clock signal Clk_fb is in the state of lost clock (i.e. a high level or a low level for a period of time) at this time, the phase comparison result PD of the phase detector 123 cannot accurately reflect the phase difference between the internal and external clock signals. If the DLL controller adjusts the length of the delay line 121 (i.e. the size of the delay amount) according to the false phase comparison result PD output by the phase detector 123, the DLL loop 12 will not be able to align the phases of the internal and external clock signals, that is, the DLL loop 12 cannot complete locking at this time.

[0049] To solve the above problems, the application provides a delay-locked loop system and a memory, which adds a clock loss detection circuit (feedback monitor) on the basis of the existing delay-locked loop system, so as to detect whether there is a clock loss at the clock feedback node of the DLL loop during the locking process of the DLL loop through the clock loss detection circuit, and if the clock loss is detected, the current delay line length of the DLL loop (i.e. the current delay amount of the DLL loop) is frozen, and at the same time, the DCC loop continues to work, and the duty cycle of the output clock signal output by the DCC loop is adjusted to a set value (for example, 50%), until the clock loss detection circuit re-detects that the clock feedback node of the DLL loop no longer loses the clock, and then the DLL loop is unfreezed (i.e. unfreezes the delay line length), at which time the DLL loop can complete the locking by continuing to adjust the delay line length.

[0050] The technical solutions of the application are further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the application will be clearer according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the application.

[0051] Please refer to Figure 2 An embodiment of the application provides a delay-locked loop system, which at least comprises a DLL loop 22, a DCC loop 23 and a clock loss detection circuit 27.

[0052] The DLL loop 22 is used to align the phase of the input clock signal Clk_rcv and the output clock signal Clk_out output by the DLL loop 22, so as to realize the synchronization of the external clock signal Clk received by the clock receiving end 20 and the internal clock signal DQS output by the clock output end 26.

[0053] The DCC loop 23 is coupled to the output end of the DLL loop 22, and is used to adjust the duty cycle of the output clock signal Clk_out output by the DLL loop 22, so as to output a clock signal Lf_clk with a duty cycle reaching a set value (for example, reaching 50%).

[0054] Clock loss detection circuit 27 is coupled to the clock feedback node of DLL loop 22 and is configured to detect whether there is a clock loss at the clock feedback node of DLL loop 22 (i.e., to detect whether there is a clock loss at Clk_fb) during the locking process of DLL loop 22. When a clock loss at the clock feedback node of DLL loop 22 is detected, clock loss detection circuit 27 generates a corresponding freeze signal (e.g., invalid LCYC1D_DLL) to freeze the current length of delay line 221 of DLL loop 22, and to cause DCC loop 22 to output clock signal Lf_clk after adjusting the duty cycle of output clock signal clk_out received by DCC loop 22 to a set value (i.e., the duty cycle of clock signal Lf_clk output by DCC loop 22 reaches the set value). When the clock loss at the clock feedback node of DLL loop 22 is no longer detected, clock loss detection circuit 27 causes DLL loop 22 to unfreeze the length of delay line 221 so that the length of delay line 221 can be adjusted until DLL loop 22 is locked.

[0055] Please refer to Figure 2 Optionally, DLL loop 22 includes a DLL controller 222 configured to generate a corresponding state signal LCYC0D_PRE according to the period of input clock signal Clk_rcv (which is also the period of external clock signal Clk). As an example, state signal LCYC0D_PRE is valid once every N Tcks, and the length of each valid period is 1 Tck. In this case, the period of state signal LCYC0D_PRE is N*Tck, where Tck is the period of input clock signal Clk_rcv, and N is a pre-set value that is an integer greater than 1. In an embodiment, the value of N is determined according to the MRS (Model Register Set) of the delay-locked loop system or a trim set determined by pre-factory testing. In an embodiment, the trim set is set by programming an efuse (electronic fuse) before factory. In an embodiment, a state machine (not shown) is provided inside DLL controller, and the value of N is stored in the state machine. The state machine outputs state signal LCYC0D_PRE based on the value of N and Tck. In another embodiment, the state machine not only stores the value of N, but also generates and stores a control code DLL code for adjusting the length of delay line of DLL loop 22 during the locking process of DLL loop 22.

[0056] Please refer to Figure 2 and Figure 4 Optionally, clock loss detection circuit 27 includes a reset signal generation circuit 271, a clock edge detection circuit 272, and an unfreeze signal generation circuit 273.

[0057] The reset signal generating circuit 271 is coupled to the DLL controller 222 and is configured to generate a corresponding reset signal RST according to the state signal LCYC0D_PRE outputted by the DLL controller 222. In one example, the reset signal generating circuit 271 generates the reset signal RST by performing a corresponding logical operation on the state signal LCYC0D_PRE. Alternatively, the reset signal RST is delayed relative to the state signal LCYC0D_PRE. For example, the rising edge of the reset signal RST is aligned with the falling edge of the state signal LCYC0D_PRE.

[0058] The clock edge detecting circuit 272 is coupled to the output of the reset signal generating circuit 271 and the clock feedback node of the DLL loop 22 (i.e. the output of the replica delay circuit 224), and is configured to reset according to the reset signal RST to clear the number of edges it previously detected, and, after the reset ends, to detect the number of rising edges or falling edges of the feedback clock signal Clk_fb outputted by the clock feedback node of the DLL loop 22 during the period between the falling edge of the reset signal RST and the next rising edge of the state signal LCYC0D_PRE (i.e. the period between the falling edge of the reset signal RST and the next rising edge of the state signal LCYC0D_PRE in the state signal LCYC0D_PRE), and to output a corresponding indication signal LCYC_gating according to the detection result, wherein the indication signal LCYC_gating is active (e.g. high) when there is no missing clock in the clock signal Clk_fb outputted by the clock feedback node of the DLL loop 22. Figure 8

[0059] The thaw signal generating circuit 273 is coupled to the DLL controller 222 and the clock edge detecting circuit 272, and is configured to generate an active thaw signal LCYC1D_DLL and output it to the DLL controller 222 when both the indication signal LCYC_gating and the state signal LCYC0D_PRE are active, so as to make the DLL controller 222 release the freeze on the length of the delay line according to the active thaw signal LCYC1D_DLL, thereby continuing to adjust the length of the delay line 221 and successfully complete the locking of the DLL loop 22. As an example, after the active thaw signal LCYC1D_DLL is transmitted to the DLL controller 222, the state machine (not shown) in the DLL controller 222 continues to sample the phase comparison result PD outputted by the phase detector 223 in the DLL loop 22 and update the control code DLL code therein, so as to adjust the length of the delay line 221. In one embodiment, the thaw signal LCYC1D_DLL is active when the DLL controller 222 is sampling the phase comparison result PD outputted by the phase detector 223.

[0060] ​It should be understood that the reset signal generating circuit 271, the clock edge detecting circuit 272 and the unfreezing signal generating circuit 273 can be implemented by any suitable circuit design capable of achieving their functions, and the present application does not make specific limitation thereon.

[0061] As an example, referring to Figure 5 , the reset signal generating circuit 271 includes a delay device delay, an inverter INV and a NOR logic circuit NOR. The input terminal of the delay device delay and the first input terminal of the NOR logic circuit NOR are both coupled to the corresponding terminals of the DLL controller 222 to receive the state signal LCYC0D_PRE output by the DLL controller 222. The output terminal of the delay device delay is coupled to the input terminal of the inverter INV, the output terminal of the inverter INV is coupled to the second input terminal of the NOR logic circuit NOR, and the output terminal of the NOR logic circuit NOR outputs the reset signal RST. The delay device delay can be implemented by any suitable circuit design such as an RC delay circuit, and the NOR logic circuit NOR can be implemented by any suitable circuit design such as a NOR gate.

[0062] As an example, referring to Figure 6 , the clock edge detecting circuit includes a trigger chain formed by cascading m trigger devices DFF1-DFFm. The clock terminal (i.e. Clk terminal) of each trigger device DFF1-DFFm is coupled to the clock feedback node (e.g. the output terminal of the replica delay circuit 224) of the DLL loop 22 to receive the feedback clock signal Clk_fb, the reset terminal Reset of each trigger device DFF1-DFFm is coupled to the output terminal of the reset signal generating circuit 271 to receive the reset signal RST (e.g. active high), the input terminal D of the first trigger device DFF1 is coupled to a power supply voltage (not shown), and the output terminal Q of the last trigger device DFFm outputs the indication signal LCYC_gating. The trigger chain is used to detect whether the number of rising edges or falling edges of the feedback clock signal Clk_fb is greater than or equal to a set threshold value k during the period from the end of the reset to the next active (e.g. high level) of the state signal LCYC0D_PRE (i.e. the period between the falling edge of the reset signal RST in Figure 8 and the next rising edge of the state signal LCYC0D_PRE), and outputs the active indication signal LCYC_gating (e.g. high level) to represent that there is no clock loss of the clock signal Clk_fb if yes.

[0063] In an embodiment, the flip-flops DFF1-DFFm are D-type flip-flops, the state signal LCYC0D_PRE is active once every N Tcks, and the length of each active period is 1 Tck, where Tck is the period of the input clock signal Clk_rcv. In this case, k = m and m < N-1 must be satisfied. In this case, the actual detection period is (N-1) * Tck, i.e., the time between two high levels of the state signal LCYC0D_PRE.

[0064] When the reset signal RST is active (e.g., high), each flip-flop DFF1-DFFm is reset, and the output of each flip-flop at the output terminal Q is cleared. After the reset signal RST becomes inactive (i.e., the reset ends) until the next time the state signal LCYC0D_PRE becomes active, if the number of rising edges (or falling edges) of the clock signal Clk_fb output by the replica delay circuit 224 is detected to be greater than or equal to a set threshold k (e.g., k is equal to the number m of flip-flops DFF1-DFFm), the indication signal LCYC_gating is set to be active (e.g., “1”), and if the number of rising edges (or falling edges) of Clk_fb is detected to be less than the set threshold k, the indication signal LCYC_gating is set to be inactive (e.g., “0”), until the next time the reset signal RST is active (e.g., high).

[0065] It should be understood that the number m of flip-flops in the flip-flop chain can be set by a user or a circuit designer, and the present application does not make a specific limitation thereon. In addition, Figure 6 The flip-flops in the flip-flop chain are shown by way of example using D-type flip-flops, but in other embodiments of the present application, any other suitable type of flip-flop can be used to construct the flip-flop chain. Alternatively, in other embodiments of the present application, any other suitable signal edge detection circuit and counting circuit can be used to construct the clock edge detection circuit 272, and the present application does not make a specific limitation thereon.

[0066] As an example, please refer to Figure 7The thawing signal generation circuit 273 includes an AND logic circuit, a first input terminal of the AND logic circuit being coupled to a corresponding terminal of the DLL controller 222 to receive the state signal LCYC0D_PRE output by the DLL controller 222, and a second input terminal of the AND logic circuit being coupled to an output terminal of the clock edge detection circuit 272 (i.e. an output terminal Q of the last stage flip-flop DFFm) to receive the indication signal LCYC_gating. The AND logic circuit is configured to perform an AND logic operation on the state signal LCYC0D_PRE and the indication signal LCYC_gating, and output a valid thawing signal LCYC1D_DLL (e.g. a high level valid) when both the indication signal LCYC_gating and the state signal LCYC0D_PRE are valid. The AND logic circuit can be implemented by using any suitable circuit design such as an AND gate, and the present application does not make any specific limitation in this regard.

[0067] Please refer to Figures 2 to 8 The thawing signal LCYC1D_DLL, the reset signal RST and the indication signal LCYC_gating are all invalid in the initial state or default state, and the working timing of the clock loss detection circuit 27 in the embodiment is as follows:

[0068] Firstly, the state machine of the DLL controller 222 outputs the state signal LCYC0D_PRE, and the period of the state signal LCYC0D_PRE is N*Tck.

[0069] When the state signal LCYC0D_PRE changes from a low level to a high level in the time period t1-t2, the reset signal generation circuit 271 in the clock loss detection circuit 27 generates the reset signal RST with a rising edge that is delayed relative to the rising edge of the state signal LCYC0D_PRE RST. During the high valid stage of the reset signal RST, the clock edge detection circuit 272 in the clock loss detection circuit 27 is reset, and after the reset is completed, the clock edge detection circuit 272 is in a reset state until t2 (i.e. the time point when the state signal LCYC0D_PRE changes from a high level to a low level). Figure 8The clock edge detection circuit 272 detects the number of rising edges (or falling edges) of the feedback clock signal Clk_fb at the clock feedback node of the DLL loop during the period from the first falling edge of the reset signal RST to the second rising edge of the state signal LCYC0D_PRE, and determines that there is a clock loss if the number of rising edges (or falling edges) of the feedback clock signal Clk_fb is less than m. In this case, the indication signal LCYC_gating remains at the low level to indicate that the feedback clock signal Clk_fb is lost, so that the unfreezing signal LCYC1D_DLL output by the unfreezing signal generation circuit 273 is still at the low level and invalid, the state machine in the DLL controller 222 freezes the current length of the delay line 221 (i.e. the control code DLL code is no longer updated), and the DCC loop 23 adjusts the duty of the output clock signal Clk_out of the DLL loop 22 to adjust the duty of the clock signal Lf_clk output by the DCC loop 23 to a set value (e.g. 50%).

[0070] At time t2, the state signal LCYC0D_PRE is high again.

[0071] During the period from time t2 to time t3, the reset signal RST is high again, and the clock edge detection circuit 272 in the clock loss detection circuit 27 is reset again during the high active stage of the reset signal RST, so that the clock edge detection circuit 272 re-counts the edges of the clock signal Clk_fb. After the reset ends, the clock edge detection circuit 272 detects the number of rising edges (or falling edges) of the feedback clock signal Clk_fb at the clock feedback node of the DLL loop during the period from time t3 (i.e. the second falling edge of the reset signal RST to the third rising edge of the state signal LCYC0D_PRE), and determines that there is no clock loss if the number of rising edges (or falling edges) of the feedback clock signal Clk_fb is greater than or equal to m. In this case, the indication signal LCYC_gating is set to the high level to indicate that the feedback clock signal Clk_fb is no longer lost.

[0072] At the moment t3, the state signal LCYC0D_PRE becomes high valid, and at the same time, the indication signal LCYC_gating is high valid, the unfreezing signal LCYC1D_DLL output by the unfreezing signal generation circuit 273 becomes high valid, the DLL controller 222 resumes operation, and the state machine in the DLL controller 222 unfreezes the length of the delay line 221 (i.e., starts to continue updating the control code DLL code), so as to continue adjusting the length of the delay line 221, and at the same time, the DCC loop 23 adjusts the duty of the output clock signal Clk_out of the DLL loop 22, and finally completes the locking of the DLL loop 22, that is, the DLL loop 22 can finally make the clock signal Clk received by the clock receiving end 10 and the signal DQS output by the clock output end 26 phase-aligned, so as to realize the synchronization of the internal and external clock signals of the delay-locked loop system. In addition, due to the action of the DCC loop 23, the duty of the internal clock signal DQS output by the clock output end 26 is a set value (for example, 50%).

[0073] In an example, the falling edge of the unfreezing signal LCYC1D_DLL can be triggered by the falling edge of the state signal LCYC0D_PRE.

[0074] Optionally, referring to Figure 2 The delay-locked loop system of the embodiment further includes a clock receiving end (Clk pad) 20, an input buffer (Receiver, RCV) 21, a clock tree (clk tree) 24, an output buffer (OCD) 25, and a clock output end (DQS pad) 26.

[0075] The clock receiving end 20 is an external pin of a chip of a memory such as a DRAM, which receives an external input external clock signal Clk (i.e., a clock signal outside the delay-locked loop system, which can be from a host or a controller outside the memory chip). The output end of the input buffer 21 is coupled to the input end of the DLL loop 22, and the input buffer 21 delays and outputs the clock signal Clk received by the clock receiving end 20 as an input clock signal Clk_rcv to provide to the DLL loop 22.

[0076] The input end of the clock tree 24 is coupled to the output end of the DCC loop 23, and the clock tree 24 is configured to distribute the clock signal Lf_clk output by the DCC loop 23 to other circuits inside the delay-locked loop system.

[0077] The input end of the output buffer 25 is coupled to the output end of the clock tree 24, and the output buffer 25 is configured to delay and output the clock signal output by the clock tree 24 as an internal clock signal DQS and provide to the clock output end 26.

[0078] It should be understood that the input buffer 21, the DLL loop 22, the DCC loop 23, the clock tree 24 and the output buffer 25 in the delay-locked loop system of the present embodiment can be implemented by any suitable conventional design in the art. In addition, in the present embodiment, the clock loss detection circuit 27 is considered as a circuit external to the DLL loop 22 to indicate that the clock loss detection circuit 27 adds little modification to the circuits internal to the DLL loop 22, but the clock loss detection circuit 27 can also be considered as a circuit internal to the DLL loop 22, thereby obtaining an improved DLL loop 22 different from the existing DLL loop 22.

[0079] Please continue to refer to Figure 2 Optionally, the DLL loop 22 further includes a delay line 221, a phase detector 223 and a replica delay circuit 224 in addition to the DLL controller 222.

[0080] Please continue to refer to Figure 2 The input end of the delay line 221 is the input end of the DLL loop 22 (or the clock input node of the DLL loop 22) and is coupled to the output end of the input buffer 21, and the output end of the delay line 221 is the output end of the DLL loop 22 (or the clock output node of the DLL loop 22) and is coupled to the input end of the DCC loop 23. The length of the delay line 221 can be adjusted under the control of the DLL controller 222 to complete the locking of the DLL loop 22. Thus, the delay line 221 receives the input clock signal Clk_rcv and delays the input clock signal Clk_rcv by a corresponding delay amount to output the input clock signal Clk_rcv as an output clock signal Clk_out to the input end of the DCC loop 23.

[0081] The replica delay circuit 224 is a replica circuit corresponding to the input buffer 21, the clock tree 24 and the output buffer 25, which can replicate (or simulate) the delay amount on the path from the input buffer 21 to the output buffer 25 except for the delay amount of the delay line 221. Please refer to Figure 3, the replica delay circuit 224 can include an output buffer replica circuit 224a, a clock tree replica circuit 224b, and an input buffer replica circuit 224c, wherein the input end of the output buffer replica circuit 224a is coupled to the output end of the DCC loop 23 (or the clock output node of the DCC loop 23), and is configured to output the output clock signal Clk_out output by the delay line 221 after delaying the output clock signal Clk_out by the delay amount of the output buffer 25, the input end of the clock tree replica circuit 224b is coupled to the output end of the input buffer replica circuit 224c, and is configured to output the clock signal output by the output buffer replica circuit 224a after delaying the clock signal by the delay amount of the clock tree 24, the input end of the input buffer replica circuit 224c is coupled to the output end of the clock tree replica circuit 224b, the output end of the input buffer replica circuit 224c is coupled to an input end of the phase detector 223 and an input end of the clock loss detection circuit 27 as the clock feedback node of the DLL loop 22, and the input buffer replica circuit 224c is configured to output the clock signal output by the clock tree replica circuit 224b after delaying the clock signal by the delay amount of the input buffer 21, and the output clock signal of the input buffer replica circuit 224c is the feedback clock signal Clk_fb output by the replica delay circuit 224, and is provided to the clock loss detection circuit 27 and the phase detector 223.

[0082] Please refer to Figure 2 The phase detector 223 is configured to compare the phase between the input clock signal Clk_rcv output by the input buffer 21 and the feedback clock signal Clk_fb output by the replica delay circuit 224.

[0083] Please refer to Figure 2 The DLL controller 222 is not only coupled to the output end of the phase detector 223 and the control end of the delay line 221, but also coupled to the clock loss detection circuit 27. The DLL controller 222 is configured to freeze the current delay line length (i.e., freeze the current DLL control code DLL code, so as to temporarily not adjust the length of the delay line 221, or in other words, temporarily not adjust the delay amount of the delay line 221) when the clock loss detection circuit 27 detects that the clock feedback node of the DLL loop 22 has clock loss (i.e., detects that the feedback clock signal Clk_fb has clock loss), and to resume (or unfreeze) the adjustment of the delay line length after the clock loss detection circuit 27 re-detects that the clock feedback node of the DLL loop 22 no longer has clock loss (i.e., detects that the feedback clock signal Clk_fb no longer has clock loss), so as to continue adjusting the length (i.e., the delay amount) of the delay line 221 according to the phase comparison result PD of the phase detector 223 until the DLL loop 22 is locked.

[0084] Please continue to referFigure 2 Optionally, the DCC loop 23 comprises a DCC adjusting circuit 231, a DCC controller 233 and a DCC detecting circuit 232. The input end of the DCC detecting circuit 232 is coupled to the output end of the DCC adjusting circuit 231, the output end of the DCC detecting circuit 232 is coupled to the input end of the DCC controller 233, the output end of the DCC controller 233 is coupled to the control end of the DCC adjusting circuit 231, the input end of the DCC adjusting circuit 231 is coupled to the output end of the delay line 221, and the output end of the DCC adjusting circuit 231 is coupled to the input end of the clock tree 24. The DCC detecting circuit 232 is configured to detect the duty cycle of the clock signal Lf_clk output by the DCC adjusting circuit 231, the DCC controller 233 is configured to control the duty cycle adjustment amount of the DCC adjusting circuit 231 according to the duty cycle detection result of the DCC detecting circuit 232, and the DCC adjusting circuit 231 outputs the clock signal Lf_clk with a duty cycle reaching a set value (for example, 50%) after adjusting the duty cycle of the output clock signal Clk_out output by the delay line 221 under the control of the DCC controller 233, for example, the duty cycle of the clock signal Lf_clk output by the DCC adjusting circuit 231 is adjusted to 50%.

[0085] In summary, compared with the original delay-locked loop system Figure 1 As shown in the circuit structure of the original delay-locked loop system, only a clock loss detection circuit is added, which is used to detect whether there is clock loss at the clock feedback node of the DLL loop. The scheme is simple and easy to implement. When the clock loss detection circuit detects clock loss, the DLL loop freezes the current delay line length (i.e. temporarily does not adjust the delay line length), and the DCC loop adjusts the duty cycle of the output clock signal of the DLL loop to a set value. Until the clock loss detection circuit detects no clock loss, the DLL loop resumes work to adjust the delay line length until the DLL loop is locked. Thus, even when the working condition of the memory (or the system chip of the memory) is very poor, the DLL loop can also complete locking smoothly.

[0086] The delay-locked loop system can be applied to any memory that needs to set a delay-locked loop. Based on this, please refer to Figures 2 to 8 The embodiment of the application further provides a memory comprising the delay-locked loop system.

[0087] Since the memory adopts the delay-locked loop system, even when the working condition is very poor, the DLL loop can also complete locking smoothly.

[0088] Optionally, the memory is a DRAM memory.

[0089] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any modification, change or improvement made by those skilled in the art based on the above disclosure shall fall within the scope of the technical scheme of the present application.

Claims

1. A delay-locked-loop system, characterized by, The application relates to a clock signal outputting circuit, comprising: a DLL loop for phase aligning an input clock signal received by the DLL loop with an output clock signal output by the DLL loop, the DLL loop comprising a DLL controller for generating a corresponding state signal according to a period of the input clock signal; a DCC loop coupled to the DLL loop and for adjusting a duty cycle of the output clock signal; a clock loss detection circuit coupled to a clock feedback node of the DLL loop and comprising: a reset signal generation circuit coupled to the DLL controller and for generating a corresponding reset signal according to the state signal; a clock edge detection circuit coupled to an output terminal of the reset signal generation circuit and the clock feedback node and for resetting according to the reset signal, and detecting a number of rising edges or falling edges of a feedback clock signal output by the clock feedback node during a period from the end of the resetting to the next validity of the state signal, and outputting a corresponding indication signal according to the detection result, wherein the indication signal is valid when the clock feedback node has no clock loss; a thaw signal generation circuit coupled to the DLL controller and the clock edge detection circuit and for, during DLL loop locking, freezing the current delay line length of the DLL loop when the indication signal indicates that the clock feedback node has clock loss, and adjusting the duty cycle of the output clock signal to a set value by the DCC loop, and generating a valid thaw signal to the DLL controller when both the indication signal and the state signal are valid, so as to unfreeze the delay line length of the DLL loop to adjust the delay line length and complete the locking of the DLL loop.

2. The delay-locked-loop system of claim 1, wherein, The state signal is valid once every N Tck, and the valid period is 1 Tck, wherein Tck is the period of the input clock signal, and N is a set value determined by a corresponding mode register or a trimming setting determined according to pre-shipment test.

3. The delay-locked-loop system of claim 2, wherein the delay line is a ring delay line. The DLL controller is internally provided with a state machine, the N value is stored into the state machine, and the state machine outputs the state signal based on the N value and the Tck.

4. The delay-locked-loop system of claim 1, wherein, The reset signal is delayed relative to the state signal.

5. The delay-locked-loop system of any one of claims 1-4, wherein, The reset signal generation circuit comprises a delay device, an inverter and an NOR logic circuit; the input terminal of the delay device and the first input terminal of the NOR logic circuit both receive the state signal; the output terminal of the delay device is coupled to the input terminal of the inverter, the output terminal of the inverter is coupled to the second input terminal of the NOR logic circuit, and the output terminal of the NOR logic circuit outputs the reset signal.

6. The delay-locked-loop system of any one of claims 1-4, wherein, The clock edge detection circuit comprises a flip-flop chain formed by cascading a plurality of flip-flops, the clock terminal of each flip-flop is coupled to the clock feedback node, the reset terminal of each flip-flop is coupled to the output terminal of the reset signal generation circuit, the input terminal of the flip-flop in the first stage is coupled to a power voltage, and the output terminal of the flip-flop in the last stage outputs the indication signal; the flip-flop chain is used to detect whether the number of rising edges or falling edges of the feedback clock signal output by the clock feedback node is greater than or equal to a set threshold during the period from the end of the reset to the next time when the state signal is active, and if yes, the active indication signal is output.

7. The delay-locked-loop system of any one of claims 1-4, wherein, The thawing signal generation circuit comprises an AND logic circuit, the first input terminal of the AND logic circuit receives the state signal, the second input terminal of the AND logic circuit is coupled to the output terminal of the clock edge detection circuit to receive the indication signal, and the AND logic circuit is used to perform AND logic operation on the state signal and the indication signal to output an active thawing signal when both the indication signal and the state signal are active.

8. The delay-locked-loop system of any one of claims 1-4, wherein, The DLL loop further comprises: a delay line for delaying and outputting the input clock signal, and the length of the delay line determines the delay amount of the DLL loop to the input clock signal; a replica delay circuit, the input terminal of which is coupled to the output terminal of the DCC loop, and the output terminal of which is the clock feedback node, and the replica delay circuit is used to feedback and output the clock signal output by the DCC loop; a phase detector, which is coupled to the output terminal of the replica delay circuit and is used to compare the phase between the input clock signal and the feedback clock signal output by the replica delay circuit; wherein the DLL controller is further coupled to the phase detector and the delay line, and is used to adjust the delay amount of the delay line according to the comparison result of the phase detector during the locking process of the DLL loop to complete the locking of the DLL loop.

9. The delay-locked-loop system of claim 1, wherein, The DCC loop comprises: a DCC adjustment circuit for adjusting the duty cycle of the output clock signal; a DCC detection circuit for detecting the duty cycle of the clock signal output by the DCC adjustment circuit; a DCC controller, which is coupled to the DCC detection circuit and is used to control the duty cycle adjustment amount of the DCC adjustment circuit according to the detection result of the DCC detection circuit.

10. The delay-locked loop system of claim 1, wherein, Further comprising: an input buffer, the output terminal of which is coupled to the DLL loop, and which is used to receive the externally input clock signal and output it as the input clock signal and provide it to the DLL loop; a clock tree, the input terminal of which is coupled to the output terminal of the DLL loop, and which is used to distribute the output clock signal to other circuits inside the delay-locked loop system; an output buffer, the input terminal of which is coupled to the output terminal of the clock tree, and which is used to delay and output the clock signal output by the clock tree.

11. A memory, comprising: The delay-locked loop system comprises any one of claims 1-10.

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