Test system and equipment

Abstract

The invention discloses a test system and equipment, and relates to the field of communication module testing, and the test system comprises a first verification module which is used for testing a JTAG communication protocol; the second verification module is used for testing an I2C communication protocol; the third verification module is used for testing an SPI communication protocol; the fourth verification module is used for testing a UART communication protocol; the multiplexing interface module is respectively connected with the first verification module, the second verification module, the third verification module and the fourth verification module; and the power supply module is respectively connected with the first verification module, the second verification module and the third verification module. By setting the multiplex interface module, the first verification module, the second verification module, the third verification module and the fourth verification module share a plurality of ports of the multiplex interface module, so that the test of JTAG, I2C, SPI and UART communication protocols can be realized only by using one test system, and the test efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of communication module testing, and particularly to a testing system and device. Background Art

[0002] In the prior art, a testing system often only targets a single communication protocol. Therefore, when comprehensively testing I2C, SPI, UART, and JTAG communication protocols, multiple independent testing systems and devices are required to complete the testing, which increases the testing cost and reduces the testing efficiency. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems existing in the prior art. For this purpose, this application provides a testing system and device that can simultaneously support the testing of I2C, SPI, UART, and JTAG communication protocols.

[0004] The testing system according to the first aspect embodiment of this application includes: a first verification module for testing the JTAG communication protocol; a second verification module for testing the I2C communication protocol; a third verification module for testing the SPI communication protocol; a fourth verification module for testing the UART communication protocol; a multiplexing interface module respectively connected to the first verification module, the second verification module, the third verification module, and the fourth verification module, wherein the first verification module, the second verification module, the third verification module, and the fourth verification module share multiple ports of the multiplexing interface module; and a power supply module respectively connected to the first verification module, the second verification module, and the third verification module, and the power supply module is used to supply power to the first verification module, the second verification module, and the third verification module.

[0005] The voltage regulation method of the voltage converter according to the embodiment of this application has at least the following beneficial effects: By setting the power supply module, it is convenient to supply power to the first verification module, the second verification module, and the third verification module, ensuring the stability of the modules. And by setting the multiplexing interface module, the first verification module, the second verification module, the third verification module, and the fourth verification module are made compatible. When communication protocol testing is required, switch to the corresponding verification module, so that the testing of I2C, SPI, UART, and JTAG communication protocols can be achieved with only one system, thereby reducing the testing cost and improving the testing efficiency.

[0006] According to some embodiments of the present application, the power supply module includes an external power supply and an internal power supply. The external power supply is respectively connected to the first verification module, the second verification module, and the third verification module. The internal power supply includes a linear step-down chip, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. One end of the first capacitor is respectively connected to the external power supply and the input end of the linear step-down chip, and the other end is connected to the ground end of the linear step-down chip. One end of the second capacitor is connected to the input end of the linear step-down chip, and the other end is connected to the ground end of the linear step-down chip. One end of the third capacitor is connected to the output end of the linear step-down chip, and the other end is connected to the ground end of the linear step-down chip. One end of the fourth capacitor is respectively connected to the output end of the linear step-down chip, the first verification module, the second verification module, and the third verification module, and the other end is connected to the ground end of the linear step-down chip.

[0007] According to some embodiments of the present application, the power supply module further includes a first row of pins. The fourth capacitor is respectively connected to the first verification module, the second verification module, and the third verification module through the first row of pins. The first input end of the first row of pins is connected to the output end of the linear step-down chip, the second input end of the first row of pins is connected to the external power supply, and the output end of the first row of pins is connected to the first verification module, the second verification module, and the third verification module. The output end of the first row of pins includes a first output end and a second output end. The first output end is used to output the voltage of the internal power supply, and the second output end is used to output the voltage of the external power supply.

[0008] According to some embodiments of the present application, the first verification module includes a complex programmable logic device and a DIP switch assembly. The multiplexing interface module is connected to the first group of pins of the complex programmable logic device, and the DIP switch assembly is connected to the second group of pins of the complex programmable logic device. The DIP switch assembly is used to control the potential change of the second group of pins.

[0009] According to some embodiments of the present application, the DIP switch assembly includes a first DIP switch and a second DIP switch. The second group of pins is respectively connected to the first DIP switch and the second DIP switch. The first DIP switch is used to access the high level of the second group of pins, and the second DIP switch is used to access the low level of the second group of pins.

[0010] According to some embodiments of the present application, the second verification module includes a first storage chip, a first resistor, a second resistor, a third resistor, and a fifth capacitor. One end of the first resistor is grounded, and the other end is connected to the first address terminal of the first storage chip. One end of the second resistor is connected to the output terminal of the first row of pins, and the other end is connected to the clock terminal of the first storage chip. One end of the third resistor is connected to the output terminal of the first row of pins, and the other end is connected to the data terminal of the first storage chip. The power supply terminal of the first storage chip is connected to the output terminal of the first row of pins and is grounded through the fifth capacitor. The multiplexing interface module is respectively connected to the clock terminal and the data terminal of the first storage chip.

[0011] According to some embodiments of the present application, the third verification module includes a second storage chip, a fourth resistor, a fifth resistor, a sixth resistor, and a sixth capacitor. One end of the fourth resistor is connected to the output terminal of the linear buck chip, and the other end is connected to the first input terminal of the second storage chip. One end of the fifth resistor is connected to the output terminal of the linear buck chip, and the other end is connected to the second input terminal of the second storage chip. One end of the sixth resistor is grounded through the sixth capacitor and is connected to the output terminal of the linear buck chip, and the other end is connected to the output terminal of the second storage chip. The read / write terminal of the second storage chip is connected to the output terminal of the linear buck chip, and the read / write terminal is active low. The multiplexing interface module is respectively connected to the first input terminal, the second input terminal, the output terminal, and the clock terminal of the second storage chip.

[0012] According to some embodiments of the present application, the fourth verification module includes a second row of pins. The output terminal and the input terminal of the second row of pins are both connected to the multiplexing interface module, and the input terminal of the second row of pins is short-circuited to the output terminal of the second row of pins.

[0013] According to some embodiments of the present application, the second verification module further includes a seventh resistor and an eighth resistor. One end of the seventh resistor is grounded, and the other end is connected to the second address terminal of the first storage chip. One end of the eighth resistor is grounded, and the other end is connected to the third address terminal of the first storage chip. The first resistor, the seventh resistor, and the eighth resistor have the same resistance value.

[0014] The test device according to the second aspect embodiment of the present application includes:

[0015] The test system according to the first aspect embodiment of the present application.

[0016] The additional aspects and advantages of the present application will be partially given in the following description, partially become apparent from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where:

[0018] Figure 1 Schematic diagram of the frame structure of the test system according to an embodiment of the present application;

[0019] Figure 2 Schematic diagram of the circuit structure of the internal power supply according to an embodiment of the present application;

[0020] Figure 3 Schematic diagram of the multiplexing of connector pins according to an embodiment of the present application;

[0021] Figure 4 Schematic diagram of the circuit structure of the second verification module according to an embodiment of the present application;

[0022] Figure 5 Schematic diagram of the circuit structure of the third verification module according to an embodiment of the present application;

[0023] Figure 6 Schematic diagram of the circuit structure of the fourth verification module according to an embodiment of the present application;

[0024] Figure 7 Schematic diagram of the structure of the complex programmable logic device according to an embodiment of the present application;

[0025] Figure 8 Schematic diagram of the circuit structure of the DIP switch assembly according to an embodiment of the present application. Detailed implementation manners

[0026] The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation to the present application.

[0027] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as up, down, front, back, left, right, etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and thus should not be construed as a limitation to the present application.

[0028] In the description of the present application, the meaning of "a number of" is one or more, the meaning of "a plurality of" is two or more, and understandings such as "greater than", "less than", and "exceeding" do not include the corresponding number, while understandings such as "above", "below", and "within" include the corresponding number. If there is a description of "first" and "second", it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0029] In the description of the present application, unless otherwise clearly defined, terms such as "arrangement", "installation", and "connection" should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present application in combination with the specific content of the technical solution.

[0030] Currently, communication protocols such as IC2, SPI, UARI, and JTAG play a key role in data transmission and control between devices. However, devices for testing these communication protocols are often incompatible, making most test systems capable of testing only one communication protocol. Therefore, multiple test systems need to cooperate during communication protocol testing, resulting in low test efficiency and waste of resources.

[0031] Based on this, the present application proposes a test system and a test device, aiming to enable the testing of I2C, SPI, UART, and JTAG communication protocols through the test system of the present application, thereby improving the test efficiency.

[0032] It can be understood that the test system of the embodiment of the present application includes a first verification module, a second verification module, a third verification module, a fourth verification module, a multiplexing interface module, and a power supply module. The first verification module is used to test the JTAG communication protocol; the second verification module is used to test the I2C communication protocol; the third verification module is used to test the SPI communication protocol; the fourth verification module is used to test the UART communication protocol; the multiplexing interface module is respectively connected to the first verification module, the second verification module, the third verification module, and the fourth verification module. Among them, the first verification module, the second verification module, the third verification module, and the fourth verification module share multiple ports of the multiplexing interface module; the power supply module is respectively connected to the first verification module, the second verification module, and the third verification module, and the power supply module is used to supply power to the first verification module, the second verification module, and the third verification module.

[0033] The beneficial effects of the test system according to the embodiments of the present application can be manifested as follows: By setting up a power supply module, it is convenient to supply power to the first verification module, the second verification module, and the third verification module, ensuring the stability of the modules. And by setting up a multiplexing interface module, the first verification module, the second verification module, the third verification module, and the fourth verification module are made compatible. When communication protocol testing is required, switch to the corresponding verification module, so that the testing of I2C, SPI, UART, and JTAG communication protocols can be achieved with only one system, thereby reducing the testing cost and improving the testing efficiency.

[0034] Exemplarily, in some embodiments, referring to Figure 1 and Figure 3 , in this embodiment, in this embodiment, the multiplexing interface module is a connector J7 with 34 pins. The first verification module is connected to pins 1 to 32 of the first connector J7, and the second verification module is also connected to pins 1 to 32 of the first connector J7, and the third verification module is also connected to pins 1 to 32 of the first connector J7. The fourth verification module is connected to pins 1, 3, 5, and 7 of the first connector J7. Referring to Figure 3 , the first column is the names of the 34 pins of the connector J7, the second column is the corresponding pin names of the third verification module, the third column is the corresponding pin names of the second verification module, the fourth column is the corresponding pin names of the fourth verification module, and the fifth column is the corresponding pin names of the first verification module. Among them, the corresponding pins in the same row are the same pin, resulting in the pins of the first connector J7 being multiplexed multiple times. The setting of the first verification module is convenient for testing the JTAG (Joint Test Action Group) communication protocol, the setting of the second verification module is convenient for testing the I2C (Inter-Integrated Circuit) communication protocol, the setting of the third verification module is convenient for testing the SPI (Serial Peripheral Interface) communication protocol, and the testing of the fourth verification module is convenient for testing the UART (Universal Asynchronous Receiver / Transmitter) communication protocol, which promotes the compatibility of the testing of I2C, SPI, UART, and JTAG communication protocols on the connector J7, enabling the testing of I2C, SPI, UART, and JTAG communication protocols with only one testing system, improving the testing efficiency, and at the same time reducing the testing cost.

[0035] It can be understood that: The power supply module includes an external power supply and an internal power supply. The external power supply is respectively connected to the first verification module, the second verification module, and the third verification module. The internal power supply includes a linear step-down chip U10, a first capacitor C9, a second capacitor C10, a third capacitor C11, and a fourth capacitor C12. One end of the first capacitor C9 is respectively connected to the external power supply and the input end of the linear step-down chip U10, and the other end is connected to the ground end of the linear step-down chip U10. One end of the second capacitor C10 is connected to the input end of the linear step-down chip U10, and the other end is connected to the ground end of the linear step-down chip U10. One end of the third capacitor C11 is connected to the output end of the linear step-down chip U10, and the other end is connected to the ground end of the linear step-down chip U10. One end of the fourth capacitor C12 is respectively connected to the output end of the linear step-down chip U10, the first verification module, the second verification module, and the third verification module, and the other end is connected to the ground end of the linear step-down chip U10.

[0036] Exemplarily, in some embodiments, referring to Figure 2 , in this embodiment, the model of the linear step-down chip U10 is AMS1117. The power supply module has an external power supply and an internal power supply. The external power supply has two power supply methods. One is that a 5V power socket is connected to a 5V-2A power adapter to provide a 5V current. The other is to be connected to a power indicator through the third row of pins to provide a 5V current. The external power supply directly powers the first verification module, the second verification module, and the third verification module, and is connected to the internal power supply. The internal power supply converts the 5V voltage of the external power supply into 3.3V through the linear step-down chip U10 and then supplies it to the first verification module, the second verification module, and the third verification module. The 5V input by the external power supply passes through the first capacitor C9 and the second capacitor C10 and is input to the step-down chip U10, and then outputs through the third capacitor C11 and the fourth capacitor C12. Among them, the first capacitor C9 is a 22uF input capacitor, the second capacitor C10 is a 100nF filtering capacitor, the third capacitor C11 is a 10uF output capacitor, and the fourth capacitor is a 22uF filtering capacitor, which makes the input and output of the voltage more stable, reduces the interference of noise, and is more convenient for the voltage drop.

[0037] It can be understood that: The power supply module further includes a first row of pins J2. The fourth capacitor C12 is respectively connected to the first verification module, the second verification module, and the third verification module through the first row of pins J2. The first input end of the first row of pins J2 is connected to the output end of the linear step-down chip U10, the second input end of the first row of pins J2 is connected to the external power supply, and the output end of the first row of pins J2 is connected to the first verification module, the second verification module, and the third verification module. The output end of the first row of pins J2 includes a first output end and a second output end. The first output end is used to output the voltage of the internal power supply, and the second output end is used to output the voltage of the external power supply.

[0038] Exemplarily, in some embodiments, referring to Figure 2 , in this embodiment, the first row of pins J2 has four pins. Among them, pin 1 and pin 3 of the first row of pins J2 are respectively used as the first input terminal and the second input terminal. Pin 1 of the first row of pins J2 is connected to an external power supply, and the external power supply provides a voltage of 5V. Pin 3 of the first row of pins J2 is connected to the output terminal of the linear buck chip U10, and the linear buck chip U10 provides a voltage of 3.3V. Pin 2 of the first row of pins J2 is used as the first output terminal, outputting a 5V voltage, and pin 4 of the first row of pins J2 is used as the second output terminal, outputting a 3.3V voltage. When the first verification module, the second verification module, and the third verification module require an input voltage of 5V or 3.3V, they are connected to the corresponding output pins of the first row of pins J2. The provision of different output voltages improves the compatibility of the first verification module, the second verification module, and the third verification module with different storage chips.

[0039] It can be understood that: the first verification module includes a complex programmable logic device U9 and a DIP switch assembly. The multiplexing interface module is connected to the first set of pins of the complex programmable logic device U9, and the DIP switch assembly is connected to the second set of pins of the complex programmable logic device U9. The DIP switch assembly is used to control the potential change of the second set of pins.

[0040] Exemplarily, in some embodiments, referring to Figure 3 and Figure 7 , in this embodiment, the complex programmable logic device U9 has 100 pins. The first set of pins of the complex programmable logic device U9 are pins 22 to 25. Among them, pins 22 to 25 of the first set of pins of the complex programmable logic device U9 are sequentially connected to pins 7, 3, 1, and 5 of the connector J7. The second set of pins of the complex programmable logic device U9 are pins 1 to 8, and pins 14 to 21. The DIP switch assembly is used to control the level change of the second set of pins of the complex programmable logic device U9. The test of the JTAG communication protocol uses the boundary scan method, which can detect the level change of the second set of pins of the complex programmable logic device U9 in real time. The DIP switch assembly is provided with a plurality of light-emitting diodes. When the pin in the second set of pins is adjusted to a high level through the DIP switch assembly, the corresponding light-emitting diode will light up. When the pin in the second set of pins is adjusted to a low level, the corresponding light-emitting diode will go out. By comparing the situation of the plurality of diodes lighting up with the monitored results, it can be determined whether the complex programmable logic device U9 can work normally. For example: when the light-emitting diode lights up, it is considered that the level of pin 1 of the complex programmable logic device U9 connected to the light-emitting diode is high at this time, and then it is compared with the detected structure, thereby realizing the test of the JTAG communication protocol.

[0041] It can be understood that: the DIP switch assembly includes a first DIP switch S1 and a second DIP switch S2. The second group of pins are respectively connected to the first DIP switch S1 and the second DIP switch S2. The first DIP switch S1 is used to access the high level of the second group of pins, and the second DIP switch S2 is used to access the low level of the second group of pins.

[0042] Exemplarily, in some embodiments, referring to Figure 8 and Figure 7 , in this embodiment, the DIP switch assembly is divided into a first DIP switch S1 and a second DIP switch S2. The first DIP switch S1 is connected to the high-level pins of the second group of pins, that is, the first DIP switch S1 pulls pins 1 to 8 of the complex programmable logic device U9 to a high level. The second DIP switch S2 is connected to the low-level pins of the second group of pins, that is, the second DIP switch S2 pulls pins 14 to 21 of the complex programmable logic device U9 to a low level. At this time, when the light-emitting diode of the first DIP switch S1 is lit, it is considered that the corresponding pin among pins 1 to 8 of the complex programmable logic device U9 is at a high level, and when the light-emitting diode of the first DIP switch S1 is extinguished, it is considered that the corresponding pin among pins 1 to 8 of the complex programmable logic device U9 is at a low level. Similarly, when the light-emitting diode of the second DIP switch S2 is lit, it is considered that the corresponding pin among pins 14 to 21 of the complex programmable logic device U9 is at a low level, and when the light-emitting diode of the second DIP switch S2 is extinguished, it is considered that the corresponding pin among pins 14 to 21 of the complex programmable logic device U9 is at a high level. By setting the first DIP switch S1 and the second DIP switch S2, more kinds of level combinations are generated, so as to comprehensively test the driving ability, responsiveness, and connection status of the pins of the complex programmable logic device U9.

[0043] It can be understood that: the second verification module includes a first storage chip EEPROM, a first resistor R5, a second resistor RN1A, a third resistor RN1B, and a fifth capacitor C13. One end of the first resistor R5 is grounded, and the other end is connected to the first address terminal of the first storage chip EEPROM. One end of the second resistor RN1A is connected to the output terminal of the first row of pins J2, and the other end is connected to the clock terminal SCL of the first storage chip EEPROM. One end of the third resistor RN1B is connected to the output terminal of the first row of pins J2, and the other end is connected to the data terminal SDA of the first storage chip EEPROM. The power supply terminal of the first storage chip EEPROM is connected to the output terminal of the first row of pins J2 and is grounded through the fifth capacitor C13. The multiplexing interface module is respectively connected to the clock terminal SCL and the data terminal SDA of the first storage chip EEPROM.

[0044] Exemplarily, in some embodiments, referring to Figure 4, in this embodiment, the second resistor RN1A and the third resistor RN1B serve as pull-up resistors to pull up the voltages of the clock terminal SCL and the data terminal SDA of the first storage chip EEPROM to be the same as the output voltage of the first row of pins J2. Among them, the clock terminal SCL of the first storage chip EEPROM is connected to pin 2 of the connector J7, and the data terminal SDA of the first storage chip EEPROM is connected to pin 4 of the connector J7. And the second verification module has 16 first storage chips EEPROM, and the connection of the other 15 first storage chips EEPROM to the pins of the connector J7 is based on Figure 2 corresponding to achieve the function of testing the I2C communication protocol. The test of the I2C communication protocol mainly tests whether the data terminal SDA of the first storage chip EEPROM can send or receive data.

[0045] It can be understood that: the third verification module includes a second storage chip FLASH, a fourth resistor RN9A, a fifth resistor RN9B, a sixth resistor RN9C, and a sixth capacitor C4. One end of the fourth resistor RN9A is connected to the output terminal of the linear voltage regulator chip U10, and the other end is connected to the first input terminal CS of the second storage chip FLASH. One end of the fifth resistor RN9B is connected to the output terminal of the linear voltage regulator chip U10, and the other end is connected to the second input terminal SO of the second storage chip FLASH. One end of the sixth resistor RN9C is grounded through the sixth capacitor C4 and is connected to the output terminal of the linear voltage regulator chip U10, and the other end is connected to the output terminal SI of the second storage chip FLASH. The read / write terminal WP# of the second storage chip FLASH is connected to the output terminal of the linear voltage regulator chip U10, and the read / write terminal WP# is active low. The multiplexing interface module is respectively connected to the first input terminal CS, the second input terminal SO, the output terminal SI, and the clock terminal of the second storage chip FLASH.

[0046] Exemplarily, in some embodiments, refer to Figure 5 , in this embodiment, the first input terminal CS of the second storage chip FLASH outputs the chip select signal during the SPI communication protocol test, the second input terminal SO inputs the data signal, and the output terminal SI outputs the data signal. The fourth resistor RN9A, the fifth resistor RN9B, and the sixth resistor RN9C all serve as pull-up resistors to pull up the first input terminal CS, the second input terminal SO, and the read / write terminal WP# of the second storage chip FLASH to the output voltage of the linear voltage regulator chip U10, where the read / write terminal WP# is active low, thereby improving the anti-interference ability of the circuit. Among them, the first input terminal CS, the second input terminal SO, the output terminal SI, and the clock terminal of the second storage chip FLASH are respectively connected to pins 8, 4, 6, and 2 of the connector J7, and the third verification module includes 8 second storage chips FLASH, and the connection of the other 7 second storage chips FLASH to the pins of the connector J7 is based onFigure 2 corresponds to, thereby realizing the function of testing the SPI communication protocol.

[0047] It can be understood that: the fourth verification module includes a second row of pins J3. The output end and the input end of the second row of pins J3 are both connected to the multiplexing interface module, and the input end of the second row of pins J3 is short-circuited with the output end of the second row of pins J3.

[0048] Exemplarily, in some embodiments, referring to Figure 6 , in this embodiment, the second row of pins J3 is a row of pins with eight pins. Among them, pins 1, 3, 5, and 7 of the second row of pins J3 are input ends. Pin 1 of the second row of pins J3 is connected to pin 1 of the connector J7, pin 3 of the second row of pins J3 is connected to pin 5 of the connector J7, pin 5 of the second row of pins J3 is connected to pin 9 of the connector J7, and pin 7 of the second row of pins J3 is connected to pin 13 of the connector J7. And pins 2, 4, 6, and 8 of the second row of pins J3 are output ends. Pin 2 of the second row of pins J3 is connected to pin 3 of the connector J7, pin 4 of the second row of pins J3 is connected to pin 7 of the connector J7, pin 6 of the second row of pins J3 is connected to pin 11 of the connector J7, and pin 8 of the second row of pins J3 is connected to pin 15 of the connector J7. By short-circuiting the input end and the output end of the second row of pins J3, when testing UART communication, the signal sent by the output end of the second row of pins J3 of the device under inspection is received back by the input end of the second row of pins J3. By comparing the received signal with the sent signal, the integrity of the sending and receiving functions of the device under inspection can be confirmed, thereby realizing the test function of the UART communication protocol. Among them, it also includes a third row of pins J4, a fourth row of pins J5, and a fifth row of pins J6. The functions of the third row of pins J4, the fourth row of pins J5, and the fifth row of pins J6 are the same as those of the second row of pins J3. The connection of the third row of pins J4, the fourth row of pins J5, and the fifth row of pins J6 to the connector J7 can refer to Figure 2 .

[0049] It can be understood that: the second verification module also includes a seventh resistor R8 and an eighth resistor R11. One end of the seventh resistor R8 is grounded, and the other end is connected to the second address terminal of the first storage chip EEPROM. One end of the eighth resistor R11 is grounded, and the other end is connected to the third address terminal of the first storage chip EEPROM. The resistance values of the first resistor R5, the seventh resistor R8, and the eighth resistor R11 are the same.

[0050] Exemplarily, in some embodiments, referring to Figure 4, in this embodiment, the first resistor R5, the seventh resistor R8, and the eighth resistor R11 have the same resistance value, and all are used as pull-down resistors to pull to the low level. By replacing the first resistor R5, the seventh resistor R8, and the eighth resistor R11, the address information can be changed. For example, when the first resistor R5, the seventh resistor R8, and the eighth resistor R11 are all normally connected, the address information is "000", and when the first resistor R5 is disconnected and the seventh resistor R8 and the eighth resistor R11 are both normally connected, the address information becomes "100".

[0051] The test device according to the second aspect embodiment of the application includes the test system of the first aspect embodiment of the application above.

[0052] Since the test device includes the test system of the first aspect embodiment, the corresponding content of the test system in the first aspect embodiment can all be applied to the test device of the second aspect, and has the same implementation principle and technical effect. To avoid redundant description content, it will not be described in detail here.

[0053] The embodiments described in the embodiments of the present application are for more clearly explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation to the technical solutions provided by the embodiments of the present application. Those skilled in the art know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0054] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation to the embodiments of the present application, and may include more or fewer steps than shown in the figures, or combine some steps, or different steps.

[0055] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0056] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and their appropriate combinations.

[0057] In the description of this application and the above-mentioned drawings, terms such as "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0058] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally means that the associated objects before and after are in an "or" relationship. "At least one (one) of the following" or its similar expressions refer to any combination of these items, including any combination of single items (ones) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0059] In several embodiments provided by this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the above-mentioned unit division is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical, or other forms.

[0060] The units described above as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0061] In addition, in each embodiment of the present application, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0062] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store programs.

[0063] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, and thus do not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the rights of the embodiments of the present application.

Claims

1. A testing system, characterized in that: include: A first verification module, the first verification module is used to test the Joint Test Action Group JTAG communication protocol; A second verification module, the second verification module is used to test the integrated circuit bus I2C communication protocol; A third verification module, the third verification module is used to test the serial peripheral interface SPI communication protocol; A fourth verification module, wherein the fourth verification module is used to test a universal asynchronous receiver / transmitter UART communication protocol; a multiplexing interface module, wherein the multiplexing interface module is connected to the first verification module, the second verification module, the third verification module and the fourth verification module respectively, wherein the first verification module, the second verification module, the third verification module and the fourth verification module share a plurality of ports of the multiplexing interface module; A power supply module, wherein the power supply module is respectively connected to the first verification module, the second verification module and the third verification module, and the power supply module is used to supply power to the first verification module, the second verification module and the third verification module.

2. The test system according to claim 1, characterized in that: The power supply module includes an external power supply and an internal power supply, the external power supply is respectively connected to the first verification module, the second verification module and the third verification module, the internal power supply includes a linear buck chip, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, one end of the first capacitor is respectively connected to the external power supply and the input end of the linear buck chip, and the other end is connected to the ground end of the linear buck chip, one end of the second capacitor is connected to the input end of the linear buck chip, and the other end is connected to the ground end of the linear buck chip, one end of the third capacitor is connected to the output end of the linear buck chip, and the other end is connected to the ground end of the linear buck chip, one end of the fourth capacitor is respectively connected to the output end of the linear buck chip, the first verification module, the second verification module and the third verification module, and the other end is connected to the ground end of the linear buck chip.

3. The test system according to claim 2, characterized in that: The power supply module also includes a first row of needles, and the fourth capacitor is respectively connected to the first verification module, the second verification module and the third verification module through the first row of needles, the first input end of the first row of needles is connected to the output end of the linear buck chip, the second input end of the first row of needles is connected to the external power supply, the output end of the first row of needles is connected to the first verification module, the second verification module and the third verification module, the output end of the first row of needles includes a first output end and a second output end, the first output end is used to output the voltage of the internal power supply, and the second output end is used to output the voltage of the external power supply.

4. The test system according to claim 1, characterized in that: The first verification module includes a complex editable logic device and a dip switch component, the multiplexing interface module is connected to a first group of pins of the complex editable logic device, the dip switch component is connected to a second group of pins of the complex editable logic device, and the dip switch component is used to control the potential change of the second group of pins.

5. The test system according to claim 4, characterized in that: The dip switch assembly includes a first dip switch and a second dip switch, the second group of pins are connected to the first dip switch and the second dip switch respectively, the first dip switch is used to access the high level of the second group of pins, and the second dip switch is used to access the low level of the second group of pins.

6. The test system according to claim 3, characterized in that: The second verification module includes a first storage chip, a first resistor, a second resistor, a third resistor and a fifth capacitor, one end of the first resistor is grounded, and the other end is connected to the first address end of the first storage chip, one end of the second resistor is connected to the output end of the first row of pins, and the other end is connected to the clock end of the first storage chip, one end of the third resistor is connected to the output end of the first row of pins, and the other end is connected to the data end of the first storage chip, the power end of the first storage chip is connected to the output end of the first row of pins and is grounded through the fifth capacitor, and the multiplexing interface module is respectively connected to the clock end and the data end of the first storage chip.

7. The test system according to claim 2, characterized in that: The third verification module includes a second storage chip, a fourth resistor, a fifth resistor, a sixth resistor and a sixth capacitor, one end of the fourth resistor is connected to the output end of the linear buck chip, and the other end is connected to the first input end of the second storage chip, one end of the fifth resistor is connected to the output end of the linear buck chip, and the other end is connected to the second input end of the second storage chip, one end of the sixth resistor is grounded through the sixth capacitor and connected to the output end of the linear buck chip, and the other end is connected to the output end of the second storage chip, the read-write end of the second storage chip is connected to the output end of the linear buck chip, and the read-write end is valid at a low level, and the multiplexing interface module is respectively connected to the first input end, the second input end, the output end and the clock end of the second storage chip.

8. The test system according to claim 1, characterized in that: The fourth verification module includes a second row of pins, the output end and the input end of the second row of pins are both connected to the multiplexing interface module, and the input end of the second row of pins is short-circuited with the output end of the second row of pins.

9. The test system according to claim 6, characterized in that: The second verification module also includes a seventh resistor and an eighth resistor, one end of the seventh resistor is grounded, and the other end is connected to the second address end of the first storage chip, one end of the eighth resistor is grounded, and the other end is connected to the third address end of the first storage chip, and the first resistor, the seventh resistor and the eighth resistor have the same resistance value.

10. A testing device, characterized in that: include: A test system as claimed in any one of claims 1 to 9.

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