Adaptive data selection for DCG / dag

Abstract

The invention relates to an adaptive data selection for DCG / DAG. A pixel circuit includes: a pixel array including a plurality of pixels; a plurality of analog-to-digital converters (ADCs), where, during pixel data readout, the plurality of ADCs are communicatively coupled to respective ones of the plurality of pixels to receive image data from the respective ones of the plurality of pixels; a plurality of decision blocks, where each decision block is communicatively coupled to a respective ADC of the plurality of ADCs, and where each decision block is configured to select and transmit gain data based on comparing an output of the respective ADC to a predetermined threshold of the respective ADC; and an image signal processor (ISP) configured to: receive an output from the plurality of ADCs; and combining the outputs of the plurality of ADCs to produce a combined converted value for the respective pixel.

Description

Technical Field

[0001] The present disclosure generally relates to the design of image sensors, and more particularly to image sensors having improved photodiode illumination. Background Art

[0002] Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, and medical, automotive, and other applications. The technology for manufacturing image sensors continues to evolve rapidly. For example, the demand for higher image sensor resolution and lower power consumption has driven the further miniaturization of image sensors and their integration into digital devices.

[0003] An image sensor operates in response to image light from an external scene that is incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate corresponding charges in response. The charge of an individual pixel can be measured as an output voltage of each photosensitive element. Generally, the output voltage varies as a function of the intensity and duration of the incident light. The output voltages of the individual photosensitive elements are used to generate a digital image (i.e., image data) representing the external scene.

[0004] In some applications, the photodiodes are illuminated by incoming light through a combination of a lens and a color filter, thereby exposing the individual photodiodes to light of a given color (wavelength), such as blue, green, or red. Based on photodiodes that are only exposed to a limited wavelength range, the properties of the photodiodes can be optimized such that, for example, the peak sensitivity of a given photodiode is within a target range of the light wavelength. However, the lens and color filter necessarily attenuate the incoming light, thus limiting the dynamic range of the photodiodes. Accordingly, there is a need for systems and methods for improving the illumination and dynamic range of image sensors. Summary of the Invention

[0005] One aspect of the present disclosure relates to a pixel circuit that includes: a pixel array including a plurality of pixels; a plurality of analog-to-digital converters (ADCs) that, during pixel data readout, are communicatively coupled to respective ones of the plurality of pixels to receive image data from the respective pixels of the plurality of pixels; a plurality of decision blocks, where each decision block is communicatively coupled to a respective one of the plurality of ADCs, and where each decision block is configured to select and transmit gain data based on comparing an output of the respective ADC with a predetermined threshold of the respective ADC; and an image signal processor (ISP) configured to: receive outputs from the plurality of ADCs; and combine the outputs of the plurality of ADCs to generate a combined converted value for the respective pixels.

[0006] Another aspect of the present disclosure relates to a method of generating a combined converted value of a pixel circuit, the pixel circuit including: a pixel array including a plurality of pixels; a plurality of analog-to-digital converters (ADCs), wherein during pixel data readout, the plurality of ADCs are communicatively coupled to respective ones of the plurality of pixels to receive image data from the respective pixels of the plurality of pixels; and a plurality of determination blocks, wherein each determination block is communicatively coupled to a respective one of the plurality of ADCs, and wherein each determination block is configured to select and transmit gain data based on comparing an output of the respective ADC with a predetermined threshold of the respective ADC, the method including: transmitting the image data from each respective pixel of the plurality of pixels to the plurality of ADCs; comparing the output of the respective ADC with the predetermined threshold of the respective ADC; selecting the gain data from the output of each ADC using each determination block of the plurality of determination blocks; transmitting the gain data of each ADC of the plurality of ADCs to the ISP; receiving, by the ISP, outputs from the plurality of ADCs; and combining the outputs of the plurality of ADCs to generate a combined converted value for the respective pixel.

[0007] Another aspect of the present disclosure relates to a method of generating a combined converted value of the pixel circuit according to Technical Solution 1, the method including: transmitting the image data from each respective pixel of the plurality of pixels to the plurality of ADCs; comparing the output of the respective ADC with the predetermined threshold of the respective ADC; selecting the gain data from the output of each ADC using each determination block of the plurality of determination blocks; transmitting the gain data of each ADC of the plurality of ADCs to the ISP; receiving, by the ISP, outputs from the plurality of ADCs; and combining the outputs of the plurality of ADCs to generate a combined converted value for the respective pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, in which like reference numerals refer to like components throughout the various views unless otherwise specified.

[0009] Figure 1 Illustrates an imaging system according to an embodiment of the present disclosure.

[0010] Figure 2 is an illustrative schematic diagram of a conventional pixel circuit according to the present disclosure.

[0011] Figure 3 is an illustrative schematic diagram of a conventional pixel circuit for generating a combined converted value of pixels according to the present disclosure.

[0012] Figure 4It is an illustrative schematic diagram of a pixel circuit for generating a combined converted value of pixels according to the present disclosure.

[0013] Figure 5A It is an illustrative schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

[0014] Figure 5B It is an illustrative representation of an ADC code according to the present disclosure.

[0015] Figure 5C It is a graph of a predetermined threshold for selecting a conversion gain according to an embodiment of the present disclosure.

[0016] Figure 6A It is an illustrative schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

[0017] Figure 6B It is an illustrative graph of a determination timing pulse according to an embodiment of the present disclosure.

[0018] Figure 7A It is an illustrative schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

[0019] Figure 7B It is a graph for determining a first threshold and a second threshold of a selected conversion gain according to an embodiment of the present disclosure.

[0020] Figure 7C It is a graph for determining a first threshold and a second threshold of a selected conversion gain according to an embodiment of the present disclosure.

[0021] Figure 8A It is a graph for determining a first threshold and a second threshold of a selected conversion gain according to an embodiment of the present disclosure.

[0022] Figure 8B It is a graph of a predetermined threshold for determining a selected conversion gain according to an embodiment of the present disclosure.

[0023] Figure 8C It is a graph of a predetermined threshold T for determining a selected conversion gain according to an embodiment of the present disclosure.

[0024] Figure 9 It is a method for generating a combined converted value for pixels in a pixel circuit according to an embodiment of the present disclosure.

[0025] Figure 10 It is another method for generating a combined converted value for pixels in a pixel circuit according to an embodiment of the present disclosure.

[0026] Figure 11 It is another method for generating a combined converted value for pixels in a pixel circuit according to an embodiment of the present disclosure.

[0027] Figure 12 is another method for generating a combined converted value for a pixel in a pixel circuit according to an embodiment of the present disclosure.

[0028] Throughout several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to help improve the understanding of the various embodiments of the present invention, the dimensions of some of the elements in the figures may be enlarged relative to other elements. Also, common and well-known elements that are useful or necessary in a commercially viable embodiment are generally not depicted to facilitate an unobstructed view of these various embodiments of the present invention. Detailed Description

[0029] An image sensor is disclosed, and more particularly an image sensor including a color router. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein may be practiced without one or more of the specific details or may be practiced using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0030] References to "one example" or "one embodiment" in the present specification mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0031] Spatial relative terms, such as "beneath", "below", "lower", "under", "above", "upper", etc., may be used herein for ease of description to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as being "between" two layers, that layer may be the only layer between the two layers or there may also be one or more intervening layers.

[0032] In view of the foregoing, it will be understood that while specific embodiments of the technology have been described herein for purposes of illustration, various modifications can be made without departing from the disclosure. Additionally, although various advantages and features associated with specific embodiments have been described in the context of those embodiments, other embodiments may exhibit such advantages and / or features, and not all embodiments must exhibit such advantages and / or features to fall within the scope of the technology. In the case of describing a method, the method may include more, fewer, or other steps. Additionally, the steps can be performed in any suitable order. Accordingly, the disclosure can encompass other embodiments not expressly shown or described herein. In the context of the disclosure, the terms "about", "approximately", etc. mean + / - 5% of the stated value.

[0033] Throughout this specification, several technical terms are used. These terms will assume their ordinary meaning in the art to which they pertain, unless specifically defined herein otherwise or the context in which they are used otherwise clearly implies. It should be noted that in this document, element names and symbols may be used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0034] Briefly, embodiments of the technology relate to image sensors for use at multiple illumination levels. In some embodiments, the image sensor transmits both low-gain data and high-gain data via a plurality of analog-to-digital converters (ADCs). In some embodiments, a decision block selects the low-gain data or the high-gain data based on a predetermined threshold. In some embodiments, the predetermined threshold is the saturation state of the most significant bit (MSB). In some embodiments, the predetermined threshold is a voltage reading at a decision timing pulse issued at a predetermined time. In some embodiments, the predetermined threshold is based on a high-gain code. In some embodiments, the predetermined threshold includes a first threshold and a second threshold. In some embodiments, when the output of an ADC among the plurality of ADCs is below the first threshold, high-gain is transmitted, and when the output of the ADC is above the second threshold, low-gain is transmitted. When the output of the ADC among the plurality of ADCs is between the first threshold and the second threshold, a mixture of high-gain data and low-gain data is transmitted.

[0035] Figure 1Illustrate an exemplary imaging system 100 in accordance with an embodiment of the present disclosure. The imaging system 100 includes a pixel array 102, control circuitry 104, readout circuitry 106 (also referred to as pixel circuitry), and functional logic 110. In one example, the pixel array 102 is a two-dimensional (2D) array of photodiodes or image sensor pixels 112 (e.g., pixels P1, P2, …, Pn). As illustrated, the photodiodes are arranged in a number of rows (e.g., rows R1 to Ry) and a number of columns (e.g., columns C1 to Cx). In operation, the photodiodes acquire image data of an external scene, which can then be used to reproduce a 2D image of a person, place, object, etc. However, in other embodiments, the photodiodes can be arranged in a configuration different from a number of rows and columns.

[0036] In an embodiment, after each pixel 112 in the pixel array 102 acquires its image charge, the image data is read out by the readout circuitry 106 via bit lines 118 and then transmitted to the functional logic 110. In various embodiments, the readout circuitry 106 can include signal amplifiers, analog-to-digital (ADC) conversion circuitry, and data transmission circuitry. The functional logic 110 can store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red-eye, adjusting brightness, adjusting contrast, or others). In some embodiments, the control circuitry 104 and the functional logic 110 can be combined into a single functional block to control the capture of an image by the pixels 112 and the readout of the image data from the readout circuitry 106. For example, the functional logic 110 can be a digital processor. In one embodiment, the readout circuitry 106 can read out one row of image data at a time along the readout column lines (bit lines 118) or can read the image data using a variety of other techniques, such as serial readout or simultaneous full parallel readout of all pixels (not illustrated).

[0037] In one embodiment, the control circuitry 104 is coupled to the pixel array 102 to control the operation of a plurality of photodiodes in the pixel array 102. For example, the control circuitry 104 can generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal for simultaneously enabling all pixels within the pixel array 102 to capture their respective image data during a single data acquisition window. In another embodiment, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during successive acquisition windows. In another embodiment, the image acquisition is synchronized with an illumination effect such as a flash.

[0038] In one embodiment, the readout circuitry 106 includes an analog-to-digital converter (ADC) that converts analog image data received from the pixel array 102 into a digital representation. The digital representation of the image data can be provided to the functional logic 110. In some embodiments, the data transfer circuitry 108 can receive the digital representation of the image data from the ADC in parallel and can provide the image data to the functional logic 110 serially.

[0039] In various embodiments, the imaging system 100 can be included in a digital camera, a cellular phone, a laptop computer, etc. Additionally, the imaging system 100 can be coupled to other pieces of hardware, such as a processor (general or otherwise), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), an illumination / flash, an electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and / or a display. The other pieces of hardware can deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate the image data supplied by the imaging system 100.

[0040] Figure 2 FIG. 7 is an illustrative schematic diagram of a conventional pixel 210 according to the present disclosure. The pixel 210 can be coupled to a bit line 218, such as a readout column that provides image data to a readout circuitry such as the readout circuitry 106. In operation, the pixel 210 can receive control signals from a control circuitry such as the control circuitry 104 to control the operation of various transistors of the pixel 210. The control circuitry can control the operation of the transistors in a desired sequence with a relative timing that ensures an orderly readout of the image data.

[0041] The illustrated embodiment of the pixel 210 includes a photodiode (PD) 211, a floating diffusion (FD1) 213 having an inherent capacitor (FDC) 219, a transfer transistor 212, an optional dual floating diffusion (DFD) transistor 216, an optional floating diffusion (FD2) 217 connected to an optional lateral overflow integrating capacitor (LOFIC) 215, a reset (RST) transistor 214, a row select (RS) transistor 221, and a source follower (SF) transistor 220. The transfer (TX) transistor 212 (which can also be referred to as the transfer gate 212) is coupled between the photodiode PD 211 and the floating diffusion FD1 213. The TX transistor 212 operates based on a TX control signal on its gate terminal. Although the floating diffusion FD1 213 is depicted as being connected to the inherent capacitor FDC 219 (which is connected to ground), the combination of FD1 213 and FDC 219 can also be collectively referred to as the floating diffusion.

[0042] The RST transistor 214 can be coupled to the reference voltage AVDD and can receive a reset control signal at its gate terminal. An additional capacitor LOFIC 215 can be coupled between the variable reference voltage VCAP and the floating diffusion node FD2 217. The DFD transistor 216 can be coupled between FD1 213 and FD2 217 and is further coupled to receive a DFD control signal at its gate terminal. In addition, the gate terminal of the SF transistor 220 is coupled to the floating diffusion node FD1 213. The source / drain terminal of the SF transistor is coupled between the reference voltage AVDD and the RS transistor. The RS transistor 221 can be coupled between the bit line 218 and the SF transistor 220.

[0043] In operation, the transistor TX 212 receives a gate signal to effect charge transfer from the PD 211 to the floating diffusion FD1 213. Generally, the amount of charge transfer depends on the exposure of the PD 211 and the operation of the pixel 210. An equivalent capacitor FDC219 is illustrated as being coupled to ground.

[0044] In some embodiments, the LOFIC 215 can increase the storage of the floating diffusion FD2 217, such as capacitance. For example, in response to high-intensity illumination, the photodiode PD 211 can generate more charge than the floating diffusion FD1 213 can store. The additional charge can be stored by the LOFIC 215. In some embodiments, the reference voltage VCAP can be modulated between two or more voltage levels (e.g., a high voltage level "H" and a low voltage level "L") to regulate how much charge is stored by the LOFIC 215. Generally, the FDC 219 has a smaller capacitance than the LOFIC 215. Thus, the floating diffusion FD1 213 is read in conjunction with the high conversion gain (HCG) portion of the data readout, while the floating diffusion FD2 217 and the floating diffusion 213 are read in conjunction with the low conversion gain (LCG) portion of the readout. Overall, the HCG and LCG readouts constitute a dual conversion gain (DCG) data readout.

[0045] In some embodiments, the operation of the RST transistor 214 and the DFD transistor 216 can reset the floating diffusion FD1 213 to a high voltage representative of the dark state because the photo-generated electrons reduce the voltage proportional to the intensity of the charge of the PD 211 when transferred to the floating diffusion FD1 213. To reset the floating diffusion FD1 213, both the RST transistor 214 and the DFD transistor 216 are enabled (turned on) by their respective gate signals. In other embodiments, the RST transistor 214 can be in the on state while the DFD transistor remains in the off state, thus resetting the floating diffusion FD2 217 but not the floating diffusion FD1 213.

[0046] During integration, the variable voltage VCAP coupled to the LOFIC 215 can be modulated between two or more voltage levels. In some embodiments, depending on the value of AVDD, the VCAP can be modulated between approximately 0.4V and approximately 1.8V. In other embodiments, other voltage levels can be implemented depending on the underlying semiconductor material. When the DFD 216 is enabled, the coupling of FD2 217 to FD1 213 can provide additional capacitance to store the charge generated by the PD 211. For example, when the TX 212 is enabled to transfer image charge to the floating diffusion section FD1 213, the DFD 216 can be enabled to couple the additional capacitance LOFIC 215 to the floating diffusion section FD1 213 to increase the full well capacity (FWC) of the floating diffusion section. In some embodiments, depending on whether the TX transistor 212 is enabled or disabled, the variable voltage VCAP can be at different voltages.

[0047] Figure 3 FIG. 5 is an illustrative schematic diagram of a conventional pixel circuit 300 for generating a combined converted value of pixels according to the present disclosure. In some embodiments, the pixel array 303 is coupled to two or more analog-to-digital converters (ADCs) 311A, 311B, an image signal processor (ISP) 312, and a high dynamic range (HDR) 313. The two or more ADCs 311A, 311B are configured to simultaneously transfer both high conversion gain (HCG) data 330 and low conversion gain (LCG) data 335 to the ISP 312. Generally, the HCG data 330 is read from the FD1 213 (or FDC 219), while the LCG data 335 is read from the FD2 217 (or LOFIC 215).

[0048] In operation, the conventional pixel circuit 300 includes a pixel array 303 composed of a number of pixels (e.g., as Figure 1 shown in FIG. 5). During pixel data readout, the two or more ADCs 311A, 311B are communicatively coupled to respective pixels among the plurality of pixels to receive image data from the respective pixels. The two or more ADCs 311A, 311B then output both the HCG data 330 and the LCG data 335 to the ISP 312A. Both the HCG data 330 and the LCG data 335 are processed by the ISP 312A. The HCG data 330 and the LCG data 335 are then sent to the HDR, which combines the HCG data 330 with the LCG data 335 into high-low combined (HL) conversion data, as Figure 3As shown. The combined HL conversion data is then transmitted back to the same ISP 312A or another ISP 312B. Since the ISP 312A, 312B determines or selects which conversion gain data (HCG data 330, LCG data 335 or a mixture thereof) to combine and forward, additional processing capabilities are utilized. In this way, conventional pixel circuits require complex data processing, which can result in longer digital processing times and greater power consumption in order to transfer the HCG data 330 and the LCG data 335 to the ISPA, ISPB. Illustratively, for each HCG data 330 and LCG data 335 transmitted from each pixel of the pixel array 303, transmitting both the HCG data 330 and the LCG data 335 can each require up to 10b. Additional power is required to combine the transmitted HCG data 330 and LCG data 335. In addition, an even greater power gain in the range of from about 12b to 14b is required for each of the multiple ADCs to transfer the combined HL and HC data to the ISP 312 after combination. Therefore, a large amount of power is required to transfer the HCG data 330 and the LCG data 335 to the ISP 312A, 312B and provide the combined converted values of the pixels from the pixels of the pixel array 303.

[0049] Figure 4 is an illustrative schematic diagram of a pixel circuit 400 for generating a combined converted value of a pixel in accordance with the present disclosure. In some embodiments, the pixel circuit 400 includes a pixel array 403 composed of a plurality of pixels. It should be understood that in some embodiments, the pixel array 403 is Figure 1 the pixel array 103. Thus, in some embodiments, the pixel array 403 is composed of a plurality of pixels arranged in a number of rows and a number of columns. In some embodiments, the pixel circuit 400 further includes a plurality of analog-to-digital converters (ADCs) 411A, 411B, a plurality of decision blocks 415A, 415B, an image signal processor (ISP) 412, and a high dynamic range (HDR) 413. Each of the plurality of decision blocks 415A, 415B is communicatively coupled to a corresponding one of the plurality of ADCs 411A, 411B. In some embodiments, the plurality of ADCs are at least two ADCs 411A, 411B. In some embodiments, the plurality of decision blocks are at least two decision blocks 415A, 415B.

[0050] Multiple ADCs 411A, 411B are communicatively coupled to respective pixels among the multiple pixels in pixel array 403. In operation, during pixel readout, individual ADCs 411A, 411B receive image data from respective pixels among the multiple pixels in pixel array 403. In some embodiments, each decision block 415A, 415B is configured to select and transmit gain data based on comparing the output of the respective ADC 411A, 411B with a predetermined threshold of the respective ADC 411A, 411B, as Figure 5B and 5C shown in. ISP 412 receives the outputs from the multiple ADCs 411A, 411B and combines the outputs of the multiple ADCs 411A, 411B to produce a combined converted value for the respective pixel. In some embodiments, the output of each respective ADC is a high-gain (HG) code, a low-gain (LG) code, or a combination thereof. The HG code may be interchangeably referred to herein as high-gain (HG) data. Similarly, the LG code may be interchangeably referred to herein as low-gain (LG) data.

[0051] In some embodiments, the gain data is selected from HG data 430A, 430B or LG data 435A, 435B. In some embodiments, the gain data (HG data 430A, 430B or LG data 435A, 435B) transmitted to ISP 412 is automatically selected based on each column of the signal level data (HG code, LG code, or a combination thereof) of pixel array 403. The multiple decision blocks 415A, 415B may include at least one analog level detector or at least one digital level detector and may be located inside or outside the column circuitry of pixel array 403.

[0052] In operation, decision blocks 415A, 415B select gain data (HG data 430A, 430B, LG data 435A, 435B, or a combination thereof) such that ISP 412 receives only the gain data from the selected gain (HG data 430A, 430B or LG data 435A, 435B, but not both HG data and LG data). In this way, the processing power can be up to 50% lower than that of a conventional pixel circuit (e.g., Figure 3 the pixel circuit 303 in). Additionally, the processing time can also be reduced by up to 50% compared to the processing time of the conventional pixel circuit 303. This is because only one gain data (i.e., HG data 430 or LG data 435) is transmitted to ISP 412. In some embodiments, the pixel circuit 400 may only need 10b to transmit only the high-gain data 430 or the low-gain data 435, rather than needing 10b for the gain to transmit HG data 430 and 10b to transmit LG data 435 (as Figure 3As shown, a total of 20b) is required. When transmitting HG data 430 or LG data 435 to HDR, power can be further saved. HDR can then combine the HG data with the LG data (HL combination) and pass the combined data back to ISP 412. Decision blocks 415A, 415B can select HG data 430A, 430B or LG data 435A, 435B based on a predetermined threshold, as further shown and described below Figures 5A to 8B as shown and described in further detail below.

[0053] Figure 5A is an illustrative schematic diagram of a pixel circuit 500 according to an embodiment of the present disclosure. In some embodiments, the pixel circuit 500 operates as the Figure 4 decision blocks 415A, 415B shown. The pixel 500 includes a comparator 511, a low-gain (LG) memory 535, a high-gain (HG) memory 530, at least one saturation determination block 515, and at least one multiplexer (MUX) 540. In some embodiments, the comparator 511 is located within an analog-to-digital converter (ADC) (e.g., Figure 4 ADC 411 of the plurality of ADCs 411A, 411B) or otherwise integrated into the ADC.

[0054] In some embodiments, the comparator 511 is a digital comparator. In some embodiments, the HG memory 530 is a memory of an ADC (e.g., ADC 411) and the LG memory 535 is a counter memory of the ADC. In such embodiments, the HG memory 530 and the LG memory 535 are combined as the ADC described and illustrated herein. It should be understood that the ADC can be, but is not limited to, a single-slope ADC. In some embodiments, the ADC is a successive approximation register (SAR) ADC, etc.

[0055] In some embodiments, at least one saturation determination block 515 is, for example, as Figure 4The saturation determination block among the multiple determination blocks shown. In some embodiments, the predetermined threshold of the saturation determination block 515 is the saturation state of the HG code (or data). It should be understood that the HG data 530 has a higher signal-to-noise ratio (SNR) compared to the LG data 535 until the saturation state of the HG data. In some embodiments, the saturation state is set based on whether the output (signal) of the comparator 511 is an HG code at a specific level. For example, in some embodiments, the saturation state is when the HG code is higher than the 1023-bit value, which generally depends on the bit resolution of the ADC. In some embodiments, the saturation state is when the output of the comparator 511 is an LG code at a specific level. In some embodiments, both the HG code and the LG code determine the saturation state. In some embodiments, when the saturation state is not met, the HG data 530 is selected by the saturation determination block 515 and transmitted to the ISP (such as Figure 4 the ISP 412 in

[0056] ). In some embodiments, when the saturation state is met, the LG data 535 is transmitted to the ISP. Figure 4 In operation, the comparator 511 outputs HG data and LG data. The HG data is stored in the HG memory 530, and the LG data is stored in the LG memory 535. In some embodiments, the saturation determination block 515 compares the HG data (or code) with a predetermined threshold (such as the saturation state of the LG data). When the HG code does not reach the predetermined threshold, the HG data is passed to the MUX 540 and transmitted to the image signal processor (ISP), such as

[0057] Figure 5B the ISP 412 in Figure 5B . This situation can be understood as corresponding to a low exposure of a specific pixel, whereby the intensity of the incoming light is low enough so as not to saturate the FD1 213 (or FDC 219). When the HG code reaches or exceeds the predetermined threshold, the HG data is not transmitted, but the LG data is passed to the MUX 540 and then transmitted to the ISP. This situation can be understood as corresponding to a relatively high exposure of a specific pixel, whereby the intensity of the incoming light is high enough to saturate the FD1 213 (or FDC 219), or at least high enough to exceed a specific predetermined threshold of the HG data. Therefore, the MUX can transmit the HG data or the LG data based on the selection of the saturation determination block 515. Figure 5BAn exemplary 10-bit ADC with 10 significant bits is shown. However, in different embodiments, ADCs with different resolutions are also possible.

[0058] When the maximum code is reached (i.e., the maximum HG code before reaching the saturation state), all 10 significant bits are 1. This condition represents a threshold (boundary case) where the sign bits (positive and negative) are 0 and the extra bit is also 0. For the light intensity in this case, the HG code is transmitted because the saturation state has not been reached.

[0059] When the illuminance of the environment is higher, the 10 significant bits may not be transmitted correctly, represented as "x" in Figure 5B The sign bits (positive and negative) remain 0, but the extra bit is set to 1. Therefore, when the saturation state is satisfied, the signal-to-noise ratio (SNR) of the HG code significantly decreases, meaning that the HG code may no longer produce an acceptable image quality. This condition indicates that the LG code will be transmitted by the decision block.

[0060] Similarly, when there is no light or very low light in the environment, the ADC may transmit a negative code. In this case, the sign bits (positive and negative) are set to 1, and neither the 10 significant bits nor the extra bit can be transmitted correctly and will be blocked or ignored by the saturation determination block 515.

[0061] Figure 5C is a graph of a predetermined threshold T for selecting a conversion gain (which can be high-gain (HG) data or low-gain (LG) data) according to an embodiment of the present disclosure. The horizontal axis is the illuminance in lux. The vertical axis is the signal-to-noise ratio (SNR). As Figure 5C shown, as the illuminance (or the light level in the environment) increases, the SNR of the HG increases until the predetermined threshold T. At the predetermined threshold T, even if the illuminance level increases, the SNR of the LG data continues to increase. Although the LG data generally has higher noise, the LG data can store more light data. Therefore, the LG data is more suitable for generating a clear image at a higher light (illumination) level. In some embodiments, the predetermined threshold T is the saturation state of the HG data, as Figure 5A and 5B shown and described. In some embodiments, for a 10-bit ADC, when the HG data (or code) reaches the 1023-bit value, the saturation state occurs.

[0062] In operation, when the predetermined threshold T has not been reached, Figure 5A the pixel circuit 500 transmits HG data. When the predetermined threshold is satisfied, the pixel circuit transmits LG data. In some embodiments, the predetermined threshold T may be based on the LG data (or code). In some embodiments, when the LG data is higher than a specific threshold, the LG data is transmitted.

[0063] In some embodiments, the predetermined threshold is the saturation state of the HG data. In operation, when the predetermined threshold is met, the corresponding saturation determination block 515 in the plurality of determination blocks selects the LG data, and when the predetermined threshold is not met, the corresponding determination block in the plurality of determination blocks selects the HG data.

[0064] Figure 6A FIG. 600 is an illustrative schematic diagram of a pixel circuit 600 according to an embodiment of the present disclosure. In some embodiments, the pixel circuit 600 includes a comparator 611, a high-gain (HG) memory 630, and a low-gain (LG) memory 635, at least one saturation determination block 615, and a multiplexer 640. In some embodiments, the comparator 611 is located within an analog-to-digital converter (ADC) (e.g., Figure 4 an ADC among the plurality of ADCs 411A, 411B) or otherwise integrated into the ADC. In some embodiments, the HG memory 630 is a memory of the ADC (e.g., ADC 411) and the LG memory 635 is a counter memory of the ADC. In such embodiments, the HG memory 630 and the LG memory 635 are combined as the ADC described and illustrated herein.

[0065] In some embodiments, at least one saturation determination block 615 is the saturation determination block in the plurality of determination blocks as Figure 4 shown. In some embodiments, the saturation determination block 615 selects the HG data or the LG data based on a determination timing pulse P, as Figure 6B shown. In operation, the determination timing pulse P triggers an evaluation of the output of the ADC in the plurality of ADCs (e.g., the comparator 611 of the ADC) at a predetermined time. The saturation determination block 615 can then determine whether the output of the ADC (comparator 611) exceeds a predetermined threshold. If it does not exceed the predetermined threshold, the HG data can be transmitted, and if it exceeds the predetermined threshold, the LG data can be transmitted.

[0066] In some embodiments, the comparator 611 can be an analog comparator. In operation, when the analog input exceeds a threshold voltage (e.g., 1023 for a 10-bit ADC), the comparator 611 generates a binary-valued voltage that switches or flips between two binary levels. In some embodiments, the comparator 611 flips when transitioning between low light and high light in the environment. In some embodiments, a determination timing pulse P is issued at a predetermined time, as Figure 6B shown. When the determination timing pulse is issued, the output of the comparator 611 is measured. When the comparator 611 does not flip at the predetermined time, the HG data 630 is transmitted. When the comparator 611 has flipped at the predetermined time, the LG data 635 is transmitted.

[0067] Figure 6BIs an illustrative diagram of a determination timing pulse P according to an embodiment of the present disclosure. Time is on the horizontal axis. At the top of the diagram are the voltages of the reset low-gain (LG) data, reset high-gain (HG) data, HG signal, and LG signal. After the reset voltages of the HG data and the LG data ramp up, the pixel circuit (e.g., pixel circuit 600) is turned on. After the pixel circuit is turned on, the HG signal ramps down, and then the LG signal ramps down. On the vertical axis are the voltages of at least one determination block, the determination timing pulse P, the output of a comparator (e.g., comparator 611) in high light, and the output of a comparator (e.g., comparator 611) in low light. The vertical line near the HG signal is a predetermined time T1 at which the determination timing pulse is issued and the output of the comparator (or ADC) is measured.

[0068] In some embodiments, the determination timing pulse P measures the output of an ADC (or comparator) at a predetermined time T1. In operation, the determination timing pulse P determines whether the comparator is flipped at a predetermined time, as described in connection with Figure 6A As Figure 6B shown, in high-light conditions, the comparator does not flip until the ramp signal of the HG signal reaches the end point, while in low light, the comparator flips earlier during the ramp-down signal of the HG signal. This is because in low light, the HG code has not exceeded the saturation state, while in high light, the HG code has exceeded the saturation state. In this way, a predetermined threshold is evaluated by whether the comparator has flipped. When the comparator has not flipped, the determination block selects the LG data, and when the comparator has flipped, the determination block selects the HG data. Thus, when there is high light, the LG data is selected, and when there is low light, the HG data is selected. In this way, the predetermined threshold can be based on the HG code or the LG code, but whether the threshold has been met or exceeded is determined by the flip of the analog comparator.

[0069] Figure 7A Is an illustrative schematic diagram of a pixel circuit 700 according to an embodiment of the present disclosure. In some embodiments, an image signal processor (ISP) (e.g., ISP 412) mixes high-gain (HG) data with low-gain (LG) data near the saturation point (or a predetermined threshold) to achieve a smooth image transition. In some embodiments, the pixel circuit 700 includes a comparator 711, an HG memory 730, an LG memory 735, a plurality of saturation determination blocks 715A, 715B, and an AND gate 720, a NOR gate 725, a first multiplexer (MUX) 740A, and a second multiplexer (MUX) 740B. In some embodiments, the comparator 711 is located in an analog-to-digital converter (ADC) (e.g., Figure 4within or otherwise integrated into the ADCs of the plurality of ADCs 411A, 411B. In some embodiments, comparator 711 is an analog comparator or a digital comparator. In some embodiments, the predetermined threshold includes a first threshold T1 and a second threshold T2. In some embodiments, the plurality of saturation determination blocks 715A, 715B determine whether the HG code (or data) has reached the first threshold T1 and / or the second threshold T2. In some embodiments, pixel circuit 700 is configured to output a flag F. In some embodiments, HG memory 730 is a memory of the ADC (e.g., ADC 411) and LG memory 735 is a counter memory of the ADC. In such embodiments, HG memory 730 and LG memory 735 are combined as the ADC described and illustrated herein. It should be understood that the ADC can be, but is not limited to, a single-slope ADC. In some embodiments, the ADC is a successive approximation register (SAR) ADC, etc.

[0070] In some embodiments, the unselected data (i.e., HG data or LG data) is passed to the second MUXs 740A, 740B. In some embodiments, the unselected data can be clock-gated based on the flag F.

[0071] In operation, comparator 711 transmits the outputs of both HG data and LG data. In some embodiments, the HG data is stored in HG memory 730, while the LG data is stored in LG memory 735. In some embodiments, when transmitting the gain data (both LG data and HG data), the first saturation determination block 715A compares the output with the first threshold T1. In some embodiments, the first threshold T1 is based on the HG code. In some embodiments, the first threshold is a value of approximately 768 bits. In some embodiments, when the HG code does not meet the first threshold, the first saturation determination block 715A deactivates the LG data signal (LG_EN) 710. The HG data is then transmitted to the "AND" block 720, which passes the HG data to the first MUX 740A, and the first MUX finally transmits the HG data to the ISP (e.g., Figure 4 the ISP 412). Additionally, the first determination block 715A enables the LG data signal (LG_EN) 710. This LG data signal 710 is connected to the second MUX 740B, which issues the flag F, thereby indicating the LG data as unselected. In this way, the LG data 735 is not transmitted to the ISP.

[0072] In some embodiments, the predetermined threshold further includes a second threshold T2. In some embodiments, when the first threshold T1 is satisfied, the HG data is also transmitted to the second saturation determination block 715B among the plurality of saturation determination blocks 715A, 715B. In some embodiments, the second threshold is based on the HG code. In some embodiments, the second threshold is about 1023 bit values. When the first threshold T1 is satisfied but the second threshold T2 is not satisfied, the HG data is still transmitted to the AND block 720 and is transmitted to the first MUX 740A. When the second threshold T2 is not satisfied, the LG data is also transmitted to the AND gate 720, combined with the HG data, and is transmitted to the first MUX 740A.

[0073] When the second threshold T2 is also satisfied (e.g., when the HG code exceeds 1023 bit values), the second saturation determination block 715B selects the LG data 735 and does not select the HG data. As Figure 7A shown, the HG data signal (HG_EN) 707 is enabled and is connected to the second MUX 740B. The second MUX 740B outputs a flag F, thereby designating HG as the unselected data. Those skilled in the art will understand that the bit values discussed herein are merely exemplary (e.g., different bit values can be selected for different thresholds), but within the limits of the ADC bit resolution.

[0074] Figure 7B is a graph showing a first threshold T1 and a second threshold T2 for determining selected gain data (e.g., high gain (HG) data, low gain (LG) data, or both) according to an embodiment of the present disclosure. The horizontal axis is the illuminance in lux. The vertical axis is the signal-to-noise ratio (SNR). As Figure 7B shown, as the illuminance in lux increases, the SNR of the HG data increases until the saturation point SP (which determines the saturation of the FD1 213). At the saturation point SP, even though the FD1 is saturated, the SNR of the LG still continues to increase. Therefore, after the saturation point SP, the LG data (corresponding to the charge stored in the LOFIC 215) is more suitable for generating a clear image at higher light (illumination) levels than the HG data. Figure 7B also illustrates the first threshold T1 and the second threshold T2 therein. The first threshold T1 and the second threshold T2 divide three gain data transmission zones: the LG data transmission zone H, the mixed gain data transmission zone M (where both HG data and LG data are transmitted), and the HG data transmission zone L.

[0075] As Figure 7B shown, when in the high illuminance zone H, only the LG data is transmitted to the ISP (e.g., Figure 4in the ISP 412). When in the mid-level illumination zone M, both HG data and LG data are transmitted. Finally, when in the low illumination zone L, only HG data is transmitted. In some embodiments, the first threshold T1, the second threshold T2, or both are based on the HG code. In some embodiments, the first threshold T1, the second threshold T2, or both may be based only on the LG code, or on both the LG code and the HG code. In some embodiments, the first threshold T1 is an HG code of about 768 bit value and the second threshold T2 is an HG code of about 1023 bit value. In some embodiments, the mid-level illumination zone M is above the first threshold T1 and below the second threshold T2. In some embodiments, the mid-level illumination zone M is when the HG code is between 768 bit value and 1023 bit value. Thus, in some embodiments, when the HG code is between 768 bit value and 1023 bit value, both HG data and LG data are transmitted.

[0076] Figure 7C is a graph for determining a first threshold and a second threshold for a selected conversion gain according to an embodiment of the present disclosure. The horizontal axis is the illumination in lux. The vertical axis is the signal-to-noise ratio (SNR). In some embodiments, the pixel circuit is configured to transmit high gain (HG) data, low gain (LG) data, and mixed conversion gain (MCG) data. In some embodiments, the pixel circuit further includes LG data transmitted from the lateral overflow integrating capacitor (LOFIC) 215, as Figure 1 described therein.

[0077] In some embodiments, the first threshold is the saturation state of the HG data. In some embodiments, the second threshold is the saturation state of the MCG data. Thus, in some embodiments, the saturation determination block (e.g., saturation determination block 715) selects HG, MCG, or LG data based on the light level (illumination) of the environment.

[0078] As Figure 7C shown therein, the HG data has an acceptable SNR until the illumination increases to the point where the HG data reaches the saturation state at the first threshold T1. Then, the MCG data has the next acceptable SNR.

[0079] Figure 8AA graph for determining a first threshold T1 and a second threshold T2 for a selected conversion gain (i.e., HG data, LG data, or both). The horizontal axis represents LG codes, and the vertical axis represents HG codes. There are also three gain data transmission zones on the horizontal axis: an HG data transmission zone HT (marked as "HT" on the horizontal axis), a mixed gain data transmission zone MT (transmitting both HG data and LG data), and an LG data transmission zone LT (marked as "LT" on the horizontal axis). In some embodiments, the mixing of HG data and LG data is dynamically adjusted based on the HG code and the LG code. The LG data transmission zone LT, the mixed gain data transmission zone MT, and the HG data transmission zone HT are divided by the second threshold T2. In some embodiments, the combination of the first threshold T1 and the second threshold T2 may be referred to as a predetermined threshold (singular) or a plurality of predetermined thresholds (plural). Figure 8A Shows multiple conversion gain coefficients. It should be understood that when the conversion gain coefficient is 1.00x, only HG data is transmitted, and when the conversion gain coefficient is 0.00x, only LG data is transmitted. Additionally, when the conversion gain coefficient is 0.75x, both 100% of the HG data and the LG data are transmitted, and the ISP (e.g., ISP 312, 412) generates a combined image with 75% HG data and 25% LG data.

[0080] As Figure 8A Shown, when in the HG data transmission zone H, only HG data is transmitted. Similarly, when in the LG data transmission zone L, only LG data is transmitted. The mixed conversion gain transmission zone M is when the HG code and the LG code are between the first threshold T1 and the second threshold T2. When in the mixed conversion gain transmission zone M, as the illuminance increases, the amount of HG data transmitted decreases. When the illuminance level causes the HG code to exceed the second threshold, no HG data is transmitted.

[0081] In the mixed conversion gain transmission zone M, a combination of HG data and LG data is transmitted through the ADC (e.g., ADC 411A, 411B). When the LG code increases but the HG code remains low, only HG data is transmitted (1.00x) until the HG code reaches a specific level at which some LG data is transmitted (0.75x). When the HG code increases but the LG data remains low, only HG data is transmitted (1.00x) until the LG data reaches a high level at which some LG data is transmitted (0.75x). When both the HG code and the LG code increase, less HG data is transmitted and more LG data is transmitted until only LG data is transmitted (0.00x).

[0082] Figure 8BA graph for determining a predetermined threshold T for a selected conversion gain according to an embodiment of the present disclosure. In some embodiments, the predetermined threshold is based only on high-gain (HG) codes. In some embodiments, Figure 8A the predetermined threshold T in

[0083] Figure 8B is the first threshold or the second threshold as described herein. The HG codes are on the vertical axis.

[0084] As Figure 8B shown in

[0085] Figure 8C When the HG code exceeds the predetermined threshold T, the HG data is not transmitted (0.00x), and the LG data is transmitted. Conversely, when the HG code does not exceed the predetermined threshold T, the HG data is transmitted (1.00x), and the LG data is not transmitted. Figure 8C A graph for determining predetermined thresholds T1, T2 for a selected conversion gain according to an embodiment of the present disclosure. 0 is on the horizontal axis. The high-gain (HG) codes are on the vertical axis. In some embodiments, the predetermined thresholds include a first threshold T1 and a second threshold T2. In some embodiments, the first threshold T1, the second threshold T2, or both are determined based only on HG codes (or data).

[0086] As Figure 8C shown in

[0087] Figure 9Method 900 for generating a combined converted value for a pixel in a pixel circuit according to an embodiment of the present disclosure. In some embodiments, method 900 is performed using pixel circuit 400, 500, 600, 700, or a combination thereof, as described herein.

[0088] In block 905, image data of each corresponding pixel from a pixel array (e.g., pixel array 411) is transmitted to a plurality of ADCs (e.g., a plurality of ADCs 415A, 415B). In some embodiments, the pixel array is pixel array 413 as described herein. In some embodiments, the pixel array is composed of a plurality of pixels arranged in a plurality of rows and a plurality of columns, as Figure 1 shown. In some embodiments, the plurality of ADCs are at least two ADCs. In some embodiments, each ADC of the plurality of ADCs includes at least one comparator, such as comparator 511, 611, or 711. In some embodiments, at least one comparator is an analog comparator, but in other embodiments, at least one comparator is a digital comparator. In some embodiments, the pixel circuit includes a plurality of determination blocks (e.g., determination block 415). In some embodiments, the pixel circuit further includes a plurality of saturation determination blocks (e.g., saturation determination blocks 515, 615, and / or 715).

[0089] In block 910, the output of the corresponding ADC (or comparator) in the plurality of ADCs is compared with a predetermined threshold. In some embodiments, the predetermined threshold is any of the predetermined thresholds described herein. For example, in some embodiments, the predetermined threshold is the saturation state of a high-gain (HG) code, such as Figures 5A to 5B shown. In another embodiment, the predetermined threshold is based on a determination timing pulse at a predetermined time, such as Figures 6A to 6B shown. In some embodiments, the predetermined threshold includes a first threshold and a second threshold, as Figures 7A to 7B shown. In some embodiments, the predetermined threshold is based on both HG data and low-gain (LG) data.

[0090] In block 915, the corresponding determination block in the plurality of determination blocks selects the gain data of each ADC based on whether the output of the ADC satisfies the predetermined threshold. In some embodiments, the conversion gain is selected from high-gain (HG) data or low-gain (LG) data. In some embodiments, the gain data is selected from a mixture or combination of HG data and LG data, as Figures 7A to 7C shown and described in 8A and 8C. In some embodiments, the determination block in the plurality of determination blocks is configured to issue a determination timing pulse at a predetermined time and then compare the output of the corresponding ADC in the plurality of ADCs with the predetermined threshold.

[0091] In block 920, the selected gain data is transferred from each of the plurality of ADCs to an image signal processor (ISP) (e.g., ISP 412). In some embodiments, the pixel circuitry saves processing power and / or time by transferring only the HG data or the LG data to the ISP.

[0092] In block 925, the ISP receives the output of each of the plurality of ADCs. In block 930, the plurality of outputs of each of the plurality of ADCs are combined (e.g., via high dynamic range (HDR)) to produce a combined converted value for each corresponding pixel of the pixel array.

[0093] Figure 10 is another method 1000 for generating a combined converted value for a pixel in a pixel circuitry in accordance with an embodiment of the present disclosure. In some embodiments, method 1000 is performed using pixel circuitry 400, 500, 600, or 700. In some embodiments, method 1000 occurs concurrently with or after method 900.

[0094] In block 1010, the output of a corresponding one of the plurality of ADCs (e.g., the plurality of ADCs 511A, 511B) is compared with a predetermined threshold. In some embodiments, the comparison occurs at a predetermined time, e.g., when a determination timing pulse is issued, as described herein. In some embodiments, the predetermined threshold is the saturation state of a high gain (HG) code (or data).

[0095] In decision block 1015, it is determined whether the predetermined threshold (e.g., predetermined threshold T) is satisfied. As described herein, in some embodiments, the predetermined threshold is an HG code. In some embodiments, the predetermined threshold is based on low gain (LG) data, or both HG data and LG data. In some embodiments, the predetermined threshold is when the HG code is at or above 1020 kHz. In some embodiments, the predetermined threshold is based on whether an analog comparator has flipped. If the predetermined threshold is not satisfied, then method 1000 proceeds to block 1020A.

[0096] In block 1020A, the HG data is selected by a determination block. The ADC can then transfer the HG data to the ISP, as Figure 4 shown.

[0097] Returning to block 1015, if the predetermined threshold is satisfied, then method 1000 proceeds to block 1020B.

[0098] In block 1020B, the LG data is selected by a determination block. The ADC can then transfer the LG data to the ISP, as Figure 4 shown.

[0099] Figure 11Another method 1100 for generating a combined converted value for a pixel in a pixel circuit according to an embodiment of the present disclosure. In some embodiments, the method 1100 is performed using the Figure 6A pixel circuit. In some embodiments, the method 1100 occurs concurrently with or after the method 900.

[0100] In block 1110, at least one of a plurality of determination blocks transmits a determination timing pulse at a predetermined time. In some embodiments, this is achieved by one or more saturation determination blocks (such as the plurality of saturation determination blocks 615A, 615B). In some embodiments, the predetermined time is during a high-gain (HG) signal voltage ramp. In operation, the determination timing pulse determines whether a comparator (such as comparator 511 or 611) is flipped at the predetermined time. As Figure 6B shown, a comparator in high light does not flip before the signal voltage ramp of the HG signal reaches the end, while a comparator receiving low light flips earlier in the ramp signal of the HG signal. In this way, the predetermined threshold is whether the comparator is flipped. When the comparator has not flipped, the determination block selects LG data, and when the comparator has flipped, the determination block selects HG data. Therefore, based on the determination timing pulse at the HG signal voltage ramp, LG data is selected when there is high light, and HG data is selected when there is low light.

[0101] In decision block 1115, it is determined whether a predetermined threshold is satisfied. As described herein, in some embodiments, the predetermined threshold is the saturation state of a high-gain (HG) code. In some embodiments, the predetermined threshold is based on a low-gain data (LG) code, or a combination of an LG code and an HG code. If the predetermined threshold is not satisfied, the method 1100 proceeds to block 1120A.

[0102] In block 1120A, the determination block selects HG data.

[0103] Returning to block 1115, if the predetermined threshold is satisfied, the method 1100 proceeds to block 1120B.

[0104] In block 1120B, the determination block selects LG data.

[0105] Figure 12 Another method 1200 for generating a combined converted value for a pixel in a pixel circuit according to an embodiment of the present disclosure. In some embodiments, the method 1200 is performed using the pixel circuit 700. In some embodiments, the method 1200 occurs concurrently with or after the method 900.

[0106] In block 1210, the output of a respective one of a plurality of ADCs (e.g., a plurality of ADCs 511A, 511B) is compared with a predetermined threshold. In some embodiments, the predetermined threshold includes a first threshold and a second threshold. In some embodiments, both the first threshold and the second threshold are based on a high gain (HG) code. In some embodiments, the first threshold, the second threshold, or both are based on a low gain (LG) code or both an HG code and an LG code, such as as Figure 8C shown in

[0107] In decision block 1215, it is determined whether the first threshold is satisfied. As described herein, in some embodiments, the first threshold is based on a high gain (HG) code. In some embodiments, the first threshold is about 768 kHz. If the first threshold is not satisfied, then method 1200 proceeds to block 1220.

[0108] In block 1220, high gain (HG) data is selected by a decision block. In some embodiments, when the HG code is below about 768 kHz, the HG data is transmitted to the ISP, such as ISP 411.

[0109] Returning to block 1215, if the predetermined threshold is satisfied, then method 1200 proceeds to block 1225.

[0110] In decision block 1225, it is determined whether the second threshold is satisfied. As described herein, in some embodiments, the second threshold is also based on an HG code. In some embodiments, the second threshold is about 1023 kHz. If the second threshold is not satisfied, then method 1200 proceeds to block 1230A.

[0111] Optionally, in block 1230A, a combination of high gain (HG) data and low gain (LG) data is selected by a decision block. In some embodiments, when the HG code is between about 768 kHz and 1023 kHz, a mixture or combination of HG data and LG data is transmitted.

[0112] Returning to block 1225, if the second threshold is satisfied, then method 1200 proceeds to block 1230B.

[0113] In block 1230B, low gain (LG) data is selected by a decision block. In some embodiments, when the HG data is above about 1023 kHz, the LG data is transmitted.

[0114] It should be understood that all methods 900, 1000, 1100, and 1200 are to be interpreted as merely representative. In some embodiments, the process blocks of all methods 900, 1000, 1100, and 1200 may be executed simultaneously, sequentially, in a different order, or even omitted, without departing from the scope of the present disclosure.

Claims

1. A pixel circuit, comprising: a pixel array comprising a plurality of pixels; a plurality of analog-to-digital converters, wherein during a pixel data readout period, the plurality of analog-to-digital converters are communicatively coupled to a corresponding plurality of pixels to receive image data from corresponding pixels of the plurality of pixels; a plurality of decision blocks, wherein each decision block is communicatively coupled to a respective one of the plurality of analog-to-digital converters, and wherein each decision block is configured to select and transmit gain data based on comparing an output of the respective analog-to-digital converter to a predetermined threshold of the respective analog-to-digital converter; and An image signal processor configured to: receiving outputs from the plurality of analog-to-digital converters; and The outputs of the plurality of analog-to-digital converters are combined to produce a combined converted value for the corresponding pixel. 2 . The pixel circuit according to claim 1 , wherein the gain data is selected from high gain data, low gain data, or a combination thereof. The pixel circuit according to claim 2 , wherein the predetermined threshold is based on the high gain data.

4. The pixel circuit according to claim 2, wherein: When the predetermined threshold is met or exceeded, a corresponding decision block among the plurality of decision blocks selects the low gain data; and When the predetermined threshold is not satisfied, a corresponding judgment block among the plurality of judgment blocks selects the high gain data. 5 . The pixel circuit according to claim 1 , wherein the plurality of analog / digital converters include at least two analog / digital converters, and the plurality of determination blocks include at least two determination blocks.

6. The pixel circuit according to claim 1, wherein the predetermined threshold is based on at least one judgment timing pulse of the plurality of judgment blocks, wherein the judgment timing pulse provides a trigger signal for determining whether a comparator of each of the plurality of analog / digital converters is flipped at a predetermined time.

7. The pixel circuit according to claim 2, wherein: The predetermined threshold comprises a first threshold; and When the high gain data is lower than the first threshold, the high gain data is selected.

8. The pixel circuit according to claim 7, wherein: The predetermined threshold further includes a second threshold; and When the high gain data is higher than the second threshold, the low gain data is selected. 9 . The pixel circuit according to claim 8 , wherein when the high gain data is between the first threshold and the second threshold, a mixture of the high gain data and the low gain data is selected. 10 . The pixel circuit of claim 9 , wherein the mixing of the high gain data and the low gain data is a ratio of the high gain data to the low gain data based on the high gain data. 11 . The pixel circuit according to claim 10 , wherein the mixing of the high gain data and the low gain data is a ratio of the high gain data to the low gain data based on the high gain data and the low gain data. 12 . The pixel circuit of claim 10 , wherein the first threshold is approximately a 768-bit value and the second threshold is approximately a 1023-bit value.

13. A method of generating a combined converted value of a pixel circuit, the pixel circuit comprising: A pixel array comprising a plurality of pixels; a plurality of analog-to-digital converters, wherein during pixel data readout, the plurality of analog-to-digital converters are communicatively coupled to a corresponding plurality of pixels to receive image data from corresponding pixels of the plurality of pixels; and a plurality of decision blocks, wherein each decision block is communicatively coupled to a corresponding analog-to-digital converter of the plurality of analog-to-digital converters, and wherein each decision block is configured to select and transmit gain data based on comparing an output of the corresponding analog-to-digital converter with a predetermined threshold of the corresponding analog-to-digital converter, the method comprising: transmitting the image data from each corresponding pixel of the plurality of pixels to the plurality of analog-to-digital converters; comparing the output of the corresponding analog-to-digital converter with the predetermined threshold of the corresponding analog-to-digital converter; selecting the gain data from the output of each analog-to-digital converter using each decision block of the plurality of decision blocks; transmitting the gain data of each of the plurality of analog-to-digital converters to an image signal processor; receiving, using the image signal processor, outputs from the plurality of analog-to-digital converters; and The outputs of the plurality of analog-to-digital converters are combined to produce a combined converted value for the corresponding pixel. The method of claim 13 , wherein the gain data is selected from high gain data, low gain data, or a combination thereof.

15. The method according to claim 14, wherein the method further comprises: When the predetermined threshold is met, selecting the low gain data using a corresponding judgment block among the plurality of judgment blocks; and When the predetermined threshold is not satisfied, the high gain data is selected using the corresponding judgment block among the plurality of judgment blocks. The method of claim 14 , wherein the predetermined threshold comprises a saturation state of the high gain data.

17. The method of claim 14, wherein the method further comprises: Using at least one of the plurality of judgment blocks to issue a judgment timing pulse at a predetermined time; measuring the output of each of the plurality of analog-to-digital converters at the predetermined time; When the comparator of the analog / digital converter is not flipped, selecting the high gain data; and When the comparator of the analog / digital converter is flipped, the low gain data is selected.

18. The method of claim 14, wherein the predetermined threshold comprises a first threshold and a second threshold, and wherein the method further comprises: When the high gain data is lower than the first threshold, selecting the high gain data; and When the high gain data is higher than the second threshold, the low gain data is selected. 19 . The method of claim 18 , wherein the method further comprises, when the high gain data is between the first threshold and the second threshold, selecting and transmitting a mixture of the high gain data and the low gain data.

20. A method of generating a combined converted value of a pixel circuit according to claim 1, the method comprising: transmitting the image data from each corresponding pixel of the plurality of pixels to the plurality of analog-to-digital converters; comparing the output of the corresponding analog-to-digital converter with the predetermined threshold of the corresponding analog-to-digital converter; selecting the gain data from the output of each analog-to-digital converter using each decision block of the plurality of decision blocks; transmitting the gain data of each analog / digital converter of the plurality of analog / digital converters to the image signal processor; receiving, using the image signal processor, outputs from the plurality of analog-to-digital converters; and The outputs of the plurality of analog-to-digital converters are combined to produce a combined converted value for the corresponding pixel.

Images