Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. According to one embodiment, a semiconductor device includes a first wiring provided in a first direction of a first insulating film. The first wiring is arranged in the second direction and extends in the third direction. The second insulating films are correspondingly provided on the first wirings, respectively. The width of each surface of the second insulating film in the second direction that is in contact with the first wiring is narrower than the width of the first wiring corresponding thereto. The third insulating films are correspondingly provided on the first wirings, respectively, and cover both side surfaces of the second insulating film, respectively. The fourth insulating film is provided on the third insulating film, and the fifth insulating film is provided on the fourth insulating film. The first contact passes through the second to fifth insulating films and is connected to the first wiring. The second wiring is provided on the first contact. A first contact is provided in a first direction of the first wiring, or second and fourth insulating films are provided.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] There are cases where a semiconductor memory device such as a NAND type flash memory has a three-dimensional memory cell array in which a plurality of memory cells are three-dimensionally arranged. As the memory cell array is miniaturized, the interval between adjacent wirings becomes narrow. Thereby, an increase in the parasitic capacitance between the wirings and the parasitic capacitance between the wiring and the via contact is feared. Summary of the Invention

[0003] Provided are a semiconductor device and a method for manufacturing the same that can suppress the parasitic capacitance between wirings or the parasitic capacitance between a wiring and a via contact to a low level.

[0004] The semiconductor device of this embodiment includes a plurality of first wirings provided in a first direction with respect to a first insulating film. The plurality of first wirings are arranged in a second direction intersecting the first direction and extend in a third direction intersecting the first and second directions. A plurality of second insulating films are respectively provided corresponding to the plurality of first wirings. The width of each of the surfaces of the plurality of second insulating films in the second direction that are in contact with the first wiring is narrower than the width of the plurality of first wirings corresponding thereto in the second direction. A plurality of third insulating films are respectively provided corresponding to the plurality of first wirings, are arranged in the second direction, extend in the third direction, and respectively cover at least both side surfaces of the plurality of second insulating films. A fourth insulating film is provided on the plurality of third insulating films. A fifth insulating film is provided on the fourth insulating film. A first contact penetrates the second to fifth insulating films to connect to any one of the plurality of first wirings. A second wiring is provided on the first contact. The first contact is provided in the first direction of the first wiring, or at least the second and fourth insulating films are provided. Description of the Drawings

[0005] Figure 1 It is a cross-sectional view showing a configuration example of a semiconductor memory device according to the first embodiment.

[0006] Figure 2 It is a schematic plan view showing a laminate.

[0007] Figure 3 It is a schematic cross-sectional view illustrating a three-dimensional structure memory cell.

[0008] Figure 4 It is a schematic cross-sectional view illustrating a three-dimensional structure memory cell.

[0009] Figure 5 It is a cross-sectional view showing a configuration example of a bit line and its periphery of an array chip according to the first embodiment.

[0010] Figure 6It is a cross-sectional view showing an example of a manufacturing method of an array chip according to the first embodiment.

[0011] Figure 7 It is a cross-sectional view showing an example of a manufacturing method of an array chip for connecting Figure 6

[0012] Figure 8 It is a cross-sectional view showing an example of a manufacturing method of an array chip for connecting Figure 7

[0013] Figure 9 It is a cross-sectional view showing an example of a manufacturing method of an array chip for connecting Figure 8

[0014] Figure 10 It is a cross-sectional view showing an example of a manufacturing method of an array chip for connecting Figure 9

[0015] Figure 11 It is a cross-sectional view showing an example of a manufacturing method of an array chip for connecting Figure 10

[0016] Figure 12 It is a cross-sectional view showing an example of a manufacturing method of an array chip for connecting Figure 11

[0017] Figure 13 It is a cross-sectional view showing an example of a manufacturing method of an array chip for connecting Figure 12

[0018] Figure 14 It is a cross-sectional view showing an example of the configuration of a bit line and its periphery of an array chip according to the second embodiment.

[0019] Figure 15 It is a cross-sectional view showing an example of a manufacturing method of an array chip according to the second embodiment.

[0020] Figure 16 It is a cross-sectional view showing an example of the configuration of a bit line and its periphery of an array chip according to the third embodiment.

[0021] Figure 17 It is a cross-sectional view showing an example of a manufacturing method of an array chip according to the third embodiment.

[0022] Figure 18 It is a cross-sectional view showing an example of a manufacturing method of an array chip for connecting Figure 17

[0023] Figure 19 It is a cross-sectional view showing an example of a manufacturing method of an array chip for connecting Figure 18

[0024] Figure 20 This is a cross-sectional view showing an example of a method for manufacturing an array chip indicating connection. Figure 19

[0025] Figure 21 This is a cross-sectional view showing an example of a method for manufacturing an array chip indicating connection. Figure 20

[0026] Figure 22 This is a cross-sectional view showing an example of a method for manufacturing an array chip indicating connection. Figure 21

[0027] Figure 23 This is a cross-sectional view showing an example of the configuration of a bit line and its periphery of an array chip according to the fourth embodiment.

[0028] Figure 24A This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the fifth embodiment.

[0029] Figure 24B This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the fifth embodiment.

[0030] Figure 25A This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device indicating connection. Figure 24A

[0031] Figure 25B This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device indicating connection. Figure 24B

[0032] Figure 26A This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device indicating connection. Figure 25A

[0033] Figure 26B This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device indicating connection. Figure 25B

[0034] Figure 27A This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device indicating connection. Figure 26A

[0035] Figure 27B This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device indicating connection. Figure 26B

[0036] Figure 28 This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device indicating connection. Figure 27B

[0037] Figure 29 This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device indicating connection. Figure 28A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0038] Figure 30 It represents a connection Figure 29 A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0039] Figure 31A It represents a connection Figure 27A A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0040] Figure 31B It represents a connection Figure 30 A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0041] Figure 32 It is a cross-sectional view showing a comparative example.

[0042] Figure 33 It is a block diagram showing a configuration example of a semiconductor memory device using an application array chip.

[0043] Figure 34 It is a circuit diagram showing an example of the circuit configuration of a memory cell array. Detailed implementation mode

[0044] Hereinafter, embodiments of the present invention will be described with reference to the drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual. The same reference numerals are assigned to the same elements in the specification and the drawings.

[0045] (First Embodiment)

[0046] Figure 1 It is a cross-sectional view showing a configuration example of a semiconductor memory device 1 according to the first embodiment. Hereinafter, the stacking direction of the stacked body 20 is defined as the Z direction. One direction intersecting with the Z direction, for example, orthogonal, is defined as the Y direction. One direction intersecting with each of the Z direction and the Y direction, for example, orthogonal, is defined as the X direction. In addition, in this specification, the ±Z direction is an example of the first direction. The ±X direction is an example of the third direction, and the ±Y direction is an example of the second direction.

[0047] The semiconductor memory device 1 includes an array chip 2 having a memory cell array and a CMOS chip 3 having a CMOS (Complementary Metal - Oxide - Semiconductor) circuit. The array chip 2 and the CMOS chip 3 are bonded on a bonding surface B1 and are electrically connected to each other via wirings bonded on the bonding surface. Figure 1 The state where the array chip 2 is provided on the CMOS chip 3 is shown.

[0048] The CMOS chip 3 includes a substrate 30, transistors 31, vias 32, wirings 33 and 34, and an interlayer insulating film 35.

[0049] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an NMOS (N-channel type metal oxide semiconductor) or PMOS (P-channel type metal oxide semiconductor) transistor provided on the substrate 30. The transistor 31, for example, constitutes a CMOS circuit that controls the memory cell array of the array chip 2. A plurality of transistors 31 constitute logic circuits such as sense amplifiers, row decoders, and column decoders. Semiconductor elements such as resistance elements and capacitance elements other than the transistor 31 may also be formed on the substrate 30.

[0050] The via 32 is electrically connected between the transistor 31 and the wiring 33, or between the wiring 33 and the wiring 34. The wirings 33 and 34 form a multilayer wiring structure within the interlayer insulating film 35. The wiring 34 is buried in the interlayer insulating film 35 and exposed substantially flush with the surface of the interlayer insulating film 35. The wirings 33 and 34 are electrically connected to the transistor 31 and the like. The via 32, the wirings 33 and 34 are made of, for example, metals such as copper and tungsten. The interlayer insulating film 35 covers and protects the transistor 31, the via 32, the wirings 33 and 34. The interlayer insulating film 35 is made of, for example, an insulating film such as a silicon oxide film.

[0051] The array chip 2 includes a laminate 20, a columnar body CL, a slit ST(LI), a source electrode layer BSL, a metal layer 40, a contact plug CCw, a contact plug 29, a bonding pad 50, and an interlayer insulating film 25.

[0052] The laminate 20 is provided above the transistor 31 and is in the Z direction with respect to the substrate 30. The laminate 20 is formed by alternately laminating a plurality of electrode films 21 and a plurality of insulating films 22 along the Z direction. The laminate 20 constitutes a memory cell array. The electrode film 21 is made of, for example, a conductive metal such as tungsten. The insulating film 22 is made of, for example, an insulating film such as a silicon oxide film. The insulating film 22 insulates the electrode films 21 from each other. That is, the plurality of electrode films 21 are laminated in an insulated state. The number of laminations of the electrode film 21 and the insulating film 22 is arbitrary. The insulating film 22 may be, for example, a porous insulating film or an air gap.

[0053] One or more electrode films 21 at the upper and lower ends of the laminate 20 in the Z direction function as a source-side select gate SGS and a drain-side select gate SGD, respectively. The electrode film 21 between the source-side select gate SGS and the drain-side select gate SGD functions as a word line WL. The word line WL is a gate electrode of the memory cell MC. The source-side select gate SGS is a gate electrode of the source-side select transistor. The drain-side select gate SGD is a gate electrode of the drain-side select transistor. The source-side select gate SGS is provided in the upper region of the laminate 20. The drain-side select gate SGD is provided in the lower region of the laminate 20. The upper region refers to the region of the laminate 20 away from the CMOS chip 3 side (close to the metal layer 40 side), and the lower region refers to the region of the laminate 20 close to the CMOS chip 3 side.

[0054] The semiconductor memory device 1 has a plurality of memory cells MC connected in series between a source-side select transistor and a drain-side select transistor. The structure in which the source-side select transistor, the memory cell MC, and the drain-side select transistor are connected in series is called a "memory string" or a "NAND string". The memory string is connected to the bit line BL via a via hole 28, for example. The bit line BL is a wiring 23 provided below the laminate 20 and extending in the X direction ( Figure 1 the paper surface direction). Therefore, hereinafter, the bit line BL is also referred to as the bit line 23.

[0055] A plurality of columns CL are provided in the laminate 20. The columns CL extend in the laminate 20 so as to penetrate the laminate 20 along the stacking direction (Z direction) of the laminate, and are provided from the via hole 28 connected to the bit line 23 to the source layer BSL. The internal structure of the column CL will be described later. In the present embodiment, it is formed in two segments along the Z direction. However, it is also possible for the column CL to be in one segment. Alternatively, the column CL may be formed in three or more segments.

[0056] In addition, Figure 1 Although not shown, a plurality of slits ST (refer to Figure 2 ) are provided in the laminate 20. The slits ST extend in the Y direction and penetrate the laminate 20 in the stacking direction (Z direction) of the laminate. An insulating film such as a silicon oxide film is filled in the slits ST, and the insulating film is configured in a plate shape. The slits ST electrically separate the electrode films 21 of the laminate 20. Alternatively, an insulating film such as a silicon oxide film may be covered on the inner wall of the slits ST, and a conductive material may be further buried inside the insulating film. In this case, the conductive material can also function as a source wiring reaching the source layer BSL.

[0057] A source electrode layer BSL is provided on the laminate 20. The source electrode layer BSL is an example of a first semiconductor layer. The source electrode layer BSL is provided corresponding to the laminate 20. The source electrode layer BSL has a first surface F1 and a second surface F2 opposite to the first surface F1. The laminate 20 (memory cell array) is provided on the first surface F1 side of the source electrode layer BSL, and the metal layer 40 is provided on the second surface F2 side. The metal layer 40 includes a source line 41 and a power line 42. The source electrode layer BSL is commonly connected to one ends of a plurality of columnar bodies CL, and provides a common source potential to the plurality of columnar bodies CL located in the same memory cell array 2m. That is, the source electrode layer BSL functions as a common source electrode of the memory cell array 2m. The source electrode layer BSL is made of a conductive material such as doped polysilicon, for example. The metal layer 40 is made of a metal material having a lower resistance than the source electrode layer BSL, such as copper, aluminum, or tungsten, for example. In addition, 2s is a step portion of the electrode film 21 provided to connect the contact plug CCw to each electrode film 21. Regarding the step portion 2s, refer to Figure 2 which will be described later.

[0058] On the other hand, a bonding pad 50 is provided in a region above the laminate 20 and where the source electrode layer BSL is not provided. The bonding pad 50 is connected to a metal wire or the like (not shown), and receives power supply or signals from the outside of the semiconductor memory device 1. The bonding pad 50 is provided so as to be connected to one end in the Z direction of the contact plug 29. The bonding pad 50 is connected to the transistor 31 of the CMOS chip 3 via the contact plug 29, the wiring 24, and the wiring 34. Therefore, the external power supply supplied from the bonding pad 50 is supplied to the transistor 31. Alternatively, signals are supplied to the transistor 31 or the memory cell array 2m via the bonding pad 50.

[0059] The contact plug CCw is provided in the peripheral portion of the laminate 20 and extends in the Z direction within the interlayer insulating film 25. The contact plug CCw is electrically connected between the electrode film 21 (word line WL) and the wiring 24. The contact plug CCw is provided in the step portion 2s formed in a stepped shape at the end of the laminate 20 and is electrically connected to each electrode film 21. The contact plug CCw is provided to transfer the word line voltage from the CMOS chip 3 to each electrode film 21. The contact plug CCw is made of a metal such as copper or tungsten, for example.

[0060] The contact plug 29 is provided in the peripheral portion of the laminate 20 and extends in the Z direction along the interlayer insulating film 25. The contact plug 29 is a contact plug provided from the wiring 24 to the bonding pad 50. The contact plug 29 is formed simultaneously with the contact plug CCw connected to the word line WL in the same process.

[0061] The contact plug 29 is electrically connected between the bonding pad 50 and the wiring 24. The contact plug 29 is used to supply the power supply voltage or signal from the bonding pad 50 to the array chip 2 or the CMOS chip 3. The contact plug 29 is made of a metal such as copper or tungsten, for example. The power supply voltage is, for example, the power supply voltage VDD or a reference voltage (such as a ground voltage) VSS lower than the power supply voltage VDD. The signal can be a control signal from the outside or write data or read data.

[0062] In the present embodiment, the array chip 2 and the CMOS chip 3 are formed individually and bonded with the bonding surface B1. Therefore, the transistor 31 is not provided in the array chip 2. In addition, the laminate 20 (memory cell array) is not provided in the CMOS chip 3. Both the transistor 31 and the laminate 20 are on the first surface F1 side of the source layer BSL. The transistor 31 is on the opposite side of the second surface F2 where the metal layer 40 is located.

[0063] The vias 28, the wiring 23, and the wiring 24 are provided below the laminate 20. The wirings 23 and 24 are buried in the interlayer insulating film 25. The wiring 24 is exposed substantially flush with the surface of the interlayer insulating film 25. The wirings 23 and 24 are electrically connected to the semiconductor body 210 of the columnar body CL or the like. The vias 28, the wiring 23, and the wiring 24 are made of a metal such as copper or tungsten, for example. The interlayer insulating film 25 covers and protects the laminate 20, the vias 28, the wiring 23, and the wiring 24. The interlayer insulating film 25 is an insulating film such as a silicon oxide film, for example.

[0064] The interlayer insulating film 25 and the interlayer insulating film 35 are bonded on the bonding surface B1. Along with this, the wiring 24 and the wiring 34 are bonded substantially flush on the bonding surface B1. Thus, the array chip 2 and the CMOS chip 3 are electrically connected via the wiring 24 and the wiring 34.

[0065] Figure 2 is a schematic plan view showing the laminate 20. The laminate 20 includes a step portion 2s and a memory cell array 2m. The step portion 2s is provided at the end of the laminate 20, for example. The memory cell array 2m is sandwiched or surrounded by the step portion 2s. The slit ST(LI) is provided from the step portion 2s at one end of the laminate 20 through the memory cell array 2m to the step portion 2s at the other end of the laminate 20. The slit SHE is provided at least in the memory cell array 2m. The slit SHE is shallower than the slit ST(LI) in the Z direction and extends substantially parallel to the slit ST(LI). The slit SHE electrically separates the electrode film 21 for each drain-side select gate SGD. In addition, the slit ST can also be a source wiring LI that is electrically separated from the electrode film 21 of the laminate 20 and electrically connected to the source layer BSL. That is, the slit ST can also be a source wiring LI that is electrically separated from the electrode film 21 of the laminate 20 constituting the memory cell array and electrically connected to the source layer BSL.

[0066] Figure 2 The portion of the laminate 20 sandwiched between two slits ST as shown is called a block. A block constitutes, for example, the smallest unit for data erasure. A slit SHE is provided within the block. The laminate 20 between the slit ST and the slit SHE is called a finger. The drain-side select gate SGD is divided by each finger. Therefore, at the time of writing and reading data, one finger within the block can be set to a selected state through the drain-side select gate SGD.

[0067] Figure 3 and Figure 4 are schematic cross-sectional views each illustrating a three-dimensional structure of a memory cell. A plurality of columnar bodies CL are each provided within a memory hole MH provided in the laminate 20. Each columnar body CL penetrates through the laminate 20 from one end portion of the laminate 20 along the Z direction and is provided within the laminate 20 and in the source layer BSL. The plurality of columnar bodies CL each include a semiconductor main body 210, a storage film 220, and a core layer 230. The columnar body CL includes a core layer 230 provided at its central portion, a semiconductor main body (semiconductor component) 210 provided around the core layer 230, and a storage film 220 provided around the semiconductor main body 210. The semiconductor main body 210 extends in the stacking direction (Z direction) within the laminate 20. The semiconductor main body 210 is electrically connected to the source layer BSL. The storage film 220 is provided between the semiconductor main body 210 and the electrode film 21 and has a charge trapping portion. A plurality of columnar bodies CL each selected one by one from each finger are commonly connected to one bit line 23 through a through hole 28 of Figure 1 . The columnar bodies CL are each provided in, for example, the area of the memory cell array 2m.

[0068] As Figure 4 shown, the shape of the memory hole MH in the X-Y plane is, for example, a circle or an ellipse. A blocking insulating film 221a constituting a part of the storage film 220 may be provided between the electrode film 21 and the insulating film 22. The blocking insulating film 221a is, for example, a silicon oxide or a metal oxide. One example of the metal oxide is aluminum oxide. A barrier film 21b may be provided between the electrode film 21 and the insulating film 22 and between the electrode film 21 and the storage film 220. The barrier film 21b is, for example, a laminated film of titanium nitride and titanium when the electrode film 21 is tungsten. The blocking insulating film 221a suppresses the reverse tunneling of charges from the electrode film 21 to the storage film 220 side. The barrier film 21b improves the adhesion between the electrode film 21 and the blocking insulating film 221a.

[0069] The shape of the semiconductor body 210 is, for example, a cylindrical shape with a bottom. The semiconductor body 210 is made of, for example, polysilicon. The semiconductor body 210 is, for example, undoped silicon. In addition, the semiconductor body 210 may also be p-type silicon. The semiconductor body 210 serves as the channel of each of the drain-side select transistor, the memory cell MC, and the source-side select transistor. That is, the plurality of memory cells MC have a storage region between the semiconductor body 210 and the electrode film 21 serving as the word line WL, and are stacked in the Z direction. One ends of the plurality of semiconductor bodies 210 within the same memory cell array 2m are commonly electrically connected to the source layer BSL.

[0070] The storage film 220 includes, for example, a capping insulating film 221, a charge trapping film 222, a tunnel insulating film 223, and a blocking insulating film 221a. In the storage film 220, portions other than the blocking insulating film 221a are provided between the inner wall of the storage hole MH and the semiconductor body 210. The shape of the storage film 220 is, for example, cylindrical. The charge trapping film 222 and the tunnel insulating film 223 each extend in the Z direction.

[0071] The capping insulating film 221 is provided between the insulating film 22 and the charge trapping film 222, and between the blocking insulating film 221a and the charge trapping film 222. The capping insulating film 221 includes, for example, silicon oxide. The capping insulating film 221 protects the charge trapping film 222 from being etched when replacing a sacrificial film (not shown) with the electrode film 21 (replacement process). In addition, when the replacement process is not used in the formation of the electrode film 21, the capping insulating film 221 may not be provided.

[0072] The charge trapping film 222 is provided between the capping insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 includes, for example, silicon nitride and has trapping points for trapping charges in the film. The portion of the charge trapping film 222 sandwiched between the electrode film 21 serving as the word line WL and the semiconductor body 210 constitutes the storage region of the memory cell MC as a charge trapping portion. The threshold voltage of the memory cell MC varies according to the presence or absence of charges in the charge trapping portion, or the amount of charges trapped in the charge trapping portion. Thus, the memory cell MC stores information.

[0073] The tunnel insulating film 223 is provided between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 includes, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when injecting electrons from the semiconductor body 210 into the charge trapping film 222 (write operation), and when injecting holes from the semiconductor body 210 into the charge trapping film 222 (erase operation), the electrons and holes respectively pass through the potential barrier of the tunnel insulating film 223 (tunneling).

[0074] The core layer 230 is embedded in the internal space of the cylindrical semiconductor body 210. The shape of the core layer 230 is, for example, columnar. The core layer 230 contains, for example, silicon oxide and is insulating.

[0075] Figure 5 It is a cross-sectional view showing a configuration example of a bit line and its periphery of the array chip according to the first embodiment. In addition, Figure 5 represents Figure 1 a configuration that is inverted up and down. Therefore, hereinafter, the -Z direction will be described as the upper direction. In addition, Figure 5 It shows a structure above the columnar body CL (in the -Z direction), and the illustration of the structure below the columnar body CL is omitted.

[0076] The array chip 2 includes insulating films 25a to 25d, via contacts 28a, bit lines 23 (BL), insulating films 60, 70, via contacts 28b, and wirings 24.

[0077] The insulating film 25a is provided above the laminate 20 and the columnar body CL. The insulating film 25a uses, for example, an insulating material such as a silicon oxide film.

[0078] The via contact 28a is embedded in the insulating film 25a. The via contact 28a is provided so as to penetrate the insulating film 25a from the upper surface in the Z direction to the lower surface. The via contact 28a is electrically connected between the semiconductor body 210 of the columnar body CL and the bit line 23. The via contact 28a includes a barrier metal 28a1 and a contact body 28a2 embedded inside the barrier metal. The barrier metal uses, for example, a conductive metal material such as a titanium film or a titanium nitride film. The contact body uses, for example, a conductive metal material such as tungsten.

[0079] The insulating film 25b is provided on the insulating film 25a. The insulating film 25b is provided between adjacent multiple bit lines 23 and between adjacent multiple insulating films 70. The insulating film 25b uses, for example, an insulating material such as a silicon oxide film.

[0080] Multiple bit lines 23 are provided in the -Z direction with respect to the insulating film 25a and are embedded in the insulating film 25b. The multiple bit lines 23 extend in the X direction on the upper surface of the insulating film 25a and are arranged in the Y direction. The bit line 23 uses, for example, a conductive metal material such as tungsten or copper.

[0081] Multiple insulating films 60 are provided in a region where the via contact 28b does not contact on the upper surfaces of the multiple bit lines 23. The multiple insulating films 60 contact the upper surfaces F23a of the respectively corresponding bit lines 23. On the contact surface between the insulating film 60 and the bit line 23, the width W60 of the insulating film 60 in the Y direction is narrower than the width Wbl of the corresponding bit line 23 in the Y direction. The insulating film 60 uses a material film containing silicon and oxygen, and uses, for example, an insulating material such as a silicon nitride film.

[0082] A plurality of insulating films 70 are respectively disposed corresponding to the regions of the plurality of bit lines 23. The insulating film 70 is disposed on the bit line 23 where the via contact 28b is not provided so as to cover the upper surface and the side surface of the insulating film 60. That is, the insulating film 70 has an inverted U shape and covers the insulating film 60. In addition, the insulating film 70 is also disposed on the side surface of the via contact 28b between the adjacent insulating films 60. The insulating film 70 is disposed between the insulating film 60 and the insulating film 25c. In addition, on the contact surface between the insulating film 70 and the bit line 23, the width W70 of the insulating film 70 in the Y direction is substantially the same as the width Wbl of the corresponding bit line 23 in the Y direction. The insulating film 70 uses a material film containing silicon and nitrogen, for example, an insulating material such as a silicon oxynitride film. The insulating films 60 and 70 are dissimilar materials with different etching selectivities. Thus, either the insulating film 60 or 70 can be selectively etched. In addition, the insulating film 70 is a (Low-k) material having a relative dielectric constant lower than that of the insulating film 60.

[0083] The insulating film 25d is disposed on the insulating film 25c. The insulating films 25c and 25d are dissimilar materials with different etching selectivities. Therefore, when a contact hole is formed in the insulating film 25d, the insulating film 25c functions as an etching stop layer. The insulating film 25c uses an insulating material such as a silicon nitride film, for example. The insulating film 25d uses an insulating material such as a silicon oxide film, for example.

[0084] The via contact 28b is buried in the insulating films 25c and 25d. In addition, the via contact 28b penetrates a part of the insulating films 60 and 70 and is connected to the bit line 23. The via contact 28b is disposed so as to penetrate the insulating films 25d, 25c, and 60 from the upper surface of the insulating film 25d to the lower surface of the insulating film 60. The via contact 28b is electrically connected between the wiring 24 and the bit line 23. Thus, the wiring 24 can be electrically connected to any bit line 23 via the via contact 28b. In a plan view observed from the Z direction, the via contact 28b can be substantially circular, substantially elliptical, or substantially polygonal. Therefore, outside the formation region of the via contact 28b, the insulating films 60 and 70 are disposed on the bit line 23. That is, the via contact 28b is disposed in the Z direction of the bit line 23, or at least the insulating films 60 and 70 are disposed. The via contact 28b includes a barrier metal 28b1 and a contact body 28b2 buried inside the barrier metal. The barrier metal uses a conductive metal material such as a titanium film or a titanium nitride film, for example. The contact body uses a conductive metal material such as tungsten, for example.

[0085] The via contact 28b is formed self-integrally from the insulating film 25c through the insulating films 70 and 60. Accordingly, the via contact 28b has a step STP at the same height as the lower surface of the insulating film 25c. Further, at the same height as the lower surface of the insulating film 25c, the width W28b1 of the via contact 28b in the X or Y direction is wider than the width W28b2 of the via contact 28b in the X or Y direction on the connection surface with the bit line 23. Further, the width W28b2 is narrower than the width Wbl of the bit line 23 in the Y direction. The width W28b1 of the via contact 28b in the X or Y direction gradually becomes smaller from the wiring 24 toward the bit line 23, and further becomes narrower and thinner to the width W28b2 with the step STP at the lower surface of the insulating film 25c. Both side surfaces of the via contact 28b having the width W28b2 are sandwiched by the insulating films 70. Further, in the bit line 23, the width Wbl becomes wider. Thus, the via contact 28b is configured in a bottleneck shape between the insulating films 70.

[0086] The wiring 24 is provided on the via contact 28b and the insulating film 25d. The wiring 24 applies power to the semiconductor body 210 of the columnar body CL via the bit line BL. Further, the wiring 24 is electrically connected to the sense amplifier module (refer to Figure 33 ), and transmits a signal voltage based on data read from the memory cell MC to the sense amplifier module. The wiring 24 uses a conductive metal material such as tungsten or copper, for example.

[0087] In the array chip 2 of the present embodiment, in a region where the via contact 28b is not provided, the insulating films 60 and 70 are provided on the bit line 23. As described above, the insulating film 70 is, for example, a silicon oxynitride film or the like, and has a relative dielectric constant lower than that of the insulating film 60 (for example, a silicon oxynitride film or the like). The insulating film 60 is covered with the insulating film 70 having a relatively low relative dielectric constant. Accordingly, the parasitic capacitance PC1 between adjacent multiple bit lines 23, the parasitic capacitance PC2 between the via contact 28b and the bit line 23, and the parasitic capacitance PC3 between the wiring 24 and the bit line 23 are reduced as compared with the case where the insulating film 70 is not provided. When the capacitance due to the winding around the upper surface from one bit line 23 to other bit lines 23 is taken into consideration, the parasitic capacitance PC1 between adjacent multiple bit lines 23 is considered to be reduced by the insulating film 70.

[0088] By reducing the parasitic capacitance PC1 between adjacent multiple bit lines 23, the parasitic capacitance PC2 between the via contact 28b and the bit line 23, and the parasitic capacitance PC3 between the wiring 24 and the bit line 23, it is possible to narrow the interval between the arrangements of the multiple bit lines 23 in the Y direction. Further, the interval between the bit line 23 and the via contact 28b and the interval between the bit line 23 and the wiring 24 can also be narrowed. As a result, it contributes to the miniaturization of the array chip 2.

[0089] Next, a method for manufacturing the array chip 2 of the present embodiment will be described.

[0090] Figures 6 - 13 It is a cross-sectional view showing an example of a method for manufacturing an array chip according to the first embodiment.

[0091] First, structures below the insulating film 25a such as the laminate 20 and the columnar body CL are formed.

[0092] Next, as Figure 6 shown, an insulating film (e.g., a silicon oxide film) 25a is stacked on the laminate 20 and the columnar body CL. Next, a contact hole CH1 leading to the columnar body CL is formed using photolithography and etching techniques. Next, a barrier metal (e.g., a laminate film of titanium and titanium nitride) 28a1 is formed on the inner wall of the contact hole CH1, and a material (e.g., tungsten) of the contact member body 28a2 is buried inside the barrier metal. Thus, Figure 6 the via contact 28a shown is formed so as to penetrate the insulating film 25a. The via contact 28a penetrates the insulating film 25a and electrically connects to the semiconductor body 210 of any columnar body CL.

[0093] Next, as Figure 7 shown, a material (e.g., tungsten) of the bit line 23 is stacked on the insulating film 25a (-Z direction). A material (e.g., a silicon nitride film) of the insulating film 60 is stacked on the surface F23a of the material of the bit line 23.

[0094] Next, the material of the insulating film 60 is processed using photolithography and etching techniques. Next, the material of the bit line 23 is processed using the insulating film 60 as a mask. Thus, as Figure 8 shown, a plurality of bit lines 23 arranged in the Y direction and extending in the X direction and a plurality of insulating films 60 are formed. The plurality of insulating films 60 are respectively provided on the upper surface F23a of the plurality of bit lines 23. On the contact surface between the insulating film 60 and the bit line 23, the width W60a of the insulating film 60 in the Y direction is substantially equal to the width Wbl of the bit line 23 in the Y direction.

[0095] Next, as Figure 9 shown, by oxidizing the surfaces of the plurality of insulating films 60, insulating films 70 are respectively formed on the upper surfaces and both side surfaces of the plurality of insulating films 60. That is, the exposed surfaces (upper surface and both side surfaces) of the insulating film 60 are oxidized to become the insulating film 70. For example, when the insulating film 60 is a silicon nitride film, the insulating film 70 becomes a silicon nitride film, or a mixed film of a silicon oxide film and a silicon nitride film. The silicon oxide film is a material having a relative dielectric constant lower than that of the silicon nitride film. At this time, the width W70 of the insulating film 70 in the Y direction is substantially equal to the width Wbl of the bit line 23 in the Y direction. However, the width W60 of the insulating film 60 in the Y direction is narrower than the width Wbl of the bit line 23 in the Y direction.

[0096] Next, a material of an insulating film (e.g., a silicon oxide film) 25b is stacked between adjacent ones of the plurality of bit lines 23 and between adjacent ones of the plurality of insulating films 70. Next, the insulating film 25b is polished by a CMP (Chemical Mechanical Polishing) method until the surface of the insulating film 70 is exposed. Thus, as Figure 10 shown, the insulating film 25b is buried between adjacent ones of the plurality of bit lines 23 and between adjacent ones of the plurality of insulating films 70.

[0097] Next, as Figure 11 shown, an insulating film (e.g., a silicon nitride film) 25c is stacked on the insulating films 25b and 70. Further, an insulating film (e.g., a silicon oxide film) 25d is stacked on the insulating film 25c.

[0098] Next, the insulating film 25d is processed using photolithography technology and etching technology. At this time, the insulating film 25c functions as an etch stop layer. Next, the insulating film 25c is etched using the insulating film 25d as a mask. Further, depending on the difference in etching selectivity between the insulating film 70 and the insulating film 25b, the insulating film 70 is etched self-alignedly with respect to the insulating film 25b. Thus, a step difference STP is generated. After etching the insulating film 70, the insulating film 60 is etched self-alignedly and selectively with respect to the insulating film 70. Thus, as Figure 12 shown, a contact hole CH2 is formed in the formation region of the via contact 28b. The contact hole CH2 penetrates the insulating films 25d, 25c, 70, and 60 and reaches the upper surface F23a of the bit line 23.

[0099] Next, a barrier metal (e.g., a stacked film of titanium and titanium nitride) 28b1 is formed on the inner wall of the contact hole CH2, and a material (e.g., tungsten) of the contact body 28b2 is buried inside the barrier metal 28b1. Thus, Figure 13 the via contact 28b shown is formed so as to penetrate the insulating films 25d, 25c, 70, and 60 and connect to the upper surface F23a of the bit line 23. The via contact 28b is electrically connected to the semiconductor body 210 of any one of the columnar bodies CL via the bit line 23. On the other hand, in a region where the contact hole CH2 is not provided, the insulating films 25d, 25c, 60, and 70 remain on the bit line 23.

[0100] Here, in the process of forming the contact hole CH2, the insulating film 60 is etched self-alignedly and selectively. Therefore, the via contact 28b has a step difference STP at the lower surface of the insulating film 25c or at the same height (height in the Z direction) as the upper surfaces of the insulating films 25c and 70. Around the via contact 28b between the step difference STP and the bit line 23, the insulating film 70 is provided in a cylindrical shape.

[0101] Next, as Figure 5As shown, wiring 24 is formed on the via contact 28b and the insulating film 25d. Thus, the Figure 5 configuration of the array chip 2 shown is obtained.

[0102] (Second Embodiment)

[0103] Figure 14 It is a cross-sectional view showing a configuration example of a bit line and its periphery of an array chip according to the second embodiment. In the second embodiment, the insulating film 70 (e.g., a silicon nitride film, or a mixed film of a silicon oxide film and a silicon nitride film) is not provided on the insulating film 60 (e.g., a silicon nitride film). Therefore, in the region where the via contact 28b is not provided, the insulating film 25c covers the upper surfaces of the respective insulating films 60 and contacts the insulating film 70. In addition, the insulating film 70 is provided on both side surfaces of the insulating film 60. Other configurations of the second embodiment may be the same as those of the first embodiment. Therefore, the second embodiment can achieve the same effects as the first embodiment.

[0104] Figure 15 It is a cross-sectional view showing an example of a manufacturing method of an array chip according to the second embodiment. The array chip 2 of the second embodiment undergoes the process described with reference to Figures 6 - 9 After the described process, in the Figure 10 shown process, when the insulating film 25b is polished by the CMP method, the insulating film 70 is over-polished until the upper surface of the insulating film 60 is exposed. Thus, the Figure 15 shown structure is obtained. Subsequently, by undergoing the process described with reference to Figures 11 - 13 the described process, the Figure 14 configuration of the array chip 2 shown is obtained.

[0105] (Third Embodiment)

[0106] Figure 16 It is a cross-sectional view showing a configuration example of a bit line and its periphery of an array chip according to the third embodiment. In the third embodiment, an air gap AG is provided between adjacent multiple bit lines 23. The upper end Etop of the air gap AG is located below the upper surface F23a of the bit line 23 in the (-Z direction). In addition, the lower end Ebtm of the air gap AG is located below the lower surface F23b of the bit line 23.

[0107] The relative dielectric constant of the air gap AG is lower than that of the insulating film 25b. Therefore, the parasitic capacitance PC1 between adjacent multiple bit lines 23 can be further reduced. By the lower end Ebtm of the air gap AG being lower than the lower surface F23b of the bit line 23, the parasitic capacitance PC1 between adjacent multiple bit lines 23 can be further reduced. In addition, the upper end Etop of the air gap AG is lower than the upper surface F23a of the bit line 23. This is to suppress the material of the via contact 28b from entering the air gap AG during the formation process of the via contact 28b, as described later.

[0108] The other configurations of the third embodiment may be the same as those of the first embodiment. Therefore, the third embodiment can achieve the same effects as the first embodiment. In addition, the third embodiment can be combined with the second embodiment.

[0109] Next, a method for manufacturing the array chip 2 of the third embodiment will be described.

[0110] Figures 17 - 22 It is a cross-sectional view showing an example of the method for manufacturing the array chip of the third embodiment.

[0111] After going through the processes described with reference to Figures 6 - 9 as shown in Figure 17 , a sacrificial film 101 (e.g., polysilicon) is deposited between adjacent ones of the plurality of bit lines 23 and between adjacent ones of the plurality of insulating films 70. In addition, in the process described with reference to Figure 8 , when processing the bit lines 23, the insulating film 25a between adjacent ones of the plurality of bit lines 23 is etched out by over-etching. Therefore, the lower end Ebtm of the sacrificial film 101 is located below the lower surface F23b of the bit line 23 in the +Z direction.

[0112] Next, as shown in Figure 18 , the sacrificial film 101 is etched so that the upper surface F101a of the sacrificial film 101 is located below the upper surface F23a of the bit line 23 in the +Z direction.

[0113] Next, as shown in Figure 19 , a cover film (e.g., silicon oxide film) 102 is formed so as to cover the insulating film 70 and the sacrificial film 101.

[0114] Next, as shown in Figure 20 , the sacrificial film 101 is selectively etched to form an air gap AG between the cover film 102 and the bit line 23. At this time, the upper end Etop of the air gap AG is located below the upper surface F23a of the bit line 23, and the lower end Ebtm is located below the lower surface F23b of the bit line 23.

[0115] Next, as shown in Figure 21 , a material for the insulating film 25b is deposited on the cover film 102. At this time, the cover film 102 inhibits the material of the insulating film 25b from entering the air gap AG and maintains the air gap AG.

[0116] Next, as shown in Figure 22 , the insulating film 25b is polished using the CMP method until the insulating film 70 is exposed.

[0117] Subsequently, after going through the processes described with reference to Figures 11 - 13 , the configuration of the array chip 2 shown in Figure 16 is obtained.

[0118] In addition, when the upper end Etop of the air gap AG is higher than the upper surface F23a of the bit line 23 (in the -Z direction), when forming Figure 12 the contact hole CH2, the contact hole CH2 may penetrate through the insulating film 70 to communicate with the air gap AG. At this time, during the formation process of the via contact 28b, the material of the via contact 28b enters the air gap AG.

[0119] Therefore, in order to suppress the material of the via contact 28b from entering the air gap AG, in the third embodiment, the upper end Etop of the air gap AG is positioned at a position lower than the upper surface F23a of the bit line 23 (in the +Z direction). The position of the upper end Etop of the air gap AG is adjusted at the height position of the upper surface F101a of the sacrificial film 101 shown in Figure 18 . By making the upper surface F101a of the sacrificial film 101 lower than the upper surface F23a of the bit line 23, the position of the upper end Etop of the air gap AG is made lower than the upper surface F23a of the bit line 23. Thereby, it is possible to suppress the material of the via contact 28b from entering the air gap AG.

[0120] (Fourth Embodiment)

[0121] Figure 23 FIG. is a cross-sectional view showing a configuration example of a bit line and its periphery of an array chip according to the fourth embodiment. In the fourth embodiment, in the region where the via contact 28b contacts the bit line 23, the insulating film 70 is not provided on the side surface in the Y direction of the via contact 28b. The via contact 28b is provided over the entire Y direction on the bit line 23.

[0122] Other configurations of the fourth embodiment may be the same as those of the first embodiment. Therefore, the fourth embodiment can achieve the same effects as the first embodiment. In addition, the fourth embodiment may also be combined with the second or third embodiment. In this case, the fourth embodiment can achieve the same effects as the second or third embodiment.

[0123] For the manufacturing method of the semiconductor device according to the fourth embodiment, as long as the insulating film 70 at the lower part of the contact hole CH2 is removed together with the insulating film 60 during the formation process of the contact hole CH2 shown in Figure 12 . Other manufacturing processes of the fourth embodiment may be the same as those of the first embodiment.

[0124] (Fifth Embodiment)

[0125] Figures 24A - 31B FIG. is a cross-sectional view showing an example of the manufacturing method of a semiconductor device according to the fifth embodiment. Figure 24A , Figure 25A , Figure 26A , Figure 27A and Figure 31A representFigure 1 The forming process of the via contact 28b in the peripheral region PD. Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figures 28 - 30 and Figure 31B represent Figure 1 the forming process of the via contact 28b in the laminate 20.

[0126] Through the process described with reference to Figure 6 , the via contact 28a is formed in the insulating film 25a. Next, as Figure 24A and Figure 24B shown, the material of the bit line 23 (e.g., tungsten) is deposited on the insulating film 25a (-Z direction). The material of the insulating film 60 (e.g., silicon nitride film) is deposited on the surface F23a of the material of the bit line 23.

[0127] Next, the material of the insulating film 60 is processed using photolithography and etching techniques. Next, the material of the bit line 23 is processed using the insulating film 60 as a mask. Thus, as Figure 25A and Figure 25B shown, a plurality of bit lines 23 and a plurality of insulating films 60 are formed. At this time, in the region of the laminate 20 of Figure 25B , compared with the peripheral region PD of Figure 25A , the width between the bit lines 23 is narrower, and the bit lines 23 are in a dense state. Therefore, in the region of the laminate 20, compared with the peripheral region PD, more of the insulating film 60 serving as a hard mask is etched. As a result, the height of the upper surface of the insulating film 60 in the region of the laminate 20 becomes lower compared with the peripheral region PD. In addition, the grooves between the bit lines 23 are formed to a position lower than the bottom surface of the bit lines 23.

[0128] Next, as Figure 26A and Figure 26B shown, by oxidizing the surfaces of the plurality of insulating films 60, insulating films 70 are respectively formed on the upper surfaces and both side surfaces of the plurality of insulating films 60. That is, the exposed surfaces (upper surface and both side surfaces) of the insulating film 60 are oxidized to become the insulating film 70. For example, when the insulating film 60 is a silicon nitride film, the insulating film 70 becomes a silicon nitride film, or a mixed film of a silicon oxide film and a silicon nitride film.

[0129] Next, the material of the insulating film 25b (e.g., silicon oxide film) is deposited in the grooves between the bit lines 23 and on the insulating film 70. Next, as Figure 26A and Figure 26B shown, the material of the insulating film 25b is etched back until the upper surface of the insulating film 25b is lower than the upper surface of the insulating film 70 and higher than the bottom surface of the insulating film 60 or the insulating film 70. As a result, the upper surface of the insulating film 25b between the bit lines 23 is at a position lower than the upper surface of the insulating film 70, asFigure 26B As shown, the upper surfaces of the insulating films 25b and 70 become uneven.

[0130] Next, as Figure 27A and Figure 27B shown, an insulating film 25c (e.g., a silicon nitride film) and an insulating film 25d (e.g., a silicon oxide film) are deposited on the insulating film 70 and the insulating film 25b. Here, the upper surfaces of the insulating films 25c and 25d are formed into an uneven shape following the unevenness of the upper surfaces of the insulating film 70 and the insulating film 25b. That is, the upper surfaces of the insulating film 70 and the insulating film 25b are not planarized.

[0131] Next, as Figure 28 shown, the upper surface of the insulating film 25d is planarized using the CMP method or the like. Next, a photoresist PR is formed on the insulating film 25d using photolithography. The photoresist PR is processed so as to expose the formation region of the via contact 28b on the insulating film 25d.

[0132] Next, as Figure 29 shown, the insulating film 25d (e.g., a silicon oxide film) is anisotropically etched using the photoresist PR as a mask. At this time, the insulating film 25c (e.g., a silicon nitride film) functions as an etch stop layer.

[0133] Here, the unevenness of the upper surfaces of the insulating films 25b and 70 is also transferred to the upper surface of the insulating film 25c thereon. The insulating film 25c on the bit line 23 protrudes more than other upper surface regions of the insulating film 25c. Therefore, as Figure 29 shown, when etching the insulating film 25d, if the etching is stopped at the point when the insulating film 25c is exposed, the insulating film 25c on the bit line 23 can be selectively exposed.

[0134] Next, as Figure 30 shown, the insulating films 25c, 70, and 60 are anisotropically etched using the photoresist PR and the insulating film 25d as masks. Thereby, the contact hole CH2 penetrates through the insulating films 25d, 25c, 70, and 60 and reaches the bit line 23. At this time, the insulating film 25c above the bit line 23 is selectively exposed. Therefore, the contact hole CH2 selectively etches the insulating film 25c above the bit line 23, and further selectively etches the insulating films 60 and 70 on the bit line 23. Since the insulating film 25c in the recess above the insulating film 25b between the bit lines 23 is covered by the insulating film 25d, it is hardly etched and remains. Thus, even if the position of the photoresist PR is slightly shifted, the contact hole CH2 can be formed from the convex portion of the insulating film 25c on the bit line 23 to the upper part of the bit line 23. This helps to reduce the parasitic capacitance PC2 between the via contact 28b and the adjacent bit line 23.

[0135] Next, through reference Figure 13The described process, such as Figure 31A and Figure 31B shown, forms the via contact 28b in such a manner that it penetrates the insulating films 25d, 25c, 70, and 60 within the contact hole CH2 to connect to the upper surface F23a of the bit line 23. The via contact 28b is electrically connected to the semiconductor body 210 of any one of the columnar bodies CL via the bit line 23. On the other hand, in the region where the contact hole CH2 is not provided, the insulating films 25d, 25c, 60, and 70 remain on the bit line 23.

[0136] Figure 32 is a cross-sectional view showing a comparative example when the upper surface of the insulating film 25c is flat. In the comparative example, the upper surfaces of the insulating film 25b and the insulating film 60 are substantially flush, and accordingly, the upper surface of the insulating film 25c becomes flat. In this case, when there is a position shift of the photoresist PR, the contact hole CH2 is formed in the insulating films 25d and 25c according to the pattern of the photoresist PR and is selectively formed on the bit line 23 in the insulating film 60. Since the insulating film 25c is etched according to the pattern of the photoresist PR, as Figure 32 shown, the distance between the via contact 28b and the adjacent bit line 23 becomes shorter. Therefore, the parasitic capacitance PC2 between the via contact 28b and the adjacent bit line 23 is relatively large.

[0137] In contrast, in the semiconductor device of the fifth embodiment, the unevenness of the upper surfaces of the insulating films 25b and 60 is also transferred to the upper surface of the insulating film 25c thereabove. The insulating film 25c on the bit line 23 protrudes more than other upper surface regions of the insulating film 25c, and the upper surface of the insulating film 25c has an uneven shape. Thus, as Figure 29 shown, when etching the insulating film 25d, if the etching is stopped at the point when the insulating film 25c is exposed, the insulating film 25c on the bit line 23 can be selectively exposed. As a result, the distance between the via contact 28b and the adjacent bit line 23 can be longer than in the comparative example. Therefore, the parasitic capacitance PC2 between the via contact 28b and the adjacent bit line 23 in the fifth embodiment can be reduced more than in the comparative example.

[0138] In addition, in the fifth embodiment, since the allowable range of the position shift of the photoresist PR becomes wider, the alignment in the lithography process becomes easier.

[0139] Other configurations and processes of the fifth embodiment can be the same as those of any other embodiment. Thus, the fifth embodiment can also achieve the same effects as any other embodiment.

[0140] Although the above embodiments are applied to the bit lines of a memory, they can also be applied to wirings other than the bit lines.

[0141] In addition, the array chip 2 of the embodiment can be applied to the following semiconductor memory devices.

[0142] Figure 33 FIG. is a block diagram showing a configuration example of a semiconductor memory device to which any one of the array chips of the embodiment is applied. The semiconductor memory device 1 is, for example, a memory 100a such as a NAND flash memory that can store data non-volatilely, and is controlled by an external memory controller 1002. The communication between the memory 100a and the memory controller 1002 complies with, for example, the NAND interface specification.

[0143] As Figure 33 shown, the memory 100a includes, for example, a memory cell array MCA, an instruction register 1011, an address register 1012, a sequencer 1013, a driver module 1014, a row decoder module 1015, and a sense amplifier module 1016.

[0144] The memory cell array MCA includes a plurality of blocks BLK(0) to BLK(n) (n is an integer of 1 or more). A block BLK is a set of a plurality of memory cells that can store data non-volatilely, and is used, for example, as an erasure unit of data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array MCA. Each memory cell is associated with, for example, 1 bit line and 1 word line. The detailed configuration of the memory cell array MCA will be described later.

[0145] The instruction register 1011 stores an instruction CMD received by the memory 100a from the memory controller 1002. The instruction CMD includes, for example, commands for causing the sequencer 1013 to perform a read operation, a write operation, and an erase operation.

[0146] The address register 1012 stores address information ADD received by the memory 100a from the memory controller 1002. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used for selecting the block BLK, the word line, and the bit line, respectively.

[0147] The sequencer 1013 controls the operations of the entire memory 100a. For example, the sequencer 1013 controls the driver module 1014, the row decoder module 1015, the sense amplifier module 1016, etc. based on the instruction CMD stored in the instruction register 1011, and performs read operations, write operations, erase operations, etc.

[0148] The driver module 1014 generates voltages for read operations, write operations, erase operations, etc. Then, the driver module 1014 applies the generated voltage to the signal line corresponding to the selected word line based on, for example, the page address PA stored in the address register 1012.

[0149] The row decoder module 1015 includes a plurality of row decoders. Based on the block address BA stored in the address register 1012, the row decoder selects one block BLK in the corresponding memory cell array MCA. Then, the row decoder transmits, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0150] In the write operation, the sense amplifier module 1016 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 1002. Further, in the read operation, the sense amplifier module 1016 determines the data stored in the memory cell based on the voltage of the bit line, and transmits the determination result as the read data DAT to the memory controller 1002.

[0151] The memory 100a and the memory controller 1002 described above may also be combined to form one semiconductor memory device. As such a semiconductor memory device, for example, a memory card such as an SDTM (Secure Digital Touch Memory) card, or an SSD (solid state drive) can be cited.

[0152] Figure 34 It is a circuit diagram showing an example of the circuit configuration of the memory cell array MCA. One block BLK is extracted from the plurality of blocks BLK included in the memory cell array MCA. As Figure 34 shown, the block BLK includes a plurality of string units SU(0) to SU(k) (k is an integer of 1 or more).

[0153] Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL(1) to BL(m) (m is an integer of 1 or more). Each NAND string NS includes, for example, memory cells MC(0) to MC(15), and selection transistors ST(1) and ST(2). The memory cell MC includes a control gate and a charge trapping layer, and stores data non-volatilely. The selection transistors ST(1) and ST(2) are each used for selecting the string unit SU during various operations.

[0154] In each NAND string NS, the memory cells MC(0) to MC(15) are connected in series. The drain of the selection transistor ST(1) is connected to the associated bit line BL, and the source of the selection transistor ST(1) is connected to one end of the serially connected memory cells MC(0) to MC(15). The drain of the selection transistor ST(2) is connected to the other end of the serially connected memory cells MC(0) to MC(15). The source of the selection transistor ST(2) is connected to the source line SL.

[0155] In the same BLK, the control gates of memory cells MC(0) to MC(15) are commonly connected to word lines WL(0) to WL(7) respectively. The gates of respective selection transistors ST(1) in string cells SU(0) to SU(k) are commonly connected to selection gate lines SGD(0) to SGD(k) respectively. The gate of selection transistor ST(2) is commonly connected to selection gate line SGS.

[0156] In the circuit configuration of the memory cell array MCA described above, bit line BL is shared by NAND strings NS of the same column address allocated in each string cell SU. For example, source line SL is shared among multiple blocks BLK.

[0157] A set of multiple memory cells MC connected to a common word line WL within one string cell SU is, for example, called a cell group CU. For example, the storage capacity of cell group CU that respectively contains memory cells MC storing 1-bit data is defined as "1 page of data". Cell group CU can have a storage capacity of 2 pages of data or more according to the number of bits of data stored in memory cell MC.

[0158] In addition, the memory cell array MCA included in the memory 100a of the present embodiment is not limited to the circuit configuration described above. For example, the number of memory cells MC and selection transistors ST(1) and ST(2) included in each NAND string NS can be designed to any number. The number of string cells SU included in each block BLK can be designed to any number.

[0159] The above-described embodiment can be applied not only to the array chip of a memory but also to the wiring and via contacts of logic circuits such as CMOS chips.

[0160] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in many other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or their variations are included in the scope or gist of the invention, and are included in the scope equivalent to the invention described in the claims.

[0161] [Description of Reference Numerals]

[0162] 2 Array chip

[0163] 3 CMOS chip

[0164] 25a to 25d Insulating film

[0165] 28a, 28b Via contact

[0166] 23 Bit line

[0167] 60,70 Insulating film

[0168] 24 Wiring

[0169] AG Air gap.

Claims

1. A semiconductor device comprising: a plurality of first wirings, which are provided in a first direction relative to a first insulating film, are arranged in a second direction intersecting the first direction, and extend in a third direction intersecting the first and second directions; A plurality of second insulating films are provided on the plurality of first wirings respectively corresponding to each other, and the width of each second insulating film on the surface in contact with the first wiring in the second direction is narrower than the width of the plurality of first wirings corresponding thereto in the second direction; a plurality of third insulating films, which are respectively provided on the plurality of first wirings correspondingly, arranged in the second direction, extending in the third direction, and respectively covering at least two side surfaces of the plurality of second insulating films; a fourth insulating film disposed on the plurality of third insulating films; a fifth insulating film, disposed on the fourth insulating film; a first contact penetrating through the second to fifth insulating films to be connected to any one of the plurality of first wirings; and A second wiring is provided on the first contact; and The first contact is provided in the first direction of the first wiring, or at least the second and fourth insulating films are provided.

2. The semiconductor device according to claim 1, wherein the first, third and fifth insulating films include silicon and oxygen; and The second and fourth insulating films include silicon and nitrogen. 3 . The semiconductor device according to claim 1 , wherein the plurality of third insulating films cover upper surfaces of the plurality of second insulating films, respectively, and are provided between the second insulating films and the fourth insulating film. 4 . The semiconductor device according to claim 1 , wherein the fourth insulating film covers the upper surfaces of the plurality of second insulating films and is in contact with the plurality of second insulating films. 5 . The semiconductor device according to claim 1 , further comprising: a sixth insulating film provided between the plurality of first wirings. 6 . The semiconductor device according to claim 1 , wherein an air gap is provided between the plurality of first wirings. 7 . The semiconductor device according to claim 6 , wherein an upper end of the air gap is located below an upper surface of the first wiring. 8 . The semiconductor device according to claim 6 , wherein the air gap is located below a lower surface of the first wiring. 9 . The semiconductor device according to claim 1 , wherein the first contact has a step at the same height as a lower surface of the fourth insulating film.

10. The semiconductor device according to claim 9, wherein the width of the first contact at the same height as the lower surface of the fourth insulating film in the second or third direction is wider than the width of the first contact on the connection surface with the first wiring in the second or third direction. 11 . The semiconductor device according to claim 1 , wherein a width of the first contact on a connection surface with the first wiring in the second or third direction is narrower than a width of the first wiring in the second direction.

12. The semiconductor device according to claim 5, wherein the third insulating film is provided on the side surface of the first contact between the sixth insulating films adjacent to each other in the second direction.

13. The semiconductor device according to claim 1 or claim 2, further comprising: a stacked body including a plurality of first conductive films and a plurality of seventh insulating films alternately stacked in the first direction; a plurality of columnar bodies including a first semiconductor portion extending in the first direction in the laminate body, and a first insulator portion provided between the first semiconductor portion and the laminate body; and The second contact penetrates the first insulating film and connects between the plurality of pillars and the first wiring. 14 . The semiconductor device according to claim 1 , wherein an upper surface of the fourth insulating film has a concavo-convex shape so as to protrude above the first wiring. 15 . The semiconductor device according to claim 5 , wherein an upper surface of the second insulating film protrudes further than an upper surface of the sixth insulating film.

16. A method for manufacturing a semiconductor device, comprising: depositing a material for a first wiring and a material for a second insulating film in a first direction of a first insulating film; Processing the material of the first wiring and the material of the second insulating film to form a plurality of first wirings and a plurality of second insulating films arranged in a second direction intersecting the first direction and extending in a third direction intersecting the first and second directions; forming a plurality of third insulating films on at least two side surfaces of the plurality of second insulating films respectively by oxidizing the surfaces of the plurality of second insulating films; forming a fourth insulating film on the plurality of third insulating films; forming a fifth insulating film on the fourth insulating film; forming a first contact penetrating through the second to fifth insulating films to be connected to any one of the plurality of first wirings, and leaving at least the second and third insulating films in a region of the first wiring in which the first contact is not provided in the first direction; and A second wiring is formed on the first contact.

17. The manufacturing method according to claim 16, wherein the forming of the first contact further comprises: Based on the difference in etching rates between the fourth and fifth insulating films, processing the fifth insulating film to form a first contact hole; Based on the difference in etching rates between the second and third insulating films, the second insulating film is selectively removed with respect to the third insulating film, and the first contact hole is further formed up to the first wiring; and The first contact is formed by forming a metal material in the first contact hole.

18. The manufacturing method according to claim 16, further comprising: After forming the plurality of third insulating films, forming a sacrificial film between the plurality of third insulating films; etching the sacrificial film until an upper surface of the sacrificial film is located below upper surfaces of the plurality of first wirings; depositing an eighth insulating film on the sacrificial film; and The sacrificial film is removed.

19. The manufacturing method according to claim 16, wherein when processing the material of the first wiring and the material of the second insulating film, the upper surface of the first insulating film is cut away to a position lower than the lower surface of the first wiring.

20. The manufacturing method according to claim 16, wherein after forming the plurality of first wirings and the plurality of third insulating films, a sixth insulating film is formed between adjacent first wirings to a position lower than the second or third insulating film so that the second or third insulating film protrudes more than the sixth insulating film; The fourth insulating film is deposited on the third and sixth insulating films, and the upper surface of the fourth insulating film is uneven in accordance with the unevenness of the third and sixth insulating films; and The fifth insulating film and the first contact are formed without planarizing the upper surface of the fourth insulating film.

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