A substrate-triggered uniformly turned-on NMOS structure

Abstract

The present invention discloses a substrate-triggered uniformly turned-on NMOS structure, comprising a P-type substrate, a first P-type well-doped well region, multiple N-type heavily doped active regions, a polysilicon gate, an edge P-type heavily doped active region, a second P-type well-doped well region, a P-type high-voltage doped well region, and a P-type deep-doped well region. The edge P-type heavily doped active region, the second P-type well-doped well region, and the P-type high-voltage doped well region are sequentially implanted into the P-type substrate from top to bottom and are all arranged in a ring-shaped structure, with the edge P-type heavily doped active region surrounding the ring-shaped N-type heavily doped active region. The P-type deep-doped well region is implanted into the P-type substrate, and its edge extends to the bottom of the P-type high-voltage doped well region. The present invention solves the problem of uneven conduction in existing multi-finger GGNMOS structures through a specific doping structure and resistor network distribution.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor structures, and in particular to an NMOS structure with substrate-triggered uniform turn-on. Background Art

[0002] With advances in semiconductor process technology, the feature sizes of CMOS devices continue to shrink, increasing chip integration and operating speed. However, this shrinking device size reduces its ability to withstand electrostatic discharge (ESD). Therefore, integrated circuits require on-chip ESD protection devices to ensure reliability. Grounded-gate NMOS (GGNMOS) has become a widely adopted ESD protection solution due to its simple structure and compatibility with standard CMOS processes. Traditional GGNMOS typically utilizes a multi-finger layout to reduce silicon area while leveraging the avalanche breakdown characteristics of parasitic bipolar junction transistors (BJTs) to dissipate ESD current.

[0003] In existing GGNMOS multi-finger structures, uneven conduction occurs in practical applications. Specifically, due to the varying base resistances of the individual fingers within a multi-finger GGNMOS surrounded by a P+ guard ring, the parasitic NPN transistor of the middle finger (which has a higher base resistance) triggers preferentially under ESD stress. Once the middle finger is triggered, the ESD voltage is clamped to the holding voltage, causing subsequent ESD current to be concentrated in this local area, while the other fingers are unable to effectively share the current. This uneven conduction not only reduces the GGNMOS's overall ESD protection capabilities but can also cause thermal failure due to excessive local current density, seriously impacting device reliability.

[0004] Based on this, a new technical solution is needed. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a substrate-triggered uniformly turned-on NMOS structure to at least solve the problem of uneven conduction of the existing multi-finger GGNMOS.

[0006] The embodiments of the present invention provide the following technical solutions:

[0007] An embodiment of the present invention provides a substrate-triggered uniformly turned-on NMOS structure, comprising a P-type substrate, a first P-type well-doped well region, a plurality of N-type heavily doped active regions, and a polysilicon gate. The first P-type well-doped well region is implanted into the P-type substrate, the plurality of N-type heavily doped active regions are implanted into the first P-type well-doped well region at intervals, and the plurality of polysilicon gates are disposed on the first P-type well-doped well region, with their sides interlaced with the plurality of strip-shaped N-type heavily doped active regions.

[0008] It also includes an edge P-type heavily doped active region, a second P-type well doping type well region, a P-type high-voltage doped well well region and a P-type deeply doped well region;

[0009] The edge P-type heavily doped active region, the second P-type well doping type well region and the P-type high-voltage doped well well region are sequentially implanted into the P-type substrate from top to bottom and are all arranged in a ring structure. The edge P-type heavily doped active region surrounds the ring-shaped N-type heavily doped active region, wherein the edge P-type heavily doped active region and the ring-shaped N-type heavily doped active region are isolated from each other.

[0010] The P-type deep doped well region is implanted into the P-type substrate, and its edge extends to the bottom end of the P-type high-voltage doped well well region.

[0011] Furthermore, the edge P-type heavily doped active region is electrically connected to and grounded.

[0012] Furthermore, the width of the second P-type well-doping type well region is greater than the width of the edge P-type heavily doped active region; and / or the width of the second P-type well-doping type well region is greater than the width of the P-type high-voltage doped well well region.

[0013] Furthermore, the P-type deep doped well region is a planar structure, and its edges all extend to the bottom end of the P-type high-voltage doped well well region.

[0014] Furthermore, it also includes an intermediate P-type heavily doped active region, which is implanted in the middle position of the strip-shaped N-type heavily doped active region surrounded by the polysilicon gate and is isolated from the N-type heavily doped active region.

[0015] Furthermore, the middle P-type heavily doped active region is isolated from the N-type heavily doped active region by a ring-shaped STI region.

[0016] Furthermore, the middle P-type heavily doped active region is electrically connected to and grounded.

[0017] Furthermore, the edge P-type heavily doped active region is isolated from the N-type heavily doped active region by an STI region.

[0018] Furthermore, two ends of the polysilicon gate are isolated by an STI region and the first P-type well doping type well region.

[0019] Furthermore, two sections of the STI region between the polysilicon gate and the first P-type well-doping type well region extend to inner sides of the edge P-type heavily doped active region.

[0020] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0021] The present invention provides a substrate-triggered uniformly turned-on NMOS structure. By arranging an annular edge P-type heavily doped active region, a second P-type well-doping type well region, and a P-type high-voltage doped well well region at the edge of a P-type substrate, and arranging a P-type deeply doped well region inside the P-type substrate, the GGNMOS device is uniformly turned on in a multi-finger structure through a specific doping structure and resistance network distribution, thereby solving the problem of uneven conduction in existing multi-finger GGNMOS structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 A top view of a substrate-triggered uniformly turned-on NMOS structure according to an embodiment of the present invention;

[0024] Figure 2 This is a partial enlarged view of a substrate-triggered uniform opening according to an embodiment of the present invention;

[0025] Figure 3 For the Figure 1 Cross-sectional view of AA';

[0026] Figure 4 For the Figure 1 Cross-sectional view of middle BB';

[0027] Figure 5 For the Figure 1 Cross-sectional view of CC'.

[0028] The accompanying drawings of the present invention are as follows:

[0029] 10. P-type substrate; 20. First P-type well-doping type well region; 30. N-type heavily doped active region; 40. Polysilicon gate; 50. Edge P-type heavily doped active region; 60. Second P-type well-doping type well region; 70. P-type high-voltage doped well well region; 80. P-type deeply doped well region; 90. Middle P-type heavily doped active region; 100. STI region. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0032] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0033] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0034] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples, however, one skilled in the art will appreciate that the examples can be practiced without these specific details.

[0035] In existing multi-finger GGNMOS ESD structures, when a high-voltage ESD pulse is applied to T1, the N+ (N-type heavily doped active region) / Pwell (P-type well-doped well region) first experiences avalanche breakdown, generating an avalanche current. Holes then flow through Pwell, through the P+ (P-type heavily doped active region), and to T2. Due to the parasitic resistance of Pwell, a potential difference is generated between Pwell and T1. When the potential exceeds 0.7V, Pwell and the N+ at T2 become forward conductive, turning on the NPN. At this point, the drift current replaces the avalanche current, and more holes flow into T1. The conductive mechanism significantly reduces the bias voltage required to maintain the same current, causing the device to exhibit negative resistance. As the voltage decreases and the current increases, the current in the device is primarily provided by the drift current, and the negative resistance ends. As the voltage and current increase, the entire device undergoes secondary breakdown, reaching the critical burnout point.

[0036] In a multi-finger GGNMOS structure, the base parasitic resistance of the NPNs at the edges of the structure is low. Based on the aforementioned principle analysis, when an ESD pulse occurs, a lower voltage is required to trigger avalanche breakdown. However, as the ESD voltage gradually increases, avalanche breakdown occurs at the center. Because the NPNs in the center have larger parasitic base resistances (R1+R2+R3...; R4+R5+R6...), they are more likely to turn on. Subsequently, the voltage at the center quickly clamps to the holding voltage, preventing the edge NPNs from turning on. This results in a macroscopic situation in the multi-finger NMOS structure, with avalanche breakdown occurring first at the edges, followed by an uneven current distribution that drives the center NPNs to turn on.

[0037] More specifically, after the edge of the structure is broken down by avalanche, the avalanche current generated by it flows toward the middle position. The base resistance of the parasitic NPN in the middle position is larger, resulting in a larger potential difference at the base NPN in the middle position, causing the potential difference at the base NPN in the middle position to reach 0.7V earlier, and ultimately causing the parasitic NPN in the middle position to be turned on first.

[0038] In view of this, the inventors conducted in-depth research and improved exploration on base resistance, avalanche current, and the doping method of the edge P-type heavily doped active area 50 at the edge of the substrate, and found that: by doping the edge P-type heavily doped active area 50 at the edge of the substrate, and sequentially doping a second P-type well doping type well region 60 and a P-type high-voltage doped well well region 70 below the edge P-type heavily doped active area 50, and doping a P-type deep doped well region 80 in the P-type substrate 10, the longitudinal resistance of the P-type deep doped well region 80 (the region with relatively low doping concentration) can be made larger, and the lateral resistance of the edge P-type heavily doped active area 50 (due to high concentration doping) can be made smaller. By adjusting the doping concentration, the longitudinal resistance of the P-type deep doped well region 80 is made much larger than the lateral resistance of the edge P-type heavily doped active area 50, so that the total resistance of each part is close, thereby ensuring a uniform base potential distribution of the parasitic NPN transistor, and finally making all finger structures reach the turn-on voltage at the same time.

[0039] Based on this, this specification proposes a solution: Figures 1 and 2 As shown, a substrate-triggered uniformly turned-on NMOS structure of the present invention is achieved by sequentially implanting an edge P-type heavily doped active region 50, a second P-type well doping type well region 60, and a P-type high-voltage doped well well region 70 at the substrate edge of the existing ring-shaped multi-finger GGNMOS structure, and implanting a P-type deeply doped well region 80 in the P-type substrate 10, thereby enabling the GGNMOS device to be uniformly turned on in the multi-finger structure.

[0040] Specifically, if Figure 4 As shown in the figure, in the resistance network distribution formed by a specific doping structure, Rp1 / Rp2 / Rp3 represent the longitudinal resistance of the P-type deep doped well region 80 (high-voltage well), which is a region with relatively low doping concentration and large resistance value. R1 / R2 / R3 represent the lateral resistance of the edge P-type heavily doped active region 50, which has a small resistance value due to high doping concentration. For the finger structure in the middle position, the base substrate resistance path = Rp3 (vertical) + R1 + R2 + R3 (lateral); for the finger structure at the edge position, the base substrate resistance path = Rp3 (vertical) + R1 + R2 + R3 (lateral); Path = Rp1 (vertical) + R1 (horizontal). Since the resistance of the Rp series resistor (vertical) is much greater than the resistance of the R series resistor (horizontal), the resistance of each finger structure is mainly determined by the vertical resistance, and the difference in the horizontal resistance R is greatly weakened. Ultimately, the total resistance area of ​​the resistance in each path is close (Rp3 ≈ Rp1), ensuring that the base potential of the parasitic NPN transistor is evenly distributed, allowing all finger structures to reach the turn-on voltage at the same time, avoiding local current accumulation, and preventing current concentration and hot spot formation caused by a certain area being turned on first.

[0041] The following describes the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0042] like Figures 1 to 5 As shown, the present invention provides a substrate-triggered uniformly turned-on NMOS structure, comprising a P-type substrate 10, a first P-type well-doped type well region 20, a plurality of N-type heavily doped active regions 30 and a polysilicon gate 40. The first P-type well-doped type well region 20 is implanted into the P-type substrate 10, a plurality of N-type heavily doped active regions 30 are implanted into the first P-type well-doped type well region 20 at intervals, and a plurality of polysilicon gates 40 are arranged on the first P-type well-doped type well region 20, and their sides are staggered with a plurality of strip-shaped N-type heavily doped active regions 30.

[0043] Among them, the P-type substrate 10 is used to provide basic semiconductor materials as a support for the entire NMOS structure; the first P-type well doping type well region 20 forms the body region of the NMOS, which is used to isolate the N-type active region and affect the trigger characteristics of the parasitic BJT.

[0044] The P-type substrate 10 is provided with an implantation region for implanting a first P-type well doping type well region 20 by ion implantation. The first P-type well doping type well region 20 is provided with an implantation region for implanting a plurality of N-type heavily doped active regions 30.

[0045] The multiple N-type heavily doped active regions 30 include strip-type N-type heavily doped active regions and annular N-type heavily doped active regions that are spaced apart, wherein the annular N-type heavily doped active region surrounds the multiple N-type heavily doped active regions.

[0046] The multiple N-type heavily doped active regions 30 serve as the source and drain of the NMOS, and form the emitter and collector of the parasitic NPN during an ESD event.

[0047] Among them, the polysilicon gate 40 is a ring structure, with its two long sides located between two adjacent strip-shaped N-type heavily doped active regions 30, and its two short sides are isolated by the STI region 100 and the first P-type well doping type well region 20; positions for connecting metal contact holes are provided on the two short sides of the polysilicon gate 40.

[0048] The polysilicon gate 40 is used to control the conduction of the NMOS and is usually grounded during an ESD event to keep it in an off state.

[0049] The two long sides and two short sides of the polysilicon gate 40 form a ring structure and surround a strip-shaped N-type heavily doped active region 30 .

[0050] The substrate-triggered uniformly turned-on NMOS structure also includes an edge P-type heavily doped active area 50, a second P-type well-doping type well area 60, a P-type high-voltage doped well well area 70 and a P-type deep-doped well area 80; the edge P-type heavily doped active area 50, the second P-type well-doping type well area 60 and the P-type high-voltage doped well well area 70 are sequentially implanted into the P-type substrate 10 from top to bottom, and are all arranged in a ring structure, the edge P-type heavily doped active area 50 surrounds the ring-shaped N-type heavily doped active area 30, wherein the edge P-type heavily doped active area 50 and the ring-shaped N-type heavily doped active area 30 are isolated and arranged; the P-type deep-doped well area 80 is implanted into the P-type substrate 10, and its edge extends to the bottom end of the P-type high-voltage doped well well area 70.

[0051] The edge P-type heavily doped active region 50 is electrically connected to and grounded to ensure that the edge P-type heavily doped active region 50 can be effectively grounded, thereby providing an effective current discharge path during an ESD event.

[0052] Among them, the edge P-type heavily doped active area 50 is arranged around the N-type heavily doped active area 30 to form a low-resistance path, promote uniform conduction of multiple fingers, and after grounding, ensure that the edge P-type heavily doped active area 50 can quickly discharge current in an ESD event to avoid local current concentration.

[0053] The second P-type well doping type well region 60 is located below the edge P-type heavily doped active region 50 and is used to provide additional P-type doping, optimize the well region resistance distribution, and improve the uniformity of the ESD current.

[0054] Furthermore, by setting the width of the second P-type well doping type well region 60 to be larger than the width of the edge P-type heavily doped active region 50 , the protection of the N-type heavily doped active region 30 can be enhanced to prevent premature breakdown.

[0055] The P-type high-voltage doped well region 70 can improve the voltage resistance of the well region, prevent premature breakdown under ESD stress, and optimize the triggering characteristics of the parasitic NPN.

[0056] The P-type deep doped well region 80 extends to the bottom of the P-type high-voltage doped well well region 70 , which can reduce the substrate resistance, balance the current distribution among multiple fingers, and avoid local overheating.

[0057] The P-type deep doped well region 80 is provided as a planar structure, thereby ensuring uniform coverage and improving the stability of the structure.

[0058] The present application forms an optimized structural layout by introducing an edge P-type heavily doped active area 50, a second P-type well doping type well area 60, a P-type high-voltage doped well well area 70 and a P-type deep doped well area 80. The setting of the P-type deep doped well area 80 helps to balance the substrate resistance inside and outside the structure, so that the entire multi-finger GGNMOS structure can be turned on simultaneously under ESD stress.

[0059] Furthermore, the width of the second P-type well doping type well region 60 is greater than the width of the P-type high-voltage doping well well region 70 to improve the robustness and ESD protection performance of the structure.

[0060] In some embodiments, the substrate-triggered uniformly turned-on NMOS structure also includes an intermediate P-type heavily doped active region 90, which is implanted in the middle of the strip-shaped N-type heavily doped active region 30 surrounded by the polysilicon gate 40, and is isolated from the N-type heavily doped active region 30 to further optimize the current distribution and improve the conduction uniformity.

[0061] Preferably, the middle P-type heavily doped active region 90 is isolated from the N-type heavily doped active region 30 by the annular STI region 100 .

[0062] Furthermore, the middle P-type heavily doped active region 90 is electrically connected to and grounded.

[0063] The present invention dopes the edge P-type heavily doped active region 50 in the middle of the strip-shaped N-type heavily doped active region 30 surrounded by the polysilicon gate 40, which helps to disperse current in ESD events, prevent local overheating and damage, and enhance its current discharge capability.

[0064] Furthermore, the edge P-type heavily doped active region 50 is isolated from the N-type heavily doped active region 30 by the STI region 100 to prevent direct contact between the P+ and N+ regions, thereby avoiding leakage and optimizing the trigger path of the parasitic BJT.

[0065] Furthermore, both ends of the polysilicon gate 40 are isolated by the STI region 100 and the first P-type well doping type well region 20 to prevent the gate from being short-circuited with the well region, ensuring that the ESD current is mainly discharged through the parasitic BJT.

[0066] Furthermore, two sections of the STI region 100 between the polysilicon gate 40 and the first P-type well-doped well region 20 extend to the inner side of the edge P-type heavily doped active region 50 to enhance isolation effect and optimize current distribution.

[0067] Among them, the STI region 100 is used to provide effective electrical isolation to prevent interference between different doping regions, and the isolation between the polysilicon gate 40 and the first P-type well doping type well region 20 enhances the structural integrity and ESD protection performance. The STI region 100 extending to the inner side of the edge P-type heavily doped active region 50 further enhances the stability and uniformity of the structure.

[0068] The present invention uses a ring-shaped polysilicon gate structure to achieve higher area utilization efficiency of the NMOS, thereby improving the overall current discharge capability. In addition, a P-type deeply doped well region 80 is implanted in the substrate at the bottom of the structure, and a P-type high-voltage doped well well region 70, a second P-type well doping type well region 60, and an edge P-type heavily doped active region 50 are sequentially arranged at the edge of the structure substrate to connect to the ground (GND). This makes the base substrate resistance of a GGNMOS parasitic NPN structure in the middle of the multi-finger GGNMOS be Rp3+R1+R2+R3, and the base substrate resistance of a GGNMOS parasitic NPN structure at its edge be Rp1+R1.

[0069] Since Rp1, Rp2, Rp3... are much larger than R1, R2, R3..., this specific doping structure can keep the effective substrate resistance around the GGNMOS structure and in the middle of the GGNMOS structure at the same level, so that the entire multi-finger GGNMOS circuit can be turned on at the same time, avoiding the situation where a certain area is turned on first due to excessive resistance, causing excessive current and thus premature damage.

[0070] Furthermore, a heavily P-type edge active region 50 is inserted at the drain of the same ring-shaped GGNMOS and connected to the T2 ground terminal. When an ESD pulse occurs, the parasitic resistance of the reverse PN junction path between the heavily N-type active region 30, the second P-type well region 60, and the central heavily P-type active region 90 is smaller than that at other locations, causing avalanche breakdown to occur first. This improves the GGNMOS's response speed and avoids the difficulty in turning on the device due to the overall increase in resistance from the substrate to the heavily P-type edge active region 50 caused by changes in the overall structure.

[0071] In this specification, references to the same or similar parts between the various embodiments can be made to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0072] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A substrate-triggered uniformly turned-on NMOS structure, comprising a P-type substrate, a first P-type well-doped well region, a plurality of N-type heavily doped active regions, and a polysilicon gate, wherein the first P-type well-doped well region is implanted into the P-type substrate, the plurality of N-type heavily doped active regions are implanted into the first P-type well-doped well region at intervals, and the plurality of polysilicon gates are disposed on the first P-type well-doped well region, with their sides interlaced with the plurality of strip-shaped N-type heavily doped active regions, characterized in that: It also includes an edge P-type heavily doped active region, a second P-type well doping type well region, a P-type high-voltage doped well well region and a P-type deeply doped well region; The edge P-type heavily doped active region, the second P-type well doping type well region and the P-type high-voltage doped well well region are sequentially implanted into the P-type substrate from top to bottom and are all arranged in a ring structure. The edge P-type heavily doped active region surrounds the ring-shaped N-type heavily doped active region, wherein the edge P-type heavily doped active region and the ring-shaped N-type heavily doped active region are isolated from each other. The P-type deep doped well region is injected into the P-type substrate, and a layer of P-type substrate spacing is formed between the P-type deep doped well region and the first P-type well doped type well region, and its edge extends to the bottom end of the P-type high-voltage doped well well region.

2. The substrate-triggered uniformly turned-on NMOS structure according to claim 1, characterized in that: The edge P-type heavily doped active region is electrically connected to and grounded.

3. The substrate-triggered uniformly turned-on NMOS structure according to claim 2, characterized in that: The width of the second P-type well doping type well region is greater than the width of the edge P-type heavily doped active region; and / or The width of the second P-type well doping type well region is greater than the width of the P-type high-voltage doping well well region.

4. The substrate-triggered uniformly turned-on NMOS structure according to claim 2, characterized in that: The P-type deep doped well region is a planar structure, and its edges all extend to the bottom end of the P-type high-voltage doped well well region.

5. The substrate-triggered uniformly turned-on NMOS structure according to claim 1, characterized in that: It also includes an intermediate P-type heavily doped active region, which is implanted in the middle of the strip-shaped N-type heavily doped active region surrounded by the polysilicon gate and is isolated from the N-type heavily doped active region.

6. The substrate-triggered uniformly turned-on NMOS structure according to claim 5, characterized in that: The middle P-type heavily doped active region is isolated from the N-type heavily doped active region by a ring-shaped STI region.

7. The substrate-triggered uniformly turned-on NMOS structure according to claim 5, characterized in that: The middle P-type heavily doped active region is electrically connected and grounded.

8. The substrate-triggered uniformly turned-on NMOS structure according to claim 1, characterized in that: The edge P-type heavily doped active region is isolated from the N-type heavily doped active region by an STI region.

9. The substrate-triggered uniformly turned-on NMOS structure according to claim 1, characterized in that: Two ends of the polysilicon gate are isolated by the STI region and the first P-type well doping type well region.

10. The substrate-triggered uniformly turned-on NMOS structure according to claim 9, characterized in that: Two sections of the STI region between the polysilicon gate and the first P-type well-doping type well region extend to inner sides of the edge P-type heavily doped active region.

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