Low-loss reverse conducting transverse gallium oxide enhanced transistor

Abstract

The invention belongs to the technical field of power semiconductors, and relates to a low-loss reverse conducting transverse gallium oxide enhanced transistor. During forward conduction, the enhanced transistor with high threshold voltage is realized by adopting the groove gate structure, and the integrated diode hardly occupies extra conductive area, so that high output current can be realized; during forward blocking, the patterned groove optimizes electric field distribution, and the grid field plate is combined to relieve the electric field concentration effect and enhance the voltage endurance capability of the device; during forward conduction and blocking, the Schottky diode is turned off, and the conduction and blocking characteristics of the transistor are not affected; during reverse follow current, the reverse conducting transistor with low reverse conduction loss is realized by integrating the Schottky diode. The reverse conducting device has the beneficial effects that the reverse conducting device has the advantages of low reverse turn-on voltage, high breakdown voltage, high conductivity and high threshold voltage, the integrated diode is compatible with the transistor process, and the module size and the parasitic effect can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and relates to a reverse-conducting lateral gallium oxide enhancement transistor with low on-state loss. Background Art

[0002] Gallium oxide materials have advantages such as an ultra-wide bandgap (4.5 - 4.9 eV), a high critical electric field strength (8 MV / cm), low cost, and controllable N-type doping. Compared with semiconductors such as silicon, gallium nitride, and silicon carbide, gallium oxide materials have more excellent material properties. Power devices based on gallium oxide can achieve higher breakdown voltages under the same drift region length. In theory, they have the advantages of small volume, low on-resistance, and high breakdown voltage, and have broad prospects in high-voltage, high-power, and low-loss applications. However, the breakdown voltage of gallium oxide power devices is much lower than the theoretical value, and the electric field concentration effect causes the device to break down prematurely. Moreover, due to the lack of effective P-type doping, it is difficult to realize enhancement-type for gallium oxide field-effect transistors, resulting in difficult drive design, and the freewheeling ability of the device during self-freewheeling is limited by the threshold voltage and gate voltage. Using an external anti-parallel diode is a common way to achieve reverse freewheeling, but this method has the disadvantages of high parasitic impedance, high noise, and high cost, and the parallel diode will increase the system volume, resulting in reduced efficiency and increased loss of the power integrated circuit system. Summary of the Invention

[0003] In view of the above problems, the present invention proposes a reverse-conducting lateral gallium oxide enhancement transistor with low loss.

[0004] The technical solution of the present invention is as follows:

[0005] A reverse-conducting lateral gallium oxide enhancement transistor with low loss, along the vertical direction of the device, includes a gallium oxide substrate 1, an unintentionally doped gallium oxide buffer layer 2, and a gallium oxide epitaxial layer 3 stacked in sequence from bottom to top; along the lateral direction of the device, a drain metal 4 is provided at one end of the upper surface of the gallium oxide epitaxial layer 3;

[0006] Specifically, one end of the device with the drain metal 4 is defined as the first end of the device, and the end of the device far from the drain metal 4 is defined as the second end of the device; the second end of the device is sequentially defined as three regions along the longitudinal direction of the device, namely the first region of the second end of the device, the second region of the second end of the device, and the third region of the second end of the device; along the transverse direction of the device, source metal 7 and gate grooves are respectively provided at both ends of the first region of the second end of the device and the third region of the second end of the device, and the source metal 7 and gate grooves at both ends are symmetrically arranged after being separated by the second region of the second end of the device; the source metal 7 is in contact with the upper surface of the gallium oxide epitaxial layer 3, and the gate grooves are formed by etching the gallium oxide epitaxial layer 3; a patterned groove structure is formed by patterned etching in the second region of the second end of the device, wherein the process of the patterned etching is to etch away the gallium oxide epitaxial layer 3 and the unintentionally doped gallium oxide buffer layer 2 in the patterned region until reaching the upper surface of the gallium oxide substrate 1; a dielectric layer 5 is provided on the upper surface of the gallium oxide epitaxial layer 3, the bottom and side surfaces of the gate grooves, and the bottom and side surfaces of the patterned groove structure; gate metal 6 is filled in the gate grooves, and both ends of the upper surface of the gate metal 6 extend towards the drain metal 4 and the source metal 7 respectively, and there is a spacing between the gate metal 6 and the drain metal 4 and the source metal 7 in the transverse direction;

[0007] Along the transverse direction of the device, both ends of the patterned groove structure are respectively defined as the first end of the patterned groove structure and the second end of the patterned groove structure, wherein the first end of the patterned groove structure is connected to the source metal 7, and a Schottky anode metal 8 is provided on the upper surface of the gallium oxide epitaxial layer 3 connected to the second end of the patterned groove structure. Along the longitudinal direction of the device, the longitudinal width of the Schottky anode metal 8 is the same as the longitudinal width of the first end of the patterned groove structure. Along the transverse direction of the device, the spacing between the Schottky anode metal 8 and the drain metal 4 is smaller than the spacing between the gate metal 6 and the drain metal 4;

[0008] The source metal 7 and the Schottky anode metal 8 are electrically connected.

[0009] The transverse direction of the device described in the above solution corresponds to Figure 1 the x-axis direction of the coordinate system in

[0010] Further, the first end of the patterned groove structure is rectangular in the top view of the device, and the second end of the patterned groove structure is trapezoidal in the top view of the device.

[0011] Further, the first end of the patterned groove structure is rectangular in the top view of the device, and the second end of the patterned groove structure is a rounded rectangle in the top view of the device.

[0012] The beneficial effects of the present invention are as follows. The device of the present invention realizes a reverse-conducting device with a low reverse turn-on voltage through the integration of a Schottky diode, and realizes an enhancement-mode device with a high threshold voltage through a grooved gate. The patterned groove combined with the gate field plate alleviates the electric field concentration, optimizes the electric field distribution, enhances the breakdown voltage capability of the device, and realizes the advantages of both a low reverse turn-on voltage, low loss, and high threshold voltage. The integration of the diode and transistor processes is compatible, which is beneficial to reducing the module volume and parasitic effects. Description of the Drawings

[0013] Figure 1 is a schematic structural diagram of Embodiment 1 of the present invention;

[0014] Figure 2 is a schematic structural diagram of Embodiment 1 of the present invention with auxiliary lines;

[0015] Figure 3 is a cross-sectional view along line AA' in Embodiment 1;

[0016] Figure 4 is a cross-sectional view along line BB' in Embodiment 1;

[0017] Figure 5 is a cross-sectional view along line CC' in Embodiment 1;

[0018] Figure 6 is a cross-sectional view along line DD' in Embodiment 1;

[0019] Figure 7 is a schematic structural diagram of Embodiment 2 of the present invention;

[0020] Figure 8 is a schematic structural diagram of Embodiment 3 of the present invention. Detailed Description of the Invention

[0021] The technical solution of the present invention will be described in detail below in conjunction with the drawings and embodiments:

[0022] Embodiment 1:

[0023] As Figure 1 shown, this example includes, in the vertical direction of the device, a gallium oxide substrate 1, an unintentionally doped gallium oxide buffer layer 2, and a gallium oxide epitaxial layer 3 stacked in sequence from bottom to top; in the horizontal direction of the device, a drain metal 4 is provided at one end of the upper surface of the gallium oxide epitaxial layer 3;

[0024] It is characterized in that one end of the device with the drain metal 4 is defined as the first end of the device, and the end of the device far from the drain metal 4 is defined as the second end of the device; the second end of the device is sequentially defined as three regions along the longitudinal direction of the device, namely the first region of the second end of the device, the second region of the second end of the device, and the third region of the second end of the device; along the transverse direction of the device, source electrodes 7 and gate trenches are respectively provided at both ends of the first region of the second end of the device and the third region of the second end of the device, and the source electrodes 7 and gate trenches at both ends are symmetrically arranged after being separated by the second region of the second end of the device; the source electrode 7 is in contact with the upper surface of the gallium oxide epitaxial layer 3, and the gate trench is formed by etching the gallium oxide epitaxial layer 3; a patterned trench structure is formed by patterned etching in the second region of the second end of the device, wherein the process of the patterned etching is to etch away the gallium oxide epitaxial layer 3 and the unintentionally doped gallium oxide buffer layer 2 in the patterned region until reaching the upper surface of the gallium oxide substrate 1; a dielectric layer 5 is provided on the upper surface of the gallium oxide epitaxial layer 3, the bottom and side surfaces of the gate trench, and the bottom and side surfaces of the patterned trench structure; a gate metal 6 is filled in the gate trench, and the two ends of the upper surface of the gate metal 6 extend respectively towards the drain metal 4 and the source electrode 7, and there is a spacing between the gate metal 6 and the drain metal 4 and the source electrode 7 in the transverse direction;

[0025] Along the transverse direction of the device, the two ends of the patterned trench structure are respectively defined as the first end of the patterned trench structure and the second end of the patterned trench structure, wherein the first end of the patterned trench structure is connected to the source electrode 7, and a Schottky anode metal 8 is provided on the upper surface of the gallium oxide epitaxial layer 3 connected to the second end of the patterned trench structure. Along the longitudinal direction of the device, the longitudinal width of the Schottky anode metal 8 is the same as the longitudinal width of the first end of the patterned trench structure. Along the transverse direction of the device, the spacing between the Schottky anode metal 8 and the drain metal 4 is smaller than the spacing between the gate metal 6 and the drain metal 4; the source electrode 7 and the Schottky anode metal 8 are electrically connected.

[0026] The working principle of this example is:

[0027] A low-loss reverse-conducting gallium oxide enhancement transistor proposed by the present invention, when the bias voltage applied to the gate metal 6 is zero, uses the work function difference between the gate metal 6 and gallium oxide in the grooved gate structure to achieve the pinch-off effect on the channel, thereby making the transistor normally off; as the bias voltage applied to the gate metal 6 gradually increases, the channel depletion region gradually shrinks to form a conductive channel, and the transistor conducts at a higher forward bias voltage, that is, a high threshold voltage is achieved; during forward blocking, the gate field plate alleviates the electric field concentration effect near the gate electrode, combines with the patterned groove to modulate the electric field distribution, and improves the breakdown voltage of the transistor; in the forward conduction and blocking states, the drain metal 4 is at a high potential, and the Schottky anode metal 8 is at zero potential, and the integrated Schottky diode is turned off, which does not affect the conduction and blocking performance of the transistor; during reverse freewheeling, the drain metal 4 is connected to a low potential, the source metal 7 and the Schottky anode metal 8 are short-circuited and connected to a high potential, and the Schottky contact barrier height is lower than the electron barrier formed by the grooved gate, so that the Schottky diode conducts before the transistor, realizing a low turn-on voltage and a low conduction voltage drop, thereby reducing the reverse conduction loss. Therefore, the device of the present invention realizes a reverse-conducting device with a low reverse turn-on voltage by integrating a Schottky diode, and an enhancement device with a high threshold voltage by a grooved gate. The patterned groove combines with the gate field plate to alleviate the electric field concentration, optimize the electric field distribution, enhance the voltage withstand capacity of the device, and realize the advantages of both a low reverse turn-on voltage, low loss, and high threshold voltage. The integrated diode and transistor processes are compatible, which is beneficial to reducing the module volume and the parasitic effect of the power system.

[0028] Embodiment 2:

[0029] As Figure 7 shown, the difference between this embodiment and Embodiment 1 is that the first end of the patterned groove structure is rectangular in the top view of the device, and the second end of the patterned groove structure is trapezoidal in the top view of the device, and the corners of the patterned groove are all obtuse angles, further alleviating the relatively high electric field distribution near the gate metal 6 and the Schottky anode metal 8, and improving the breakdown voltage of the device.

[0030] Embodiment 3:

[0031] As Figure 8 shown, the difference between this embodiment and Embodiment 1 is that the first end of the patterned groove structure is rectangular in the top view of the device, and the second end of the patterned groove structure is a rounded rectangle in the top view of the device. The design of the rounded rectangle of the patterned groove further alleviates the curvature effect, thereby reducing the leakage current and improving the voltage withstand capacity.

Claims

1. A low-loss reverse-conducting lateral gallium oxide enhancement transistor, comprising, along the vertical direction of the device, a gallium oxide substrate (1), an unintentionally doped gallium oxide buffer layer (2) and a gallium oxide epitaxial layer (3) stacked in sequence from bottom to top; along the lateral direction of the device, a drain metal (4) is provided at one end of the upper surface of the gallium oxide epitaxial layer (3); It is characterized in that The end of the device having the drain metal (4) is defined as the first end of the device, and the end of the device away from the drain metal (4) is defined as the second end of the device; the second end of the device is defined as three regions in sequence along the longitudinal direction of the device, namely, the first region of the second end of the device, the second region of the second end of the device, and the third region of the second end of the device; along the lateral direction of the device, the two ends of the first region of the second end of the device and the third region of the second end of the device are provided with a source metal (7) and a gate groove, respectively, and the source metal (7) and the gate groove at the two ends are separated by the second region of the second end of the device and are symmetrically arranged; the source metal (7) is in contact with the upper surface of the gallium oxide epitaxial layer (3), and the gate groove is formed by etching the gallium oxide epitaxial layer (3). Formation: forming a patterned groove structure in a second region at a second end of the device by patterned etching, wherein the patterned etching process is to etch away the gallium oxide epitaxial layer (3) and the unintentionally doped gallium oxide buffer layer (2) in the patterned region and then directly reach the upper surface of the gallium oxide substrate (1); a dielectric layer (5) is provided on the upper surface of the gallium oxide epitaxial layer (3), the bottom and side of the gate groove, and the bottom and side of the patterned groove structure; a gate metal (6) is filled in the gate groove, and both ends of the upper surface of the gate metal (6) extend in the direction of the drain metal (4) and the source metal (7), respectively, and there is a gap between the gate metal (6) and the drain metal (4) and the source metal (7) in the lateral direction; Along the lateral direction of the device, two ends of the patterned groove structure are defined as a first end of the patterned groove structure and a second end of the patterned groove structure, respectively, wherein the first end of the patterned groove structure is connected to a source metal (7), a Schottky anode metal (8) is provided on the upper surface of the gallium oxide epitaxial layer (3) connected to the second end of the patterned groove structure, along the longitudinal direction of the device, the longitudinal width of the Schottky anode metal (8) is the same as the longitudinal width of the first end of the patterned groove structure, and along the lateral direction of the device, the spacing between the Schottky anode metal (8) and the drain metal (4) is smaller than the spacing between the gate metal (6) and the drain metal (4); The source metal (7) and the Schottky anode metal (8) are electrically connected.

2. A low-loss reverse-conducting lateral gallium oxide enhancement mode transistor according to claim 1, characterized in that: The first end of the patterned groove structure is rectangular in the top view of the device, and the second end of the patterned groove structure is trapezoidal in the top view of the device.

3. A low-loss reverse-conducting lateral gallium oxide enhancement mode transistor according to claim 1, characterized in that: The first end of the patterned groove structure is a rectangle in the top view of the device, and the second end of the patterned groove structure is a rounded rectangle in the top view of the device.

Images