Semiconductor device

Abstract

The invention relates to a semiconductor device. Trenches are periodically formed in the semiconductor substrate on the lower layer side of the temperature sensing diode. The source field plate is arranged in the trench via an insulating film. A P-type diffusion layer is formed between adjacent trenches. The source field plate and the P-type diffusion layer are connected to a source potential.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-216980, including the specification, drawings, and abstract, filed on December 22, 2023, is incorporated herein by reference in its entirety. Background Art

[0003] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device including, for example, a diode for temperature measurement.

[0004] The disclosed technology is listed below.

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-103272

[0006] Patent Document 1 describes a semiconductor device according to the prior art, which has a semiconductor substrate and a polysilicon diode (hereinafter also referred to as a temperature-sensing diode) for detecting the temperature of the semiconductor substrate. The semiconductor substrate has a cell region in the central portion of the chip, where an insulated-gate type power transistor (such as a power metal-oxide-semiconductor field-effect transistor (MOSFET), etc.) is arranged. A ring-shaped P-well region is embedded between the edge of the semiconductor substrate and the cell region. The polysilicon diode is arranged in the ring-shaped P-well region. Summary of the Invention

[0007] In the semiconductor device described in Patent Document 1, a P-well region is formed in the lower layer of the polysilicon diode, where the polysilicon diode is a temperature-sensing diode. In this case, a source potential is supplied to the P-well region, thereby possibly suppressing the output of the temperature-sensing diode from becoming unstable under the influence of fluctuations in the drain voltage or the substrate voltage. However, the process of forming the insulated-gate type power transistor does not necessarily include the process of forming the P-well region. If the process of forming the insulated-gate type power transistor does not include the process of forming the P-well region, then an additional process of forming the P-well region is necessary only for stabilizing the output of the temperature-sensing diode.

[0008] Other problems and novel features will become apparent from the description of this specification and the drawings.

[0009] According to an embodiment, there is provided a semiconductor device having a gate-insulated transistor, a temperature-sensing diode, and a sub-structure of the temperature-sensing diode. The sub-structure of the temperature-sensing diode includes a source field plate arranged in periodically formed trenches and a diffusion layer formed between adjacent trenches. The source field plate and the diffusion layer are connected to a source potential.

[0010] According to an embodiment, a semiconductor device having a gate-insulated transistor and a temperature-sensing diode can stabilize the forward output voltage of the temperature-sensing diode without adding a large number of processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a cross-sectional view of a structural example of a semiconductor device according to a first embodiment of the present disclosure.

[0012] Figure 2 is a top view of an example of a planar structure of a temperature-sensing diode.

[0013] Figure 3 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0014] Figure 4 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0015] Figure 5 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0016] Figure 6 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0017] Figure 7 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0018] Figure 8 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0019] Figure 9 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0020] Figure 10 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0021] Figure 11 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0022] Figure 12 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0023] Figure 13 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0024] Figure 14 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0025] Figure 15 is a cross-sectional view of the semiconductor device during its manufacturing process.

[0026] Figure 16It is a cross-sectional view of a structural example of a semiconductor device according to a second embodiment of the present disclosure.

[0027] Figure 17 It is a cross-sectional view of a semiconductor device during its manufacturing process.

[0028] Figure 18 It is a cross-sectional view of a structural example of a semiconductor device according to a third embodiment of the present disclosure.

[0029] Figure 19 It is a top view of an example of a planar structure of a temperature-sensing diode.

[0030] Figure 20 It is a cross-sectional view of a semiconductor device during its manufacturing process.

[0031] Figure 21 It is a cross-sectional view of a semiconductor device during its manufacturing process. Detailed Description of the Embodiment

[0032] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in which the above-described components for solving problems are applied. For clarity, the following description and drawings have been appropriately abbreviated and simplified. In each of the drawings in the accompanying drawings, the same elements are denoted by the same reference numerals, and redundant descriptions are appropriately omitted.

[0033] In the embodiments described below, for convenience, the present invention is described in multiple sections or embodiments when necessary. However, unless clearly specified otherwise, these sections or embodiments are not independent of each other, and one section or embodiment corresponds partially or completely to another section or embodiment as a modification, detailed or supplementary description, etc. Additionally, in the embodiments described below, when referring to the number of components (including the number of parts, numerical values, quantities, and ranges), the number is not limited to the specified quantity and may be less than or greater than the number, unless clearly specified otherwise, or unless it is obvious from the context that the number is limited to the specified number in principle.

[0034] Furthermore, in the embodiments described below, unless clearly specified otherwise, or unless it is obvious from the context that the component is indispensable in principle, each component (including operation steps) is not indispensable. Similarly, in the embodiments described below, when referring to the shape, positional relationship, etc. of components, etc., unless clearly specified otherwise, or unless it is obvious from the context that the shape, positional relationship, etc. of the component are different in principle, it includes substantially approximate shapes, similar shapes, etc. This also applies to the above numerical values (including the number of parts, numerical values, quantities, and ranges), etc.

[0035] In the following embodiments, the MOSFET includes not only FETs with an oxide film as the gate insulating film, but also FETs using an insulating film other than the oxide film as the gate insulating film. In addition, the MOSFET includes not only FETs in which the gate electrode is formed of metal, but also FETs in which a conductor other than metal is used as the gate electrode. In the following embodiments, an example of a MOSFET is described as an insulated-gate transistor having a split-gate structure. However, the insulated-gate transistor is not limited to the MOSFET and may be an insulated-gate bipolar transistor (IGBT).

[0036] [First Embodiment]

[0037] Figure 1 FIG. is a cross-sectional view showing a structural example of a semiconductor device according to the first embodiment of the present disclosure. The semiconductor device 100 includes a semiconductor substrate 101, a MOSFET 110 which is an insulated-gate transistor, and a temperature-sensing diode 120. The semiconductor substrate 101 is an N-type semiconductor substrate. In the present embodiment, the MOSFET 110 is a vertical MOSFET in which one surface of the semiconductor substrate 101 is the source and the other surface is the drain. The semiconductor device 100 is, for example, a 100V-class power discrete semiconductor.

[0038] In the region of the MOSFET 110, a plurality of trenches 111 are periodically formed in the semiconductor substrate 101. The MOSFET 110 has a source field plate 113 and a gate electrode 114 embedded in each of the trenches 111 via an insulating film 112. The source field plate 113 is supplied with a source potential. The MOSFET 110 has a channel P diffusion layer 115 and a source N+ diffusion layer 116 between two adjacent gate electrodes 114. Each of the gate electrode 114 and the source N+ diffusion layer 116 is covered with an insulating film 135 and an insulating film 136. The MOSFET 110 is a transistor having a split-gate structure in which the gate electrode 114 and the source field plate 133 are embedded in each of the trenches 111, and the source field plate 133 is supplied with a source potential.

[0039] The temperature-sensing diode 120 has a P-type region 121 and an N-type region 122. The temperature-sensing diode 120 is formed of, for example, polysilicon. The P-type region 121 and the N-type region 122 are formed by, for example, introducing impurities into each polysilicon. When current flows, the MOSFET 110 generates heat. The temperature-sensing diode 120 is a diode for temperature measurement, which is used to measure the temperature of the semiconductor device 100.

[0040] A plurality of trenches 131 are formed in the semiconductor substrate 101 in a region on the lower layer side of the temperature sensing diode 120. The width and depth of each of the trenches 131 are set to be equal to the width and thickness of each of the trenches 111 in the MOSFET 110. The distance between two adjacent trenches 131 (i.e., the pitch "a") is equal to the pitch "b" between the trenches 111. The source field plate 133 is disposed in the trench 131 via the insulating film 132. The insulating film 132 is also referred to as the field plate insulating film. The P-type diffusion layer 134 is formed between two adjacent trenches 131. In the substrate depth direction, the position of the bottom portion of the P-type diffusion layer 134 is shallower than the position of the bottom portion of the gate electrode 114 of the MOSFET 110. The source field plate 133 and the P-type diffusion layer 134 are each provided with a source potential.

[0041] In the region on the lower layer side of the temperature sensing diode 120, the insulating film 135 is formed on the upper layer side of the source field plate 133 and the P-type diffusion layer 134. The insulating film 135 covers the source field plate 133 and the P-type diffusion layer 134. The temperature sensing diode 120 is formed on the upper layer of the insulating film 135. The insulating film 135 is also referred to as the diode bottom insulating film. The insulating film 136 is formed on the upper layer side of the temperature sensing diode 120 and the insulating film 135. The insulating film 135 and the insulating film 136 are formed by using, for example, a silicon oxide film formed by chemical vapor deposition (CVD). The insulating film 135 and the insulating film 136 each have a thickness of, for example, approximately 150 nm.

[0042] Figure 2 is a top view showing an example of the planar structure of the temperature sensing diode 120. As Figure 2 shown, the P-type region 121 in the temperature sensing diode 120 is formed in, for example, a rectangular shape. The N-type region 122 is formed to surround the rectangular P-type region 121. In the semiconductor substrate 101, a plurality of trenches 131 are formed in the lower portion of the temperature sensing diode 120, and the plurality of trenches 131 have a predetermined pitch therebetween and extend along a predetermined direction. In addition, a plurality of P-type diffusion layers 134 are formed in the lower portion of the temperature sensing diode 120, and the P-type diffusion layer 134 has a predetermined pitch therebetween and extends along a predetermined direction. As Figure 1 shown, the source field plate 133 is disposed in each of the trenches 131.

[0043] In this embodiment, the semiconductor device 100 has a source field plate 133 and a P-type diffusion layer 134 as sub-structures of the temperature sensing diode 120, and a source potential is provided to the P-type diffusion layer. In the semiconductor device 100, the sub-structures of the temperature sensing diode 120 are set to the source potential, so that the influence of the drain potential fluctuation (i.e., the substrate potential fluctuation) of the MOSFET 110 on the forward output voltage of the temperature sensing diode 120 can be suppressed.

[0044] In addition, the sub-structures of the temperature sensing diode 120 in this embodiment have a structure similar to that of the MOSFET 110 which is the main unit. The trench 131 in the lower part of the temperature sensing diode 120 can be formed simultaneously with the trench 111 in the MOSFET 110. In addition, the source field plate 133 of the lower part of the temperature sensing diode 120 can be formed simultaneously with the source field plate 113 of the MOSFET 110. Further, the P-type diffusion layer 134 of the lower part of the temperature sensing diode 120 can be formed simultaneously with the channel P-diffusion layer 115 of the MOSFET 110.

[0045] Hereinafter, the manufacturing process of the semiconductor device 100 will be described. Figures 3 to 15 The cross-section of the semiconductor device 100 during the manufacturing process of the semiconductor device 100 is shown. As Figure 3 shown, during the process of forming trenches, a plurality of trenches 111 are formed in the region of the MOSFET forming the N-type semiconductor substrate 101. In addition, a plurality of trenches 131 are formed in the region of the semiconductor substrate 101 forming the sub-structures of the temperature sensing diode. Then, as Figure 4 shown, during the process of forming the feed plate insulating film, an insulating film 141 is formed on the surface of the semiconductor substrate 101. The insulating film 141 corresponds to the insulating film 112 of the MOSFET 110 (see Figure 1 ). In addition, the insulating film 141 corresponds to the insulating film 132 of the sub-structures of the temperature sensing diode.

[0046] As Figure 5 shown, during the process of forming electrodes, polysilicon 142 is deposited on the insulating film 141. The deposited polysilicon is planarized by chemical mechanical polishing (CMP). As Figure 6 shown, during the etching process, the polysilicon 142 is completely etched to remove the polysilicon 142 protruding from the trenches 111 and trenches 131.

[0047] Then, as Figure 7As shown, the region of the sub-structure of the temperature-sensing diode is covered by the photoresist 151, and the polysilicon 142 is etched using the photoresist 151 as a mask to remove the part of the polysilicon 142 in each of the trenches 111 in the trench 111. The polysilicon 142 remaining in each of the trenches 111 in the trench 111 corresponds to the source field plate 113 of the MOSFET 110. Additionally, the polysilicon 142 in each of the trenches 131 in the trench 131 corresponds to the source field plate 133 of the sub-structure of the temperature-sensing diode.

[0048] Then, as Figure 8 shown, during the process of forming the gate oxide film, etching is performed to remove part of the insulating film 141. As Figure 9 shown, during the process of forming the gate electrode, polysilicon is deposited in each of the trenches 111 in the trench 111 to form the gate electrode 114. As Figure 10 shown, during the process of forming the channel P diffusion layer, the channel P diffusion layer 115 is formed between two adjacent trenches 111. Additionally, the P-type diffusion layer 134 is formed between two adjacent trenches 131. As Figure 11 shown, during the process of forming the source N+ diffusion layer, the source N+ diffusion layer 116 is formed on part of the channel P diffusion layer 115.

[0049] As Figure 12 shown, during the process of forming the bottom insulating film of the diode, the surface of the semiconductor substrate 101 is covered by the insulating film 135. Then, as Figure 13 shown, during the process of forming the polysilicon, the polysilicon 143 is formed on the part of the insulating film 135 where the temperature-sensing diode 120 is formed. As Figure 14 shown, during the process of forming the temperature-sensing diode, impurities are introduced into the polysilicon 143 to form the P-type region 121 and the N-type region 122. Then, as Figure 15 shown, the insulating film 136 is formed on the surface of the semiconductor substrate 101 to cover the temperature-sensing diode 120.

[0050] [Effect]

[0051] The semiconductor device 100 according to the present embodiment has a sub-structure of a temperature sensing diode 120, which is provided with a trench 131 and a P-type diffusion layer 134, and a source field plate 133 is embedded in the trench 131. The source field plate 133 and the P-type diffusion layer 134 are each connected to the source potential. Even if the substrate potential (i.e., the drain potential of the MOSFET 110) fluctuates, this configuration allows the sub-structure of the temperature sensing diode 120 to be fixed at the source potential. Therefore, even if the substrate potential fluctuates, it is possible to suppress the output of the temperature sensing diode 120 from becoming unstable. In addition, in the present embodiment, the source field plate 133 in each trench 131 embedded in the trench 131 serves as a built-in RC buffer. Therefore, a recovery surge reduction effect can be expected in the semiconductor device 100.

[0052] Compared with Patent Document 1, since a P-well is formed at the lower part of the temperature sensing diode, it is necessary for the process of forming the P-well in Patent Document 1. However, the manufacturing process of the MOSFET 110 of the main body unit does not include a process for forming a P-well. Therefore, if a P-well is to be formed at the lower part of the temperature sensing diode, processes such as photolithography, ion implantation, and high-temperature diffusion need to be added to the manufacturing process of the MOSFET 110. This increases the process cost.

[0053] In the present embodiment, the sub-structure of the temperature sensing diode 120 has a structure similar to that of the MOSFET 110. Therefore, the trench 131, the source field plate 133, and the P-type diffusion layer 134 of the sub-structure of the temperature sensing diode 120 can be formed simultaneously with the trench 111, the source field plate 133, and the channel P-diffusion layer 115 of the MOSFET 110, respectively. Therefore, the present embodiment can suppress the influence of substrate potential fluctuation on the forward output voltage of the temperature sensing diode 120 without increasing the process cost.

[0054] It should be noted that in the semiconductor device 100, the pitch "a" between the trenches 131 in the sub-structure of the temperature sensing diode can be greater than the pitch "b" between the trenches 111 in the MOSFET 110. By providing a larger pitch "a" between the trenches 131 in the sub-structure of the temperature sensing diode, the breakdown voltage of the sub-structure of the temperature sensing diode can be made higher than the breakdown voltage of the main body unit. However, if the pitch "a" between the trenches 131 is significantly increased, the breakdown voltage will decrease. In order to prevent a significant decrease in the breakdown voltage, especially in a low-temperature environment, the pitch "a" between the trenches 131 is set to be, for example, greater than the pitch "b" between the trenches 111, but less than 1.1 times the pitch "b" between the trenches 111.

[0055] When the pitch “a” between the trenches 131 is set to be greater than the pitch “b” between the trenches 111 and less than or equal to 1.1 times the pitch “b”, the breakdown voltage of the sub-structure of the temperature sensing diode 120 can be set to be higher than the breakdown voltage of the main unit, and the MOSFET 110 is formed at the main unit. In this case, even when a voltage equal to or higher than BVDSS is applied between the drain and source of the MOSFET 110 and avalanche breakdown occurs, no current flows to the P-type diffusion layer 134 of the sub-structure of the temperature sensing diode 120, and potential fluctuations of the sub-structure of the temperature sensing diode 120 can be suppressed. Therefore, the output stability of the temperature sensing diode can be improved.

[0056] [Second Embodiment]

[0057] Figure 16 is a cross-sectional view of a structural example of a semiconductor device according to a second embodiment of the present disclosure. Figure 16 The configuration of the semiconductor device 100a shown in Figure 1 differs from the configuration of the semiconductor device 100 shown in that boron 137 is implanted into the bottom portion of each of the trenches 131 in the sub-structure of the temperature sensing diode. In this embodiment, the pitch between the trenches 131 in the sub-structure of the temperature sensing diode may be equal to or greater than the pitch between the trenches 111 in the MOSFET 110.

[0058] Figure 17 is a cross-sectional view of the semiconductor device 100a during the manufacturing process of the semiconductor device 100a. In Figure 3 the process shown, a plurality of trenches 111 are formed in the semiconductor substrate 101. Then, as Figure 17 shown, during the process of implanting boron, boron 137 is implanted into the bottom portion of each of the trenches 111. The subsequent process may be similar to the process shown in Figures 4 to 15 shown.

[0059] [Effect]

[0060] In this embodiment, the sub-structure of the temperature sensing diode 120 has boron 137 injected into the bottom portion of each trench 131 that is implanted into the trench 131. Injecting boron 137 into the bottom portion of each trench 131 in which the source field plate 133 is embedded allows the breakdown voltage of the sub-structure of the temperature sensing diode 120 to be higher than the breakdown voltage when boron is not injected. This configuration allows the breakdown voltage of the sub-structure of the temperature sensing diode 120 in the semiconductor device 100 to be higher than the breakdown voltage of the MOSFET 110. In this case, even when a voltage equal to or higher than the BVDSS voltage is applied between the drain and source of the MOSFET 110 and avalanche breakdown occurs, the potential fluctuation of the sub-structure of the temperature sensing diode 120 can be suppressed. Therefore, the output stability of the temperature sensing diode can be improved. Other effects are similar to those described for the first embodiment.

[0061] [Third Embodiment]

[0062] Figure 18 is a cross-sectional view showing an example of the structure of a semiconductor device according to a third embodiment of the present disclosure. Figure 19 is a top view showing an example of the planar structure of a temperature sensing diode. In this embodiment, the source field plate disposed on the sub-structure of the temperature sensing diode 120 has a source field plate 133a embedded in each trench 131 of the trench 131 and a flat source field plate 133b. The source field plate 133b is also referred to as the diode bottom plate. The source field plate 133a is also referred to as the first part of the source field plate. The source field plate 133b is also referred to as the second part of the source field plate.

[0063] In this embodiment, the source field plate 133b covers the entire lower portion of the temperature sensing diode 120 via the insulating film 135. The source field plate 133a and the source field plate 133b are each provided with a source potential. The semiconductor device 100b according to this embodiment is different from the conductor device 100 according to Figure 1 the first embodiment shown in that a P-type diffusion layer 134 is not formed between two adjacent trenches 131. The semiconductor device 100b can be configured in the same manner as Figure 16 the semiconductor device 100a shown, in which boron 137 is injected into the bottom portion of each trench 131 of the trench 131. In this embodiment, the source field plate 133a and the source field plate 133b embedded in each trench 131 of the trench 131 also function as a built-in RC buffer, and the source field plate 133b is the diode bottom plate.

[0064] Figure 20 and Figure 21 are cross-sectional views of the semiconductor device 100b during the manufacturing process of the semiconductor device 100b. In Figures 3 to 5In the process shown, a plurality of trenches 111 are formed in the semiconductor substrate 101, an insulating film 141 is formed on the surface of the semiconductor substrate 101, and polysilicon 142 is deposited on the insulating film 141. Then, as Figure 20 shown, in the process of forming the diode bottom plate, the region of the sub-structure of the temperature sensing diode is covered with a photoresist 152, and the polysilicon 142 is etched using the photoresist 152 as a mask. This process removes the polysilicon 142 protruding from the trenches 111 in the region of the MOSFET 110. As Figure 20 shown, in the region corresponding to the sub-structure of the temperature sensing diode 120, the polysilicon 142 on the surface of the semiconductor substrate 101 is not removed.

[0065] Then, as Figure 21 shown, the region of the sub-structure of the temperature sensing diode is covered with a photoresist 153, and the polysilicon 142 is etched using the photoresist 153 as a mask to remove a part of the polysilicon 142 in each of the trenches 111. The polysilicon 142 in each of the trenches 111 corresponds to the source field plate 113. The subsequent process can be similar to Figures 8 to 15 the process shown, except that different from Figure 10 the process shown, a P-type diffusion layer 134 is not formed in the region of the sub-structure of the temperature sensing diode.

[0066] In this embodiment, the sub-structure of the temperature sensing diode 120 has a source field plate 133b covering the entire temperature sensing diode 120. In this case, the breakdown voltage of the sub-structure of the temperature sensing diode 120 can be set to be higher than Figure 1 the breakdown voltage of the configuration of the first embodiment shown. In this embodiment, the semiconductor device 100b allows the breakdown voltage of the sub-structure of the temperature sensing diode 120 to be higher than the breakdown voltage of the MOSFET 110. In this case, even if a voltage equal to or higher than the BVDSS voltage is applied between the drain and source of the MOSFET 110 and avalanche breakdown occurs, the potential fluctuation of the sub-structure of the temperature sensing diode 120 can be suppressed.

[0067] In this embodiment, photolithography is added to the manufacturing process of the MOSFET 110 to form the diode bottom plate. However, the addition of photolithography is simpler than the process of forming the P-well. Therefore, this embodiment does not require adding a large number of processes in forming the sub-structure of the temperature sensing diode. Therefore, without increasing the process cost, this embodiment can stabilize the forward output voltage of the temperature sensing diode 120 even when the substrate potential fluctuates.

[0068] It should be noted that the semiconductor device according to the above-described embodiment may have a configuration in which the conductivity type (P-type or N-type) of the semiconductor substrate, semiconductor layer, diffusion layer, etc. is inverted. For example, one of the N-type and P-type conductivity types may be the first conductivity type, and the other conductivity type may be the second conductivity type. In this case, the first conductivity type may be P-type and the second conductivity type may be N-type, or conversely, the first conductivity type may be N-type and the second conductivity type may be P-type.

[0069] In the foregoing, the invention made by the present inventors has been described in detail based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention.

Claims

1. A semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a gate-insulated transistor formed on the semiconductor substrate and having a split-gate structure; Diodes for temperature measurement; as well as The diode substructure is formed on the semiconductor substrate, The substructure of the diode has: Grooves are periodically formed in the semiconductor substrate; a source field plate arranged in each of the trenches via an insulating film, the source field plate being provided with a source potential; a diffusion layer of a second conductivity type opposite to the first conductivity type, formed between adjacent trenches, and the source potential is supplied to the diffusion layer; as well as The diode bottom insulating film covers the source field plate and the diffusion layer and has an upper portion on which the diode is formed.

2. The semiconductor device according to claim 1, The transistor has: Grooves are periodically formed in the semiconductor substrate; a source field plate and a gate electrode arranged in each of the trenches via an insulating film; and The first conductivity type diffusion layer and the second conductivity type diffusion layer are formed between adjacent trenches and are stacked in a depth direction of the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein during the formation of the trenches in the transistor, each of the trenches in the substructure of the diode is formed in the semiconductor substrate, wherein during the process of forming the source field plate of the transistor, the source field plate of the substructure of the diode is formed, and In the process of forming the diffusion layer of the second conductivity type of the transistor, the diffusion layer of the second conductivity type of the substructure of the diode is formed.

4. The semiconductor device according to claim 2, wherein a pitch between the trenches in the substructure of the diode is greater than a pitch between the trenches in the transistor. 5 . The semiconductor device of claim 1 , further having boron implanted into a bottom portion of each of the trenches in the substructure of the diode.

6. A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a gate-insulated transistor formed on the semiconductor substrate and having a split-gate structure; Diodes for temperature measurement; as well as The diode substructure is formed on the semiconductor substrate, The substructure of the diode has: Grooves are periodically formed in the semiconductor substrate; a source field plate provided with a source potential and having a first portion arranged in each of the trenches via an insulating film, and a flat second portion arranged on a surface of the semiconductor substrate via the insulating film; as well as A diode bottom insulating film covers the surface of the semiconductor substrate and the source field plate and has an upper portion on which the diode is formed.

7. The semiconductor device according to claim 6, The transistor has: Grooves are periodically formed in the semiconductor substrate; a source field plate and a gate electrode arranged in each of the trenches via an insulating film; and The diffusion layer of the first conductivity type and the diffusion layer of the second conductivity type are formed between adjacent trenches and are stacked in a depth direction of the semiconductor substrate.

8. The semiconductor device according to claim 7, wherein during the formation of the trenches in the transistor, each of the trenches in the substructure of the diode is formed in the semiconductor substrate, and Wherein during the process of forming the source field plate of the transistor, the source field plate of the substructure of the diode is formed.

9. The semiconductor device of claim 6, further having boron implanted into a bottom portion of each of the trenches in the substructure of the diode.

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