Enhanced multilayer ceramic silicon carbide VDMOS and preparation method thereof

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses an enhanced multilayer ceramic silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) and a preparation method thereof, the enhanced multilayer ceramic silicon carbide VDMOS comprises a plurality of mutually parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer, the grid electrode comprises a left side grid, a ceramic dielectric and a right side grid, and the ceramic dielectric is located between the left side grid and the right side grid; a highly-doped N + layer is formed in the N drift layer through ion implantation, and the profile of the cross section of the highly-doped N + layer is in a U shape. Through the design of the U-shaped highly-doped N + layer, a carrier transverse transmission path is expanded, and the conduction current density and the switching speed are remarkably improved; electric field distribution is balanced in combination with the low-doped N-layer, edge distortion is reduced, and breakdown voltage and device reliability are enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and in particular to an enhanced multi-layer ceramic silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) VDMOS devices have wide applications in new energy, power electronics and other fields due to their advantages such as high breakdown voltage, high-temperature stability and low on-resistance. However, in the prior art, it is still difficult to balance the on-resistance and breakdown voltage performance, and the dynamic performance is insufficient. In response to these challenges, there is an urgent need for an innovative device structure and preparation method to optimize the carrier transport path, enhance the uniformity of the electric field distribution and improve the insulation performance, so as to meet the requirements of modern power electronic systems for high-efficiency and highly reliable SiC power devices.

[0003] The prior patent discloses a manufacturing method of a shielded-gate trench MOSFET with a high-k dielectric (publication number CN115810546A), including the steps of: growing an epitaxial layer above a substrate; forming a hard mask structure composed of a first oxide layer, a silicon nitride dielectric layer and a second oxide layer stacked in sequence; forming a trench by photolithography; depositing a sidewall oxide layer inside the trench; depositing and etching back to form a source polysilicon; wet-etching the sidewall oxide layer to a target depth. In the technology disclosed in this patent, there will be problems such as heat loss caused by the current crowding effect, poor thermal stability of the gate insulating material (such as an increase in the high-temperature leakage current of SiO2), and switching losses caused by the parasitic thyristor effect, thus limiting the reliability and efficiency of the device in high-power, high-frequency and extreme environments. Summary of the Invention

[0004] The present invention provides an enhanced multi-layer ceramic silicon carbide VDMOS and a preparation method thereof to solve the existing technical problems, and solves the problems in the above background art.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, an enhanced multi-layer ceramic silicon carbide VDMOS includes a plurality of MOS cells arranged in parallel. Each MOS cell includes a drain, a semiconductor epitaxial layer, a source and a gate; the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, a P well layer and an N well layer, the gate includes a left gate, a ceramic dielectric and a right gate, and the ceramic dielectric is located in the middle position between the left gate and the right gate; A highly doped N+ layer is formed inside the N drift layer by ion implantation. The cross-sectional profile of the highly doped N+ layer is in a "U" shape, and the left and right ends of the highly doped N+ layer only contact the P well layer.

[0006] Furthermore, the ceramic dielectric is one of alumina or silicon nitride.

[0007] Furthermore, a low-doped N- layer 1 is formed inside the highly doped N+ layer by ion implantation, and the low-doped N- layer 1 divides the highly doped N+ layer into left and right parts.

[0008] Furthermore, a low-doped N- layer 2 is formed inside the highly doped N+ layer by ion implantation, and the low-doped N- layer 2 penetrates to the bottom of the N drift layer and contacts the N substrate layer.

[0009] Furthermore, a low-doped P- layer 2 is formed in the middle area of the N substrate layer in a single MOS cell by ion implantation, and the top end of the low-doped P- layer 2 contacts the N drift layer.

[0010] Furthermore, a low-doped P- layer 1 is formed in the middle area of the N substrate layer in a single MOS cell by ion implantation, and the top end of the low-doped P- layer 1 penetrates the N drift layer and contacts the highly doped N+ layer.

[0011] A preparation method of an enhanced multi-layer ceramic silicon carbide VDMOS includes: S1. An N drift layer, a P+ layer, a P well layer, and an N well layer are sequentially grown on an N substrate layer, and a chemical vapor deposition process is used to control the thickness and doping concentration of each layer; S2. A highly doped N+ layer with a "U"-shaped cross-section is formed in the N drift layer by ion implantation technology, and it is necessary to ensure that its left and right ends only contact the P well layer; S3. Ion implantation is performed inside the highly doped N+ layer to form a low-doped N- layer 1, thereby separating the highly doped N+ layer into left and right parts; S4. Further ion implantation is performed inside the highly doped N+ layer to form a low-doped N- layer 2, which penetrates to the bottom of the N drift layer and contacts the N substrate layer; S5. Two ion implantations are respectively performed in the middle area of the N substrate layer; S6. A metal layer is deposited on the surfaces of the P well layer and the N well layer to form a left gate and a right gate; alumina or silicon nitride is deposited between the two as a ceramic dielectric, and the uniformity and insulation performance of the dielectric layer are controlled by chemical vapor deposition; S7. The electrode contacts of the drain, source, and gate are formed through photolithography and metallization processes.

[0012] Furthermore, in the step S5, the two ion implantations respectively performed in the middle area of the N substrate layer are specifically: 1). A low-doped P- layer 1 is formed, and its top end penetrates the N drift layer and contacts the highly doped N+ layer; 2). A low-doped P- layer 2 is formed, and its top end contacts the N drift layer.

[0013] An enhanced multi-layer ceramic silicon carbide VDMOS and its manufacturing method provided by the present invention achieve the following effects compared with the prior art: 1. Through the design of a "U"-shaped highly doped N+ layer, the present invention expands the lateral carrier transmission path, significantly improves the on-state current density and switching speed; combined with a low-doped N- layer to balance the electric field distribution, reduces edge distortion, and enhances the breakdown voltage and device reliability.

[0014] 2. By introducing a vertical low-resistance path, i.e., a low-doped N- layer penetrating through to the substrate, the present invention optimizes the current distribution, reduces the current crowding effect during dynamic conduction, and is applicable to high-power and high-temperature environments.

[0015] 3. By using alumina or silicon nitride as the ceramic dielectric and combining with the chemical vapor deposition process, the present invention improves the insulation between gates, reduces the leakage current, optimizes the electric field distribution, and avoids the risk of local breakdown.

[0016] 4. Through the design of a low-doped P- layer to form a local PN junction, the present invention reduces the accumulation of reverse recovery charge, reduces the switching loss; at the same time, it optimizes the lateral current distribution, avoids the parasitic thyristor effect, and improves the safety and lifespan in high-voltage applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic structural diagram of the first embodiment of the present invention; Figure 2 It is a schematic structural diagram of the second embodiment of the present invention; Figure 3 It is a schematic structural diagram of the third embodiment of the present invention; Figure 4 It is a schematic structural diagram of the fourth embodiment of the present invention; Figure 5 It is a schematic structural diagram of the fifth embodiment of the present invention.

[0018] In the figure: 1. Drain; 2. N substrate layer; 3. N drift layer; 4. Source; 5. P+ layer; 6. P well layer; 7. N well layer; 8. Gate; 9. Highly doped N+ layer; 10. Low-doped N- layer 1; 11. Low-doped N- layer 2; 12. Low-doped P- layer 1; 13. Low-doped P- layer 2; 81. Left gate; 82. Ceramic dielectric; 83. Right gate. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] To make the technical solutions of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments.

[0020] As Figures 1-5 shown, according to one aspect of the present invention, a manufacturing method of an enhanced multi-layer ceramic silicon carbide VDMOS is provided as follows: Step 1: Grow an N-drift layer 3, a P+-layer 5, a P-well layer 6, and an N-well layer 7 in sequence on the N-substrate layer 2, and use the chemical vapor deposition (CVD) process to control the thickness and doping concentration of each layer; this step ensures the uniformity and interface quality of the semiconductor epitaxial structure through layer-by-layer epitaxial growth, laying the foundation for subsequent processes. The high-precision regulation ability of the CVD process can optimize the electrical characteristics of each layer, reduce the on-resistance of the N-drift layer, and enhance the carrier injection efficiency of the P-well layer, thereby improving the overall breakdown voltage performance and switching response speed of the device.

[0021] Step 2: Form a highly doped N+-layer 9 with a "U"-shaped cross-section in the N-drift layer 3 through ion implantation technology, and ensure that its left and right ends are only in contact with the P-well layer 6; this "U"-shaped structure significantly increases the on-current density by expanding the lateral transport path of carriers. At the same time, the precise contact design between the highly doped N+-layer 9 and the P-well layer 6 can suppress leakage current, optimize the electric field distribution, and avoid the risk of local breakdown, thereby enhancing the reverse blocking ability and reliability of the device.

[0022] Step 3: Perform ion implantation inside the highly doped N+-layer 9 to form a low-doped N--layer 10, thereby separating the highly doped N+-layer 9 into two parts on the left and right; the introduction of the low-doped layer can balance the electric field strength in the highly doped region and reduce the edge electric field distortion, thereby increasing the breakdown voltage. In addition, by adjusting the concentration distribution of the low-doped layer, the balance between on-resistance and breakdown voltage performance can be optimized, which is suitable for high-frequency and high-power scenarios while reducing the dynamic loss of the device.

[0023] Step 4: Further perform ion implantation inside the highly doped N+-layer 9 to form a low-doped N--layer 11, which penetrates to the bottom of the N-drift layer 3 and contacts the N-substrate layer 2; this design provides a low-resistance path for the current in the vertical direction, significantly reducing the on-resistance and thermal loss. The low-doped N--layer 11 can also suppress the current crowding effect during dynamic conduction, improve the current sharing ability and high-temperature stability of the device, and is suitable for fields with strict thermal management requirements such as electric vehicles and industrial power supplies.

[0024] Step 5: Perform two ion implantations in the middle region of the N-substrate layer 2, specifically: 1) Form a low-doped P--layer 12, whose top penetrates the N-drift layer 3 and contacts the highly doped N+-layer 9; 2) Form a low-doped P--layer 13, whose top contacts the N-drift layer 3; The low-doped P--layer 12 optimizes the lateral current distribution and reduces the on-voltage drop by establishing a continuous carrier transport channel; while the low-doped P--layer 13 forms a local PN junction, suppresses the accumulation of reverse recovery charge, and reduces the switching loss. The synergistic effect of the two significantly improves the dynamic performance and radiation resistance of the device, which is suitable for high-voltage switches and extreme environment applications.

[0025] Step Six: Deposit a metal layer on the surfaces of the P-well layer 6 and the N-well layer 7 to form the left gate 81 and the right gate 83; deposit alumina or silicon nitride as the ceramic dielectric 82 between the two, and control the uniformity and insulation performance of the dielectric layer through chemical vapor deposition; the high insulation and thermal stability of the ceramic dielectric 82 can effectively isolate the left and right gates 8, reduce the gate 8 leakage current, and optimize the electric field distribution. Controlling the uniformity of the dielectric layer through chemical vapor deposition further enhances the voltage withstand capacity and long-term reliability of the device, and at the same time provides excellent insulation guarantee for high-frequency operation.

[0026] Step Seven: Form electrode contacts for the drain 1, the source 4, and the gate 8 through photolithography and metallization processes.

[0027] Example 1 As Figure 1 shown, the enhanced multi-layer ceramic silicon carbide VDMOS includes a plurality of juxtaposed MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 4, and a gate 8; the semiconductor epitaxial layer includes an N-substrate layer 2, an N-drift layer 3, a P+-layer 5, a P-well layer 6, and an N-well layer 7, and is characterized in that: the gate 8 includes a left gate 81, a ceramic dielectric 82, and a right gate 83, and the ceramic dielectric 82 is located in the middle of the left gate 81 and the right gate 83; the ceramic dielectric 82 is one of alumina or silicon nitride. By introducing the ceramic dielectric 82 (alumina or silicon nitride) into the gate structure, the left gate 81 is isolated from the right gate 83, significantly improving the voltage withstand performance and insulation performance of the device. The high thermal stability and chemical inertness of the ceramic dielectric 82 can effectively reduce the gate 8 leakage current, while optimizing the electric field distribution and reducing the risk of local electric field concentration.

[0028] A highly doped N+-layer 9 is formed inside the N-drift layer 3 through ion implantation. The cross-sectional profile of the highly doped N+-layer 9 is in a "U" shape, and the left and right ends of the highly doped N+-layer 9 only contact the P-well layer 6. The design of the "U"-shaped highly doped N+-layer 9 makes the carrier transmission path more efficient, further improving the on-state characteristics and switching speed of the device.

[0029] Example 2 As Figure 2 shown, a lowly doped N--layer 10 is formed inside the highly doped N+-layer 9 through ion implantation, and the lowly doped N--layer 10 divides the highly doped N+-layer 9 into left and right parts. Forming the lowly doped N--layer 10 inside the highly doped N+-layer 9 divides the highly doped region into left and right parts. This layered structure can balance the electric field strength, avoid electric field distortion at the edge of the highly doped region, thereby enhancing the breakdown voltage and reliability of the device. At the same time, the introduction of the lowly doped layer can adjust the carrier concentration distribution, optimize the balance between the on-resistance and the voltage withstand performance, and is suitable for high-frequency and high-power application scenarios.

[0030] Example 3 As Figure 3 shown, a low-doped N-layer II 11 is formed inside the highly doped N+ layer 9 by ion implantation, and the low-doped N-layer II 11 penetrates to the bottom of the N-drift layer 3 and contacts the N-substrate layer 11. The low-doped N-layer II 11 is implanted inside the highly doped N+ layer 9 so that it penetrates to the bottom of the N-drift layer 3 and contacts the N-substrate layer 2. This structure provides a low-resistance path for the current in the vertical direction, greatly reducing the on-resistance and thermal loss. At the same time, the low-doped N-layer II 11 can suppress the current crowding effect during dynamic conduction, improve the current sharing ability and high-temperature stability of the device, and is suitable for high-reliability fields such as electric vehicles and industrial power supplies.

[0031] Example 4 As Figure 4 shown, a low-doped P-layer II 13 is formed in the middle region of the N-substrate layer 2 in a single MOS cell by ion implantation, and the top of the low-doped P-layer II 13 contacts the N-drift layer 3. The low-doped P-layer II 13 is implanted in the middle region of the N-substrate 2, and its top contacts the N-drift layer 3. This P-type layer can form a local PN junction, effectively suppressing the accumulation of reverse recovery charge and reducing the switching loss. In addition, P-type doping can adjust the carrier recombination rate between the substrate and the drift layer, reduce the leakage current and improve the radiation resistance of the device, and is suitable for extreme environments such as aerospace and nuclear energy.

[0032] Example 5 As Figure 5 shown, a low-doped P-layer I 12 is formed in the middle region of the N-substrate layer 2 in a single MOS cell by ion implantation, and the top of the low-doped P-layer I 12 penetrates the N-drift layer 3 and contacts the highly doped N+ layer 9. The low-doped P-layer I 12 is implanted in the middle region of the N-substrate 2, and its top penetrates the N-drift layer 3 and contacts the highly doped N+ layer 9. This design optimizes the lateral current distribution and reduces the voltage drop during conduction by forming a continuous carrier transmission channel. At the same time, the contact between the P-type layer and the N+ layer can enhance the reverse blocking ability of the device, avoid the parasitic thyristor effect, and significantly improve the safety and life of the device in high-voltage switching applications.

[0033] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims

1. An enhanced multi-layer ceramic silicon carbide VDMOS, which is composed of a number of MOS cells arranged side by side. Each of the MOS cells includes a drain (1), a semiconductor epitaxial layer, a source (4), and a gate (8); the semiconductor epitaxial layer includes an N substrate layer (2), an N drift layer (3), a P+ layer (5), a P well layer (6), and an N well layer (7), and is characterized in that: The gate (8) includes a left gate (81), a ceramic dielectric (82), and a right gate (83), and the ceramic dielectric (82) is located in the middle of the left gate (81) and the right gate (83); A highly doped N+ layer (9) is formed inside the N drift layer (3) by ion implantation. The cross-sectional profile of the highly doped N+ layer (9) is in a "U" shape, and the left and right ends of the highly doped N+ layer (9) are only in contact with the P-well layer (6).

2. The enhanced multi-layer ceramic silicon carbide VDMOS according to claim 1, characterized in that: The ceramic dielectric (82) is one of alumina or silicon nitride.

3. The enhanced multi-layer ceramic silicon carbide VDMOS according to claim 1, characterized in that: A low-doped N- layer one (10) is formed inside the highly doped N+ layer (9) by ion implantation, and the low-doped N- layer one (10) divides the highly doped N+ layer (9) into two parts on the left and right.

4. The enhanced multi-layer ceramic silicon carbide VDMOS according to claim 1, wherein: A low-doped N- layer two (11) is formed inside the highly doped N+ layer (9) by ion implantation, and the low-doped N- layer two (11) penetrates to the bottom of the N drift layer (3) and contacts the N substrate layer (11).

5. The enhanced multi-layer ceramic silicon carbide VDMOS according to claim 1, characterized in that: A low-doped P- layer two (13) is formed in the middle region of the N substrate layer (2) in a single MOS cell by ion implantation, and the top of the low-doped P- layer two (13) contacts the N drift layer (3).

6. The enhanced multi-layer ceramic silicon carbide VDMOS according to claim 1, wherein: A low-doped P- layer one (12) is formed in the middle region of the N substrate layer (2) in a single MOS cell by ion implantation, and the top of the low-doped P- layer one (12) penetrates the N drift layer (3) and contacts the highly doped N+ layer (9).

7. A preparation method of an enhanced multi-layer ceramic silicon carbide VDMOS, characterized in that, Applied to the silicon carbide VDMOS according to any one of claims 1-6, the preparation method of the enhanced multi-layer ceramic silicon carbide VDMOS is as follows: S1. An N drift layer (3), a P+ layer (5), a P-well layer (6), and an N-well layer (7) are sequentially grown on the N substrate layer (2), and a chemical vapor deposition process is used to control the thickness and doping concentration of each layer; S2. A highly doped N+ layer (9) with a "U" - shaped cross-section is formed in the N drift layer (3) by ion implantation technology, and it is necessary to ensure that its left and right ends are only in contact with the P-well layer (6); S3. Ion implantation is performed inside the highly doped N+ layer (9) to form a low-doped N- layer one (10), thereby separating the highly doped N+ layer (9) into two parts on the left and right; S4. Further ion implantation is performed inside the highly doped N+ layer (9) to form a low-doped N- layer two (11), so that it penetrates to the bottom of the N drift layer (3) and contacts the N substrate layer (2); S5. Two ion implantations are respectively performed in the middle region of the N substrate layer (2); S6. A metal layer is deposited on the surfaces of the P-well layer (6) and the N-well layer (7) to form a left gate (81) and a right gate (83); alumina or silicon nitride is deposited between them as the ceramic dielectric (82); S7. The electrode contacts of the drain (1), the source (4), and the gate (8) are formed through photolithography and metallization processes.

8. The manufacturing method of the enhanced multi-layer ceramic silicon carbide VDMOS according to claim 1, characterized in that: In the step S5, the two ion implantations respectively performed in the middle region of the N substrate layer (2) are specifically as follows: 1). A low-doped P- layer one (12) is formed, and its top penetrates the N drift layer (3) and contacts the highly doped N+ layer (9); 2), form a low-doped P-layer two (13) so that its top contacts the N-drift layer (3).

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