Super junction device and manufacturing method thereof

Abstract

The invention relates to a super junction device and a manufacturing method thereof. The super junction device comprises a substrate; the super junction structure is located on the substrate and comprises N-type regions and P-type regions which are alternately arranged in the first direction; a drain region; the source electrode region and the drain electrode region are located on the two sides, in the extending direction of the N-type region and the P-type region, of the super-junction device, and the super-junction structure is located between the source electrode region and the drain electrode region; a gate over a region between the drain region and the source region; the field plate structure is located between the grid electrode and the drain electrode region and is arranged close to the drain electrode region, the field plate structure comprises an insulating layer and a conductive part, the insulating layer is arranged on the inner surface of the sunken structure, the conductive part is located in the sunken structure, and the periphery and the bottom surface of the conductive part are surrounded by the insulating layer. The drain end longitudinal field plate is introduced on the basis of the transverse super junction, so that the obvious substrate-assisted depletion effect of the drain end is counteracted to ensure super junction charge balance, and relatively high breakdown voltage can be obtained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a superjunction device, and also relates to a manufacturing method of a superjunction device. Background Art

[0002] The use of a superjunction structure with longitudinally alternating PN junction structures instead of a uniformly lightly doped high-resistance drift layer in a traditional power device can achieve a lower on-resistance.

[0003] However, in a lateral device, especially under a high voltage at the drain end, due to the influence of the substrate-assisted depletion effect, the charge balance in the P / N regions of the superjunction structure is broken, resulting in a sharp drop in breakdown voltage. Summary of the Invention

[0004] Based on this, it is necessary to provide a superjunction device with a higher breakdown voltage.

[0005] A superjunction device includes: a substrate; a superjunction structure located on the substrate, including N-type regions and P-type regions alternately arranged along a first direction, and the extending directions of the N-type regions and P-type regions in the horizontal plane are perpendicular to the first direction; a drain region; a source region, the source region and the drain region are located on both sides of the superjunction device in the extending direction, and at least part of the superjunction structure is located between the source region and the drain region; a gate, at least part of the gate is located above the region between the drain region and the source region; a field plate structure located between the gate and the drain region and close to the drain region, the field plate structure includes an insulating layer and a conductive part, the insulating layer is provided on the inner surface of a recessed structure, and the conductive part is located in the recessed structure and is surrounded by the insulating layer on all sides and the bottom surface.

[0006] The above superjunction device introduces a drain-end longitudinal field plate on the basis of a lateral superjunction to offset the significant substrate-assisted depletion effect at the drain end to ensure the charge balance of the superjunction, and can obtain a higher breakdown voltage.

[0007] In one embodiment, the source region and the drain region are strip-shaped structures extending along the first direction.

[0008] In one embodiment, the drain region is located in the superjunction structure.

[0009] In one embodiment, the field plate structure includes a plurality arranged in a row along the first direction.

[0010] In one embodiment, the field plate structures arranged in a row along the first direction are electrically connected.

[0011] In one embodiment, the field plate structure is a floating field plate.

[0012] In one embodiment, the material of the conductive part is polysilicon.

[0013] In one embodiment, the superjunction device further includes a well region, the source region is located in the well region, the conduction type of the source region is opposite to that of the well region, and at least part of the superjunction structure is located between the well region and the drain region.

[0014] In one embodiment, the device is a lateral device.

[0015] In one embodiment, the device is a laterally diffused metal oxide semiconductor field effect transistor.

[0016] In one embodiment, the superjunction device further includes a drift region, the drain region is in direct contact with the drift region, and the junction between the drift region and the superjunction structure is located between the gate and the field plate structure.

[0017] In one embodiment, the drift region is an N-type drift region, and the doping concentration is higher than that of the N-type region.

[0018] In one embodiment, the depth of the field plate structure at a position close to the drain region is greater than that at a position far from the drain region.

[0019] In one embodiment, the field plate structures are arranged in a matrix on the horizontal plane, and the depth of the field plate structure close to the drain region is greater than that of the field plate structure far from the drain region.

[0020] It is also necessary to provide a manufacturing method of a superjunction device.

[0021] A manufacturing method of a superjunction device includes: obtaining a wafer with a superjunction structure formed on a substrate; the superjunction structure includes N-type regions and P-type regions arranged alternately in a first direction, and the extending directions of the N-type regions and P-type regions on the horizontal plane are perpendicular to the first direction; forming a gate, a drain region and a source region; the source region and the drain region are located on both sides of the extending direction, the gate is located above the region between the drain region and the source region, and at least part of the superjunction structure is located between the drain region and the source region; forming a field plate structure at a position close to the drain region between the gate and the drain region; the field plate structure includes an insulating layer formed on the inner surface of a concave structure, and a conductive part formed in the concave structure and surrounded by the insulating layer on all sides and the bottom surface.

[0022] The above manufacturing method of the superjunction device introduces a drain-end longitudinal field plate on the basis of a lateral superjunction, so as to offset the significant substrate-assisted depletion effect at the drain end to ensure the charge balance of the superjunction, and a higher breakdown voltage can be obtained. Description of the Drawings

[0023] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the presently understood best mode of these inventions.

[0024] Figure 1 is a three-dimensional schematic diagram of a superjunction device according to an embodiment of the present application;

[0025] Figure 2 is a three-dimensional schematic diagram of a superjunction device according to another embodiment of the present application;

[0026] Figure 3 is a three-dimensional schematic diagram of a superjunction device according to yet another embodiment of the present application;

[0027] Figure 4 is an example of the distribution of the recessed structure (holes) of the field plate structure on a horizontal plane;

[0028] Figure 5 is a flowchart of a manufacturing method of a superjunction device according to an embodiment of the present application;

[0029] Figure 6 is an embodiment of the present application Figure 5 sub-step flowchart of step S530. Detailed Description of the Invention

[0030] To facilitate understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0032] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be denoted as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0033] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes as shown are to be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the specific shapes of regions shown herein but include shape deviations due to, for example, manufacturing. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the invention.

[0036] The semiconductor field terms used herein are common technical terms for those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentrations, simply, P+ type represents the P-type with a heavy doping concentration, P type represents the P-type with a medium doping concentration, P- type represents the P-type with a light doping concentration, N+ type represents the N-type with a heavy doping concentration, N type represents the N-type with a medium doping concentration, and N- type represents the N-type with a light doping concentration.

[0037] Figure 1 is a three-dimensional schematic diagram of a superjunction device in an embodiment of the present application. To better show the device structure, Figure 1 partial structures are made transparent. In an embodiment of the present application, the superjunction device includes a substrate 101, a source region 108, a drain region 109, a gate 110, a superjunction structure, and a field plate structure. The superjunction structure includes N-type regions 103 and P-type regions 104 alternately arranged along a first direction (i.e., Figure 1 the X-axis direction in Figure 1 ), and the N-type regions 103 and P-type regions 104 extend in the Y-axis direction in the horizontal plane. The field plate structure includes an insulating layer 106 provided on the inner surface of a recessed structure ( Figure 1 not labeled in Figure 1In the illustrated embodiment, the superjunction device is an N-channel device, more specifically an N-channel laterally diffused metal oxide semiconductor field effect transistor (NLDMOSFET). Therefore, the first conduction type is N-type and the second conduction type is P-type. In other embodiments, the first conduction type may also be P-type and the second conduction type may be N-type.

[0038] For the above-mentioned superjunction device, a drain-end longitudinal field plate is introduced on the basis of the lateral superjunction to offset the significant substrate-assisted depletion effect at the drain end to ensure superjunction charge balance, and a higher breakdown voltage can be obtained.

[0039] In an embodiment of the present application, the superjunction device further includes a well region 102 of the second conduction type. The source region 108 is located in the well region 102. At least part of the superjunction structure is located between the well region 102 and the drain region 109.

[0040] In an embodiment of the present application, the superjunction device further includes a body extraction region 107. The body extraction region 107 is located in the well region 102, has the same conduction type as the well region 102, and has a doping concentration higher than that of the well region 102. In an embodiment of the present application, the body extraction region 107 is a strip-shaped structure extending along the X-axis direction.

[0041] In an embodiment of the present application, the field plate structure is a floating field plate, that is, the conductive part 105 has no externally connected potential. In an embodiment of the present application, the field plate structure includes a plurality of ( Figure 1 arranged in a row along the first direction (the X-axis direction in Figure 1 ). In an embodiment of the present application, the field plate structures arranged in a row along the first direction are electrically connected (that is, the conductive parts 105 arranged in a row along the first direction are electrically connected). Further, each conductive part 105 can be connected to the metal wire 111 through the conductive material in the contact hole 112 penetrating the interlayer dielectric layer (not shown in

[0042] In an embodiment of the present application, the material of the conductive part 105 is polysilicon. In other embodiments, the material of the conductive part 105 can also be metal or alloy. In an embodiment of the present application, the insulating layer 106 is an oxide layer, such as a silicon dioxide layer.

[0043] In an embodiment of the present application, the gate 110 is made of polysilicon material, and the threshold voltage of the device can be adjusted by doping the polysilicon. In other embodiments, metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate 110. In an embodiment of the present application, the gate 110 extends above the source region 108 or to the edge of the source region 108, that is, overlaps with a partial region at the edge of the source region 108 or is tangent to the edge of the source region 108. A gate dielectric layer is provided at the bottom of the gate 110 (Figure 1 not shown). In an embodiment of the present application, the substrate 101 is a semiconductor substrate, and its material can be undoped single-crystalline silicon, doped single-crystalline silicon, silicon on insulator (SOI), silicon-on-insulator stacked silicon (SSOI), silicon-on-insulator stacked silicon germanium (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), etc. It can also be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In Figure 1 the illustrated embodiment, the constituent material of the substrate 101 is selected as single-crystalline silicon.

[0044] In an embodiment of the present application, the superjunction device is a lateral device.

[0045] In Figure 1 the illustrated embodiment, the well region 102 is a P well, the body extraction region 107 is a P+ region, and the source region 108 and the drain region 109 are N+ regions. The source region 108 and the drain region 109 are strip-shaped structures extending in the X-axis direction. The drain region 109 is located in the superjunction structure.

[0046] In an embodiment of the present application, the superjunction structure is disposed on one side close to the source region 208, and the drift region 213 is disposed on the side close to the drain region 209. The drain region 209 is in direct contact with the drift region 213, and the junction between the drift region 213 and the superjunction structure is located between the gate 210 and the field plate structure. This semi-superjunction structure removes the superjunction at the position close to the drain-end drift region, which can increase the process tolerance and improve the device stability. Refer to Figure 2 which also has a substrate 201, a well region 202, an N-type region 203, a P-type region 204, a conductive part 205, an insulating layer 206, a body extraction region 207, a source region 208, a drain region 209, a gate 210, a metal wire 211, and a contact hole 212. The main difference between it and Figure 1 is that the superjunction structure is only formed on the left half in the figure, and the right half is the drift region 213. The drain region 209 is located in the drift region 213. In an embodiment of the present application, the drift region 213 is an N-type drift region, and its doping concentration is higher than that of the N-type region 203. In this way, when the N-type region 203 extends to the drift region 213, there is a change in the doping concentration, which can further reduce the specific on-resistance.

[0047] In an embodiment of the present application, the depth of the field plate structure at the position close to the drain region 309 in each cell of the superjunction device is greater than the depth at the position far from the drain region 309. Further, the cross-section of the field plate structure in the horizontal plane is distributed in a matrix. Figure 4An example of the distribution of the recessed structure (hole) of the field plate structure on the horizontal plane, and the depth of the field plate structure closer to the drain region 309 is greater than the depth of the field plate structure farther from the drain region 309. Refer to Figure 3 , which also has a substrate 301, a well region 302, an N-type region 303, a P-type region 304, a conductive portion 305, an insulating layer 306, a body lead-out region 307, a source region 308, a drain region 309, a gate 310, a metal connection 311, and a contact hole 312. The difference between it and Figure 1 mainly lies in that the field plate structure has multiple columns. In each cell of the superjunction device, the deeper the depth of the field plate structure closer to the drain region 309 (i.e., the depth of the conductive portion 305), and the shallower the depth of the field plate structure closer to the source region 308, thus forming a field plate structure with a gradually changing depth. The longitudinally deepening field plate from the source to the drain is equivalent to an increasingly strong depletion effect, which can effectively shield the substrate-assisted depletion effect and maintain charge balance.

[0048] The present application correspondingly provides a manufacturing method of a superjunction device for manufacturing the superjunction device described in any of the above embodiments. Figure 5 is a flowchart of the manufacturing method of the superjunction device according to an embodiment of the present application, including the following steps:

[0049] S510, obtain a wafer with a superjunction structure formed on the substrate.

[0050] In an embodiment of the present application, an epitaxial layer can be first formed on the substrate of the wafer, and then ions with a conductive type opposite to that of the epitaxial layer are implanted into the epitaxial layer to form a superjunction structure. For example, if a P-type epitaxial layer is formed on the substrate, N-type ions are implanted to form an N-type region in the epitaxial layer; if an N-type epitaxial layer is formed on the substrate, P-type ions are implanted to form a P-type region in the epitaxial layer. The superjunction structure includes N-type regions and P-type regions alternately arranged along a first direction, and the extending direction of the N-type regions and P-type regions on the horizontal plane is perpendicular to the first direction.

[0051] The substrate is a semiconductor substrate, and its material can be undoped single-crystalline silicon, doped single-crystalline silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc., and can also be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In an embodiment of the present application, the constituent material of the substrate is selected as single-crystalline silicon of the second conductive type. In an embodiment of the present application, the first conductive type is N-type and the second conductive type is P-type; in other embodiments, it can also be that the first conductive type is P-type and the second conductive type is N-type.

[0052] S520 forms a gate, a drain region, and a source region.

[0053] The source region and the drain region are located on both sides of the aforementioned extending direction. The gate is located above the region between the drain region and the source region, and at least part of the superjunction structure is located between the drain region and the source region. The source region and the drain region have a first conductivity type. In an embodiment of the present application, the gate is made of polysilicon material, and the threshold voltage of the device can be adjusted by doping the polysilicon; in other embodiments, metals, metal nitrides, metal silicides, or similar compounds can also be used as the material of the gate.

[0054] In an embodiment of the present application, polysilicon can be deposited first, patterned (such as lithography) and etched to form the gate, and then the drain region and the source region can be formed by ion implantation (implanting ions of the first conductivity type).

[0055] S530 forms a field plate structure.

[0056] A field plate structure is formed at a position close to the drain region between the gate and the drain region. The field plate structure includes an insulating layer and a conductive part. The insulating layer is provided on the inner surface of the recessed structure (which can be a hole or a groove), and the conductive part is located inside the recessed structure and is surrounded by the insulating layer on all sides and the bottom surface.

[0057] In the manufacturing method of the above-mentioned superjunction device, a drain-side longitudinal field plate is introduced on the basis of the lateral superjunction to offset the significant substrate-assisted depletion effect at the drain end to ensure the superjunction charge balance, and a higher breakdown voltage can be obtained.

[0058] See Figure 6 , in an embodiment of the present application, step S530 includes:

[0059] S532 forms a recessed structure at a position close to the drain region between the gate and the drain region.

[0060] In an embodiment of the present application, the recessed structure is a row of blind holes, and the column direction is the first direction. The recessed structure can be formed by patterning (such as lithography) and etching.

[0061] S534 forms an insulating layer on the inner surface of the recessed structure.

[0062] In an embodiment of the present application, the insulating layer is an oxide layer, such as a silicon dioxide layer. The insulating layer can be formed by thermal oxidation or deposition process.

[0063] S536 fills the recessed structure with a conductive material to form a conductive part.

[0064] In one embodiment of the present application, the conductive material is polysilicon. The conductive portion can be formed by depositing polysilicon into the recessed structure. In other embodiments, the conductive material can also be a metal or an alloy.

[0065] In one embodiment of the present application, after step S510 and before step S520, there is also a step of forming a well region of the second conductivity type. The well region can be specifically formed by patterning (such as lithography) and ion implantation (implanting ions of the second conductivity type). The source region of step S520 is formed in the well region.

[0066] In one embodiment of the present application, after forming the well region of the second conductivity type and before step S520, there is also a step of forming a field oxide layer. The active region is defined by the field oxide layer.

[0067] In one embodiment of the present application, step S520 further includes a step of forming a body extraction region in the well region. The body extraction region has the second conductivity type and a doping concentration higher than that of the well region. The body extraction region can be formed by patterning (such as lithography) and ion implantation (implanting ions of the second conductivity type).

[0068] In one embodiment of the present application, after step S510 and before step S520, there is also a step of forming a drift region on one side of the substrate near the drain region. The junction of the drift region and the superjunction structure is located between the gate (formed subsequently) and the field plate structure. In one embodiment of the present application, the drift region is an N-type drift region, and its doping concentration is higher than that of the N-type region. In one embodiment of the present application, the drift region can be formed by patterning (such as lithography) and ion implantation (implanting N-type ions).

[0069] In one embodiment of the present application, the depth of the field plate structure at the position near the drain region is greater than that at the position far from the drain region. In one embodiment of the present application, the cross-section of each field plate structure on the horizontal plane is distributed in a matrix, and the depth of the field plate structure near the drain region is greater than that of the field plate structure far from the drain region. In one embodiment of the present application, each field plate structure is a floating field plate

[0070] In one embodiment of the present application, after step S550, it further includes: forming an interlayer dielectric layer on the wafer surface. Etching the interlayer dielectric layer to form contact holes. Filling the contact holes with a metal or an alloy. Forming a metal layer on the interlayer dielectric layer, and each column of field plate structures is electrically connected through the metal layer.

[0071] The manufacturing method of the superjunction device of the present application and the superjunction device are based on the same inventive concept. For the content not specifically described in the manufacturing method of the superjunction device, reference can be made to the introduction of the superjunction device above.

[0072] It should be understood that although the steps in the flowcharts of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0073] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0074] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0075] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A superjunction device, characterized in that, Comprising: A substrate; A superjunction structure located on the substrate, including N-type regions and P-type regions alternately arranged along a first direction, and the extending directions of the N-type regions and P-type regions in the horizontal plane are perpendicular to the first direction; A drain region; A source region, the source region and the drain region are located on both sides of the superjunction device in the extending direction, and at least part of the superjunction structure is located between the source region and the drain region; A gate, at least part of the gate is located above the region between the drain region and the source region; A field plate structure located between the gate and the drain region and close to the drain region, the field plate structure includes an insulating layer and a conductive portion, the insulating layer is provided on the inner surface of the recessed structure, and the conductive portion is located in the recessed structure and is surrounded by the insulating layer on all sides and the bottom surface; 2. The superjunction device according to claim 1, wherein The source region and the drain region are strip-shaped structures extending along the first direction; and / or The drain region is located in the superjunction structure.

3. The superjunction device according to claim 1, characterized in that, The field plate structure includes a plurality of them arranged in a row along the first direction.

4. The superjunction device according to claim 3, characterized in that, Each of the field plate structures arranged in a row along the first direction is electrically connected; and / or The field plate structure is a floating field plate.

5. The superjunction device according to claim 1, wherein The material of the conductive portion is polysilicon; and / or The superjunction device further includes a well region, the source region is located in the well region, the conductivity type of the source region is opposite to that of the well region, and at least part of the superjunction structure is located between the well region and the drain region.

6. The superjunction device according to claim 1, characterized in that, The device is a lateral device, or the device is a laterally diffused metal oxide semiconductor field effect transistor.

7. The super junction device according to any one of claims 1, 3-6, characterized in that, It further includes a drift region, the drain region is in direct contact with the drift region, and the junction of the drift region and the superjunction structure is located between the gate and the field plate structure.

8. The superjunction device according to claim 7, characterized in that, The drift region is an N-type drift region, and the doping concentration is higher than that of the N-type region.

9. The superjunction device according to any one of claims 1, 3-6, characterized in that, The depth of the field plate structure at the position close to the drain region is greater than the depth at the position far from the drain region; and / or Each of the field plate structures is distributed in a matrix on the horizontal plane, and the depth of the field plate structure close to the drain region is greater than the depth of the field plate structure far from the drain region.

10. A manufacturing method of a superjunction device, including: Obtaining a wafer with a superjunction structure formed on a substrate; the superjunction structure includes N-type regions and P-type regions alternately arranged along a first direction, and the extending directions of the N-type regions and P-type regions in the horizontal plane are perpendicular to the first direction; Forming a gate, a drain region and a source region; the source region and the drain region are located on both sides of the extending direction, the gate is located above the region between the drain region and the source region, and at least part of the superjunction structure is located between the drain region and the source region; Forming a field plate structure at the position close to the drain region between the gate and the drain region; the field plate structure includes an insulating layer formed on the inner surface of a recessed structure, and a conductive portion formed in the recessed structure and surrounded by the insulating layer on all sides and the bottom surface.

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