Design method of composite cellular power semiconductor device and power semiconductor device

Abstract

The invention discloses a method for designing a composite cellular power semiconductor device, which comprises the following steps of: adopting wide-size cells in a region needing PPlus doping, and adopting narrow-size cells in a region which does not need PPlus doping and has a large process window; and the wide-size cells and the narrow-size cells are transformed and alternately arranged, and are finally distributed in an active region of the device. The process capability and the processing precision of a chip manufacturing production line do not need to be improved; the cell size of the device can be further reduced, the on-resistance is reduced, and the product performance is improved; the yield of a single wafer chip is increased, and the production cost of the single chip is reduced; no extra process is introduced, so that the production and processing difficulty of the chip is reduced; the reliability of the device is not influenced by the reduction of the cellular size, and the yield, consistency and reliability of products are improved; the cellular structure design scheme can be suitable for cellular structure design of various types of power devices such as diodes, MOS (Metal Oxide Semiconductor), IGBT (Insulated Gate Bipolar Translator) and the like made of silicon-based, silicon carbide-based and other semiconductor materials, and the technical applicability is high.

Description

Technical Field

[0001] The present invention relates to a layout design method and a manufacturing method of a power semiconductor device, and in particular to a design method of a composite cell power semiconductor device and a power semiconductor device, belonging to the fields of semiconductor component design and semiconductor technology. Background Art

[0002] Silicon carbide MOSFET power devices are gradually becoming the best alternatives to traditional power devices due to their excellent device performance and better comprehensive benefits brought to the power processing system. In the fields of new energy vehicles, wind power, photovoltaic energy storage, etc., power devices represented by silicon carbide MOSFETs are being more widely used. However, limited by the relatively high device cost, the usage scale of silicon carbide power devices is still limited in some price-sensitive application fields.

[0003] An important way to improve the performance of silicon carbide MOSFET devices and reduce device costs is to reduce the device cell size, such as the trench device structure. Although the trench device structure can significantly reduce the device cell size, the device processing technology is complex, the manufacturing difficulty is large, and the reliability is poor. The planar device processing technology is relatively simple, the manufacturing technology is mature, and the reliability is higher. Currently, it is still the mainstream product technology solution of major silicon carbide device manufacturers. However, limited by the structural dimensions and processing accuracy of the JFET region, P+ region, etc. in the planar device, further reducing the cell size will have an adverse impact on the device performance. Summary of the Invention

[0004] In order to solve the defects existing in the prior art, the present invention discloses a design method of a composite cell power semiconductor device, and its technical solution is as follows:

[0005] A design method of a composite cell power semiconductor device, characterized in that: wide-size cells are used in the regions where PPlus doping is required, and narrow-size cells are used in the regions where PPlus doping is not required; the wide-size and narrow-size cells are arranged alternately and finally cover the active region of the device; the wide-size cells are used to ensure the process window and channel length consistency of the PPlus doping region, and the narrow-size cells are used to improve the cell distribution density and the utilization rate of the active region.

[0006] The present invention also discloses a power semiconductor device with a wide and narrow composite cell size, designed by the above method, including an active region, a gate control bus region, and a terminal region, characterized in that:

[0007] The active region is composed of alternately arranged wide-size cells (2011) and narrow-size cells (2012), wherein the wide-size cells include a PPlus doping region (202), and the narrow-size cells do not include a PPlus doping region;

[0008] The device is a SiC MOS device, which includes the following components from bottom to top:

[0009] a) An N-type heavily doped SiC substrate (101);

[0010] b) An N-type lightly doped SiC epitaxial layer (102) epitaxially grown on the substrate;

[0011] c) Alternately arranged wide-size PWell regions (2011) and narrow-size PWell regions (2012) formed in the epitaxial layer, where a PPlus implantation region (202) is provided in the wide-size PWell region; d) A channel region (203) formed at the edge of the PWell region by a self-alignment process, and the channel region maintains the same channel length in the narrow-wide cell transition region (203A) and the straight region (203B); e) An NPlus source region (204) and a JFET region (206) formed outside the channel region;

[0012] f) A gate oxide layer (301) covering the JFET region and a polysilicon gate (302) located thereon; g) An ILD dielectric layer (303) covering the polysilicon gate, and a source contact hole (207) penetrating through to the NPlus source region and the PPlus region is provided in the dielectric layer;

[0013] h) An ohmic contact metal layer (304) filling the source contact hole and a front electrode metal layer (305) covering it;

[0014] i) A back ohmic contact layer (401) and a back electrode metal layer (402) formed on the back of the substrate.

[0015] The present invention also discloses a design method for a power semiconductor device suitable for semiconductor materials, which is characterized in that: the above-mentioned composite cell power semiconductor device design method is adopted.

[0016] The present invention also discloses an electronic device, which is characterized in that: it includes a power semiconductor device with a narrow-wide composite cell size designed by the above method.

[0017] Beneficial effects

[0018] 1. There is no need to improve the process capabilities and processing accuracies of the chip manufacturing production line;

[0019] 2. The cell size of the device can be further reduced, the on-resistance can be decreased, and the product performance can be improved;

[0020] 3. The yield of single-wafer chips increases, and the production cost of a single chip decreases;

[0021] 4. No additional process is introduced, and the chip production and processing difficulty is reduced;

[0022] 5. The device reliability is not affected by the reduction of the cell size, and the product yield, consistency, and reliability are improved;

[0023] 6. The cell structure design scheme of the present invention can be applied to the cell structure design of various types of power devices such as diodes, MOS, and IGBT based on semiconductor materials such as silicon-based and silicon carbide-based, and has strong technical applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 is a layout of wide-size, narrow-size, and wide-narrow composite-size cell structures according to the present invention. Among them, (a) is the layout of wide-size cells; (b) is the layout of narrow-size cells; (c) is the layout of wide-narrow composite cells;

[0025] Figure 2 FIG. is a cross-sectional view of the device active region, gate control bus region, and terminal region. Among them, (a) is a cross-sectional view of the cell structure after cutting along the CL line of the wide-narrow composite cell shown in FIG. 1(c); (b) is a cross-sectional view of the gate control bus region and the terminal region structure;

[0026] Figure 3 FIG. is a process flow chart for manufacturing a device with a wide-narrow composite cell structure;

[0027] Figure 4 FIG. is the layout of the active region PWell and the process steps of PWell lithography and implantation. (a) is the layout of the wide-narrow composite cell PWell; (b) is the process steps of PWell lithography and implantation in the active region; (c) is the process steps of PWell lithography and implantation in the gate control bus region and the terminal region;

[0028] Figure 5 FIG. is the layout of NPlus and the process steps of self-aligned lithography. (a) is the layout of the wide-narrow composite cell NPlus; (b) is the process steps of self-aligned lithography of NPlus in the active region; (c) is the process steps of self-aligned lithography of NPlus in the gate control bus region and the terminal region;

[0029] Figure 6 FIG. is a comparison of the layout designs of wide-size, narrow-size, and wide-narrow composite-size cell PWell+NPlus. (a) is the superimposed layout of the wide-narrow composite cell PWell+NPlus, (b) is the superimposed layout of the wide-size cell PWell+NPlus, (c) is the superimposed layout of the narrow-size cell PWell+NPlus;

[0030] Figure 7 FIG. is the superimposed layout of NPlus self-alignment and the process steps of self-aligned implantation. (a) is the superimposed layout of the wide-narrow composite cell PWell+NPlus+self-aligned NPlus implantation region, (b) is the process steps of self-aligned etching and implantation of NPlus in the active region; (c) is the process steps of self-aligned etching and implantation of NPlus in the gate control bus region and the terminal region;

[0031] Figure 8For the PPlus layout and PPlus lithography and implantation process steps, (a) narrow-wide composite cell PPlus layout; (b) narrow-wide composite cell PWell + NPlus + self-aligned NPlus implant region + PPlus overlay layout; (c) active region PPlus lithography and implantation process steps; (d) gate control bus region and terminal region PPlus lithography and implantation process steps;

[0032] Figure 9 For the field oxide layer lithography and etching process steps;

[0033] Figure 10 For the Poly layout and Poly lithography process steps, (a) narrow-wide composite cell Poly layout, (b) narrow-wide composite cell PWell + NPlus + self-aligned NPlus implant region + PPlus + Poly overlay layout, (c) active region Poly lithography process steps; (d) gate control bus region and terminal region Poly lithography process steps;

[0034] Figure 11 For the SourceContact layout and SourceContact lithography and ohmic contact process steps, (a) narrow-wide composite cell SourceContact layout, (b) active region Source Contact lithography and ohmic contact process steps; (c) gate control bus region and terminal region Source Contact lithography and ohmic contact process steps;

[0035] Figure 12 For the GateContact lithography and etching process steps;

[0036] Figure 13 For the front-side metal and passivation process steps (a) active region front-side electrode metal and passivation lithography process steps; (b) gate control bus region and terminal region front-side electrode metal and passivation lithography process steps.

[0037] Taking an N-channel enhancement-mode SiC MOSFET device as an example for illustration, 101 is a SiCN-type heavily doped substrate wafer; 102 is an N-type lightly doped epitaxial layer epitaxially grown on the SiC substrate wafer; 201 is a PWell layout and the corresponding PWell implantation region; 2011 is a wide-size cell PWell layout and the corresponding PWell implantation region; 2012 is a narrow-size cell PWell layout and the corresponding PWell implantation region; 202 is a PPlus doped region in the active region; 2021 and 2022 are staggered PPlus doped regions; 202A is an NPlus layout and an NPlus implantation shielding region corresponding to the to-be-PPlus implanted region; 202A1 and 202A2 are NPlus implantation shielding region layouts arranged in a staggered manner; 202B is a PPlus layout and a PPlus implantation window region; 202B1 and 202B2 are PPlus implantation window layouts arranged in a staggered manner; 203 is a channel region; 2031 and 2032 are channels in the wide-narrow cell transition region and the straight cell region respectively (the channel lengths are the same); 203A and 203B are channels with and without PPlus doped regions respectively (using wide-narrow composite cells to ensure that the channel lengths at both places are the same); 204 is an NPlus self-aligned implantation region; 205 is a Poly layout and a Poly gate region; 2051 and 2052 are Poly layouts in the straight region and the wide-narrow cell transition region respectively (the Poly gate widths are the same); 206 is a JFET region; 207 is a source contact hole layout and a source ohmic contact window; 2071 and 2071 are source contact hole layouts in the wide-size and narrow-size cell regions; 208 is the step distance between the NPlus implantation shielding region and the PWell hard mask; 209 is a PPlus main junction doped region in the gate control bus and terminal region; 210 is a PPlus terminal ring doped region in the terminal region; 211 is a Poly bus in the gate control bus region; 212 is a gate contact hole; 213 is a source electrode metal in the active region; 214 is a gate electrode metal in the gate control bus region; 215 is a source electrode metal in the terminal region; 216 is a gate control bus and terminal region; 217 is a PPlus main junction implantation window; 218 is a PPlus terminal ring implantation window; 219 is an open passivation window; 300 is a field oxide layer; 301 is a gate oxide layer; 302 is a Poly polysilicon layer; 303 is an ILD dielectric layer; 304 is a source ohmic contact layer; 305 is a front electrode metal layer; 306 is a hard mask layer; 307 is a sidewall formed by self-aligned etching; 308 is a self-aligned hard mask layer; 309 is a photoresist; 310 is a passivation dielectric layer; 311 is a polyimide passivation layer; 401 is a back ohmic contact metal layer; 402 is a back drain electrode metal layer. Detailed implementation manners

[0038] When designing the layout of a silicon carbide MOSFET device, the cell size is a parameter that needs to be considered with emphasis. The size of the cell directly affects the utilization rate of the active region of the device. The smaller the cell size, the larger the number of cells distributed in the active region, the higher the current density of the device, and the smaller the specific conductance. Under the same current capacity, the device can be designed smaller, and more device chips can be produced from the same-sized wafers, reducing production costs. As shown in Figure 1(a), it is a layout design scheme of a common planar strip cell structure. Taking an N-channel field-effect transistor as an example, where 201 is the PWell implantation region, 202 is the PPlus implantation region, 203 is the channel region, 204 is the NPlus self-aligned implantation region, 205 is the Poly gate region, 206 is the JFET region, and 207 is the SourceContact region. According to the design requirements, the PPlus implantation regions 202 in different rows can be cross-staggered, as shown by the staggered PPlus doping regions 2021 and 2022, or aligned row by row. If you want to reduce the cell size, usually the widths of the PWell layout and the corresponding PWell implantation region 201, the NPlus self-aligned implantation region 204, the source contact hole layout, and the source ohmic contact window 207 can be reduced, as shown in Figure 1(b). Among them, adjusting the widths of the channel region 203, the Poly layout and the Poly gate region 205, and the JFET region 206 will have a significant impact on the device performance, and the adjustable space is limited. The 202 PPlus implantation region needs to be shielded by a hard mask layer during the NPlus implantation. The hard mask layer in this region is retained through the protection of photoresist during the hard mask layer etching. However, too small a size photoresist will fall off due to insufficient adhesion during development and cleaning, ultimately resulting in incomplete chip patterns and affecting the wafer yield. Therefore, the reduction of the width of the PPlus doping region 202 in the active region is limited by the process processing ability and the reduction space is limited. When reducing the width of the PWell layout and the corresponding PWell implantation region 201 while the width of the PPlus doping region 202 in the active region cannot be reduced synchronously, it will cause the distance between the boundary of the PWell implantation region 201 and the boundary of the PPlus doping region 202 to decrease, as shown by the comparison of 208 in Figure 6 (b) and (c). When the distance between the boundary of the PWell implantation region 201 and the boundary of the PPlus doping region 202 is too small, during the self-aligned etching process, due to the "proximity" effect, the etching rate in this region will decrease and the etching will be insufficient, resulting in Figure 7 (b) the channel lengths of the channel region 203A and the channel region 203B are inconsistent, ultimately affecting the consistency of the channel current density in different regions of the chip, resulting in device performance degradation and reduced reliability.

[0039] To avoid the problems of insufficient process processing capabilities and inconsistent channel length caused by the above-mentioned reduction in cell size, the present invention absorbs the advantages of a large process window for wide-sized cells and improved device performance for narrow-sized cells, and innovatively proposes a design scheme for a wide-narrow composite size cell structure. As shown in Fig. 1(c), that is, a wide-sized PWell region 2011 cell structure is adopted in the region where the PPlus doping region 202 structure is distributed in the active region, and a narrow-sized PWell region 2012 cell structure is adopted in the region where there is no PPlus doping region 202 structure in the active region. The wide and narrow size cell structures alternate and extend to finally cover the entire active region of the device. As Figure 6 shown, when the length of 1 unit of wide-sized cell is L1 and the length of 1 unit of narrow-sized cell is L2, the length L3 of 1 unit of wide-narrow composite size cell in the design scheme of this invention is L3=(L1 + L2) / 2. Compared with the wide-sized cell structure, the cell size is effectively reduced. Through the design scheme of the present invention, it can be ensured that in the region where the 202 structure is distributed, the boundary distance between the PWell injection region 201 and the PPlus doping region 202 in the active region does not decrease, ensuring the process processing window and the consistency of the channel length; in the region where there is no 202 structure distribution, a smaller cell size is adopted to improve the cell distribution density and the utilization rate of the active region, and the device performance is improved. The cell structure of the present invention ensures that the widths of the channel regions 203, Poly gate regions 205, and JFET regions 206 in each part are consistent, improving the reliability of the device; the 203 region, 205 region, and 206 region extend in a wavy shape, increasing the total width of the channel and the area of the JFET region, thereby increasing the current-carrying capacity of the device and further reducing the specific conductance. Through the design scheme of the present invention, without increasing the process processing difficulty of the chip, the cell size of the device is effectively reduced, the device performance is improved, the high reliability of the device is ensured, and the production cost is reduced.

[0040] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments. The embodiments are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, the components illustrated in the drawings are not necessarily drawn to scale. The present invention also omits the description of well-known components and processing techniques and processes to avoid unnecessarily limiting the present invention.

[0041] A design method for a composite cell power semiconductor device, characterized in that: wide-sized cells are adopted in the regions that need to be PPlus doped, and narrow-sized cells are adopted in the regions that do not need to be PPlus doped; the wide-sized and narrow-sized cells are arranged alternately and finally cover the active region of the device; the wide-sized cells are used to ensure the process window and the consistency of the channel length in the PPlus doping region, and the narrow-sized cells are used to improve the cell distribution density and the utilization rate of the active region. Example 1:

[0042] A SiCMOSFET device with a wide and narrow composite cell (taking a planar gate N-channel enhancement-mode silicon carbide vertical field-effect transistor as an example)

[0043] The layout design of the device cells in this embodiment is compared with the strip cell layout design of traditional planar SiCMOSFET devices as shown in Figures 1(a) and 1(c). The cross-section of the device cell area after cutting the device along the CL line in Figure 1(c) is as Figure 2 shown. The device in this embodiment includes an active region, a gate control bus region, and a terminal region. The gate control bus region and the terminal region are consistent with the design and process manufacturing methods of traditional SiCMOSFET devices. The active region of the device in this embodiment is composed of an extended distribution of a wide and narrow composite cell structure, specifically including an N-type heavily doped SiC substrate 101; an N-type lightly doped SiC epitaxial layer 102 grown on the substrate; a PWell region 201 formed by selective ion implantation; a channel region 203 formed inside the edge of the PWell region by a self-alignment process; an NPlus region 204 formed by self-alignment and selective ion implantation; a PPlus region 202 formed by selective ion implantation; a gate oxide layer 301 and a Poly gate 302 grown and lithographed above the JFET region 206; an ILD dielectric layer 303 deposited on the surface and a source ohmic contact opening 207 opened by lithography; an ohmic contact layer 304 formed by depositing an ohmic contact metal and alloying; a front electrode metal layer 305 deposited and lithographed; an ohmic contact layer 401 and a back electrode metal layer 402 formed by laser annealing the metal layer deposited on the back of the substrate 101. The following combines Figure 3 to specifically describe the process manufacturing method of the device in this embodiment. The steps are as follows:

[0044] In step 501, a SiC substrate wafer 101 with appropriate size, thickness, and resistivity is selected according to the product specifications, and a SiC epitaxial layer 102 with a certain thickness and doping concentration is epitaxially grown on the substrate wafer. The thickness and doping concentration of the epitaxial layer are directly related to the breakdown voltage and on-resistance of the device.

[0045] In step 502, a pattern that can provide alignment marks for subsequent lithography steps is formed on the wafer surface by lithography and etching a certain thickness of the SiC layer.

[0046] In step 503, a hard mask layer 306 is deposited on the surface of the SiC wafer epitaxial layer 102. The hard mask layer can be silicon dioxide, silicon nitride, polysilicon, or a combination thereof, etc. Through the process steps of lithography and etching the hard mask layer, wide and narrow PWell implantation regions 2011 and 2012 are formed on the wafer surface. After removing the photoresist, high-temperature ion implantation of B or Al is performed to form a PWell doping region 201 in the N-type lightly doped epitaxial layer 102, as Figure 4 shown.

[0047] In step 504, a hard mask layer 308 with a certain thickness is continuously deposited on the wafer surface after the foregoing steps according to the channel length design requirements. The photoresist 309 in the 202A region is retained by NPlus lithography and development, as Figure 5 shown. After etching the hard mask layer 308 with a self-aligned process to the thickness, sidewalls 307 will be formed on both sides of the step of the hard mask layer 306, and the hard mask layer 308 under the photoresist 309 is retained, as Figure 7 shown. Because a narrow-wide composite size cell is adopted, the distance between the edge of the photoresist 309 from the PWell region 201 and the distance 208 of the step of the hard mask layer 306 are not reduced. When etching the hard mask layer 308, it can be ensured that the etching rates of the hard mask layers in the PWell injection regions 2011 and 2012 are basically the same, and the channel lengths of 203A and 203B can be kept the same.

[0048] In step 505, after removing the photoresist 309 on the wafer surface, N or P is implanted at a high temperature. Under the shielding of the hard mask layer 306 and the self-aligned hard mask layer 308, the NPlus doping region 204 is selectively implanted in the PWell region 201. The channel region 203 is formed in the PWell region masked by the sidewalls 307.

[0049] In step 506, after removing all the hard mask layers on the wafer surface, the hard mask layer 306 is redeposited and PPlus lithography and etching are performed to form the PPlus region injection window 202B. After removing the photoresist, B or Al is implanted at a high temperature, and the PPlus doping region 202 is selectively implanted in the 201 region, as Figure 8 shown.

[0050] In step 507, the 506 process steps are repeated to define the JFET injection window. After removing the photoresist, N or P is implanted at room temperature or high temperature to adjust the doping concentration of the JFET region 206, and then all the hard mask layers on the wafer surface are removed.

[0051] In step 508, a carbon film is deposited on the wafer surface and the doped impurities in each injection region are activated at a high temperature, and then the carbon film on the wafer surface is removed.

[0052] In step 509, the wafer is subjected to a high-temperature oxidation treatment to oxidize and consume the surface SiC layer with certain damage on the wafer surface, and the sacrificial oxide layer is removed by an etching process to expose the SiC surface layer with fewer defects.

[0053] In step 510, a field oxide layer is deposited on the above-mentioned wafer surface, and the field oxide layer is selectively removed through photolithography and etching process steps to form the active region.

[0054] In step 511, a gate oxide layer 301 with a certain thickness is grown by thermal oxidation on the surface of the above-mentioned wafer active region, and a heavily doped polysilicon layer 302 with a certain thickness is deposited. The polysilicon and the gate oxide layer are lithographically etched to form a polysilicon gate 205, as Figure 10 shown.

[0055] In step 512, an ILD dielectric layer 303 is deposited on the surface of the above-mentioned wafer, generally USG + BPSG. Source contact holes 207 are formed through lithography and etching processes. After removing the photoresist, a layer of ohmic contact metal (generally a Ni metal layer) is deposited and rapid thermal annealing is performed. The ohmic contact metal reacts with SiC in the region of the source contact holes 207 to form an ohmic contact layer 304, and the unreacted ohmic metal in other regions can be removed through an etching process, as Figure 11 shown.

[0056] In step 513, the gate contact holes are opened in the gate control bus region by continuing the ILD lithography and etching processes, and then the photoresist is removed.

[0057] In step 514, a front electrode metal composite layer 305 (generally Ti / TiN / Al) is deposited on the wafer surface. Gate and source metal electrodes are formed through lithography and etching of the metal layer process, and then the photoresist is removed, as Figure 13 shown.

[0058] In step 515, a PA passivation dielectric layer (generally SiO2 / SiN) is deposited on the wafer surface. The electrode lead-out region is opened through lithography and etching of the passivation layer process, and then the photoresist is removed.

[0059] In step 516, a PI passivation layer is coated on the surface of the above-mentioned wafer. The PAD electrode contact region is opened through lithography, and then a curing process is performed.

[0060] In step 517, the back surface of the above-mentioned wafer is thinned to reduce the device on-resistance.

[0061] In step 518, an ohmic contact metal layer 401 (generally a Ni metal layer) is deposited on the back surface of the above-mentioned wafer. After laser annealing, a back drain electrode metal composite layer 402 (generally Ti / Ni / Ag) is deposited to form a drain electrode, as Figure 2 shown. Finally, the wafer is inspected in step 519.

[0062] Example 2

[0063] A power semiconductor device with a wide and narrow composite cell size, designed by the above method, includes an active region, a gate-controlled bus region, and a terminal region, and is characterized in that: the active region is composed of alternately arranged wide-size cells (2011) and narrow-size cells (2012), where the wide-size cells contain PPlus doping regions (202), and the narrow-size cells do not contain PPlus doping regions;

[0064] The power semiconductor device is a SiCMOS device, and the device includes, from bottom to top:

[0065] a) An N-type heavily doped SiC substrate (101);

[0066] b) An N-type lightly doped SiC epitaxial layer (102) epitaxially grown on the substrate;

[0067] c) Alternately arranged wide-size PWell regions (2011) and narrow-size PWell regions (2012) formed in the epitaxial layer, where a PPlus implantation region (202) is provided in the wide-size PWell region; d) A channel region (203) formed by a self-alignment process at the edge of the PWell region, and the channel region maintains the same channel length in the wide and narrow cell transition region (203A) and the straight region (203B); e) An NPlus source region (204) and a JFET region (206) formed outside the channel region; f) A gate oxide layer (301) covering the JFET region and a polysilicon gate (302) located thereon; g) An ILD dielectric layer (303) covering the polysilicon gate, and source contact holes (207) penetrating through to the NPlus source region and the PPlus region are provided in the dielectric layer;

[0068] h) An ohmic contact metal layer (304) filling the source contact holes and a front electrode metal layer (305) covering it;

[0069] i) A back ohmic contact layer (401) and a back electrode metal layer (402) formed on the back of the substrate.

[0070] The present invention changes the design idea of the traditional single cell size. By alternately combining wide and narrow cell sizes, that is, using a wide-size cell structure in areas where the P+ region structure and processing accuracy are difficult to guarantee, and using a narrow-size cell structure in areas without a P+ region structure and with guaranteed processing accuracy. Through this design scheme, problems such as uneven etching and inconsistent channel length caused by insufficient process processing capabilities can be avoided. Without the need to improve the process capabilities and processing accuracy of the chip manufacturing production line, the reduction of the device cell size can be achieved, the product performance can be improved, and the production cost can be reduced.

[0071] The basic principles, main features and advantages of the present invention have been shown and described above. Those skilled in the art should understand that the present invention is not limited by the above embodiments, and what is described in the above embodiments and the specification is only the principle of the present invention. Without departing from the spirit and scope of the present invention, various changes and improvements will occur to the present invention, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. A composite cell power semiconductor device design method, characterized in that: Wide-sized cells are used in areas where PPlus doping is required, and narrow-sized cells are used in areas where PPlus doping is not required; Wide-sized and narrow-sized cells are arranged alternately, and eventually cover the active area of ​​the device; the wide-sized cells are used to ensure the consistency of the process window and channel length of the PPlus doping area, and the narrow-sized cells are used to improve the cell distribution density and the utilization rate of the active area.

2. The method for designing a power semiconductor device layout with wide and narrow composite cell sizes according to claim 1, characterized in that: The following steps are involved: Step 501: Select a substrate wafer and epitaxially grow an epitaxial layer; Step 502: forming alignment marks by photolithography and etching; Step 503: depositing a hard mask layer, forming a PWell injection window and performing ion implantation; Step 504: depositing a hard mask layer, performing NPlus lithography and self-aligned etching; Step 505: performing NPlus ion implantation to form a channel region; Step 506: performing PPlus photolithography and ion implantation; Step 507: define a JFET injection window and perform ion implantation; Step 508: depositing a carbon film and activating doping impurities; Step 509: performing high temperature oxidation treatment; Step 510: depositing a field oxide layer and forming an active region; Step 511: growing a gate oxide layer and depositing a polysilicon layer to form a polysilicon gate; Step 512: depositing an ILD dielectric layer, forming a source contact hole and performing ohmic contact processing; Step 513: opening a gate contact hole; Step 514: depositing a front electrode metal layer and forming an electrode; Step 515: depositing a passivation dielectric layer and opening an electrode lead-out region; Step 516: Apply a PI passivation layer and cure; Step 517: Thinning the back side of the wafer; Step 518: depositing a back ohmic contact metal layer and forming a drain electrode; Step 519: Perform film output inspection.

3. The composite cell power semiconductor device design method according to claim 1, characterized in that: The PPlus-doped areas are arranged in a staggered pattern.

4. The composite cell power semiconductor device design method according to claim 1, characterized in that: The channel region extends in a wave shape, with a uniform channel length and increasing width.

5. The composite cell power semiconductor device design method according to claim 1, characterized in that: The average value of the wide cell length L1 and the narrow cell length L2 is L3 = (L1+L2) / 2.

6. The composite cell power semiconductor device design method according to claim 1, characterized in that: The design method is applicable to strip, rectangular, hexagonal cell structures and planar or grooved cells.

7. The composite cell power semiconductor device design method according to claim 1, characterized in that: The design method is applicable to the cellular structure design of power devices such as diodes, MOS, IGBT, etc. made of semiconductor materials such as silicon-based and silicon carbide-based.

8. A power semiconductor device with wide and narrow composite cell size, designed by the method of claim 1, comprising an active area, a gate control bus area, and a terminal area, characterized in that: The active area is composed of wide-sized cells (2011) and narrow-sized cells (2012) arranged alternately, wherein the wide-sized cells contain PPlus-doped regions (202) and the narrow-sized cells do not contain PPlus-doped regions; The power semiconductor device is a SiC MOS device, which includes from bottom to top: a) N-type heavily doped SiC substrate (101); b) an N-type lightly doped SiC epitaxial layer (102) epitaxially grown on the substrate; c) alternately arranged wide PWell regions (2011) and narrow PWell regions (2012) formed in the epitaxial layer, wherein a PPlus injection region (202) is provided in the wide PWell region; d) a channel region (203) formed at the edge of the PWel l region by a self-alignment process, wherein the channel region maintains the same channel length in the wide-narrow cell transition region (203A) and the straight region (203B); e) an NPlus source region (204) and a JFET region (206) formed outside the channel region; f) a gate oxide layer (301) covering the JFET region and a polysilicon gate (302) located thereon; g) an ILD dielectric layer (303) covering the polysilicon gate, wherein the dielectric layer is provided with a source contact hole (207) penetrating to the NPlus source region and the PPlus region; h) an ohmic contact metal layer (304) filling the source contact hole and a front electrode metal layer (305) covering the ohmic contact metal layer; i) A back ohmic contact layer (401) and a back electrode metal layer (402) are formed on the back side of the substrate.

9. A method for designing power semiconductor devices using semiconductor materials, characterized in that: A composite cellular power semiconductor device design method according to any one of claims 1 to 6 is adopted.

10. An electronic device, characterized in that: The electronic device comprises a power semiconductor device with a wide and narrow composite cell size designed by the method described in claim 1.

Images