Power semiconductor device

Abstract

The present invention relates to a power semiconductor device, and more particularly, to a power semiconductor device in which a current path is formed between a P-TOP region and a field oxide film by separating the P-TOP region formed in a resistor unit and the field oxide film on the upper side thereof from each other, thus, a decrease in the overall amount of current due to an increase in the length of the current movement path is prevented in advance.

Description

Technical Field

[0001] The present invention relates to a power semiconductor device, and more particularly, to a power semiconductor device that forms a current path between a P-TOP region formed in a resistance unit and a field oxide film on an upper side thereof by separating the P-TOP region from the field oxide film, thereby preventing a decrease in the overall current amount due to an increase in the length of a current movement path in advance. Background Art

[0002] Generally, a power semiconductor device may include a high-voltage part and a low-voltage part, and a bootstrap circuit may be used to ensure stable operation of the high-voltage part. The bootstrap circuit as described above may include: a capacitor that supplies power by being connected to the high-voltage part. The bootstrap circuit may include: a diode that charges the capacitor by connecting the capacitor to a driving voltage during a period when the low-voltage part outputs a low voltage, and prevents the driving power source from being electrically connected to the high-voltage part during a period when the high-voltage part outputs a high voltage.

[0003] However, when a high voltage is directly applied to the diode, the diode may be damaged. Therefore, a separate transistor for preventing the high voltage from being applied to the diode may be provided between the high-voltage part and the diode. As described above, when a separate transistor is used, the size of the power semiconductor device may increase, and during a period of charging the capacitor, the electron movement distance may also increase due to the separate transistor, thereby possibly causing a decrease in the current flowing to the capacitor.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Korean Patent Publication No. 10-2012-0052478, "Bootstrap Circuit" Summary of the Invention

[0007] Technical Problem

[0008] The present invention aims to solve the problems existing in the prior art as described above.

[0009] An object of the present invention is to provide a power semiconductor device that can reduce its overall size without using a separate transistor for preventing a high voltage from being applied from a high-voltage unit to a switching unit.

[0010] In addition, an object of the present invention is to provide a power semiconductor device that can prevent a reduction in the overall current amount due to an increase in the forward current movement path in advance by separating a P-TOP region formed in a resistance unit from a field oxide film on its upper side.

[0011] Solution

[0012] To achieve the above object, the present invention can be implemented by an embodiment configured as described below.

[0013] In an embodiment of the present invention, a power semiconductor device according to the present invention is characterized by including: a high-voltage unit that outputs a high voltage; a low-voltage unit that outputs a low voltage; a capacitor electrically connected to the high-voltage unit and providing power to the high-voltage unit during the output of the high voltage; a switch unit electrically connected to the high-voltage unit and the capacitor, connecting the capacitor to a driving power source for charging the capacitor during the output of the low voltage, and preventing the high-voltage unit and the driving power source from being electrically connected to each other during the output of the high voltage; and a resistance unit electrically connected between the switch unit and the high-voltage unit, reducing the high voltage to a voltage lower than the breakdown voltage of the switch unit during the output of the high voltage; and the resistance unit includes: a second-conductive-type deep well region located in a substrate; a field oxide film located on the surface of the substrate accordingly; and a P-TOP region separated from the field oxide film within the deep well region.

[0014] In another embodiment of the present invention, a power semiconductor device according to the present invention is characterized in that the P-TOP region is separated from the bottom surface of the field oxide film on the lower side of the field oxide film.

[0015] In still another embodiment of the present invention, a power semiconductor device according to the present invention is characterized in that the P-TOP region is separated from the bottom surface of the deep well region.

[0016] In still another embodiment of the present invention, a power semiconductor device according to the present invention is characterized in that the switch unit includes a bipolar junction transistor.

[0017] In still another embodiment of the present invention, a power semiconductor device according to the present invention is characterized in that the resistance unit further includes: a first electrode layer electrically connected to a ground terminal on a side field oxide film adjacent to the switch unit; and a second electrode layer electrically connected to a high-voltage unit on a side field oxide film adjacent to the high-voltage unit.

[0018] In yet another embodiment of the present invention, the power semiconductor device according to the present invention is characterized in that the resistor unit further includes: a first contact region formed in the deep well region and electrically connected to the switching unit; and a second contact region separated from the first contact region in the deep well region and electrically connected to the high-voltage unit.

[0019] In yet another embodiment of the present invention, the power semiconductor device according to the present invention is characterized in that the resistor unit further includes: a second-conductivity-type buried layer located below the second contact region.

[0020] In yet another embodiment of the present invention, the power semiconductor device according to the present invention is characterized in that the resistor unit further includes: a single electrode layer located on the field oxide film.

[0021] In yet another embodiment of the present invention, the power semiconductor device according to the present invention is characterized in that the electrode layer is a polysilicon film doped with second-conductivity-type impurities.

[0022] In yet another embodiment of the present invention, the power semiconductor device according to the present invention is characterized in that the switching unit includes: a diode located on the substrate.

[0023] In yet another embodiment of the present invention, the power semiconductor device according to the present invention includes: a field oxide film located on one surface side of the substrate; and an anode layer and a cathode layer located on the field oxide film on one surface side of the substrate.

[0024] In yet another embodiment of the present invention, the power semiconductor device according to the present invention is characterized in that the anode layer is a polysilicon film doped with first-conductivity-type impurities.

[0025] In yet another embodiment of the present invention, the power semiconductor device according to the present invention is characterized in that the bipolar junction transistor includes: a second-conductivity-type emitter region located on one surface side of the substrate; a first-conductivity-type base region separated from the emitter region on one surface side of the substrate; and a collector region separated from the emitter region and the base region on one surface side of the substrate.

[0026] In yet another embodiment of the present invention, the power semiconductor device according to the present invention is characterized in that the base region and the collector region are electrically connected to a driving power source.

[0027] In yet another embodiment of the present invention, the power semiconductor device according to the present invention is characterized in that: the emitter region is electrically connected to the resistor unit.

[0028] In yet another embodiment of the present invention, a power semiconductor device according to the present invention may include: a high-voltage unit that outputs a high voltage; a low-voltage unit that outputs a low voltage; a capacitor electrically connected to the high-voltage unit that supplies power to the high-voltage unit during the output of the high voltage; a switching unit electrically connected to the high-voltage unit and the capacitor that connects the capacitor to a driving power source to charge the capacitor during the output of the low voltage; and a resistance unit electrically connected between the switching unit and the high-voltage unit that reduces the high voltage to a voltage lower than the breakdown voltage of the switching unit during the output of the high voltage. The resistance unit includes: a second-conductivity-type deep well region located within a substrate; a field oxide film located on the surface of the substrate; and a P-TOP region whose upper side is separated from the field oxide film within the deep well region.

[0029] Advantages of the Invention

[0030] The present invention can achieve the following effects through the configuration described above.

[0031] The present invention can reduce its overall size without using a separate transistor for preventing a high voltage from being applied from the high-voltage unit to the switching unit.

[0032] Furthermore, the present invention can prevent a reduction in the overall current amount due to an increase in the forward current movement path in advance by separating the P-TOP region formed in the resistance unit from the field oxide film on its upper side.

[0033] Furthermore, even effects not explicitly mentioned herein, the effects and potential effects described in the following specification that can be achieved through the technical features of the present invention will be regarded as being described in the specification of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is an equivalent circuit diagram for explaining a power semiconductor device according to an embodiment of the present invention.

[0035] Figure 2 is for Figure 1 a power semiconductor device for explanation.

[0036] Figure 3 is a cross-sectional view taken along line AA' of a power semiconductor device according to a first embodiment of the present invention.

[0037] Figure 4 is a cross-sectional view taken along line AA' of a power semiconductor device according to a second embodiment of the present invention.

[0038] Figure 5AA' cross-sectional view of a power semiconductor device according to a third embodiment of the present invention.

[0039] Symbol Explanation

[0040] 10: Power semiconductor device, 20: Level shift region, 30: High voltage unit, 40: Low voltage unit, 50: First device isolation region, 60: Second device isolation region, 70: Third device isolation region, 100: Switching unit, 200: Resistance unit, C: Capacitor. Detailed Description of the Embodiment

[0041] Next, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The embodiments of the present invention can be deformed into various forms, and the scope of the present invention should not be construed as being limited to the following embodiments, but should be interpreted based on the matters described in the claims. In addition, the present embodiment is only used to more completely introduce the present invention to those with average knowledge in the industry.

[0042] Unless otherwise clearly stated in the context, the singular forms used in this specification may also include plural forms. In addition, the terms "comprise" and / or "comprising" used in this specification are only used to indicate the existence of the mentioned shapes, numbers, steps, actions, components, elements, and / or combinations thereof, and do not exclude the possibility of the existence or addition of one or more other shapes, numbers, actions, components, elements, and / or combinations thereof.

[0043] It should be noted that in the following content, when it is described that a certain component (or layer) is disposed on another component (or layer), a certain component may be directly disposed on another component, or there may be other components or layers between the corresponding components. In addition, when it is described that a certain component is directly disposed on or above another component, there will be no other components between the corresponding components. In addition, "above", "upper part", "lower part", "upper side", "lower side", "one side" or "side surface" of a certain component refers to the relative positional relationship.

[0044] In addition, the conductivity or doping region of a component can be defined as "P-type" or "N-type" according to the main carrier characteristics, but this is only for the convenience of explanation, and the technical idea of the present invention is not limited by the exemplified content. For example, the "P-type" or "N-type" in the following content can be replaced with more general terms, namely "first conductivity type" or "second conductivity type", where the first conductivity type refers to P-type and the second conductivity type refers to N-type. However, in some cases, the first conductivity type may refer to N-type and the second conductivity type may refer to P-type.

[0045] In addition, the "high concentration" and "low concentration" representing the doping concentration of the impurity region should be understood as the relative doping concentration of one constituent element to another.

[0046] Next, the power semiconductor device 10 according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0047] The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device that forms a current path between a P-TOP region formed in a resistance unit and a field oxide film on its upper side by separating the P-TOP region from the field oxide film, thereby preventing in advance a reduction in the overall current amount due to an increase in the current movement path length.

[0048] Figure 1 is an equivalent circuit diagram for explaining a power semiconductor device according to an embodiment of the present invention, Figure 2 is for according to Figure 1 The plan view of the power semiconductor device is described.

[0049] Refer to Figure 1 and Figure 2 According to an embodiment of the present invention, the power semiconductor device 10 may include a high-voltage unit 30, a low-voltage unit 40, a capacitor C, a switch unit 100, and a resistance unit 200. The high-voltage unit 30 may include a high-voltage drive circuit 32 and a first power transistor T1, and the low-voltage unit 40 may include a low-voltage drive circuit 42 and a second power transistor T2.

[0050] In addition, the capacitor C may be connected in parallel to a power line connected to power supply terminals V B , V S Connected. The output terminal H O of the high-voltage drive circuit 32 may be connected to the gate of the first power transistor T1, and the first power transistor T1 may be connected in parallel with the first diode D1. The output terminal L O of the low-voltage drive circuit 42 may be connected to the gate of the second power transistor T2, and the second power transistor T2 may be connected in parallel with the second diode D2. The source of the first power transistor T1 may be connected to the high voltage HV, the first power transistor T1 and the second power transistor T2 may be connected in series, and the drain of the second power transistor T2 may be linked to the ground terminal GND.

[0051] The low-voltage drive circuit 42 may output a signal to the low-voltage output terminal L in input according to a signal input through the low-voltage input terminal L OOutput a low-voltage control signal to control the second power transistor T2. The low-voltage drive circuit 42 can receive power and operate through a common terminal COM, for example, the potential difference between the low voltage and the drive power supply V CC Receive power and operate based on the potential difference between the drive voltages.

[0052] The high-voltage drive circuit 32 can output a high-voltage control signal to control the first power transistor T1 in response to a signal provided from the level-shifting circuit 22 to the high-voltage output terminal H O Output a high-voltage control signal to control the first power transistor T1. The high-voltage drive circuit 32 can receive power and operate through a capacitor C connected between a terminal V having the same potential as the output terminal OUT and the terminal V S And the terminal V B The level-shifting circuit 22 can provide a signal input from the high-voltage input terminal H in To the high-voltage drive circuit 32. According to the state of the pulse-width modulation (PWM) signal output from the output terminal OUT, the reference voltage of the high-voltage drive circuit 32 can be a high voltage HV or a low voltage, such as the ground voltage.

[0053] The power semiconductor device 10 can output a high voltage HV or a low voltage, such as the ground voltage, to the output terminal OUT in response to signals input from the high-voltage input terminal H in And the low-voltage input terminal L in Specifically, when the low-voltage drive circuit 42 turns on the second power transistor T2 through the low-voltage output terminal L O The output terminal OUT can output a low voltage, such as the ground voltage. At this time, the second diode D2 can prevent reverse voltage. In addition, to prevent high voltage and low voltage from being simultaneously applied to the output terminal OUT, the high-voltage drive circuit 32 can turn off the first power transistor T1. That is, the ground voltage applied to the output terminal OUT and the drive voltage from the drive power supply V CC Can be applied to the high-voltage drive circuit 32.

[0054] In addition, the drive power supply V CC Can supply current to the capacitor C through the switch unit 100 and the resistor unit 200 to charge the capacitor C with approximately the drive voltage.

[0055] When the low-voltage drive circuit 42 outputs a turn-off signal and the high-voltage drive circuit 32 passes through the high-voltage output terminal H OWhen a turn-on signal is provided to the first power transistor T1 to turn on the first power transistor T1, the output terminal OUT can output a high voltage HV. At this time, the first diode D1 can prevent a reverse voltage. At the same time, the high voltage HV can be applied to the terminal V S and the high voltage HV and the charging voltage of the capacitor C can be applied to the terminal V B .

[0056] According to an embodiment of the present invention, the switching unit 100 may include a bipolar junction transistor or a diode. In particular, when the high voltage unit 30 outputs a high voltage, a driving voltage can be applied to the node a, and the high voltage HV and the charging voltage of the capacitor C can be applied to the node b. As a result, a reverse voltage will be applied to the switching unit 100, whereby the switching unit 100 can prevent the high voltage unit 30 from being electrically connected to the driving power supply V CC to each other.

[0057] However, since the potential difference between the node a and the node b is as high as the high voltage HV, it may cause the switching unit 100 to be broken down. In order to prevent the above phenomenon, a resistor unit 200 can be disposed between the switching unit 100 and the high voltage unit 30. The resistor unit 200 can reduce the high voltage HV to a voltage lower than the breakdown voltage of the switching unit 100 during the output of the high voltage HV, thereby preventing the switching unit 100 from being damaged due to the reverse voltage.

[0058] Referring to Figure 2 , the power semiconductor device 10 can be formed on a substrate, such as a semiconductor wafer. Specifically, the low voltage unit 40 can be formed to surround the high voltage unit 30, and a first device isolation region 50 and a second device isolation region 60 can be formed between the high voltage unit 30 and the low voltage unit 40. In addition, a level shift region 20 equipped with a level shift circuit 22 can be formed between the high voltage unit 30 and the low voltage unit 40. In addition, a switching unit 100 and a resistor unit 200 can be formed between the high voltage unit 30 and the low voltage unit 40. At this time, the resistor unit 200 can be formed between the switching unit 100 and the high voltage unit 30.

[0059] Figure 3 is a cross-sectional view taken along the line AA' of the power semiconductor device according to the first embodiment of the present invention.

[0060] Referring to Figure 3, the switching unit 100 according to an embodiment of the present invention may include an NPN bipolar junction transistor 110. The NPN bipolar junction transistor 110 as described above may include, for example, an emitter region, a base region 113, and a collector region 115 located on the substrate 101 or on one surface side of the substrate 101. At this time, the substrate 101 may include a silicon substrate 103 of a first conductivity type and an epitaxial layer 105 of a second conductivity type grown on the silicon substrate 103. In addition, the emitter region 111 is a region highly doped with impurities of the second conductivity type, the base region 113 is a region highly doped with impurities of the first conductivity type, and the collector region 115 is a region highly doped with impurities of the second conductivity type.

[0061] In addition, for example, the base region 113 may be in a ring shape and formed to surround the emitter region 111, and the collector region 115 may also be in a ring shape and formed to surround the base region 113. A field oxide film 120 may be formed between the emitter region 111, the base region 113, and the collector region 115. The emitter region 111, the base region 113, and the collector region 115 may be separated from each other by means of the field oxide film 120. As an example, the field oxide film 120 may be a shallow trench isolation (STI) region, but is not limited thereto.

[0062] The base region 113 and the collector region 115 as described above may be electrically connected to the driving power supply V CC through metal wiring and contact plugs, and the emitter region 111 may be electrically connected to the resistance unit 200 through metal wiring and contact plugs. With the above-described structure, when a low voltage is output from the low voltage unit 40, current may flow from the base region 113 and the collector region 115 to the emitter region 111, and the current may charge the capacitor C through the resistance unit 200.

[0063] In addition, a deep well region 130 of the first conductivity type formed at a specific depth within the substrate 101 may be formed in the switching unit 100. The deep well region 130 of the first conductivity type is preferably a region doped with impurities at a lower concentration than the base region 113. The deep well region 130 as described above may be formed to surround the emitter region 111 and the base region 113.

[0064] In addition, a well region 140 of the second conductivity type formed at a specific depth within the substrate 101 may be formed in the switching unit 100. The well region 140 of the second conductivity type is configured to surround the collector region 115, and by means of the well region 140 of the second conductivity type, the internal resistance of the bipolar junction transistor 110 may be reduced.

[0065] In addition, a buried layer 150 of a second conductivity type may be formed below the deep well region 130 in the substrate 101. The buried layer 150 of the second conductivity type as described above is a structure for reducing the leakage current of the bipolar junction transistor 110.

[0066] In addition, a first device isolation region 50 may be formed between the low-voltage unit 40 and the switching unit 100. The first device isolation region 50 as described above may include: a first buried layer 510 located in the substrate 101; a first contact region 530 located on one surface side of the substrate 101; and a first impurity diffusion region 550 located between the first buried layer 510 and the first contact region 530. At this time, the first contact region 530 may be a first conductivity type doping region as a high-concentration impurity doping region compared with the first buried layer 510 and the first impurity diffusion region 550, but is not limited thereto.

[0067] In addition, the second device isolation region 60 may include: a second buried layer 610 located in the substrate 101; a second contact region 630 located on one surface side of the substrate 101; and a second impurity diffusion region 650 located between the second buried layer 610 and the second contact region 630. At this time, the second contact region 630 may be a first conductivity type doping region as a high-concentration impurity doping region compared with the second buried layer 610 and the second impurity diffusion region 650, but is not limited thereto. At this time, the second device isolation region 60 may be formed between the high-voltage unit 30 and the resistor unit 200.

[0068] Next, although not shown in Figure 2 a third device isolation region 70 may be formed between the switching unit 100 and the resistor unit 200. The third device isolation region 70 may include: a third buried layer 710 located in the substrate 101; a third contact region 730 located on one surface side of the substrate 101; and a third impurity diffusion region 750 located between the third buried layer 710 and the third contact region 730. The third contact region 730 may be a first conductivity type doping region as a high-concentration impurity doping region compared with the third buried layer 710 and the third impurity diffusion region 750, but is not limited thereto.

[0069] The resistance unit 200 may be formed between the second device isolation region 60 and the third device isolation region 70. The resistance unit 200 as described above may include: a deep well region 210 of a second conductivity type, formed within the substrate 101. The deep well region 210 of the second conductivity type may be formed, for example, on the epitaxial layer 105. When the low-voltage unit 40 outputs a low voltage, since a forward voltage is applied to the bipolar junction transistor 110 and the resistance unit 200, the resistance of the deep well region 210 of the second conductivity type can be reduced. When the high-voltage unit 30 outputs a high voltage, since a reverse voltage is applied to the bipolar junction transistor 110 and the resistance unit 200, the resistance of the deep well region 210 can be increased.

[0070] In addition, the resistance unit 200 may include: a field oxide film 220, formed on one side of the surface (or upper side) of the substrate 101. The field oxide film 220 may be, for example, a local oxidation of silicon (LOCOS) or a shallow trench isolation (STI) region, and may be formed on the deep well region 210 of the second conductivity type.

[0071] In addition, the resistance unit 200 may include: a fourth contact region 211 and a fifth contact region 213, formed on one side of the surface of the substrate 101. The fourth contact region 211 and the fifth contact region 213 are separated from each other and may be formed in a manner surrounded by the deep well region 210 of the second conductivity type. The fourth contact region 211 and the fifth contact region 213 are regions highly doped with impurities of the second conductivity type. The fourth contact region 211 may be formed on the side adjacent to the switching unit 100, while the fifth contact region 213 may be formed on the side adjacent to the high-voltage unit 30.

[0072] In addition, within the deep well region 210, a first well region 215 may be formed in a manner surrounding the fourth contact region 211, and a second well region 217 may be formed in a manner surrounding the fifth contact region 213. Both the first well region 215 and the second well region 217 are regions doped with impurities of the second conductivity type, and may be regions doped with a lower concentration of impurities compared to the fourth contact region 211 and the fifth contact region 213. In addition, the deep well region 210 is a region doped with a lower concentration of impurities compared to the first well region 215 and the second well region 217, and may be formed in a manner surrounding the first well region 215 and the second well region 217.

[0073] In addition, the fourth contact region 211 may be electrically connected to the switching unit 100 through metal wiring and contact plugs, while the fifth contact region 213 may be electrically connected to the high-voltage unit 30 and the capacitor C through metal wiring and contact plugs.

[0074] In addition, the impurity concentration of the deep well region 210 can be appropriately adjusted so as to reduce the high voltage to a voltage lower than the breakdown voltage of the switching unit 100 during the period of outputting the high voltage. Specifically, the deep well region 210 can reduce the high voltage to a voltage lower than the breakdown voltage of the switching unit 100 but higher than the driving voltage. As a result, even when a reverse voltage is applied to the switching unit 100 during the period of applying the high voltage, since the reverse voltage is lower than the breakdown voltage of the switching unit 100, the switching unit 100 can be prevented from being damaged.

[0075] In addition, in the substrate 101, a second conductivity type buried layer 230 can be formed for dispersing the electric field formed by the high voltage when the high voltage is applied from the high voltage unit 30 to the fifth contact region 213. As an example, the second conductivity type buried layer 230 can be formed on the lower side of the second well region 217.

[0076] In addition, on the field oxide film 220 formed in the resistance unit 200, a first electrode layer 241 can be formed adjacent to the switching unit 100, and a second electrode layer 243 can be formed adjacent to the high voltage unit 30. The first electrode layer 241 as described above can be electrically connected to the ground terminal GND, and the second electrode layer 243 can be electrically connected to the high voltage unit 30. The first electrode layer 241 and the second electrode layer 243 can include, for example, polysilicon doped with second conductivity type impurities.

[0077] In addition, the resistance unit 200 can include a P-TOP region 250 in the deep well region 210 of the second conductivity type. The P-TOP region 250 is a first conductivity type impurity doped region and can be formed separated from the field oxide film 220. That is, the P-TOP region 250 can be formed on the lower side of the field oxide film 220 in a manner separated from the bottom surface of the field oxide film 220. With the above-described structure, depletion layers can be formed between the upper side surface of the P-TOP region 250 and the deep well region 210 and between the bottom surface of the P-TOP region 250 and the deep well region 210. Specifically, during the period when the high voltage unit 30 outputs a high voltage, the depletion layer can expand by means of the high voltage applied to the fifth contact region 213, and thereby the resistance of the resistance unit 200 can be increased. In addition, the depletion layer can be formed more uniformly by means of the first electrode layer 241 and the second electrode layer 243. By forming the P-TOP region 250 in the above-described manner, a triple RESURF (Reduced SURface Field) structure composed of the upper side surface and one side of the lower side surface of the P-TOP region 250 and the interface between the silicon substrate 103 and the epitaxial layer 105 can be formed.

[0078] As described above, the P-TOP region 250 may be formed on the lower side of the field oxide film 220 in a manner separated from the bottom surface of the field oxide film 220. In contrast, when the P-TOP region 250 is formed in contact with the bottom surface of the field oxide film 220, the current flowing from the fifth contact region 213 to the fourth contact region 211 will flow circuitously along the lower side of the P-TOP region 250, and the length of the current path will also become longer, which may cause a problem of a decrease in the total current amount.

[0079] To solve the above-described problem, by separating the P-TOP region 250 according to an embodiment of the present invention from the bottom surface of the field oxide film 220, it is possible to prevent the forward current from circuitously flowing through the P-TOP region 250, thereby relatively shortening the current path. Thereby, the problem of a decrease in the total current amount can be solved.

[0080] Figure 4 It is a cross-sectional view taken along line AA' of a power semiconductor device according to a second embodiment of the present invention.

[0081] Refer to Figure 4 , in the present embodiment, the resistor unit 200' may include a single electrode layer 260' on the field oxide film 220' to replace the first electrode layer 241 and the second electrode layer 243 as described above. The electrode layer 260' as described above extends relatively long on the field oxide film 220', and may be electrically connected to the switching unit 100' on the side adjacent to the switching unit 100', and is configured to be electrically connected to the high-voltage unit 30' and the capacitor C on the side adjacent to the high-voltage unit 30'. The electrode layer 260' may be a polysilicon film doped with impurities of a second conductivity type, and the impurity concentration thereof may be controlled so as to reduce the high voltage to a voltage lower than the breakdown voltage of the switching unit 100' during the period of outputting a high voltage.

[0082] Figure 5 It is a cross-sectional view taken along line AA' of a power semiconductor device according to a third embodiment of the present invention.

[0083] Refer to Figure 5 , in the present embodiment, the switching unit 100", may include: a diode 110", located on the substrate 101". The diode 110", may include: a field oxide film 111", located on one side of the surface of the substrate 101" and including, for example, an oxide film; an anode layer 113" and a cathode layer 115", located on the field oxide film 111". At this time, the anode layer 113" and the cathode layer 115" may be in contact with each other. In addition, the anode layer 113" may be a polysilicon film doped with impurities of a first conductivity type, and the cathode layer 115" may be a polysilicon film doped with impurities of a second conductivity type.

[0084] In addition, the anode layer 113" may be connected to the driving power supply VCC is electrically connected, and the cathode layer 115" can be electrically connected to the fourth contact area 211" of the resistance unit 200".

[0085] The above detailed description is an illustration of the present invention. In addition, the above content is only an explanation of the preferred embodiments of the present invention, and the present invention can be used in a variety of different combinations, changes, and environments. That is, the present invention can be changed or modified within the scope of the concept of the invention disclosed in this specification and the scope equivalent to the described disclosure content and / or within the scope of the technology or knowledge in this industry. The above-described embodiments are only explanations of the best state for implementing the technical idea of the present invention, and the present invention can be variously changed according to the specific application fields and usage requirements. Therefore, the above detailed description of the present invention is not intended to limit the present invention to the disclosed embodiments.

Claims

1. A power semiconductor device, characterized in that: include: a high voltage unit which outputs a high voltage; a low voltage unit, which outputs a low voltage; a capacitor electrically connected to the high voltage unit and providing power to the high voltage unit during a period of outputting the high voltage; a switch unit electrically connected to the high voltage unit and the capacitor, connecting the capacitor to a driving power source in order to charge the capacitor during the period of outputting the low voltage, and preventing the high voltage unit and the driving power source from being electrically connected to each other during the period of outputting the high voltage; as well as, a resistance unit electrically connected between the switch unit and the high voltage unit, and reducing the high voltage to a voltage lower than a breakdown voltage of the switch unit during a period of outputting the high voltage; The resistance unit comprises: A second conductive type deep well region located in the substrate; a field oxide film located on a surface side of the substrate; and A P-TOP region is separated from the field oxide film in the deep well region.

2. The power semiconductor device according to claim 1, characterized in that: The P-TOP region is spaced apart from a bottom surface of the field oxide film at a lower side of the field oxide film.

3. The power semiconductor device according to claim 2, characterized in that: The P-TOP region is separated from a bottom surface of the deep well region.

4. The power semiconductor device according to claim 2, characterized in that: The switch unit includes a bipolar junction transistor.

5. The power semiconductor device according to claim 2, characterized in that: The resistor unit further includes: a first electrode layer electrically connected to a ground terminal on the field oxide film on a side adjacent to the switch unit; and The second electrode layer is electrically connected to the high voltage unit on the field oxide film on the side adjacent to the high voltage unit.

6. The power semiconductor device according to claim 5, characterized in that: The resistor unit further includes: A first contact region is formed in the deep well region and is electrically connected to the switch unit; and A second contact region is separated from the first contact region in the deep well region and is electrically connected to the high voltage unit.

7. The power semiconductor device according to claim 6, characterized in that: The resistor unit further includes: The second conductive type buried layer is located at the lower side of the second contact region.

8. The power semiconductor device according to claim 3, characterized in that: The resistor unit further includes: A single electrode layer is located on the field oxide film.

9. The power semiconductor device according to claim 8, characterized in that: The electrode layer is a polysilicon film doped with second conductivity type impurities.

10. The power semiconductor device according to claim 2, characterized in that: The switch unit comprises: A diode is located on the substrate.

11. The power semiconductor device according to claim 2, characterized in that: The switch unit comprises: an oxide film located on a surface side of the substrate; and The anode layer and the cathode layer are located on the field oxide film on the surface side of the substrate.

12. The power semiconductor device according to claim 11, characterized in that: The anode layer is a polysilicon film doped with first conductivity type impurities.

13. The power semiconductor device according to claim 4, characterized in that: The bipolar junction transistor comprises: A second conductive type emitter region located on a surface side of the substrate; A first conductive type base region separated from the emitter region on a surface side of the substrate; and The collector region is separated from the emitter region and the base region on the surface side of the substrate.

14. The power semiconductor device according to claim 13, characterized in that: The base region and the collector region are electrically connected to a driving power source.

15. The power semiconductor device according to claim 14, characterized in that: The emitter region is electrically connected to the resistance unit.

16. A power semiconductor device, characterized in that: include: a high voltage unit which outputs a high voltage; a low voltage unit, which outputs a low voltage; a capacitor electrically connected to the high voltage unit and providing power to the high voltage unit during a period of outputting the high voltage; a switch unit electrically connected to the high voltage unit and the capacitor, and connecting the capacitor to a driving power source in order to charge the capacitor during a period of outputting the low voltage; as well as a resistance unit electrically connected between the switch unit and the high voltage unit, and reducing the high voltage to a voltage lower than a breakdown voltage of the switch unit during a period of outputting the high voltage; The resistance unit comprises: A second conductive type deep well region located in the substrate; a field oxide film located on a surface side of the substrate; and The upper side of the P-TOP region is separated from the field oxide film in the deep well region.

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