Semiconductor device including field effect transistor and method of manufacturing same

Abstract

A semiconductor device includes: a substrate; a power distribution network layer disposed on a lower surface of the substrate; the source electrode / drain electrode pattern is arranged on the substrate; the source electrode / drain electrode pattern is arranged on the substrate; a backside conductive structure configured to penetrate the substrate and electrically connect the source / drain pattern and the power distribution network layer to each other; and a remaining pattern covering a side surface of an upper portion of the backside conductive structure.

Description

Technical Field

[0001] Embodiments of the inventive concept relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same. Background Art

[0002] Generally, a semiconductor device may include an integrated circuit including a metal oxide semiconductor field effect transistor (MOSFET). As the size and design rules of semiconductor devices have decreased, the size of MOSFETs has also been reduced. The operating characteristics of semiconductor devices may deteriorate due to the scaling of MOSFETs. Accordingly, semiconductor devices capable of overcoming the limitations caused by high integration density and having improved performance have been developed. Summary of the Invention

[0003] According to an embodiment of the inventive concept, a semiconductor device includes: a substrate; a power distribution network layer disposed on a lower surface of the substrate; a source / drain pattern disposed on the substrate; a backside conductive structure configured to penetrate the substrate and electrically connect the source / drain pattern and the power distribution network layer to each other; and a remaining pattern covering a side surface of an upper portion of the backside conductive structure.

[0004] According to an embodiment of the inventive concept, a semiconductor device includes: a substrate; a power distribution network layer disposed on a lower surface of the substrate; a source / drain pattern disposed on the substrate; a backside conductive structure penetrating the substrate and electrically connecting the source / drain pattern and the power distribution network layer to each other; and a remaining pattern disposed on a side surface of the backside conductive structure, wherein the backside conductive structure has a step at a first height, and wherein a lower surface of the remaining pattern is located at a height substantially the same as or lower than the first height.

[0005] According to an embodiment of the inventive concept, a semiconductor device includes: a substrate; a power distribution network layer disposed on a lower surface of the substrate; an insulating pattern disposed on the substrate; a source / drain pattern disposed on the insulating pattern; a channel pattern disposed on side surfaces of the source / drain pattern and including a plurality of semiconductor patterns stacked and spaced apart from each other; a gate electrode disposed between the plurality of semiconductor patterns; a backside conductive structure penetrating the substrate and electrically connecting the source / drain pattern and the power distribution network layer to each other; and a remaining pattern disposed on a side surface of the backside conductive structure, wherein the backside conductive structure has a step at a first height, and wherein a lower surface of the remaining pattern is located at a height substantially the same as or lower than the first height. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other aspects of the inventive concept will become more apparent by describing embodiments of the inventive concept in detail with reference to the accompanying drawings, in which:

[0007] Figure 1 is a plan view showing a semiconductor device according to an embodiment of the inventive concept.

[0008] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D are cross-sectional views corresponding to lines A-A', B-B', C-C', and D-D' of Figure 1 respectively.

[0009] Figure 3 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept.

[0010] Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 7A 、 Figure 7B 、 Figure 8 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10A 、 Figure 10B and Figure 10C are views showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0011] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0012] Figure 1 is a plan view showing a semiconductor device according to an embodiment of the inventive concept. Figures 2A to 2D are respectively Figure 1 cross-sectional views corresponding to lines A-A', B-B', C-C', and D-D'.

[0013] Referring to Figure 1 and Figures 2A to 2D , a substrate 105 including a PMOS region PR and an NMOS region NR can be provided. As an example, the substrate 105 may include a silicon-based insulating layer. For example, the substrate 105 may be an insulating substrate. As an example, the substrate 105 may include at least one of a silicon oxide layer (SiO2), a silicon nitride layer (SiN), and / or a silicon oxynitride layer (SiON). As used herein, each phrase such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include any one or all possible combinations of the items listed together in the respective phrase of the plurality of phrases.

[0014] Both the PMOSFET region PR and the NMOSFET region NR may extend in a first direction D1 and be spaced apart from each other in a second direction D2. The first direction D1 and the second direction D2 may be parallel to the lower surface of the substrate 105 and may intersect each other (e.g., be perpendicular).

[0015] Insulating patterns IP1 and IP2 may be defined by forming trenches TR in the upper portion of the substrate 105. The insulating patterns IP1 and IP2 may be parts of the substrate 105. For example, this part of the substrate 105 may protrude in a third direction D3. The third direction D3 may be a direction perpendicular to the lower surface of the substrate 105. For ease of explanation, unless otherwise stated, in this specification, the substrate 105 is defined to refer to the part of the substrate 105 other than the above-mentioned parts (i.e., the insulating patterns IP1 and IP2) of the substrate 105. The insulating patterns IP1 and IP2 may include a first insulating pattern IP1 provided on the PMOSFET region PR and a second insulating pattern IP2 provided on the NMOSFET region NR. The first insulating pattern IP1 and the second insulating pattern IP2 may extend in the first direction D1.

[0016] The device isolation pattern ST may be disposed on the substrate 105 and fill the trench TR. The device isolation pattern ST may at least partially surround the first insulating pattern IP1 and the second insulating pattern IP2. The device isolation pattern ST may include an insulating material. As an example, the device isolation pattern ST may include silicon oxide (SiO2).

[0017] The first channel pattern CH1 may be disposed on the first insulating pattern IP1, and the second channel pattern CH2 may be disposed on the second insulating pattern IP2. A plurality of first channel patterns CH1 may be provided and may be spaced apart from each other in the first direction D1. A plurality of second channel patterns CH2 may be provided and may be spaced apart from each other in the first direction D1. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 adjacent to each other in the third direction D3, but the inventive concept is not limited thereto. As an example, each of the first channel pattern CH1 and the second channel pattern CH2 may include four or more semiconductor patterns. As an example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon.

[0018] The first recess RS1 may be defined between the first channel patterns CH1 adjacent to each other in the first direction D1. The second recess RS2 may be defined between the second channel patterns CH2 adjacent to each other in the first direction D1.

[0019] The first source / drain pattern SD1 may be disposed on the first insulating pattern IP1, and the second source / drain pattern SD2 may be disposed on the second insulating pattern IP2. The first source / drain pattern SD1 may fill the first recess RS1, and the second source / drain pattern SD2 may fill the second recess RS2. Each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be electrically connected to the first to third semiconductor patterns SP1, SP2, and SP3. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., p-type), and the second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., n-type). As an example, a pair of first source / drain patterns SD1 may be electrically connected to each other through the first channel pattern CH1. As an example, a pair of second source / drain patterns SD2 may be electrically connected to each other through the second channel pattern CH2.

[0020] The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the first channel pattern CH1. Thus, the pair of first source / drain patterns SD1 may provide compressive stress to the first channel pattern CH1 therebetween. The second source / drain pattern SD2 may include the same semiconductor element as the second channel pattern CH2 (e.g., Si).

[0021] The first source / drain pattern SD1 may include a buffer layer BFL and a main layer MAL. The buffer layer BFL covers the inner surface of the first recess RS1, and the main layer MAL fills most of the remaining region of the first recess RS1 not filled by the buffer layer BFL. As an example, each of the buffer layer BFL and the main layer MAL may include silicon germanium (SiGe). The buffer layer BFL may include a relatively low concentration of germanium (Ge). The main layer MAL may include a relatively high concentration of germanium (Ge). As another example, the buffer layer BFL may include only silicon (Si).

[0022] The first source / drain pattern SD1 and the second source / drain pattern SD2 may include a first pattern T1 and a second pattern T2. The first pattern T1 is electrically connected to a power distribution network layer PDN to be described later, and the second pattern T2 is electrically connected to an active contact AC to be described later.

[0023] The gate electrode GE may be disposed on the first channel pattern CH1 and the second channel pattern CH2 and may cross the first channel pattern CH1 and the second channel pattern CH2. A plurality of gate electrodes GE may be provided. The gate electrodes GE may all extend in the second direction D2 and be spaced apart from each other in the first direction D1.

[0024] The gate electrode GE may include an inner electrode and an outer electrode. The inner electrode of the gate electrode GE may be disposed between the uppermost semiconductor pattern among the plurality of semiconductor patterns SP1, SP2, and SP3 and the insulating patterns IP1 and IP2. The outer electrode of the gate electrode GE may be disposed on the uppermost semiconductor pattern. For example, the inner electrode of the gate electrode GE may include a first electrode portion GE1, a second electrode portion GE2, and a third electrode portion GE3, but the inventive concept is not limited thereto. For example, the inner electrode of the gate electrode GE may include four or more electrode portions. For example, the first electrode portion GE1 may be interposed between the insulating patterns IP1 and IP2 and the first semiconductor pattern SP1. The second electrode portion GE2 may be interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The third electrode portion GE3 may be interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3. For example, the outer electrode of the gate electrode GE may include a fourth electrode portion GE4. For example, the fourth electrode portion GE4 may be disposed on the third semiconductor pattern SP3.

[0025] The gate electrode GE may include a first metal pattern and a second metal pattern disposed on the first metal pattern. The first metal pattern may include a work function metal for adjusting the threshold voltage of the transistor. As an example, the first metal pattern may include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and / or a metal nitride (e.g., a nitride including Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co). As an example, the first metal pattern may further include carbon (C). As an example, the first metal pattern may include metal materials having different work functions from each other.

[0026] As an example, the second metal pattern may include a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) having a lower resistance than the resistance of the first metal pattern.

[0027] For example, the first to third electrode portions GE1, GE2, and GE3 of the gate electrode GE may include the first metal pattern. For example, the fourth electrode portion GE4 of the gate electrode GE may include the first metal pattern and the second metal pattern.

[0028] The gate covering pattern GC may be disposed on the upper surface of the gate electrode GE. As an example, the gate covering pattern GC may include at least one of SiON, SiCN, SiOCN, and / or SiN.

[0029] The gate spacer GS may be disposed on a side surface of the fourth electrode portion GE4 of the gate electrode GE and may extend to side surfaces of the gate capping pattern GC, respectively. The gate spacer GS may include a single layer or a composite layer. As an example, the gate spacer GS may include at least one of SiON, SiCN, SiOCN, and / or SiN.

[0030] The gate insulating pattern GI may be interposed between the gate electrode GE and the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating pattern GI may cover upper surfaces, lower surfaces, and two side surfaces of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating pattern GI may cover an upper surface of the device isolation pattern ST under the gate electrode GE. The gate insulating pattern GI may be interposed between the fourth electrode portion GE4 and the gate spacer GS. As an example, the gate insulating pattern GI may include at least one of silicon oxide (SiO2), silicon oxynitride (SiON), and / or a high-k dielectric material. In the present specification, the high-k dielectric material is defined as a material having a dielectric constant higher than that of silicon oxide.

[0031] The inner spacer ISP may be interposed between a side surface of the second source / drain pattern SD2 and the gate electrode GE. As an example, the inner spacer ISP may be interposed between an inner electrode and the second source / drain pattern SD2. As an example, the inner spacer ISP may include an insulating material.

[0032] The first interlayer insulating layer ILD1 may be disposed on the substrate 105. The first interlayer insulating layer ILD1 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. An upper surface of the first interlayer insulating layer ILD1 may be located at substantially the same height as upper surfaces of the gate capping pattern GC and the gate spacer GS.

[0033] The second interlayer insulating layer ILD2 may cover the gate capping pattern GC and may be disposed on the first interlayer insulating layer ILD1. The third interlayer insulating layer ILD3 may be disposed on the second interlayer insulating layer ILD2. As an example, each of the first to third interlayer insulating layers ILD1, ILD2, and ILD3 may include silicon oxide (SiO2).

[0034] The active contact AC may penetrate the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 in the third direction D3. A plurality of active contacts AC may be provided, and a lower portion of each active contact AC may be disposed in an upper portion of the second pattern T2 of the source / drain patterns SD1 and SD2.

[0035] The active contact AC may include a conductive pattern CP and a barrier pattern BM. The conductive pattern CP penetrates through the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2, and the barrier pattern BM at least partially surrounds the conductive pattern CP. As an example, the conductive pattern CP may include a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). As an example, the barrier pattern BM may include a metal nitride (e.g., nitrides of such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0036] The ohmic pattern OM may be interposed between the active contact AC and the second pattern T2 of the source / drain patterns SD1 and SD2. Accordingly, the contact resistance between the active contact AC and the second pattern T2 of the source / drain patterns SD1 and SD2 can be improved. As an example, the ohmic pattern OM may include a metal silicide (e.g., silicides of such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, etc.).

[0037] The metal pattern MT may be disposed in the third interlayer dielectric layer ILD3. The via VI may be interposed between the metal pattern MT and the active contact AC. The metal pattern MT may be electrically connected to the active contact AC through the via VI. As an example, the gate contact may be connected to the gate electrode GE, and the metal pattern MT may be electrically connected to the gate contact through the via VI. As an example, each of the metal pattern MT and the via VI may be disposed in multiple layers, and the metal pattern MT and the via VI may be stacked alternately with each other. The metal pattern MT and the via VI may include a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0038] The power distribution network layer PDN may be disposed on the lower surface of the substrate 105. The power distribution network layer PDN may include a plurality of lower wirings electrically connected to the source / drain patterns SD1 and SD2 through a backside conductive structure BCS to be described later. As an example, the power distribution network layer PDN may include a wiring network for applying a source voltage. As an example, the power distribution network layer PDN may include a wiring network for applying a drain voltage.

[0039] The backside conductive structure BCS may be disposed in the substrate 105. The backside conductive structure BCS may penetrate through the substrate 105 and may be interposed between the first pattern T1 of the source / drain patterns SD1 and SD2 and the power distribution network layer PDN. The backside conductive structure BCS may electrically connect the first pattern T1 of the source / drain patterns SD1 and SD2 and the power distribution network layer PDN to each other.

[0040] The backside conductive structure BCS may have a step at a first height LV1. For example, a side surface Bs of the backside conductive structure BCS may have a step at the first height LV1. The side surface Bs may be a surface facing a first direction D1 or a direction opposite to the first direction D1. Due to the step, the backside conductive structure BCS may have a first side surface Bs1 and a second side surface Bs2. The first side surface Bs1 may be at a height higher than the first height LV1, and the second side surface Bs2 may be at a height lower than the first height LV1.

[0041] The backside conductive structure BCS may include an upper BCSy and a lower BCSx that do not have an interface with each other at the first height LV1. The first side surface Bs1 of the backside conductive structure BCS may be the side surface Bs1 of the upper BCSy of the backside conductive structure BCS, and the second side surface Bs2 may be the side surface Bs2 of the lower BCSx of the backside conductive structure BCS. In the first direction D1, the width of the upper BCSy of the backside conductive structure BCS at the first height LV1 may be smaller than the width of the lower BCSx of the backside conductive structure BCS at the first height LV1, but the inventive concept is not limited thereto.

[0042] The backside conductive structure BCS may include a backside conductive pattern BT and a backside barrier pattern BBM surrounding the backside conductive pattern BT. As an example, the backside conductive pattern BT may include a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). As an example, the backside barrier pattern BBM may include a metal nitride (e.g., nitrides such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0043] The backside alignment pattern BA may be disposed on the substrate 105 and may be embedded in the insulating patterns IP1 and IP2. The backside alignment pattern BA may be disposed below a second pattern T2 of the source / drain patterns SD1 and SD2. The second pattern T2 of the source / drain patterns SD1 and SD2 may overlap perpendicularly with and / or may contact the backside alignment pattern BA. As an example, the backside alignment pattern BA may include silicon germanium (SiGe). The backside alignment pattern BA may be spaced apart from the power distribution network layer PDN through the substrate 105.

[0044] The remaining pattern RP may be disposed on the substrate 105. The remaining pattern RP may be disposed in the insulating patterns IP1 and IP2. A plurality of remaining patterns RP may be provided, and the remaining patterns RP may be adjacent to each other in the first direction D1 in the insulating patterns IP1 and IP2 extending in the first direction D1. The remaining pattern RP may include a semiconductor material. As an example, the remaining pattern RP may include silicon (Si).

[0045] The remaining pattern RP may include a first remaining pattern RP1 and a second remaining pattern RP2. The first remaining pattern RP1 may be disposed on the side surface Bs of the backside conductive structure BCS, and the second remaining pattern RP2 may be disposed on the side surface of the backside alignment pattern BA.

[0046] The first remaining pattern RP1 may cover the side surface Bs1 of the upper portion BCSy of the backside conductive structure BCS. As an example, the first remaining pattern RP1 may completely cover the side surface Bs1 of the upper portion BCSy of the backside conductive structure BCS. Accordingly, the upper portion BCSy of the backside conductive structure BCS may be spaced apart from the insulating patterns IP1 and IP2 by the first remaining pattern RP1. The first remaining pattern RP1 may cover a portion of the side surface Bs2 of the lower portion BCSx of the backside conductive structure BCS. As described above, when the first remaining pattern RP1 covers the side surface Bs of the backside conductive structure BCS, the side surface of the first remaining pattern RP1 in contact with the backside conductive structure BCS may have a step.

[0047] The lower surface R1b of the first remaining pattern RP1 may be located at a height lower than a first height LV1. The lower surface R1b of the first remaining pattern RP1 may extend along a first direction D1 or a direction opposite to the first direction D1 on the side surface Bs of the backside conductive structure BCS. For example, the first remaining pattern RP1 may have a width in the first direction D1 or in a direction opposite to the first direction D1. For example, the height of the lower surface R1b of the first remaining pattern RP1 may be substantially constant.

[0048] The first remaining pattern RP1 may have a side surface R1s opposite to the side surface Bs of the backside conductive structure BCS. The side surface R1s of the first remaining pattern RP1 may be spaced apart from the side surface Bs of the backside conductive structure BCS. The side surface R1s and the lower surface R1b of the first remaining pattern RP1 may intersect at a specific angle. For example, the side surface R1s and the lower surface R1b of the first remaining pattern RP1 may intersect to form an angle of 90 degrees or greater. For example, the side surface R1s of the first remaining pattern RP1 may have a profile inclined in a direction away from the backside conductive structure BCS.

[0049] A plurality of first remaining patterns RP1 may be provided. The first remaining patterns RP1 adjacent to each other in the first direction D1 may be disposed on two side surfaces Bs of the corresponding backside conductive structure BCS.

[0050] The second remaining pattern RP2 can surround and cover the dorsal alignment pattern BA. The dorsal alignment pattern BA can be spaced apart from the insulating patterns IP1 and IP2 by the second remaining pattern RP2. The lower surface R2b of the second remaining pattern RP2 can be located at substantially the same height as the lower surface B1 of the dorsal alignment pattern BA, or can be located at a lower height.

[0051] The profile of the side surface R2s of the second remaining pattern RP2 and the angle between the side surface R2s and the lower surface R2b can be the same / similar to those described with reference to the first remaining pattern RP1.

[0052] The first remaining pattern RP1 and the second remaining pattern RP2 can be spaced apart from each other. Thus, the first remaining pattern RP1 and the second remaining pattern RP2 may not be electrically connected to each other. Thus, unnecessary leakage current does not flow from the first remaining pattern RP1 to the second remaining pattern RP2 or from the second remaining pattern RP2 to the first remaining pattern RP1. Thus, the reliability of the semiconductor device can be increased.

[0053] The distance between the first remaining pattern RP1 and the second remaining pattern RP2 can decrease as the first remaining pattern RP1 and the second remaining pattern RP2 extend in the third direction D3. The side surface R1s of the first remaining pattern RP1 and the side surface R2s of the second remaining pattern RP2 can overlap perpendicularly with the gate electrode GE. The side surface R1s of the first remaining pattern RP1 and the side surface R2s of the second remaining pattern RP2 can extend together in the direction in which the gate electrode GE extends. Due to the first remaining pattern RP1 and the second remaining pattern RP2, portions of the insulating patterns IP1 and IP2 can protrude in the third direction D3. The width of this portion of the insulating patterns IP1 and IP2 in the first direction D1 can decrease toward the third direction D3.

[0054] Hereinafter, reference will be made to Figure 3 a description of a semiconductor device according to an embodiment of the inventive concept. For simplicity of explanation, descriptions of content overlapping with the above will be omitted, and the description will focus on the differences from the above.

[0055] Figure 3 is a cross-sectional view showing a semiconductor device according to an embodiment of the inventive concept.

[0056] Reference Figure 3 is made, in the first direction D1, the width of the lower portion BCSx of the dorsal conductive structure BCS at the first height LV1 can be greater than the width of the lower portion BCSx of the dorsal conductive structure BCS at the first height LV1 described with reference to Figure 2A Thus, the lower surface of the first remaining pattern RP1 can be located at substantially the same height as the first height LV1.

[0057] Figures 4A to 10C is a view showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0058] Referring Figure 1 、 Figure 4A and Figure 4B , a semiconductor substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided. For example, the semiconductor substrate 100 may be a semiconductor substrate including a semiconductor material, such as a silicon single crystal substrate, a silicon germanium substrate, or an SOI substrate. A stacked pattern STP may be formed on the PMOSFET region PR and the NMOSFET region NR. For example, forming the stacked pattern STP may include: alternately stacking a semiconductor layer SL and a sacrificial layer SAL on the semiconductor substrate 100; forming a mask pattern extending in a first direction D1; and performing a patterning process using the mask pattern as an etch mask. During the patterning process, a portion of the semiconductor substrate 100 may be removed, and trenches TR defining a first active pattern AP1 and a second active pattern AP2 may be formed.

[0059] The first active pattern AP1 may be formed on the PMOSFET region PR, and the second active pattern AP2 may be formed on the NMOSFET region NR. The first active pattern AP1 and the second active pattern AP2 may extend in the first direction D1. A device isolation pattern ST may be formed to fill the trenches TR.

[0060] The sacrificial layer SAL may include a material having an etch selectivity with respect to the semiconductor layer SL. Thus, during a sacrificial layer SAL removal process described later, even when the sacrificial layer SAL is removed, the semiconductor layer SL may not be removed or may be removed to a very small extent. As an example, the semiconductor layer SL may include one of silicon (Si), germanium (Ge), or silicon germanium (SiGe), and the sacrificial layer SAL may include one of silicon (Si), germanium (Ge), or silicon germanium (SiGe), but different from the semiconductor layer SL.

[0061] Referring Figure 1 、 Figure 5A and Figure 5B, a sacrificial pattern PP can be formed on a semiconductor substrate 100 to extend in a second direction D2, respectively. The sacrificial pattern PP can be formed to cover the upper surface of the device isolation pattern ST and the side surface and upper surface of the stacked pattern STP. For example, forming the sacrificial pattern PP can include: forming a sacrificial layer on the front surface of the semiconductor substrate 100; forming a hard mask pattern MP on the sacrificial layer; and removing a portion of the sacrificial layer using the hard mask pattern MP as an etching mask to form the sacrificial pattern PP. As an example, the sacrificial pattern PP can include polysilicon. Thereafter, a gate spacer GS can be formed on the side surface of the sacrificial pattern PP.

[0062] Reference Figure 1 and Figures 6A to 6C , a first recess RS1 can be formed in the stacked pattern STP on the first active pattern AP1. A second recess RS2 can be formed in the stacked pattern STP on the second active pattern AP2. As an example, the first recess RS1 and the second recess RS2 can be formed by removing a portion of the stacked pattern STP using the hard mask pattern MP as an etching mask.

[0063] A semiconductor layer SL disposed on the first active pattern AP1 and separated by the first recess RS1 can be formed as a first channel pattern CH1 spaced apart from each other in a first direction D1. A semiconductor layer SL disposed on the second active pattern AP2 and separated by the second recess RS2 can be formed as a second channel pattern CH2 spaced apart from each other in the first direction D1. Each of the first channel pattern CH1 and the second channel pattern CH2 can include first to third semiconductor patterns SP1, SP2, and SP3.

[0064] The portion of the sacrificial layer SAL exposed by the second recess RS2 can be replaced with an insulating material, and thus, inner spacers ISP can be formed on both side surfaces of the sacrificial layer SAL.

[0065] A first lower recess LRS1 can be formed under the first recess RS1. A second lower recess LRS2 can be formed under the second recess RS2. A backside alignment pattern BA can be formed using the semiconductor substrate 100 as a seed to fill the interiors of the lower recesses LRS1 and LRS2 by SEG.

[0066] A first source / drain pattern SD1 can be formed in the first recess RS1. The first source / drain pattern SD1 can be formed by SEG using the first to third semiconductor patterns SP1, SP2, SP3 and the backside alignment pattern BA on the PMOSFET region PR as seeds.

[0067] For example, during the formation of the first source / drain pattern SD1, p-type impurities (e.g., boron, gallium, or indium) can be in-situ implanted into the first source / drain pattern SD1. As another example, after the formation of the first source / drain pattern SD1, impurities can be implanted into the first source / drain pattern SD1.

[0068] The second source / drain pattern SD2 can be formed in the second recess RS2. The first to third semiconductor patterns SP1, SP2, and SP3 on the NMOSFET region NR and the backside alignment pattern BA can be used as seeds to form the second source / drain pattern SD2 by SEG.

[0069] For example, during the formation of the second source / drain pattern SD2, n-type impurities (e.g., phosphorus, arsenic, or antimony) that cause n-type can be in-situ implanted into the second source / drain SD2. As another example, after the formation of the second source / drain pattern SD2, impurities can be implanted into the second source / drain pattern SD2.

[0070] Reference Figure 1 、 Figure 7A and Figure 7B and, the first interlayer insulating layer ILD1 can be formed to cover the first source / drain pattern SD1, the second source / drain pattern SD2, the hard mask pattern MP, and the gate spacer GS. Thereafter, the first interlayer insulating layer ILD provided on the upper surface of the sacrificial pattern PP can be removed. During the removal process, the hard mask pattern MP can also be removed, and the sacrificial pattern PP can be exposed.

[0071] Thereafter, the exposed sacrificial pattern PP can be removed, and an external region ORG can be formed in the region where the sacrificial pattern PP has been removed. The first channel pattern CH1, the second channel pattern CH2, and the sacrificial layer SAL can be exposed to the outside through the external region ORG.

[0072] Then, the exposed sacrificial layer SAL can be selectively removed. In this case, due to the high etching selectivity of the sacrificial layer SAL, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may not be removed or may be removed to a very small extent.

[0073] An internal region IRG can be formed in the region where the sacrificial layer SAL has been removed. For example, the internal region IRG can be formed between the first to third semiconductor patterns SP1, SP2, and SP3. The internal region IRG can include first to third internal regions IRG1, IRG2, and IRG3 spaced apart from each other in the third direction D3.

[0074] A gate insulating pattern GI may be formed in each of an inner region IRG and an outer region ORG. The gate insulating pattern GI may be formed to surround each of a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3.

[0075] Reference Figure 8 and Figures 9A to 9C , a gate electrode GE may be formed on the gate insulating pattern GI. The gate electrode GE may include: inner electrodes (e.g., first to third electrode portions GE1, GE2, and GE3) formed in each of a first to third inner regions IRG1, IRG2, and IRG3, and an outer electrode (e.g., a fourth electrode portion GE4) formed in the outer region ORG. Thereafter, a gate capping pattern GC may be formed on the fourth electrode portion GE4.

[0076] A second interlayer insulating layer ILD2 may be formed on the first interlayer insulating layer ILD1 and the gate capping pattern GC. An active contact AC may be formed to penetrate the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, and may be connected to a first source / drain pattern SD1 and a second source / drain pattern SD2, respectively. The source / drain patterns SD1 and SD2 may include a first pattern T1 not connected to the active contact AC and a second pattern T2 connected to the active contact AC. A backside alignment pattern BA may include: a first backside alignment pattern BA1 disposed under the first pattern T1 of the source / drain patterns SD1 and SD2, and a second backside alignment pattern BA2 disposed under the second pattern T2 of the source / drain patterns SD1 and SD2.

[0077] A gate contact GT may be formed to penetrate the second interlayer insulating layer ILD2 and the gate capping pattern GC, and may be connected to the gate electrode GE.

[0078] Forming the active contact AC and the gate contact GT may include: forming a barrier pattern BM, and forming a conductive pattern CP on the barrier pattern BM. An ohmic pattern OM may be formed between the active contact AC and the second pattern T2 of the source / drain patterns SD1 and SD2.

[0079] A third interlayer insulating layer ILD3 may be formed on the second interlayer insulating layer ILD2 and the active contact AC. A metal pattern MT and a via VI may be formed in the third interlayer insulating layer ILD3.

[0080] After completing the BEOL process, the top and bottom of the semiconductor substrate 100 described in Reference Figure 4A and 4B may be reversed. When the top and bottom of the semiconductor substrate 100 (e.g., Figure 4A ) are in view and are the same as those in Reference Figures 2A to 2DWhen it is opposite to the described completed semiconductor device, "upper surface" and "upper part" may respectively represent "lower surface" and "lower part". As seen from the completed semiconductor device described in reference Figures 2A to 2D "lower surface" and "lower part" may represent "upper surface" and "upper part".

[0081] The isolation trench ITR may penetrate the semiconductor substrate 100 (e.g., Figure 4A ) and the active patterns AP1 and AP2 (e.g., Figure 4A ), and may be formed to extend in the second direction D2. For example, the isolation trench ITR may overlap perpendicularly with the gate electrode GE. In addition, the isolation trench ITR may extend in the direction in which the gate electrode GE extends. Through the isolation trench ITR, the semiconductor substrate 100 (e.g., Figure 4A ) and the active patterns AP1 and AP2 (e.g., Figure 4A ) may be divided into a plurality of remaining patterns RP spaced apart from each other in the first direction D1.

[0082] According to an embodiment of the inventive concept, after the top and bottom of the semiconductor substrate 100 (e.g., Figure 4A ) are inverted, the isolation trench ITR may be formed to penetrate the semiconductor substrate 100 (e.g., Figure 4A ) and the active patterns AP1 and AP2 (e.g., Figure 4A ) and extend in the direction in which the gate electrode GE extends. The isolation trench ITR may divide the semiconductor substrate 100 (e.g., Figure 4A ) and the active patterns AP1 and AP2 (e.g., Figure 4A ) into a plurality of remaining patterns RP spaced apart from each other in the first direction D1. Since the remaining patterns RP are spaced apart from each other, leakage current caused by the remaining patterns RP between the source / drain patterns SD1 and SD2 can be prevented. In the case of the inventive concept, leakage current can be prevented only by forming the isolation trench ITR without removing the semiconductor substrate 100 (e.g., Figure 4A ) and the active patterns AP1 and AP2 (e.g., Figure 4A ). The inventive concept can simplify the removal process of the semiconductor substrate 100 (e.g., Figure 4A ) and the active patterns AP1 and AP2 (e.g., Figure 4A ), and can increase the productivity of the semiconductor device.

[0083] The width of the isolation trench ITR in the first direction D1 may become smaller toward the third direction D3. For example, the isolation trench ITR may have a tapered shape. A portion of the gate insulating pattern GI may be exposed through the inner surface of the isolation trench ITR. A plurality of isolation trenches ITR may be provided, and the isolation trenches ITR may be spaced apart from each other in the first direction D1. Each isolation trench ITR may overlap perpendicularly with a corresponding gate electrode GE.

[0084] Thereafter, a removal process may be performed on the upper portion of the remaining pattern RP. Accordingly, the upper surface of the remaining pattern may be formed to be substantially coplanar with the upper surface of the backside alignment pattern BA. As an example, the removal process may include a CMP process.

[0085] The remaining pattern RP may include a first remaining pattern RP1 and a second remaining pattern RP2. The first remaining pattern RP1 may be formed on the first backside alignment pattern BA1, and the second remaining pattern RP2 may be formed on the second backside alignment pattern BA2.

[0086] Reference Figure 1 and Figures 10A to 10C , the substrate 105 may be formed to fill the regions where the semiconductor substrate 100 (e.g., Figure 4A ), the active patterns AP1 and AP2 (e.g., Figure 4A ), and the upper portion of the remaining pattern RP have been removed, respectively. As an example, the substrate 105 may be formed by filling an insulating material to a height higher than the height of the removed region of the semiconductor substrate 100 (e.g., Figure 4A ).

[0087] A backside via BVH may be formed to penetrate the substrate 105. At this time, the backside via BVH may further penetrate the upper portion of the first remaining pattern RP1 and the upper portion of the first backside alignment pattern BA1. Accordingly, the first backside alignment pattern BA1 may be exposed on the inner surface of the backside via BVH. Thereafter, the exposed first backside alignment pattern BA1 may be removed.

[0088] Referring again to Figure 1 and Figures 2A to 2D , a backside conductive structure BCS may be formed to fill the inside of the backside via BVH. Forming the backside conductive structure BCS may include: forming a backside barrier pattern BBM that conformally covers each of the inner walls and the inner surface of the backside via BVH; and filling the inside of the backside via BVH on the backside barrier pattern BBM to form a backside conductive pattern BT. As an example, the backside conductive pattern BT may be formed through a single process, and thus, a separate interface may not be formed in the backside conductive pattern BT. Accordingly, the resistance of the backside conductive pattern BT may be relatively small, thereby improving the electrical characteristics of the semiconductor device.

[0089] In a first direction D1, based on a reference Figure 1 and Figures 10A to 10C the formation width of the back via hole BVH described, a reference Figures 2A to 2D shown backside conductive structure BCS can be formed, or a reference Figure 3 described backside conductive structure BCS can be formed.

[0090] Thereafter, a power distribution network layer PDN can be formed on the lower surface of the substrate 105.

[0091] According to an embodiment of the inventive concept, after the BEOL process is completed and the top and bottom of the semiconductor substrate are inverted, isolation trenches can be formed that penetrate the semiconductor substrate and the active patterns and extend in the direction in which the gate electrodes extend. The semiconductor substrate and the active patterns can be divided into a plurality of remaining patterns spaced apart from each other in a first direction by the isolation trenches. Since the remaining patterns are spaced apart from each other, leakage current caused by the remaining patterns between the source / drain patterns can be prevented. According to an embodiment of the inventive concept, leakage current can be prevented simply by forming the isolation trenches without removing the semiconductor substrate and the active patterns. Embodiments of the inventive concept can simplify the removal process of the semiconductor substrate and the active patterns and can improve the productivity of semiconductor devices.

[0092] Although the inventive concept has been described with reference to embodiments of the inventive concept, those of ordinary skill in the art will understand that various changes in form and detail can be made thereto without departing from the spirit and scope of the inventive concept.

Claims

1. A semiconductor device, comprising: substrate; a power distribution network layer, the power distribution network layer being disposed on the lower surface of the substrate; a source / drain pattern, wherein the source / drain pattern is disposed on the substrate; a backside conductive structure configured to penetrate the substrate and electrically connect the source / drain pattern and the power distribution network layer to each other; A remaining pattern covers a side surface of an upper portion of the backside conductive structure.

2. The semiconductor device according to claim 1, wherein The remaining pattern includes silicon.

3. The semiconductor device according to claim 1, wherein The height of the lower surface of the remaining pattern is constant.

4. The semiconductor device according to claim 1, wherein: A lower surface of the remaining pattern extends on a side surface of the backside conductive structure in a direction parallel to the lower surface of the substrate.

5. The semiconductor device according to claim 1, wherein The lower surface and the side surface of the remaining pattern intersect each other to form an angle of 90 degrees or more, The side surface of the remaining pattern is opposite to the side surface of the upper portion of the back-side conductive structure.

6. The semiconductor device according to claim 1, wherein The remaining pattern covers at least a portion of a side surface of a lower portion of the backside conductive structure.

7. The semiconductor device according to claim 1, wherein The backside conductive structure has a step at a first height, and Wherein, a lower surface of the remaining pattern is located at a height that is the same as or lower than the first height.

8. The semiconductor device according to claim 1, wherein The remaining pattern is a first remaining pattern, Wherein, the source / drain pattern includes a first pattern, Wherein, the source / drain pattern further includes a second pattern adjacent to the first pattern, and The semiconductor device further comprises a backside alignment pattern and a second remaining pattern, wherein the backside alignment pattern is arranged below the second pattern, and the second remaining pattern covers a side surface of the backside alignment pattern.

9. The semiconductor device according to claim 8, wherein: The first residual pattern and the second residual pattern are spaced apart from each other.

10. The semiconductor device according to claim 8, further comprising a gate electrode disposed on the substrate, in, A side surface of the first residual pattern and a side surface of the second residual pattern facing the side surface of the first residual pattern vertically overlap the gate electrode.

11. The semiconductor device according to claim 8, wherein As the first and second residual patterns extend in a direction perpendicular to the lower surface of the substrate, a distance between the first and second residual patterns becomes smaller.

12. The semiconductor device according to claim 8, wherein A lower surface of the second residual pattern is located at a height equal to or lower than a lower surface of the backside alignment pattern.

13. A semiconductor device comprising: substrate; a power distribution network layer, the power distribution network layer being disposed on the lower surface of the substrate; a source / drain pattern, wherein the source / drain pattern is disposed on the substrate; a backside conductive structure penetrating the substrate and electrically connecting the source / drain pattern and the power distribution network layer to each other; as well as a remaining pattern, the remaining pattern being arranged on a side surface of the backside conductive structure, The back conductive structure has a step at a first height, and Wherein, a lower surface of the remaining pattern is located at a height that is the same as or lower than the first height.

14. The semiconductor device according to claim 13, wherein: The remaining pattern includes silicon.

15. The semiconductor device according to claim 13, wherein: The height of the lower surface of the remaining pattern is constant.

16. The semiconductor device according to claim 13, wherein: The lower surface of the remaining pattern extends on the side surface of the backside conductive structure in a direction parallel to the lower surface of the substrate.

17. The semiconductor device according to claim 13, wherein: The remaining pattern is a first remaining pattern, Wherein, the source / drain pattern includes a first pattern, Wherein, the source / drain pattern further includes a second pattern adjacent to the first pattern, The semiconductor device further comprises a backside alignment pattern and a second remaining pattern, wherein the backside alignment pattern is arranged below the second pattern, and the second remaining pattern is arranged on a side surface of the backside alignment pattern, and Wherein, the first residual pattern and the second residual pattern are spaced apart from each other.

18. A semiconductor device comprising: substrate; a power distribution network layer, the power distribution network layer being disposed on the lower surface of the substrate; an insulating pattern, wherein the insulating pattern is disposed on the substrate; a source / drain pattern, wherein the source / drain pattern is disposed on the insulating pattern; a channel pattern disposed on a side surface of the source / drain pattern and including a plurality of semiconductor patterns stacked and spaced apart from each other; a gate electrode disposed between the plurality of semiconductor patterns; a backside conductive structure penetrating the substrate and electrically connecting the source / drain pattern and the power distribution network layer to each other; as well as a remaining pattern, the remaining pattern being arranged on a side surface of the backside conductive structure, The back conductive structure has a step at a first height, and Wherein, a lower surface of the remaining pattern is located at a height that is the same as or lower than the first height.

19. The semiconductor device according to claim 18, wherein: The remaining pattern includes silicon.

20. The semiconductor device according to claim 18, wherein The lower surface of the remaining pattern extends on the side surface of the backside conductive structure in a direction parallel to the lower surface of the substrate.

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