Electrostatic discharge protection structure and forming method thereof

Abstract

The invention discloses an electrostatic discharge protection structure and a forming method thereof, and the structure comprises a substrate which comprises an active region; a gate structure on the substrate; the source doped region and the drain doped region are located in the active region; the silicide barrier layer covers the side wall of the gate structure and extends to a part of the surface of the gate structure outside the active region; and the electric interconnection structure is electrically connected with the source doped region and the gate structure respectively. When electrostatic discharge exists outside and the current of the electrostatic discharge is not enough to conduct the parasitic BJT structure, the voltage loaded on the gate structure can be raised by the tiny current due to a section of high-resistance region on the gate structure extending out of the active region, so that the channel of the active region covered by the gate structure is opened, and the channel of the BJT structure is opened. The current of electrostatic discharge can be led out from the channel path; and when the parasitic BJT structure can be conducted by the electrostatic discharge current, the electrostatic discharge current can be led out from the two paths, so that the protection on the internal circuit is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to an electrostatic discharge protection structure and a method for forming the same. Background Art

[0002] Integrated circuits are vulnerable to electrostatic damage. Generally, protection circuits are designed at the input / output ends or power protection devices of the circuit to prevent the internal circuit from being damaged by static electricity.

[0003] In existing integrated circuit designs, electrostatic discharge (ESD) protection structures are often used to reduce electrostatic damage. The existing electrostatic discharge protection structures mainly include: a Gate Grounded NMOS (GGNMOS) protection circuit with a gate electrically connected to a low potential, a Silicon Controlled Rectifier (SCR) protection circuit, a Lateral Double Diffused MOSFET (LDMOS) protection circuit, a Bipolar Junction Transistor (BJT) protection circuit, etc.

[0004] Among them, GGNMOS is a widely used electrostatic discharge protection structure. In the ESD network of the entire chip, when an ESD event occurs, GGNMOS may conduct both forward and backward, which is determined by the potential ESD path. The ESD current always flows to the low-resistance path. Therefore, it is necessary to consider the forward and backward ESD performances of GGNMOS during design to ensure the reliability of the integrated circuit. GGNMOS, as a BJT, has a breakdown device working mechanism, and relies on the avalanche breakdown between the drain and the substrate to trigger the formation of a low-resistance path to discharge the ESD current.

[0005] However, the performance of the electrostatic discharge protection structure formed by the existing technology needs to be improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide an electrostatic discharge protection structure and a method for forming the same to enhance the protection of the internal circuit.

[0007] To solve the above problems, the technical solution of the present invention provides an electrostatic discharge protection structure, including: a substrate having first doping ions therein, the substrate including an active region; a gate structure located on the substrate, the gate structure spanning across the active region; a source doping region and a drain doping region located within the active region, the source doping region and the drain doping region being respectively located on both sides of the gate structure, the source doping region and the drain doping region having second doping ions therein, the electrical type of the second doping ions being different from that of the first doping ions; a silicide blocking layer covering the sidewall of the gate structure near the drain doping region and a part of the surface of the gate structure extending outside the active region; an electrical interconnection structure electrically connected to the source doping region and the gate structure respectively, for electrically connecting the source doping region and the gate structure to a low potential, wherein the electrical connection position of the electrical interconnection structure and the gate structure is located on the top surface of the gate structure in a direction away from the active region and outside the coverage area of the silicide blocking layer.

[0008] Optionally, it further includes: a heavily doped region located within the substrate, electrically isolated from the source doping region, the heavily doped region having the first doping ions therein, and the doping concentration of the first doping ions in the heavily doped region being greater than that of the first doping ions in the substrate.

[0009] Optionally, the electrical interconnection structure is also electrically connected to the heavily doped region for electrically connecting the heavily doped region to a low potential.

[0010] Optionally, it further includes: an isolation structure located within the substrate, the isolation structure being located between the heavily doped region and the source doping region for electrically isolating the heavily doped region from the source doping region.

[0011] Optionally, the material of the isolation structure includes: silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, aluminum oxide or aluminum nitride.

[0012] Optionally, the first doping ions are P-type ions, and the P-type ions include: boron or indium; the second doping ions are N-type ions, and the N-type ions include: phosphorus or arsenic.

[0013] Optionally, the material of the silicide blocking layer includes: silicon oxide, silicon oxynitride or silicon nitride.

[0014] Correspondingly, the technical solution of the present invention also provides a method for forming an electrostatic discharge protection structure, including: providing a substrate having first doping ions therein, the substrate including an active region; forming a gate structure on the substrate, the gate structure spanning across the active region; forming a source doping region and a drain doping region in the active region, the source doping region and the drain doping region being respectively formed on two sides of the gate structure, the source doping region and the drain doping region having second doping ions therein, the electrical type of the second doping ions being different from that of the first doping ions; forming a silicide blocking layer, the silicide blocking layer covering the sidewall of the gate structure near the drain doping region and a partial surface of the gate structure extending outside the active region; forming an electrical interconnection structure, the electrical interconnection structure being electrically connected to the source doping region and the gate structure respectively, for electrically connecting the source doping region and the gate structure to a low potential, wherein the electrical connection position of the electrical interconnection structure and the gate structure is located on the top surface of the gate structure in a direction away from the active region and outside the coverage area of the silicide blocking layer.

[0015] Optionally, before forming the silicide blocking layer, it further includes: forming a heavily doped region in the substrate, the heavily doped region being electrically isolated from the source doping region, the heavily doped region having the first doping ions therein, and the doping concentration of the first doping ions in the heavily doped region being greater than that of the first doping ions in the substrate.

[0016] Optionally, the electrical interconnection structure is also electrically connected to the heavily doped region for electrically connecting the heavily doped region to a low potential.

[0017] Optionally, the method for electrically isolating the heavily doped region from the source doping region includes: forming an isolation structure in the substrate, the isolation structure being located between the heavily doped region and the source doping region for electrically isolating the heavily doped region from the source doping region.

[0018] Optionally, the method for forming the isolation structure includes: forming an isolation trench in the substrate; forming an isolation material layer in the isolation trench and on the surface of the substrate; performing a planarization process on the isolation material layer until the surface of the substrate is exposed, to form the isolation structure.

[0019] Optionally, the material of the isolation structure includes: silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, aluminum oxide or aluminum nitride.

[0020] Optionally, the method for forming the silicide blocking layer includes: forming a silicide blocking material layer on the surface of the gate structure and on the top surface of the substrate; using an etching process to remove a part of the silicide blocking material layer to form the silicide blocking layer.

[0021] Optionally, the forming process of the silicide blocking material layer includes: a plasma enhanced chemical vapor deposition process.

[0022] Optionally, the material of the silicide blocking layer includes: silicon oxide, silicon oxynitride or silicon nitride.

[0023] Optionally, the first doping ion is a P-type ion, and the P-type ions include: boron or indium; the second doping ion is an N ion, and the N-type ions include: phosphorus or arsenic.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the electrostatic discharge protection structure of the technical solution of the present invention, the silicide blocking layer further covers and extends to a part of the surface of the gate structure outside the active region, thereby increasing the resistance of the gate structure extending outside the active region. When there is an electrostatic discharge from the outside and the current of the electrostatic discharge is not sufficient to turn on the parasitic BJT structure, at this time, due to the existence of a high-resistance region on the gate structure extending outside the active region, a small current will raise the voltage applied to the gate structure, thereby opening the channel of the active region covered by the gate structure. The current of the electrostatic discharge can flow from the drain doping region through the channel into the source doping region, and then be led out through the electrical interconnection structure; when the current of the electrostatic discharge can turn on the parasitic BJT structure, at this time, the current of the electrostatic discharge can be led out from two paths, effectively improving the efficiency of the electrostatic discharge, thereby improving the protection of the internal circuit.

[0026] In the forming method of the electrostatic discharge protection structure of the technical solution of the present invention, the silicide blocking layer further covers and extends to a part of the surface of the gate structure outside the active region, thereby increasing the resistance of the gate structure extending outside the active region. When there is an electrostatic discharge from the outside and the current of the electrostatic discharge is not sufficient to turn on the parasitic BJT structure, at this time, due to the existence of a high-resistance region on the gate structure extending outside the active region, a small current will raise the voltage applied to the gate structure, thereby opening the channel of the active region covered by the gate structure. The current of the electrostatic discharge can flow from the drain doping region through the channel into the source doping region, and then be led out through the electrical interconnection structure; when the current of the electrostatic discharge can turn on the parasitic BJT structure, at this time, the current of the electrostatic discharge can be led out from two paths, effectively improving the efficiency of the electrostatic discharge, thereby improving the protection of the internal circuit. Description of the Drawings

[0027] Figure 1 is a schematic structural diagram of an electrostatic discharge protection structure;

[0028] Figures 2 to 11 These are schematic diagrams of the structures at each step in the formation process of the electrostatic discharge protection structure in an embodiment of the present invention. Detailed implementation manners

[0029] As described in the background art, the performance of the electrostatic discharge protection structure formed by the prior art needs to be improved. The following will be specifically described with reference to the accompanying drawings.

[0030] Please refer to Figure 1 , an electrostatic discharge protection structure, comprising: a substrate 100 having first doping ions therein, the substrate 100 including an active region (not labeled); a gate structure 101 located on the substrate 100, the gate structure 101 spanning across the active region; a source doping region 102 and a drain doping region 103 located within the active region, the source doping region 102 and the drain doping region 103 being respectively located on both sides of the gate structure 101, the source doping region 102 and the drain doping region 103 having second doping ions therein, the electrical type of the second doping ions being different from that of the first doping ions; a heavily doped region 104 located within the substrate 100, the heavily doped region 104 being electrically isolated from the source doping region 102, the heavily doped region 104 having the first doping ions therein, and the doping concentration of the first doping ions in the heavily doped region 104 being greater than the doping concentration of the first doping ions in the substrate 100; a silicide blocking layer 105 covering the sidewall of the gate structure 101 near the drain doping region 103; an electrical interconnection structure 106 electrically connected to the heavily doped region 104, the source doping region 102, and the gate structure 101 respectively, for electrically connecting the heavily doped region 104, the source doping region 102, and the gate structure 101 to a low potential.

[0031] Please continue to refer to Figure 1 , the electrostatic discharge protection structure utilizes the reverse cut-off characteristic of the PN junction to keep the device in a cut-off state during normal operation of the circuit. When there is an electrostatic discharge from the outside, the electrostatic discharge protection structure undergoes avalanche breakdown, and the parasitic BJT structure conducts, forming a low-resistance path, and the large current will be discharged (the current path is as shown by S1 in Figure 1 ), without breaking through the gate oxide layer in the functional device structure, thereby achieving the purpose of protecting the internal circuit.

[0032] However, the electrostatic discharge protection structure requires a relatively large electrostatic discharge to conduct the parasitic BJT structure, so the protection of the internal circuit still needs to be improved.

[0033] On this basis, the present invention provides an electrostatic discharge protection structure and a method for forming the same. The silicide blocking layer further covers a part of the surface of the gate structure extending outside the active region, thereby increasing the resistance of the gate structure extending outside the active region. When there is an electrostatic discharge from the outside and the current of the electrostatic discharge is not sufficient to turn on the parasitic BJT structure, at this time, due to the existence of a high-resistance region on the gate structure extending outside the active region, a small current will raise the voltage applied on the gate structure, thereby opening the channel of the active region covered by the gate structure. The current of the electrostatic discharge can flow from the drain doping region through the channel into the source doping region and then be led out through the electrical interconnection structure; when the current of the electrostatic discharge can turn on the parasitic BJT structure, at this time, the current of the electrostatic discharge can be led out through two paths, effectively improving the efficiency of the electrostatic discharge.

[0034] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0035] Figures 2 to 11 It is a schematic structural diagram of the formation process of an electrostatic discharge protection structure according to an embodiment of the present invention.

[0036] Please refer to Figure 2 , a substrate 200 is provided. The substrate 200 has a first doping ion therein, and the substrate 200 includes an active region (not labeled).

[0037] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, or silicon carbide; or the substrate may also be other materials, such as III-V compounds such as gallium arsenide.

[0038] Please continue to refer to Figure 2 , an isolation structure 201 is formed in the substrate 200.

[0039] The isolation structure 201 is located between the subsequently formed heavily doped region and the source doping region for electrically isolating the heavily doped region and the source doping region.

[0040] The method for forming the isolation structure 201 includes: forming an isolation trench (not labeled) in the substrate 200; forming an isolation material layer (not shown) in the isolation trench and on the surface of the substrate 200; and performing a planarization process on the isolation material layer until the surface of the substrate 200 is exposed to form the isolation structure 201.

[0041] The material of the isolation structure 201 includes: silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, aluminum oxide, or aluminum nitride.

[0042] In this embodiment, the material of the isolation structure 201 is silicon oxide.

[0043] In this embodiment, the first doped ions are doped into the substrate 200 by an ion implantation process after the isolation structure 201 is formed; in other embodiments, the first doped ions may also be doped into the substrate before the isolation structure is formed.

[0044] Please refer to Figure 3 , a gate structure 202 is formed on the substrate 200, and the gate structure 202 straddles the active region.

[0045] The gate structure 202 includes: a gate dielectric layer and a gate layer (not labeled) located on the gate dielectric layer.

[0046] In this embodiment, the material of the gate dielectric layer is silicon oxide, and the material of the gate layer is polysilicon.

[0047] Please refer to Figure 4 , a source doped region 203 and a drain doped region 204 are formed in the active region, the source doped region 203 and the drain doped region 204 are respectively formed on both sides of the gate structure 202, the source doped region 203 and the drain doped region 204 have second doped ions, and the electrical types of the second doped ions are different from those of the first doped ions.

[0048] In this embodiment, the first doped ions are P-type ions, and the P-type ions include: boron or indium; the second doped ions are N-type ions, and the N-type ions include: phosphorus or arsenic.

[0049] Please refer to Figure 5 , after the source doped region 203 and the drain doped region 204 are formed, a heavily doped region 205 is formed in the substrate 200.

[0050] The heavily doped region 205 and the source doped region 203 are electrically isolated by the isolation structure 201. The heavily doped region 205 has the first doped ions, and the doping concentration of the first doped ions in the heavily doped region 205 is greater than the doping concentration of the first doped ions in the substrate 200, so as to reduce the contact resistance between the substrate 200 and the subsequently formed electrical interconnection structure.

[0051] The method for forming the heavily doped region 205 includes: forming a second mask layer (not shown) on the substrate 200, and the second mask layer exposes a part of the top surface of the substrate 200; using the second mask layer as a mask, performing an implantation process of the first doped ions into the active region to form the heavily doped region 205.

[0052] Please refer to Figures 6 to 8 , Figure 7 which Figure 6 is a schematic cross-sectional view along line A-A in Figure 8 and Figure 6 is a schematic cross-sectional view along line B-B in , forming a silicide blocking layer 206, where the silicide blocking layer 206 covers the sidewalls of the gate structure 202 near the drain doping region 204 and a portion of the surface of the gate structure 202 extending outside the active region.

[0053] Since all the external electrostatic discharges will be fully loaded on the drain doping region 204, it is easy to break down the gate dielectric layer of the gate structure 202. Therefore, by forming the high-resistance silicide blocking layer 206 to cover the sidewalls of the gate structure 202 near the drain doping region 204, the compressive resistance of the electrostatic discharge protection structure can be improved. And the silicide blocking layer 206 covering a portion of the surface of the gate structure 202 extending outside the active region can effectively increase the resistance of the gate structure 202 extending outside the active region, which is equivalent to the existence of a high-resistance region on the gate structure 202 extending outside the active region.

[0054] The forming method of the silicide blocking layer 206 includes: forming a silicide blocking material layer on the surface of the gate structure 202 and the top surface of the substrate 200; using an etching process to remove a portion of the silicide blocking material layer to form the silicide blocking layer 206.

[0055] The forming process of the silicide blocking material layer uses a plasma-enhanced chemical vapor deposition process.

[0056] The material of the silicide blocking layer 206 includes: silicon oxide, silicon oxynitride or silicon nitride. In this embodiment, the material of the silicide blocking layer 206 is silicon oxide.

[0057] Please refer to Figures 9 to 11 , Figure 9 which is a top view of the electrostatic discharge protection structure showing only a part of the electrical interconnection structure, Figure 10 and Figure 9 is a schematic cross-sectional view along line C-C in Figure 11 and Figure 9 is a schematic cross-sectional view along line D-D in Figure 11The electrical interconnection structure in the embodiment only shows an electrical connection relationship, forming an electrical interconnection structure 207, wherein the electrical interconnection structure 207 is electrically connected to the source doping region 203 and the gate structure 202, respectively, and is used to electrically connect the source doping region 203 and the gate structure 202 to a low potential, wherein the electrical connection position between the electrical interconnection structure 207 and the gate structure 202 is located in a direction away from the active area and on the top surface of the gate structure 202 outside the coverage area of ​​the silicide blocking layer 206.

[0058] The electrical interconnect structure 207 is also electrically connected to the heavily doped region 205 for electrically connecting the heavily doped region 205 to a low potential.

[0059] It should be noted that, in this embodiment, the low potential is relative to the high voltage in the internal circuit.

[0060] It should be noted that, in this embodiment, during the test phase, when used to characterize the protection capability of the electrostatic discharge protection structure, the drain doped region 204 is electrically connected to a transmission line pulse generator (TLP) through the electrical interconnect structure 207. The transmission line pulse generator pre-charges a charge storage device and then discharges it instantaneously to form a square wave to strike the electrostatic discharge protection structure under test. The pulse width is generally 100ns. In the actual chip structure, the drain doped region 204 is electrically connected to the device structure with actual function to protect the internal circuit.

[0061] When there is electrostatic discharge in the outside world, and the electrostatic discharge current is not enough to turn on the parasitic BJT structure, at this time, due to the presence of a high-resistance region on the gate structure 202 extending outside the active area, a small current will raise the voltage loaded on the gate structure 202, thereby opening the channel of the active area covered by the gate structure 202, and the electrostatic discharge current can flow from the drain doping region 204 through the channel into the source doping region 203, and then be extracted through the electrical interconnection structure 207 (the current path is as shown in FIG. Figure 11 When the electrostatic discharge current can conduct the parasitic BJT structure, the electrostatic discharge current can be derived from two paths (the current path is shown as Figure 11 The efficiency of electrostatic discharge is effectively improved, thereby improving the protection of the internal circuit.

[0062] It should be noted that the electrical connection position between the electrical interconnect structure 207 and the gate structure 202 is located in a direction away from the active area and on the top surface of the gate structure 202 outside the area covered by the silicide blocking layer 206. Its function is to ensure that when the current of electrostatic discharge is not sufficient to turn on the parasitic BJT structure, the path of the tiny current passes through the high-resistance region on the gate structure 202 extending outside the active area, thereby raising the voltage loaded on the gate structure 202 and opening the channel of the active area covered by the gate structure 202.

[0063] The technical solution of the present invention provides an electrostatic discharge protection structure, please continue to refer to Figures 9 to 11 , comprising: a substrate 200, wherein the substrate 200 has first doping ions, and the substrate 200 includes an active area; a gate structure 202 located on the substrate 200, wherein the gate structure 202 spans the active area; a source doping area 203 and a drain doping area 204 located in the active area, wherein the source doping area 203 and the drain doping area 204 are located on both sides of the gate structure 202, respectively, wherein the source doping area 203 and the drain doping area 204 have second doping ions, and the electrical type of the second doping ions is different from that of the first doping ions; a silicide blocking layer 206, wherein the silicide blocking layer 206 covers the sidewalls of the gate structure 202 near the drain doping region 204 and a portion of the surface of the gate structure 202 extending outside the active region; an electrical interconnection structure 207, the electrical interconnection structure 207 is electrically connected to the source doping region 203 and the gate structure 202, respectively, and is used to electrically connect the source doping region 203 and the gate structure 202 to a low potential, wherein the electrical connection position between the electrical interconnection structure 207 and the gate structure 202 is located in a direction away from the active region and on the top surface of the gate structure 202 outside the area covered by the silicide blocking layer 206.

[0064] The silicide blocking layer 206 also covers a portion of the surface of the gate structure 202 extending outside the active area, thereby increasing the resistance of the gate structure 202 extending outside the active area. When there is electrostatic discharge in the outside, and the current of the electrostatic discharge is not enough to conduct the parasitic BJT structure, at this time, due to the presence of a high-resistance region on the gate structure 202 extending outside the active area, a small current will raise the voltage loaded on the gate structure 202, thereby opening the channel of the active area covered by the gate structure 202, and the current of the electrostatic discharge can flow from the drain doping area 204 through the channel into the source doping area 203, and then be extracted through the electrical interconnection structure 207; when the current of the electrostatic discharge can conduct the parasitic BJT structure, the current of the electrostatic discharge can be extracted from two paths at this time, effectively improving the efficiency of the electrostatic discharge.

[0065] The electrostatic discharge protection structure further includes: a heavily doped region 205 located in the substrate 200, the heavily doped region 205 being electrically isolated from the source doped region 203, the heavily doped region 205 having the first doping ions, and the doping concentration of the first doping ions in the heavily doped region 205 being greater than the doping concentration of the first doping ions in the substrate 200.

[0066] The electrical interconnection structure 207 is also electrically connected to the heavily doped region 205 for electrically connecting the heavily doped region 205 to a low potential.

[0067] The electrostatic discharge protection structure further includes: an isolation structure 201 located in the substrate 200, the isolation structure 201 being located between the heavily doped region 205 and the source doped region 203 for electrically isolating the heavily doped region 205 from the source doped region 203.

[0068] The material of the isolation structure 201 includes: silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, aluminum oxide or aluminum nitride.

[0069] In this embodiment, the material of the isolation structure 201 is silicon oxide.

[0070] The first doping ions are P-type ions, and the P-type ions include: boron or indium; the second doping ions are N ions, and the N-type ions include: phosphorus or arsenic.

[0071] The material of the silicide blocking layer 206 includes: silicon oxide, silicon oxynitride or silicon nitride. In this embodiment, the material of the silicide blocking layer 206 is silicon oxide.

[0072] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. An electrostatic discharge protection structure, characterized in that, Comprising: A substrate having first doping ions therein, the substrate including an active region; A gate structure located on the substrate, the gate structure spanning across the active region; A source doping region and a drain doping region located within the active region, the source doping region and the drain doping region being respectively located on two sides of the gate structure, the source doping region and the drain doping region having second doping ions therein, the second doping ions being of a different electrical type from the first doping ions; A silicide blocking layer covering the sidewalls of the gate structure near the drain doping region and a partial surface of the gate structure extending outside the active region; An electrical interconnection structure electrically connected to the source doping region and the gate structure respectively, for electrically connecting the source doping region and the gate structure to a low potential, wherein the electrical connection position of the electrical interconnection structure and the gate structure is located on the top surface of the gate structure in a direction away from the active region and outside the coverage area of the silicide blocking layer.

2. The electrostatic discharge protection structure according to claim 1, wherein, Further comprising: A heavily doped region located within the substrate, electrically isolated from the source doping region, the heavily doped region having the first doping ions therein, the doping concentration of the first doping ions in the heavily doped region being greater than the doping concentration of the first doping ions in the substrate.

3. The electrostatic discharge protection structure according to claim 2, wherein, The electrical interconnection structure is also electrically connected to the heavily doped region for electrically connecting the heavily doped region to a low potential.

4. The electrostatic discharge protection structure according to claim 2, wherein, Further comprising: An isolation structure located within the substrate, the isolation structure being located between the heavily doped region and the source doping region for electrically isolating the heavily doped region from the source doping region.

5. The electrostatic discharge protection structure according to claim 4, wherein, The material of the isolation structure includes: silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, aluminum oxide or aluminum nitride.

6. The electrostatic discharge protection structure according to claim 1, wherein, The first doping ions are P-type ions, and the P-type ions include: boron or indium; the second doping ions are N-type ions, and the N-type ions include: phosphorus or arsenic.

7. The electrostatic discharge protection structure according to claim 1, wherein The material of the silicide blocking layer includes: silicon oxide, silicon oxynitride or silicon nitride.

8. A method for forming an electrostatic discharge protection structure, characterized in that, Comprising: Providing a substrate having first doping ions therein, the substrate including an active region; Forming a gate structure on the substrate, the gate structure spanning across the active region; Forming a source doping region and a drain doping region within the active region, the source doping region and the drain doping region being respectively formed on two sides of the gate structure, the source doping region and the drain doping region having second doping ions therein, the second doping ions being of a different electrical type from the first doping ions; Forming a silicide blocking layer covering the sidewalls of the gate structure near the drain doping region and a partial surface of the gate structure extending outside the active region; Forming an electrical interconnection structure electrically connected to the source doping region and the gate structure respectively, for electrically connecting the source doping region and the gate structure to a low potential, wherein the electrical connection position of the electrical interconnection structure and the gate structure is located on the top surface of the gate structure in a direction away from the active region and outside the coverage area of the silicide blocking layer.

9. The method for forming the electrostatic discharge protection structure according to claim 8, wherein, Before forming the silicide blocking layer, it further includes: forming a heavily doped region in the substrate, the heavily doped region being electrically isolated from the source doped region, the first doping ions being present in the heavily doped region, and the doping concentration of the first doping ions in the heavily doped region being greater than the doping concentration of the first doping ions in the substrate.

10. The method for forming the electrostatic discharge protection structure according to claim 9, wherein, The electrical interconnection structure is also electrically connected to the heavily doped region for electrically connecting the heavily doped region to a low potential.

11. The method for forming the electrostatic discharge protection structure according to claim 9, wherein, The method for electrically isolating the heavily doped region from the source doped region includes: forming an isolation structure in the substrate, the isolation structure being located between the heavily doped region and the source doped region for electrically isolating the heavily doped region from the source doped region.

12. The method for forming the electrostatic discharge protection structure according to claim 11, wherein The method for forming the isolation structure includes: forming an isolation trench in the substrate; forming an isolation material layer in the isolation trench and on the surface of the substrate; and performing a planarization process on the isolation material layer until the surface of the substrate is exposed to form the isolation structure.

13. The method for forming the electrostatic discharge protection structure according to claim 11, wherein, The material of the isolation structure includes: silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, aluminum oxide or aluminum nitride.

14. The method for forming the electrostatic discharge protection structure according to claim 8, wherein, The method for forming the silicide blocking layer includes: forming a silicide blocking material layer on the surface of the gate structure and on the top surface of the substrate; and removing a part of the silicide blocking material layer by an etching process to form the silicide blocking layer.

15. The method for forming the electrostatic discharge protection structure according to claim 14, wherein, The formation process of the silicide blocking material layer includes: a plasma enhanced chemical vapor deposition process.

16. The method for forming the electrostatic discharge protection structure according to claim 8, wherein The material of the silicide blocking layer includes: silicon oxide, silicon oxynitride or silicon nitride.

17. The method for forming the electrostatic discharge protection structure according to claim 8, wherein, The first doping ions are P-type ions, and the P-type ions include: boron or indium; the second doping ions are N-type ions, and the N-type ions include: phosphorus or arsenic.

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