VCMA MRAM device

Abstract

In one aspect, a memory stack for a VCMA-MRAM device is provided, comprising: an MTJ layer structure; the auxiliary magnetic layer structure comprises a second hard magnetic layer and an auxiliary magnetic layer; and an interposer structure interposed between the free layer of the MTJ layer structure and the auxiliary magnetic layer of the auxiliary magnetic layer structure and including a second barrier layer configured to induce VCMA in the auxiliary magnetic layer and a non-magnetic spacer layer interposed between the second barrier layer and the free layer; wherein, in response to a first bias voltage across the memory stack exceeding a first threshold voltage, the induced VCMA in the secondary magnetic layer causes the secondary magnetic layer to destabilize from a pinned magnetization state having magnetization oriented in the first direction, and into an unstable magnetization state; wherein the free layer is arranged in a bias field generated by the memory stack.

Description

Technical Field

[0001] The present disclosure generally relates to memory stacks for voltage-controlled magnetic anisotropy VCMA, magnetic random access memory MRAM devices, VCMA MRAM devices, and methods for programming VCMA MRAM devices. Background Art

[0002] Magnetic random access memory (MRAM) is a promising memory technology that allows non-volatile data storage, high write and read speeds, and low power consumption. The non-volatile storage function of an MRAM device is provided by a magnetic tunnel junction (MTJ) device. A magnetic tunnel junction structure can include a free layer, a barrier layer (usually an oxide), a reference layer, and a hard magnetic layer. The magnetization state of the reference layer is fixed or pinned by the hard magnetic layer. The orientation of the magnetization of the free layer can be switched between a first orientation and a second orientation relative to the (fixed) orientation of the magnetization of the reference layer. In the first orientation, the magnetization orientation of the free layer is aligned with the magnetization orientation of the reference layer, and in the second orientation, the magnetization orientation of the free layer is opposite to the magnetization orientation of the reference layer. The first and second orientations can be referred to as the parallel magnetization orientation or state (“P”) and the antiparallel magnetization orientation or state (“AP”), respectively. The relative orientation of the magnetization of the reference layer and the free layer determines the resistance of the MTJ device to current, where the P orientation or P state can correspond to a lower resistance state (“LRS”), and the AP orientation or AP state corresponds to a higher resistance state (”HRS”). The tunneling magnetoresistance ratio (TMR) is a measure of the MTJ resistance difference between the AP state and the P state. Therefore, by measuring the resistance of the MTJ, the magnetization state of the free layer can be sensed.

[0003] Current MRAM technologies generally rely on spin transfer torque (STT) as the key switching mechanism for free layer magnetization. However, STT writing may require a large amount of spin-polarized current to flow through the oxide barrier of the magnetic tunnel junction (MTJ), which may limit the power efficiency of the write operation. The strong tunneling current also degrades the tunnel barrier of the MTJ, thus affecting the reliability of the memory cell.

[0004] Voltage-controlled magnetic anisotropy (VCMA) is another promising method for achieving ultra-low power write operations. Contrary to STT-assisted free layer switching, VCMA utilizes a bias voltage applied across the MTJ device to induce a voltage across the barrier layer. This generates an electric field within the tunnel layer, which can change the charge distribution at the local interface between the barrier layer and the free layer. The changed charge distribution results in an observable modulation of the free layer magnetic anisotropy, thereby reducing the energy barrier between the P and AP states and thus making the initially stable device more easily switchable by means of an external magnetic field. The amount of modulation depends on the quality of the MTJ materials and interfaces and is quantified by the VCMA coefficient (in units of fJ / V.m).

[0005] Although the VCMA-assisted write scheme is clearly a low-power solution, there are many associated challenges.

[0006] First, current proof-of-concept write schemes are typically based on the precession of the free layer magnetization and thus allow the MTJ to switch between AP and P states without any current flowing through the device. This precession requires an external magnetic field orthogonal to the magnetization orientation of the free layer (e.g., in-plane in the case of a free layer with perpendicular magnetic anisotropy (PMA)). The external magnetic field needs to be synchronized with the (pulsed) bias voltage.

[0007] Second, the precession-based write scheme requires high-frequency voltage pulses and very precise timing control to operate with a sufficiently low write error rate. This means that the voltage pulses should be very short and within very strict tolerances to achieve reliable switching, as the switching precession depends strongly on the pulse width. For example, the typical median duration of a voltage pulse can be 1 ns with a tolerance of + / -0.2 ns. Any longer or shorter pulse duration will result in a significant reduction in the switching success rate and thus a large write error rate (WER).

[0008] Third, traditional VCMA writes are sequential read-write operations. Since the anti-parallel (AP) and parallel (P) states are equally stable, the AP-P and P-AP transitions share the same polar write pulses. Therefore, to ensure the desired final state, a pre-read is needed to decide whether a write is required. For example, to write to an LRS, the write pulse should be applied only to the HRS MTJ device. This is because an MTJ device already in the LRS will switch to the HRS in response to the write pulse and vice versa. Thus, the entire write process of "read + evaluate + write" may reduce the time and power efficiency promised by VCMA writes. Summary of the Invention

[0009] The object of the present invention is to provide a memory stack with an improved design that allows a deterministic VCMA-assisted free layer switching protocol to reduce the need for pre-reading, thereby enabling a VCMA-MRAM device to have one or more of reduced complexity, increased power efficiency, and increased speed. Further objects and / or additional objects can be understood from the following.

[0010] Accordingly, in a first aspect, there is provided a memory stack for a voltage-controlled magnetic anisotropy (VCMA) magnetic random access memory (MRAM) device, the memory stack comprising:

[0011] MTJ layer structure, the MTJ layer structure includes a first hard magnetic layer, a reference layer having a magnetization state pinned by the first hard magnetic layer, a free layer capable of switching between a first magnetization state having a magnetization oriented in a first direction and a second magnetization state having a magnetization oriented in a second direction opposite to the first direction, and a first barrier layer inserted between the reference layer and the free layer and configured to induce VCMA in the free layer;

[0012] Auxiliary magnetic layer structure, the auxiliary magnetic layer structure includes a second hard magnetic layer and an auxiliary magnetic layer; and

[0013] Intermediate layer structure, the intermediate layer structure is inserted between the free layer of the MTJ layer structure and the auxiliary magnetic layer of the auxiliary magnetic layer structure and includes a second barrier layer and a non-magnetic spacer layer, the second barrier layer is configured to induce VCMA in the auxiliary magnetic layer, and the non-magnetic spacer layer is inserted between the second barrier layer and the free layer;

[0014] Wherein, in the case of no bias voltage across the memory stack, the magnetization state of the auxiliary magnetic layer is pinned by the second hard magnetic layer in a pinned magnetization state having a magnetization oriented in the first direction;

[0015] Wherein, in response to a first bias voltage across the memory stack exceeding a first threshold voltage, the VCMA induced in the auxiliary magnetic layer causes the auxiliary magnetic layer to become unstable from the pinned magnetization state and enter an unstable magnetization state;

[0016] Where the free layer is arranged in an offset field generated by the memory stack, and wherein the auxiliary magnetic layer is configured to:

[0017] When the auxiliary magnetic layer is in the pinned magnetization state, provide a first contribution to the offset field such that the offset field is oriented in the first direction at the free layer, and,

[0018] When the auxiliary magnetic layer is in the unstable magnetization state, provide a second contribution to the offset field such that the offset field is oriented in the second direction at the free layer; and,

[0019] Where the first threshold voltage exceeds a second threshold voltage for causing a VCMA-induced switching of the free layer from the second magnetization state to the first magnetization state.

[0020] According to a second aspect, there is provided a MRAM device, which includes a memory stack according to the first aspect or any of its embodiments or variations, and further includes a programming circuit configured to apply a first bias voltage to set the free layer to the second magnetization state, and apply a second bias voltage between the first and second threshold voltages to set the free layer to the first magnetization state.

[0021] According to a third aspect, there is provided a method for programming a memory stack of an MRAM device according to the second aspect or any embodiment or variant thereof, the method comprising:

[0022] setting the free layer to the first magnetization state by applying a bias voltage between the first threshold voltage and the second threshold voltage to the memory stack; or

[0023] setting the free layer to the second magnetization state by applying a bias voltage exceeding the first threshold voltage to the memory stack.

[0024] Thus, the present invention is based on the recognition that a synthetic antiferromagnetic layer structure including a pinned synthetic antiferromagnetic layer with VCMA can be used to modulate the (magnetostatic) offset field (interchangeably, "stray field") at the free layer, such that the sign of the offset field can be changed. Thus, the orientation of the magnetization of the free layer can be coupled to the offset field, such that the offset field (whose orientation depends on the amplitude of the bias voltage across the memory stack) can be used to orient the magnetization orientation of the free layer to align with the offset field during switching.

[0025] As a result, there is no longer a need for the conventionally used precession-induced external field, as this functionality is now provided by the synthetic antiferromagnetic layer structure and the modulation of the stray field direction.

[0026] Furthermore, since the offset field can provide an exact tilt or bias of the layer magnetization towards the first or second free layer directions and the corresponding free layer magnetization states, the pulse-width dependence of the conventional VCMA write scheme is eliminated. The tilt is determined by the superposition of the intrinsic stray field generated by the synthetic antiferromagnetic layer structure (i.e., the second hard magnetic layer and the synthetic antiferromagnetic layer) and the stray field generated by another magnetic layer of the memory stack (e.g., the first hard magnetic layer and the reference layer). Thus, regardless of the time for which the bias voltage is applied, as long as it is sufficient to tilt the free layer towards the desired final state, the free layer magnetization will precess predictably in a direction determined in principle only by the pulse amplitude. This can greatly facilitate memory circuit design and reduce variability factors.

[0027] Since the tilt of the free layer magnetization is actually determined only by the voltage amplitude, deterministic switching of the free layer magnetization can be achieved using a unipolar write voltage without the need for a pre-read before writing to determine the magnetization state of the free layer. In other words, regardless of the current state of the free layer, a bias voltage that exceeds the second threshold voltage and is less than the first threshold voltage will deterministically set the free layer in the first magnetization state (magnetization orientation in the first direction), while a bias voltage that exceeds the second threshold voltage will deterministically set the free layer in the second magnetization state (magnetization orientation in the second direction). That is, the free layer magnetization either tilts towards the opposite state or simply returns to a tilt that favors the same state as before. In other words, the final magnetization state of the free layer will depend on whether the amplitude of the applied bias voltage is sufficient to drive the antiferromagnetic layer into an unstable magnetization state, thereby flipping the sign of the offset field.

[0028] The VCMA in the antiferromagnetic layer is enabled by the second barrier layer of the interlayer structure. At the same time, a non-magnetic spacer layer inserted between the second barrier layer and the free layer can cancel or prevent the second barrier layer from inducing VCMA in the free layer at the free layer interface opposite to the interface facing the first barrier layer. Therefore, the non-magnetic spacer layer can act as a VCMA interruption layer between the free layer and the second barrier layer.

[0029] For example, by configuring the memory stack such that the VCMA coefficient of the antiferromagnetic layer is less than that of the free layer, and / or such that the antiferromagnetic layer has a stronger magnetic anisotropy than the free layer, a first threshold voltage (for driving the antiferromagnetic layer into an unstable magnetization state) that exceeds the second threshold voltage (for driving the antiferromagnetic layer from the second to the first magnetization state) can be achieved.

[0030] As used herein, unless otherwise expressly stated, the term "magnetization" of a layer is used to refer to the net magnetization of the layer, i.e., equal to the sum of the fundamental magnetic moments of the layer.

[0031] The "orientation" of the magnetization of a layer (such as the free layer or the antiferromagnetic layer) refers to the orientation of the magnetization vector of the layer, or equivalently, the orientation of the net magnetic moment of the layer. The magnetization of a layer being oriented along a given direction (e.g., the first direction or the second direction) means that the component (usually the main component) of the magnetization (i.e., the magnetization vector) is parallel to the given direction. Conversely, the magnetization of a layer being oriented opposite or relative to a given direction (e.g., the first direction or the second direction) means that the component (usually the main component) of the magnetization (i.e., the magnetization vector) is antiparallel to the given direction.

[0032] The free layer is a layer having magnetization that can be switched between a first and a second magnetization state. The first magnetization state corresponds to a free layer magnetization oriented in a first direction. The second magnetization state corresponds to a free layer magnetization oriented in an opposite second direction. In an implementation of a memory stack in which the magnetization of the reference layer is oriented along the first direction, the first and second magnetization states can correspond to the anti-parallel (AP) state and the parallel (P) state of the MTJ layer structure, respectively. In an implementation of a memory stack in which the magnetization of the reference layer is oriented along the second direction, the first and second magnetization states can correspond to the P state and the AP state of the MTJ layer structure, respectively.

[0033] The first hard magnetic layer, the reference layer, the free layer, the auxiliary magnetic layer, and the second hard magnetic layer can each be a layer having perpendicular magnetic anisotropy (PMA). Accordingly, the first and second directions can be mutually opposite out-of-plane directions with respect to the free layer, i.e., transverse to the in-plane direction of the free layer.

[0034] Alternatively, the first hard magnetic layer, the reference layer, the free layer, the auxiliary magnetic layer, and the second hard magnetic layer can each be a layer having in-plane magnetic anisotropy (IPMA). Accordingly, the first and second directions can be mutually opposite in-plane directions with respect to the free layer.

[0035] In some embodiments, the destabilized magnetization state of the auxiliary magnetic layer corresponds to the magnetization of the auxiliary magnetic layer being oriented transverse to the first direction. Accordingly, in response to a first bias voltage, the VCMA effect caused by the second barrier layer can modulate the magnetic anisotropy of the auxiliary magnetic layer such that the magnetization vector (in an implementation where the auxiliary magnetic layer has PMA) rotates from an out-of-plane orientation to an in-plane orientation, or (in an implementation where the auxiliary magnetic layer has PMA) from an in-plane orientation to an out-of-plane orientation. Accordingly, the contribution of the auxiliary magnetic layer to the offset field along the first direction can be effectively reduced, ideally substantially to zero, such that the sign of the offset field at the free layer is flipped.

[0036] In some embodiments, the non-magnetic spacer layer is formed of Ta, Ir, Pt, Ru, CoFeX, CoX, FeX, or CoFeBX, where X is a non-magnetic material such as W, Ta, or Mo. These materials can effectively prevent the second tunnel barrier layer from altering the charge distribution in the free layer while allowing the desired magnetic anisotropy (e.g., PMA or IPMA) to be provided in the MTJ layer structure and the auxiliary magnetic layer structure.

[0037] In some embodiments, the auxiliary magnetic layer structure further includes a spacer layer that is inserted between the auxiliary magnetic layer and the second hard magnetic layer and is configured to provide parallel or antiparallel coupling of the magnetizations of the auxiliary magnetic layer and the second hard magnetic layer. By coupling the magnetization of the auxiliary magnetic layer to the second hard magnetic layer, a pinned equilibrium magnetization state can be defined for the auxiliary magnetic layer. Thus, the auxiliary magnetic layer has a deterministic single final state regardless of whether the bias voltage is between the first and second thresholds or exceeds the first threshold.

[0038] The spacer layer can be configured to provide interlayer exchange coupling (IEC), also known as Ruderman-Kittel-Kasuya-Yosida (RKKY) exchange coupling. Thus, the coupling can be parallel or antiparallel, which is determined by the thickness of the spacer layer.

[0039] The programming circuit of the MRAM device according to the second aspect can be configured to apply the first bias voltage and the second bias voltage as respective voltage pulses having substantially equal durations. As described above, the final magnetization state of the free layer will actually be determined by the amplitude of the applied voltage rather than the pulse duration. Thus, the durations of the first and second voltage pulses can be substantially equal. This can facilitate the write protocol and enable the P and AP states to be programmed in approximately the same amount of time. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] This and other aspects of the invention will now be described in more detail with reference to the drawings showing embodiments of the invention.

[0041] Figure 1 A memory stack and an MRAM device according to an example embodiment are schematically shown.

[0042] Figure 2a -b shows Figure 1 the free layer switching of the memory stack from the P state to the AP state.

[0043] Figure 3a -b shows Figure 1 the free layer switching of the memory stack from the AP state to the P state.

[0044] Figure 4a -b shows the free layer switching between the AP state and the P state of a memory stack according to another example embodiment. DETAILED DESCRIPTION

[0045] An example embodiment of a memory stack of an MRAM device suitable for implementing VCMA-assisted switching of free layer magnetization will now be described with reference to the accompanying drawings. The memory stack will be depicted in a schematic cross-section, where it will be understood that the relative sizes of some structures and layers may be exaggerated and not drawn to scale. Instead, the dimensions may be adjusted to make the illustration clear and easy to understand. When appearing in the accompanying drawings, the indicated axes X and Y consistently represent the horizontal or in-plane direction and the vertical direction transverse to X, respectively. As used herein, the terms "horizontal" and "in-plane" refer to the direction parallel to the main extension plane of each layer of the corresponding memory stack, or equivalently, parallel to the direction of the (main surface) of the substrate supporting the memory stack of the MRAM device. At the same time, the term "vertical" refers to the normal direction of the layer extension plane, or equivalently perpendicular to the (main surface) of the substrate. Therefore, the vertical direction Y corresponds to the direction in which the layers of the memory stack are stacked. In addition, in the accompanying drawings, arrows are used to indicate the magnetization state of the relevant magnetic layer of the corresponding memory stack. Arrows parallel to or opposite to the Y direction represent vertical or out-of-plane magnetization states. Arrows parallel to or opposite to the X direction represent in-plane magnetization states. Unless otherwise specified, a layer comprising a single arrow represents a layer having a fixed or pinned magnetization. Meanwhile, a layer comprising two oppositely oriented arrows represents a layer having a switchable magnetization state (usually a free layer).

[0046] Figure 1 An example embodiment of a memory stack 1 is schematically shown, the memory stack 1 comprising an MTJ layer structure 4 , an auxiliary magnetic layer structure 6 , and an interposer structure 5 interposed between the MTJ layer structure 4 and the auxiliary magnetic layer structure 6 .

[0047] The MTJ layer structure 4 includes a first hard magnetic layer (HL) 41, a reference layer (RL) 43, a free layer (FL) 45, and a first tunnel barrier layer or a first barrier layer (BL) 44 inserted between the RL 43 and the FL 45. The first BL layer 44 is configured to induce VCMA in the FL 45 to implement the VCMA-assisted switching method described in detail below. As shown in the figure, the MTJ layer structure 4 may also include a spacer layer (SL) 42 inserted between the first HL 41 and the RL 43.

[0048] The auxiliary magnetic layer structure 6 includes an auxiliary magnetic layer 61 and a second hard magnetic layer 63. As shown, the auxiliary magnetic layer structure 6 may further include a spacer layer 63 inserted between the second hard magnetic layer 63 and the auxiliary magnetic layer 61. For simplicity, the term drive layer (DL) structure will be used hereinafter to refer to the auxiliary magnetic layer structure 6. Accordingly, the auxiliary magnetic layer 61 and the second hard magnetic layer 63 will be referred to as the "variable" DL layer (VDL) 61 and the "fixed" layer (FDL) 63, respectively. The motivation for the term "drive layer" is that the DL structure can be functionally regarded as being configured to "drive" the VCMA-assisted switching of the FL 45, as described in detail below.

[0049] The interlayer structure 5 is inserted between the FL 45 and the VDL 61. The interlayer structure 5 includes a second BL 52. The second BL 52 is configured to induce VCMA in the VDL 61. The interlayer structure 5 further includes a non-magnetic SL 51 inserted between the second BL 52 and the FL 45. Thus, the interlayer structure 5 is arranged such that the second BL 52 faces the VDL 61 of the DL structure 6, and the non-magnetic SL 51 faces the FL 45 of the MTJ layer structure 4.

[0050] The memory stack 1 is configured to have PMA as Figure 1 shown. That is, the magnetic layers (HL 41, RL 43, FL 45, VDL 61, and FDL 62) of the memory stack 1 are each configured as a PMA layer.

[0051] The RL 43 has a fixed or pinned magnetization state pinned by the first HL 41. Accordingly, the first HL 41 is configured as the pinned layer of the MTJ layer structure 4. In the example shown, the first HL 41 and the RL 43 are configured as synthetic antiferromagnet (SAF), which have magnetization vectors with opposite orientations coupled by the SL 42, providing antiferromagnetic coupling. However, this is merely an example, and a parallel coupling configuration is also possible. The type of coupling between the HL 41 and the RL 43 is itself known in the art and can be controlled by the thickness and composition of the SL 42.

[0052] The VDL 61 is configured to be pinned in the magnetization state by the FDL 63 without any bias voltage across the memory stack 1, and the magnetization is oriented along the first direction. Thus, the FDL 63 is configured as the pinned layer of the DL structure 6. In the present disclosure, the first direction conventionally corresponds to the orientation along which the magnetization vector of the FDL 63 is oriented when in the pinned magnetization state. In the illustrated example, the first direction corresponds to the vertical Y direction. In the illustrated example, the VDL 61 and the FDL 63 are configured as synthetic ferromagnetic (SFM), which have substantially parallel magnetization vectors coupled by the SL 62, providing parallel coupling. However, this is merely an example, and an antiparallel coupling configuration is also possible, in which the VDL 61 and the FDL 63 are configured as SAF. The type of coupling between the VDL 61 and the FDL 63 itself is known in the art and can be controlled by the thickness and composition of the SL 62.

[0053] The FL 45 has variable magnetization and can be switched between a first magnetization state in which the magnetization is oriented along the first direction Y and a second magnetization state in which the magnetization is oriented along a second direction opposite to the first direction (i.e., -Y (negative Y)). Due to the PMA of the memory stack 1, the first and second directions Y and -Y define mutually opposite out-of-plane directions. For the depicted memory stack 1, the first magnetization state corresponds to the antiparallel (AP) state of the MTJ layer structure 4, while the second magnetization state corresponds to the parallel (P) state of the MTJ layer structure 4. This is due to the opposite orientations of the respective pinned magnetization states of the RL 43 and the VDL 61.

[0054] Non-limiting examples of the materials of the HL 41 and the FDL 63 include CoPt alloys with different compositions, Co / Pt nanolaminates, CoCd alloys with different compositions, Co / Pd nanolaminates, Co-Ni alloys with different compositions, Co / Ni nanolaminates, FePt alloys with different compositions, and Fe / Pt nanolaminates. The HL 41 and the FDL 63 can generally be formed to have a thickness of about 10 nm or less.

[0055] Non-limiting examples of the materials of the RL 43, the FL 45, and the VDL 61 include iron-based and / or cobalt-based layers, such as Fe, Co, FeB, CoB, CoFe, and CoFeB (with different compositions of Co, Fe, and B). The RL 43, the FL 45, and the VDL 61 can generally be formed to have a thickness of about 2 nm or less.

[0056] Non-limiting examples of the materials for the first BL 44 and the second BL 52 include MgO x , AlO x and MgAlO x . The BL44 and 52 can generally be formed to be 5 - 20 angstroms Thickness.

[0057] The purpose of inserting SL 51 between the second BL 52 and FL 45 is to counteract or prevent the second BL 51 from inducing VCMA at the side of FL 45 facing the interlayer structure 5. That is, the VCMA at the side of FL 45 facing the first BL 44 is desired, while the VCMA at the opposite side of FL 45 will be restricted and advantageously minimized. Therefore, the composition of SL 51 can be such that SL 51 can act as a VCMA interruption layer between the free layer 45 and the second BL 52. Non-limiting examples of the material of SL 51 include Ta, Ir, Pt, Ru, or alloys of CoFeX, CoX, FeX, or CoFeBX, where X is a non-magnetic material such as W, Ta, or Mo, or another conventional non-magnetic boron getter known in the art. The amount of the non-magnetic material X can vary. It can be understood that the larger the amount of X, the lower the amount of other components. SL 51 can generally be formed to have a thickness of about 2 nm or less.

[0058] Non-limiting examples of the material for the coupling or spacer layers SL 42 and 62 include typical RKKY spacer materials such as Cr, Ir, Ru, Ag, RuAl, and the thickness is selected to achieve the desired type of coupling (e.g., parallel or antiparallel). The thickness can generally be less than about 2 nm.

[0059] As shown in the figure, the memory stack 1 can be disposed on the substrate 2. The substrate 2 can be any conventional substrate or wafer, such as a semiconductor substrate. By way of example only, examples of semiconductor substrates include Si substrates, Ge substrates, SiGe substrates, SiC substrates, SOI substrates, GeOI substrates, SiGeOI substrates. Although not explicitly shown in FIG. 2, the substrate 2 can support an active device portion or include a front-end-of-line (FEOL) portion including active devices. The memory stack 1 can be more specifically included in a back-end interconnect structure disposed on the substrate 2. The interconnect structure can include a stack of interconnect layers or metallization layers, which includes interconnect structures (lines and vias) embedded in the interlayer dielectric. The interconnect structure can couple the memory stack 1 to the programming and read circuitry, for example, via bit lines and word lines, which is known in the art per se. The interconnect structure can define, together with the active devices of the FEOL portion, the circuitry for controlling the programming and read operations, which will be further discussed below. Figure 1The circuit system 9 is shown in a highly schematic manner and can apply programming and / or read operations to the memory stack 1. As shown, the circuit system 9 can be connected to the memory stack 1 through bottom and top electrodes 7, 8 (BE, TE) known in the art. The memory stack 1, the substrate 2, the interconnect structure, and the circuit system 9 can be included in the MRAM device 10, where the memory stack 1 can be arranged to include an array of multiple corresponding memory stacks.

[0060] Compared with MTJ devices that rely on conventional precession-based VCMA-assisted free layer magnetization state switching, according to the present disclosure, the memory stack 1 is configured to achieve deterministic VCMA-assisted switching. The deterministic switching is enabled by the VDL 61 of the DL structure 6, which is used to modulate the offset field acting on the FL 45. As described above, the VDL 61 is configured to be maintained in the pinned magnetization state along the first direction Y through the FDL 63 without any bias voltage across the memory stack 1.

[0061] In practice, if the energy contributing to pinning exceeds the demagnetization energy E that tends to align the magnetization of the VDL 61 to in-plane orientation demag , the VDL 61 will remain in the pinned equilibrium magnetization state oriented along the first direction Y.

[0062] Several magnetic energies contribute to the pinning of the magnetization state of the VDL 61, and the main contributions are: E couple - The coupling energy provided by the FDL 63 (in the shown example, given by RKKY coupling through the SL 62); and E k - The magnetic anisotropy energy (PMA in the shown example). For simplicity, assuming no other contributions, as long as E couple +E k >E demag , the VDL 61 will remain in the equilibrium state. By applying a voltage across the memory stack 1, an electric field will be generated in the second BL 52, such that in response, the magnetic anisotropy energy E k can be modulated by the VCMA effect, where the modulation is given by:

[0063] E k = E k0 * (1 – VCMA Coeff * |E|),

[0064] where E k0 is the magnetic anisotropy energy at zero bias, and |E| = V bias / t BL is the magnitude of the electric field at the interface between the second BL 52 and the VDL 61, V bias is the voltage across the second BL 52, tBL is the thickness of the second BL 52.

[0065] This means that by applying a voltage exceeding a certain threshold voltage, here denoted as "first threshold voltage V th-1->2 ", the VDL 61 can be destabilized from the pinned magnetization state (oriented along Y) and enter the destabilized magnetization state corresponding to the in-plane magnetization state (oriented along X). The exact magnitude of the first threshold voltage naturally depends on E couple 、E k0 、E demag and VCMA Coeff etc., all of which depend on the design of the memory stack 1.

[0066] Bringing the VDL 61 into the destabilized in-plane magnetization state will further cause modulation of the offset field acting on the FL 45. The offset field at the FL 45 is given by the net static magnetic field generated by all the magnetic layers of the memory stack 45 other than the FL 45 (including the HL 41, RL 43, VDL61, and FDL 63). Therefore, the VDL 61 can provide a first contribution to the offset field when maintaining the equilibrium magnetization state and a second contribution to the offset field when reaching the destabilized magnetization state.

[0067] The memory stack 1, and specifically the VDL 61, is configured such that the first contribution, together with the contributions of the other magnetic layers of the memory stack 1, generates an offset field oriented along the first direction Y at the FL 45, while the second contribution, together with the contributions of the other magnetic layers of the memory stack 1 (which will remain substantially unchanged), generates an offset field oriented along the second direction at the FL 45. Thus, in summary, by applying a first bias voltage exceeding the first threshold voltage across the memory stack 1, the VDL 61 can change from the equilibrium magnetization state (out-of-plane, along the Y direction) to the destabilized magnetization state (in-plane, along the X direction), thereby causing a sign change in the Y component of the offset field at the FL 45.–

[0068] The memory stack 1 is also configured such that the first threshold voltage for destabilizing the VDL 61 is greater than the threshold voltage for VCMA-induced switching that causes the FL 45 to change from the second magnetization state (in the example shown is P, where the FL magnetization is oriented along the -Y direction) to the first magnetization state (in the example shown is AP, where the RL magnetization is oriented along the Y direction), here referred to as "second threshold voltage, V th-2->1 ".

[0069] Therefore, the memory stack 1 provides a first write window V th-2->1 < V < V th-1->2 for setting the FL 45 to the first magnetization state (e.g., AP), and a second write window V > Vth-1->2, for setting FL 45 to a second magnetization state (e.g., P). A second threshold voltage V th-2->1 smaller than the first threshold voltage V th-2->1 can be achieved by different techniques. As a first example, VDL 61 can be configured to exhibit a stronger magnetic anisotropy (e.g., PMA) than FL 45. As a second example, the VCMA coefficient of VDL61 can be smaller than the VCMA coefficient of FL 45. Combinations of these techniques are also possible.

[0070] Figure 2a -b and Figure 3a -b summarizes the above discussion through schematic diagrams. Figure 2b and 3b respectively show the memory stack 1, but for simplicity, the substrate 2, BE 7, and TE 8 are omitted.

[0071] Figure 2a -b depicts the switching from the first magnetization state P to the second magnetization state AP. Figure 2a The left diagram shows the residual state of FL 45 and the equally stable magnetization states P and AP without the bias voltage V across the memory stack 1. Figure 2b The right diagram shows, as a result of the VCMA effect induced in FL 45 in response to the second bias voltage V2 applied as a voltage pulse within the first write window V th-2->1 < V2 < V th-1->2 , the hysteresis curve narrows.

[0072] Figure 2b Shows the magnetization states of the magnetic layers of the memory stack 1 in each row aligned with the corresponding layer: the initial first magnetization state (P column); when the second bias voltage V2 is applied (column P -> AP); and after the second bias voltage V2 is removed (column AP). The arrows covering the arrows representing the magnetization of FL 45 in the dashed outline schematically indicate the orientation of the offset field at FL 45.

[0073] Since the second bias voltage V2 is within the first write window and thus exceeds the second threshold voltage V th-2->1 , but is lower than the first threshold voltage V th-1->2 , VDL 61 remains in the pinned magnetization state, and thus the sign of the Y component of the offset field remains unchanged, and thus the magnetization of FL 45 modulated by the VCMA effect tilts towards the first magnetization state AP, which thus becomes the final state of FL 45 after the second bias voltage V1 is removed.

[0074] Figure 3a -b shows the switching from the second magnetization state AP to the first magnetization state P in a corresponding manner.

[0075] Figure 3a The diagram on the left is identical to Figure 2a basically. Figure 3a The central diagram shows the shift of the hysteresis curve caused by the switching of VDL 61 from the pinned equilibrium state to the unstable magnetization state, and the corresponding modulation of the offset field at FL 45, which is triggered by a first bias voltage V1 that exceeds the first threshold voltage and is applied as a voltage pulse, V1 > Vth-1->2 , triggered. The diagram on the right also shows that as a result of the VCMA effect induced in FL 45 in response to V1, the hysteresis curve narrows.

[0076] Figure 3b shows the magnetization states of the magnetic layers of the memory stack 1 in the rows aligned with the respective layers: the initial second magnetization state (column AP); when the first bias voltage V1 is applied (column AP -> P); and after the first bias voltage V1 is removed (column P). Similarly, the arrows covering the arrows representing the magnetization of FL 45 schematically indicate the orientation of the offset field at FL 45.

[0077] Since the first bias voltage V1 exceeds V th-1->2 (and thus also exceeds V th-2->1 ), VDL 61 enters the unstable magnetization state with an in-plane orientation, the sign of the Y component of the offset field is flipped, and thus the magnetization of FL 45 modulated by the VCMA effect tilts towards the second magnetization state P, thus becoming the final state of FL 45 after the first bias voltage V1 is removed.

[0078] Referring again to Figure 1 , the programming circuit of the circuit system 9 of the MRAM device 10 can apply the first and second bias voltages V1 to the memory stack 1. Thus, the programming circuit system can set FL 45 to the first magnetization state (AP) by applying a second bias voltage V2 to the memory stack 1 within the first write window V th-2->1 < V2 < Vth-1->2 . Conversely, the programming circuit system can set FL 45 to the second magnetization state by applying a first bias voltage V1 that exceeds V th-1->2 . The first bias voltage V1 and the second bias voltage V2 can be applied as respective voltage pulses. Since the memory stack 1 enables deterministic switching, the durations of the first voltage pulse V1 and the second voltage pulse V2 can be substantially equal, such that the P and AP states can be programmed in approximately the same time. For the same reason, the relative durations of the first voltage pulse V1 and the second voltage pulse V2 are not important, and thus different durations can also be used, for example, to achieve other optimization goals, such as, by way of non-limiting example, fine-tuning the write performance.

[0079] For the above-described memory stack 1 and MRMA device 10, when in the pinned magnetization state, the first direction along which the magnetization vector of the FDL 63 is oriented corresponds to the perpendicular Y direction, i.e., away from the MTJ layer structure 6. Since the orientation of the magnetization vector of the RL 43 is opposite to the first direction, the threshold voltage (i.e., the second threshold voltage V th-2->1 ) is lower than the threshold voltage for switching FL 45 from AP to P.

[0080] Figure 4a -b shows a memory stack 100 corresponding to the memory stack 1, but designed so that the magnetization vector of the VDL 61 is oriented along the negative Y direction when in the pinned magnetization state. That is, the first direction is in the negative Y direction, toward the MTJ layer structure 6. Since the orientation of the magnetization vector of the RL 43 is the same as in the memory stack 1, Figure 4a The threshold voltage (i.e., the second threshold voltage V th-2->1 ) is lower than Figure 4b The threshold voltage that switches FL 45 from P to AP is shown.

[0081] Those skilled in the art realize that the present invention is by no means limited to the above-described embodiments. On the contrary, many modifications and variations are possible within the scope of the appended claims. For example, in the above-described memory stack 1, 100 with PMA is shown. The present disclosure can also be applied to memory stacks in which IPMAs exist in the magnetic layers (HL, RL, FL, VDL, FDL). The above description applies accordingly to this configuration, with the difference that the VDL in the pinned equilibrium magnetization state has an in-plane magnetization, while the VDL in the unstable magnetization state has an out-of-plane magnetization. Therefore, the VCMA effect in the VDL will be used to modularize the offset field so that the in-plane component (e.g., the X component) of the offset field at the FL changes sign.

Claims

1. A memory stack (1) for a voltage controlled magnetic anisotropy (VCMA) magnetic random access memory (MRAM) device, the memory stack comprising: An MTJ layer structure (4), the MTJ layer structure comprising a first hard magnetic layer (41), a reference layer (43) having a magnetization state pinned by the first hard magnetic layer (41), a free layer (45) switchable between a first magnetization state having a magnetization oriented in a first direction and a second magnetization state having a magnetization oriented in a second direction opposite to the first direction, and a first barrier layer (44) interposed between the reference layer (43) and the free layer (45) and configured to induce VCMA in the free layer (45); An auxiliary magnetic layer structure (6), the auxiliary magnetic layer structure (6) comprising a second hard magnetic layer (63) and an auxiliary magnetic layer (61); as well as An interlayer structure (5), the interlayer structure (5) being inserted between the free layer (45) of the MTJ layer structure (4) and the auxiliary magnetic layer (61) of the auxiliary magnetic layer structure (6), and comprising a second barrier layer (52) and a non-magnetic spacer layer (51), the second barrier layer (52) being configured to induce VCMA in the auxiliary magnetic layer (61), the non-magnetic spacer layer (51) being inserted between the second barrier layer (52) and the free layer (45); wherein, in the absence of a bias voltage across the memory stack (1), the magnetization state of the auxiliary magnetic layer (61) is pinned by the second hard magnetic layer (63) to a pinned magnetization state oriented along the first direction; wherein, in response to a first bias voltage exceeding a first threshold voltage across the memory stack (1), a VCMA induced in the auxiliary magnetic layer (61) causes the auxiliary magnetic layer to destabilize from the pinned magnetization state and enter an unstable magnetization state; wherein the free layer (45) is arranged in a bias field generated by the memory stack (1), and wherein the auxiliary magnetic layer (61) is configured to: When the auxiliary magnetic layer (61) is in the pinned magnetization state, a first contribution is provided to the bias field so that the bias field is oriented along the first direction at the free layer (45), and When the auxiliary magnetic layer (61) is in the unstable magnetization state, providing a second contribution to the bias field so that the bias field is oriented along the second direction at the free layer (45); and The first threshold voltage exceeds a second threshold voltage for inducing VCMA-induced switching of the free layer from the second magnetization state to the first magnetization state.

2. The memory stack according to claim 1, wherein: The unstable magnetization state of the auxiliary magnetic layer corresponds to the magnetization of the auxiliary magnetic layer being oriented transversely to the first direction.

3. The memory stack according to any one of the preceding claims, characterized in that The nonmagnetic spacer layer is formed of Ta, Ir, Pt, Ru, CoFeX, CoX, FeX, or CoFeBX, where X is a nonmagnetic material such as W, Ta, or Mo.

4. The memory stack according to any one of the preceding claims, characterized in that The auxiliary magnetic layer structure further includes a spacer layer interposed between the auxiliary magnetic layer and the second hard magnetic layer and configured to provide parallel or antiparallel coupling of magnetizations of the auxiliary magnetic layer and the second hard magnetic layer.

5. The memory stack according to any one of the preceding claims, characterized in that The first hard magnetic layer, the reference layer, the free layer, the auxiliary magnetic layer, and the second hard magnetic layer are each a layer having perpendicular magnetic anisotropy, and wherein the first direction and the second direction are mutually opposite out-of-plane directions.

6. The memory stack according to any one of the preceding claims, characterized in that The VCMA coefficient of the auxiliary magnetic layer (61) is smaller than the VCMA coefficient of the free layer (45), and / or the auxiliary magnetic layer (61) has a stronger magnetic anisotropy than the free layer (45).

7. An MRAM device (10), comprising a memory stack (1100) according to any one of the preceding claims and further comprising a programming circuit (9), wherein the programming circuit (9) is configured to apply the first bias voltage to set the free layer to the second magnetization state, and to apply a second bias voltage between the first threshold voltage and the second threshold voltage to set the free layer to the first magnetization state.

8. The MRAM device according to claim 7, characterized in that: The first bias voltage and the second bias voltage are applied as respective voltage pulses of substantially equal duration.

9. A method for programming a memory stack of an MRAM device according to any one of claims 7-8, the method comprising: Setting the free layer (45) to the first magnetization state by applying a bias voltage between the first threshold voltage and the second threshold voltage to the memory stack (1); or The free layer (45) is set to the second magnetization state by applying a bias voltage exceeding the first threshold voltage to the memory stack (1).

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