Leadless semiconductor device assembly with dual-side cooling

Abstract

In a general aspect, a semiconductor device assembly (200) includes a first substrate (220) and a second substrate (210). Patterned metal layers (224, 214) included with the first substrate and the second substrate, respectively, are electrically coupled with opposite sides of a pre-molded semiconductor device module (230a), respectively. A conductive via (216) is defined through the second substrate. The conductive vias electrically couple the signal terminals of the module with another patterned metal layer (217) disposed on a surface of the second substrate opposite the first patterned metal layer.

Description

Technical Field

[0001] This specification relates to semiconductor device assemblies. More particularly, this specification relates to a leadless power semiconductor device assembly that provides bilateral cooling. Background Art

[0002] Semiconductor device assemblies (such as assemblies that include power semiconductor devices (which may be referred to as power modules, multi-chip power modules, etc.)) can be implemented using semiconductor die, substrates (e.g., direct bond metal substrates, ceramic substrates, etc.), wire bonding, etc., and include lead frames. Summary of the Invention

[0003] In general aspects, a semiconductor device assembly includes a first substrate that includes a first dielectric layer and a first patterned metal layer disposed on a surface of the first dielectric layer. The assembly further includes: a pre-molded semiconductor device module having a first side disposed on the first patterned metal layer and electrically coupled to the first patterned metal layer; and a second substrate that includes a second dielectric layer and a second patterned metal layer disposed on a first surface of the second dielectric layer. The second patterned metal layer is disposed on a second side of the pre-molded semiconductor device module that is opposite the first side and is electrically coupled to the second side. The second substrate further includes a conductive via defined through the second dielectric layer. The conductive via electrically couples a signal terminal of the pre-molded semiconductor device module to a third patterned metal layer disposed on a second surface of the second dielectric layer that is opposite the first surface.

[0004] Embodiments may singly or in combination include one or more of the following features or aspects. For example, the assembly may include at least one power terminal soldered to the first patterned metal layer. The assembly may include an output signal terminal soldered to the first patterned metal layer.

[0005] The assembly may include a plurality of conductive spacers that are: respectively coupled to the first patterned metal layer; and respectively coupled to the second patterned metal layer.

[0006] The conductive via may be a first conductive via among a plurality of conductive vias defined through the second dielectric layer. The plurality of conductive vias may electrically couple respective signal terminals of the pre-molded semiconductor device module to respective portions of the third patterned metal layer.

[0007] The pre-molded semiconductor device module may be a first pre-molded semiconductor device module. The assembly may include a second pre-molded semiconductor device module having a first side disposed on the first patterned metal layer and electrically coupled to the first patterned metal layer, and a second side disposed on the second patterned metal layer that is opposite the first side and is electrically coupled to the second patterned metal layer.

[0008] The conductive via can be a first conductive via. The second substrate can include a second conductive via that electrically couples a signal terminal of the second pre-molded semiconductor device module to a third patterned metal layer disposed on a second surface of the second dielectric layer.

[0009] The first conductive via can be included in a first plurality of conductive vias defined through the second dielectric layer. The second conductive via can be included in a second plurality of conductive vias defined through the second dielectric layer. The first plurality of conductive vias can electrically couple corresponding signal terminals of the first pre-molded semiconductor device module to corresponding portions of the third patterned metal layer. The second plurality of conductive vias can electrically couple corresponding signal terminals of the second pre-molded semiconductor device module to corresponding portions of the third patterned metal layer.

[0010] The assembly can include a molding compound that encapsulates the first pre-molded semiconductor device module, the second pre-molded semiconductor device module, and a plurality of conductive spacers respectively coupled to the first patterned metal layer and the second patterned metal layer. The molding compound can partially encapsulate the first substrate, the second substrate, an output signal terminal soldered to the first patterned metal layer, and a plurality of power source terminals respectively soldered to the first patterned metal layer.

[0011] The surface of the patterned metal layer disposed on the second surface of the second dielectric layer can be exposed by the molding compound.

[0012] The area of the surface of the first dielectric layer of the first substrate can be greater than the area of the first surface of the second dielectric layer of the second substrate.

[0013] In another general aspect, a semiconductor device assembly includes a first substrate including: a first dielectric layer; and a first patterned metal layer. The first patterned metal layer includes a first portion disposed on a surface of the first dielectric layer and a second portion extending away from the surface of the first dielectric layer. The assembly further includes a pre-molded semiconductor device module having a first side disposed on and electrically coupled to the first portion of the first patterned metal layer. The second portion of the first patterned metal layer is electrically coupled to a signal terminal of the pre-molded semiconductor device module via the first portion of the first patterned metal layer. The assembly further includes a second substrate including a second dielectric layer and a second patterned metal layer disposed on a surface of the second dielectric layer. The second patterned metal layer is disposed on a second side of the pre-molded semiconductor device module opposite the first side and is electrically coupled to the second side.

[0014] The embodiments may include, individually or in combination, one or more of the following features or aspects. For example, the component may include at least one power terminal soldered to the second patterned metal layer. The component may include an output signal terminal soldered to the second patterned metal layer.

[0015] The component may include a conductive spacer coupled to the pre-molded semiconductor device module and the second patterned metal layer.

[0016] The component may include a plurality of conductive spacers that are respectively coupled to a first portion of the first patterned metal layer and are respectively coupled to the second patterned metal layer.

[0017] A second portion of the first patterned metal layer may include a plurality of extensions that are electrically coupled to corresponding signal terminals of the pre-molded semiconductor device module.

[0018] The pre-molded semiconductor device module may be a first pre-molded semiconductor device module. The semiconductor device component may include a second pre-molded semiconductor device module having: a first side disposed on and electrically coupled to the first patterned metal layer; and a second side opposite the first side disposed on and electrically coupled to the second patterned metal layer.

[0019] A second portion of the first patterned metal layer may include a first plurality of extensions electrically coupled to corresponding signal terminals of the first pre-molded semiconductor device module and a second plurality of extensions electrically coupled to corresponding signal terminals of the second pre-molded semiconductor device module.

[0020] The component may include a molding compound that encapsulates the first pre-molded semiconductor device module, the second pre-molded semiconductor device module, and the plurality of conductive spacers respectively coupled to the first patterned metal layer and the second patterned metal layer. The molding compound may partially encapsulate the first substrate, the second substrate, the output signal terminal soldered to the second patterned metal layer, and the plurality of power source terminals respectively soldered to the second patterned metal layer.

[0021] The molding compound may encapsulate a first portion of the first patterned metal layer. The molding compound may be excluded from a second portion of the first patterned metal layer.

[0022] The area of the surface of the first dielectric layer of the first substrate may be greater than the area of the surface of the second dielectric layer of the second substrate.

[0023] In another general aspect, a method for producing a semiconductor device assembly includes: coupling at least one pre-molded semiconductor device module to a first patterned metal layer disposed on a surface of a first dielectric layer of a first substrate; and coupling an output terminal and at least one power source terminal to a second patterned metal layer disposed on a first surface of a second dielectric layer of a second substrate. The second substrate has a plurality of conductive vias disposed therethrough the second dielectric layer. The plurality of conductive vias electrically couple corresponding signal terminals of the at least one pre-molded semiconductor device module to corresponding portions of a patterned metal layer disposed on a second surface of the second dielectric layer opposite the first surface. The method further includes: coupling the second patterned metal layer to the at least one pre-molded semiconductor device module; and coupling the second patterned metal layer to the first patterned metal layer via a plurality of conductive spacers. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram schematically illustrating an example semiconductor device assembly.

[0025] Figures 2A to 2E is a diagram illustrating an example semiconductor device assembly and components of the assembly.

[0026] Figures 3A to 3D is a diagram illustrating another example semiconductor device assembly and components of the assembly.

[0027] Figure 4 is a flowchart illustrating a method for producing a semiconductor device assembly such as Figures 2A to 2D a semiconductor component.

[0028] Figure 5 is a flowchart illustrating a method for producing a semiconductor device assembly such as Figures 3A to 3D a semiconductor component.

[0029] In the drawings, which are not necessarily to scale, like reference numerals may indicate like and / or similar components (elements, structures, etc.) in different views. The drawings generally illustrate, by way of example and not limitation, various embodiments discussed in the present disclosure. Reference numerals shown in one drawing may not be repeated for the same and / or similar elements in related views. Reference numerals that are repeated in multiple figures may not be specifically discussed with respect to each of those figures, but rather provide context between related views. Additionally, not all like elements in the drawings are specifically referenced with reference numerals when illustrating multiple instances of the element. DETAILED DESCRIPTION

[0030] This disclosure relates to the implementation of electronic device assemblies (e.g., power semiconductor device assemblies such as multi-chip modules (MCMs) facilitating bilateral cooling). Such assemblies can be used, for example, in automotive applications, industrial applications, etc. For example, the embodiments described herein can implement (include) high-power semiconductor device modules such as power converters, ignition circuits, power transistor pairs, half-bridge circuits, etc. For illustrative purposes and by way of example, the disclosed embodiments of the invention are described as implementing a half-bridge circuit. In some embodiments, the methods described herein can be used to implement other circuits.

[0031] In existing embodiments, a semiconductor device assembly (assembly) with bilateral cooling can include (in addition to a plurality of semiconductor die) a plurality of substrates (such as direct bond metal (DBM) substrates) and a lead frame (e.g., a single-body lead frame including signal leads and power and / or output terminals). The DBM substrate (e.g., direct bond copper (DBC) substrate) is used, for example, in combination with a heat sink, a fluid cooling jacket, etc., to dissipate the thermal energy generated during the electrical operation of the assembly. In such embodiments, the size of the associated assembly (e.g., the size of the associated substrate) can be limited by its lead frame. In other words, the use of the lead frame can prevent or limit the reduction of the size of the corresponding assembly, such as the size (or corresponding size) of the DBM substrate included in the assembly. This limitation can in turn prevent the reduction of material costs and associated manufacturing costs.

[0032] Moreover, the tools used to produce such existing assemblies including lead frame structures can limit manufacturing throughput, e.g., can be a factor limiting the number of assemblies that can be produced within a given time period (such as the number of units per hour (uph)). In addition, the use of the lead frame can contribute to parasitic impedance associated with the overall length (in the direction of current conduction) and size of the power terminals of the lead frame structure included in the associated power semiconductor device assembly, e.g., stray inductance.

[0033] Existing embodiments can also include conductive spacers for providing interconnections between semiconductor die (e.g., bare semiconductor die) and the associated substrate (e.g., DBM substrate such as direct bond copper (DBC) substrate). Suitable materials for such spacers in existing embodiments can be limited to materials having an appropriate coefficient of thermal expansion, e.g., to prevent reliability issues associated with thermal cycling such as die cracking. For example, such materials include copper molybdenum (CuMo) or aluminum silicon carbide (AlSiC). For example, the use of such spacer materials can increase the associated product cost because they are relatively costly compared to other conductive spacer materials such as pure copper.

[0034] Compared with existing semiconductor device components, the embodiments described herein are lead-frame-free semiconductor device components facilitating bilateral cooling. That is, the exemplary embodiments described herein do not include a lead frame. Thus, such embodiments can provide a reduction in substrate size that cannot be achieved in existing embodiments. Such size reduction can in turn reduce material and overall product costs.

[0035] The embodiments described herein may be referred to as having a package-in-package configuration. That is, in an exemplary embodiment, at least one pre-molded semiconductor device module may be included in the semiconductor device component. For example, at least one pre-molded semiconductor device module may be disposed between and coupled to a first (top) DBM substrate and a second (bottom) DBM substrate, and then the first (top) DBM substrate and the second (bottom) DBM substrate may be molded using an epoxy molding compound. In the exemplary embodiments described herein, the first pre-molded semiconductor device module of the component may include one or more low-side transistors of a corresponding half-bridge circuit implemented in the component, while the second pre-molded semiconductor device module may include one or more high-side transistors of the half-bridge circuit.

[0036] Also in the exemplary embodiments described herein, power terminals (and output terminals) that are shorter (along the direction of current flow) compared to the power terminals of existing embodiments may be used. Thus, compared with existing embodiments having longer power terminals included in a single-piece lead-frame structure, the parasitic impedance (stray inductance) associated with the power terminals can be reduced in the exemplary embodiments.

[0037] Figure 1 is a block diagram schematically illustrating an exemplary semiconductor device component 100. The semiconductor device component 100 is a lead-frame-free semiconductor device component having a package-in-package arrangement. As Figure 1 shown, the semiconductor device component 100 includes a top substrate 110 and a bottom substrate 120. In this example, the indication of top and bottom is based on the arrangement in the view of Figure 1 For example, the top substrate 110 may also be referred to as the first substrate, substrate, etc. Similarly, the bottom substrate 120 may also be referred to as the second substrate, substrate, etc. In other words, in the example of Figure 1 the designation of top and bottom is for illustrative purposes.

[0038] The semiconductor device component 100 further includes pre-molded semiconductor modules 130a and 130b, e.g., encapsulated semiconductor device modules included in the package-in-package arrangement of the semiconductor device component 100. In this example, the pre-molded semiconductor module 130a may include one or more low-side transistors of a half-bridge circuit implemented by the semiconductor device component 100, while the pre-molded semiconductor module 130b may include one or more high-side transistors of the half-bridge circuit. Although Figure 1Although not specifically shown in the figure, electrical connections can be made between the pre-molded semiconductor modules 130a, the top substrate 110, the bottom substrate 120, one or more power source terminals 140, the output terminals 150, and the signal terminals 160 to implement a half-bridge circuit (or other circuit) of the semiconductor device assembly 100. That is, although not specifically shown in Figure 1 the figure, the pre-molded semiconductor modules 130a and 130b can be electrically and / or physically coupled to the top substrate 110 and / or the bottom substrate 120. For example, the top substrate 110, the bottom substrate 120, at least one conductive spacer, and the corresponding solder connections can provide electrical connections between the pre-molded semiconductor modules 130a and 130b and the substrates 110 and 120, for example, to electrically couple the low-side transistor of the pre-molded semiconductor module 130a to the high-side transistor of the pre-molded semiconductor module 130b.

[0039] As Figure 1 shown, the semiconductor device assembly 100 further includes one or more power source terminals 140 (e.g., positive power source terminal, negative or ground power source terminal, etc.), output terminals 150, and signal terminals 160. In this example, the output terminal 150 can be a terminal for an output signal (e.g., a switch node signal) of the half-bridge circuit of the semiconductor device assembly 100, and the signal terminal 160 can provide connections for the gates, source sensing, and thermal sensing of the transistors of the half-bridge circuit.

[0040] The semiconductor device assembly 100 further includes a molding compound 170, such as an epoxy molding compound, which can encapsulate portions of other elements of the semiconductor device assembly 100. For example, the molding compound 170 can encapsulate the pre-molded semiconductor modules 130a and 130b (and any conductive spacers included in the semiconductor device assembly 100). In addition, the molding compound 170 can at least partially encapsulate the top substrate 110, the bottom substrate 120, one or more power source terminals 140, the output terminals 150, and the signal terminals 160. That is, the corresponding portions of each of the top substrate 110, the bottom substrate 120, one or more power source terminals 140, and the output terminals 150 can be encapsulated in the molding compound 170, while the other corresponding portions are accessible and / or disposed outside the molding compound 170 (by being exposed, etc.). In some embodiments, the exposed portions (e.g., metal layers) of the top substrate 110 and the bottom substrate 120 can be coupled to corresponding heat dissipation devices, such as heat sinks or fluid cooling jackets, which can provide efficient bilateral cooling of the semiconductor device assembly 100 during operation.

[0041] In semiconductor device assembly 100 (and other example embodiments described herein), signal terminals 160 are implemented, for example, using the methods described below without using signal leads of a lead frame. In brief, in some embodiments, signal terminals 160 may be implemented using corresponding portions of a patterned metal layer of top substrate 110, corresponding portions of a patterned metal layer of bottom substrate 120, and / or at least one of corresponding conductive vias formed (e.g., defined as, etc.) through top substrate 110 and / or bottom substrate 120. Such methods are provided by way of example, and other methods for implementing signal terminals 160 in semiconductor device assembly 100 are possible.

[0042] In some embodiments, as noted above, semiconductor device assembly 100 may include additional elements in addition to Figure 1 the elements shown. For example, semiconductor device assembly 100 may include one or more conductive spacers for coupling (e.g., physically and / or electrically coupling) top substrate 110 to bottom substrate 120 and / or for coupling pre-molded semiconductor modules 130a and 130b to one or both of substrates 110 and 120 (e.g., physically and / or electrically coupling).

[0043] Figures 2A to 2E is a diagram illustrating example semiconductor device assembly 200 and components of the assembly. Semiconductor device assembly 200 may implement Figure 1 semiconductor device assembly 100. For example, semiconductor device assembly 200 may include a half-bridge circuit, where assembly 200 has a package-in-package configuration without a lead frame.

[0044] Referring to Figure 2A , substrate 220 (e.g., bottom substrate) is shown. Substrate 220 has a width x1 and a height y1. Substrate 220 includes a patterned metal layer 224 disposed (directly bonded to) on dielectric layer 226, which may be a ceramic base layer of a DBM substrate. Although not specifically discussed for each example substrate described herein, each substrate in the example embodiments may have an arrangement similar to substrate 220, e.g., the dielectric layer has at least a metal layer (patterned or unpatterned) disposed (directly bonded to) on a respective surface of the dielectric layer. For example, the substrate may have a first metal layer (e.g., a patterned metal layer) on a first surface and a second metal layer (e.g., patterned or unpatterned) on a second surface opposite the first surface.

[0045] In Figures 2A to 2E the example of Figure 2AAs shown, a plurality of conductive spacers 222 (conductive spacers) are coupled to the patterned metal layer 224 of the substrate 220. In some embodiments, the conductive spacers 222 can be soldered to the patterned metal layer 224. In other embodiments, the conductive spacers 222 can be brazed, sintered, etc. to the patterned metal layer 224.

[0046] As Figure 2A Further shown, pre-molded semiconductor modules 230a and pre-molded semiconductor modules 230b are also disposed on (coupled to) the patterned metal layer 224. For example, the pre-molded semiconductor modules 230a and 230b can be coupled to the patterned metal layer 224 via respective solder connections.

[0047] In this example, the pre-molded semiconductor module 230a includes Figures 2A to 2E the first low-side transistor and the second low-side transistor of the half-bridge circuit of the semiconductor device assembly. The two low-side transistors can be connected in parallel with each other in the pre-molded semiconductor module 230a, and the common drain connection (e.g., the die attach pad of the pre-molded semiconductor module 230a) is coupled to the corresponding portion of the patterned metal layer 224.

[0048] Also in this example, the pre-molded semiconductor module 230b includes Figures 2A to 2E the first high-side transistor and the second high-side transistor of the half-bridge circuit of the semiconductor device assembly. The two high-side transistors can be connected in parallel with each other in the pre-molded semiconductor module 230b, and the common drain connection (e.g., the die attach pad of the pre-molded semiconductor module 230b) is coupled to the corresponding portion of the patterned metal layer 224. The pre-molded semiconductor modules 230a and 230b also include respective source connections 232a and 232b for the low-side transistors and the high-side transistors. In addition, the pre-molded semiconductor modules 230a and 230b include respective signal connections 234a and 234b, such as for gate, source sense, and thermal sense signals corresponding to the pre-molded semiconductor modules.

[0049] Also as Figure 2AAs shown, a power terminal 240a (e.g., a negative power source or an electrical ground terminal), a power terminal 240b (e.g., a positive power source terminal), and an output signal terminal 250 (e.g., a switch node terminal) are coupled to respective portions of the patterned metal layer 224. In some embodiments, the power terminal 240a, the power terminal 240b, and the output terminal 250 can be laser welded to their respective portions of the patterned metal layer 224. In some embodiments, other attachment processes can be used, such as soldering, brazing, sintering, etc. In this example, the power terminal 240a, the power terminal 240b, and the output terminal 250 can be shorter in length (e.g., in the direction of current flow during electrical operation) than the power and output terminals of existing components implemented using a single-piece lead frame structure. Thus, compared with existing device components, lower parasitic inductance (stray inductance) can be achieved through Figures 2A to 2E example embodiments thereof.

[0050] In this example, a conductive spacer 222 is used to electrically couple and physically couple (e.g., via a solder connection) the substrate 220 to a corresponding substrate (top substrate) such as Figure 2B and Figure 2C the substrate 210 shown. Specifically, Figure 2B a first side of the substrate 210 is illustrated, which in this example is coupled to the conductive spacer 222, and Figure 2C a second side of the substrate 210 is illustrated, e.g., which can be exposed by the molding compound of the semiconductor device assembly 200. In this example, the second side of the substrate 210 is opposite to the first side of the substrate 210.

[0051] As Figure 2B shown, the substrate 210 has a width x2 and a height y2. In this example, the width x2 of the substrate 210 is less than the width x1 of the substrate 220. Also in this example, the height y2 of the substrate 210 is less than the height y1 of the substrate 220. Figures 2A to 2E The lead-frame-free arrangement of the semiconductor device assembly 200 of

[0052] Reference Figure 2B, an exemplary side of the substrate 210 includes a patterned metal layer 214. The patterned metal layer 214 may include signal terminal portions 215 that are configured to be coupled to signal connections 234a and 234b of pre-molded semiconductor modules 230a and 230b, respectively. As Figure 2B (and Figure 2C ) shown, the substrate 210 also includes a plurality of conductive vias 216 that are configured to electrically couple Figure 2B corresponding portions (e.g., signal terminal portions 215) of the patterned metal layer 214 on the side of the substrate 210 shown in Figure 2B to a signal metal portion 218 of a patterned metal layer 217 disposed on a second side of the substrate 210, e.g., as shown in

[0053] In this example, as Figure 2C illustrated, the plurality of conductive vias 216 are also coupled to the signal metal portion 218 on the second side of the substrate 210, e.g., to electrically couple the signal metal portion 218 to the corresponding signal connections 234a of the pre-molded semiconductor module 230a and the corresponding signal connections 234b of the pre-molded semiconductor module 230b. In some embodiments, the plurality of conductive vias 216 may be filled with a conductive material (e.g., copper, tungsten, copper alloy, etc.). In other embodiments, the plurality of conductive vias 216 may be inner cavities lined with a conductive material, where the plurality of conductive vias 216 are configured to receive corresponding signal pins. In this example, the patterned metal layer 217 also includes portions 219a and 219b that are illustrated as separate metal portions. In some embodiments, a heat dissipation device (e.g., a heat sink, a fluid cooling tube, etc.) may be coupled to portions 219a and 219b of the patterned metal layer 217. In some embodiments, portions 219a and 219b may be joined into a single metal layer portion. That is, a continuous metal layer portion may be used instead of the separate portions 219a and 219b.

[0054] Referring to Figure 2D , a diagram illustrating a combination of the structure of the substrate 210 and Figure 2A is shown. That is, in the Figure 2D example, the substrate 210 is coupled to a conductive spacer 222 and is coupled to pre-molded semiconductor modules 230a and 230b in the arrangement shown in Figure 2A . Similarly, in this example, the surface of the substrate 210 that is coupled to the conductive spacer 222 is the surface of the substrate 210 illustrated in Figure 2B . In this arrangement, Figure 2C the surface of the substrate 210 shown in

[0055] Figure 2Dis illustrated as a perspective view in which features inside the illustrated structure are visible to show the relative arrangement of the various elements of the illustrated components. However, to avoid obscuring the illustrated arrangement, Figure 2D is not shown in Figure 2A , Figure 2B and Figure 2C all of the features shown. For example, Figure 2C the signal metal portion 218 shown is not specifically shown in Figure 2D so as not to obscure the arrangement of the signal terminal portion 215 and the respective signal connections 234a of the pre-molded semiconductor module 230a and the respective signal connections 234b of the pre-molded semiconductor module 230b with the multiple conductive vias 216. In this example, the signal terminal portion 215 may be coupled to the respective signal connections 234a and the respective signal connections 234b using solder connections. As pointed out above, in this example, the multiple conductive vias 216 provide respective electrical connections between the signal terminal portion 215 and the signal metal portion 218, although the signal metal portion 218 is not specifically illustrated in Figure 2D .

[0056] Figure 2D also includes line 2E-2E, which corresponds to a cross-sectional view of the semiconductor device assembly 200 shown in Figure 2E . In this example, Figure 2E the view of Figure 2D illustrates the structure shown in Figure 2D after the molding operation and the curing operation to encapsulate and / or partially encapsulate the elements of the semiconductor device assembly 200, such as described herein. As Figure 2D shown, line 2E-2E is not a straight line and changes its path through the illustrated components such that line 2E-2E intersects various elements of the semiconductor device assembly 200 corresponding to the view shown in Figure 2E .

[0057] As Figure 2E shown, the substrate 210 is coupled to the conductive spacer 222 and the pre-molded semiconductor module 230a. For example, the illustrated signal terminal portion 215 is coupled to the illustrated signal connection 234a of the pre-molded semiconductor module 230a using a solder connection, for example. The conductive vias 216 then couple the signal terminal portion 215 to the respective signal metal portion 218, which is exposed through the molding compound 270 of the semiconductor device assembly 200. In addition, as Figure 2E shown, the source connection 232a of the pre-molded semiconductor module 230a is also coupled to the substrate 210 (e.g., to a portion of the patterned metal layer 214).

[0058] In this example, the pre-molded semiconductor module 230a and the conductive spacer 222 are encapsulated in the molding compound 270. In addition, the substrate 210, the substrate 220, the power terminal 240a, and the output terminal 250 are partially encapsulated in the molding compound 270. For example, the signal metal portion 218 is partially encapsulated, and for example, the surface of the signal metal portion 218 is exposed by the molding compound 270. Similarly, the surfaces of the metal layers of the substrate 210 (e.g., the patterned metal layer 217) and the substrate 220 (e.g., the metal layer 219) are exposed by the molding compound, for example, to facilitate the attachment of heat dissipation devices (e.g., heat sinks and / or fluid cooling jackets). Similar to Figure 2E the elements shown, other elements of the semiconductor device assembly 200 not shown in the Figure 2E cross-sectional view may be encapsulated or partially encapsulated in the molding compound 270.

[0059] Figures 3A to 3D FIG. is a diagram illustrating another example semiconductor device assembly 300 and components of the assembly. Similar to the semiconductor device assembly 200, the semiconductor device assembly 300 can implement Figure 1 the semiconductor device assembly 100. For example, the semiconductor device assembly 300 can include a half-bridge circuit, where the assembly 300 has a package-in-package configuration without a lead frame.

[0060] Referring to Figure 3A , a substrate 320 (e.g., a bottom substrate) is shown. The substrate 320 has a width x3 and a height y3. The substrate 320 includes a patterned metal layer 324. The patterned metal layer 324 includes a portion 324a disposed on the dielectric layer 326 of the substrate 320, and a portion 324b including a plurality of extensions that extend from being disposed on the dielectric layer 326 to being away from the dielectric layer 326 (e.g., extending away from the surface of the dielectric layer 326, extending away from the surface, etc.). In this example, the portion 324b of the patterned metal layer 324 can include corresponding signal terminal metal portions, for example, for gate, source sense, and thermal sense signals of the pre-molded semiconductor modules 330a and 330b.

[0061] In the Figures 3A to 3D example of Figure 3A shown, as Figures 3A to 3DAt least one high-side transistor of a half-bridge circuit of a semiconductor device assembly, wherein a plurality of high-side transistors may be connected in parallel with each other in a pre-molded semiconductor module 330a, and a common drain connection 335a (e.g., a die attach pad of the pre-molded semiconductor module 330a) faces out of the page. A source connection (not shown) of the pre-molded semiconductor module 330a is coupled to a portion 324a of the patterned metal layer 324, and a signal connection 334a is coupled to a corresponding portion (a patterned metal layer extension) of a portion 324b of the patterned metal layer 324. In this example, the signal connection 334a is shown in perspective view in Figure 3A and is shown in Figure 3C because they face downward in the views of Figure 3A and Figure 3C .

[0062] Also in this example, the pre-molded semiconductor module 330b includes at least one low-side transistor of a half-bridge circuit, wherein a plurality of low-side transistors may be connected in parallel with each other in the pre-molded semiconductor module 330b, and a common drain connection 335b (e.g., a die attach pad of the pre-molded semiconductor module 330b) faces out of the page. A source connection (not shown) of the pre-molded semiconductor module 330b is coupled to a portion 324a of the patterned metal layer 324, and a signal connection 334b is coupled to a corresponding portion (a patterned metal layer extension) of a portion 324b of the patterned metal layer 324. In this example, like the signal connection 334a, the signal connection 334b is shown in perspective view in Figure 3A and is shown in Figure 3C because they face downward in the views of Figure 3A and Figure 3C .

[0063] Referring to Figure 3B , a structure of a substrate 310 (e.g., a top substrate) of a semiconductor device assembly 300 including Figures 3A to 3D is shown. In this example, Figure 3B one side of the structure shown is coupled to Figure 3A the structure shown to produce the semiconductor device assembly 300. That is, in this example, Figure 3B the structure is inverted (rotated one hundred and eighty degrees) for attachment to Figure 3A the structure, such as Figure 3C shown. In this example, Figure 3B the side of the structure facing the page may, for example, have a metal layer disposed thereon. As Figure 3D shown, this metal layer may be exposed by the molding compound to facilitate attachment of a heat dissipation device.

[0064] As Figure 3BAs shown, the substrate 310 has a width x4 and a height y4. In this example, the width x3 of the substrate 310 is less than the width x3 of the substrate 320. Also in this example, the height y4 of the substrate 310 is less than the height y3 of the substrate 320. Similar to the substrates 210 and 220, Figures 3A to 3D the lead - free frame arrangement of the semiconductor device assembly 300 of Figures 3A to 3D at least partially facilitates such size reduction. That is, the size of the substrate 310 and / or the size of the substrate 320 are not restricted by the connection of the corresponding lead - frame structure. Thus, since the dimensions of the substrate 310 are smaller than the dimensions of the substrate 320 in this example, the area of the substrate 310 is less than the area of the substrate 320 (e.g., the area of the substrate 320 is greater than the area of the substrate 310). Compared with existing methods, this arrangement can reduce the material cost and, in turn, can reduce the overall product cost.

[0065] As Figure 3B shown, a plurality of conductive spacers 322 and 323 (conductive spacers) are coupled to the patterned metal layer 314 of the substrate 310. In some embodiments, the conductive spacers 322 and 323 can be welded to the patterned metal layer 314. In other embodiments, the conductive spacers 322 and 323 can be brazed, sintered, etc. to the patterned metal layer 314. In this example, the conductive spacer 322 can be coupled to a portion 324a of the patterned metal layer 324 on the substrate 320 in the corresponding semiconductor device assembly, while the conductive spacer 323 can be coupled to the common drain connections 335a and the common drain connection 335b of the pre - molded semiconductor modules 330a and 330b disposed on the substrate 320, respectively. In some embodiments, the conductive spacers 322 and 323 can be copper spacers, which can reduce the material cost compared with previous embodiments including CuMo and / or AlSiC conductive spacers.

[0066] Also as Figure 3B shown, a power terminal 340a (e.g., a positive power source terminal), a power terminal 340b (e.g., a negative power source or electrical ground terminal), and an output signal terminal 350 (e.g., a switch node terminal) are coupled to respective portions of the patterned metal layer 314. In some embodiments, the power terminal 340a, the power terminal 340b, and the output terminal 350 can be laser - welded to their respective portions of the patterned metal layer 314. In other embodiments, the power terminal 340a, the power terminal 340b, and the output terminal 350 can be attached to the substrate 310 simultaneously with the conductive spacers 322 and 323, for example, using a solder reflow process, a brazing process, or a sintering process. In this example, the power terminal 340a, the power terminal 340b, and the output terminal 350 can be shorter in length (e.g., in the direction of current flow during electrical operation) than the power supply and output terminals of existing components implemented using a single - body lead - frame structure. Thus, compared with existing device assemblies, it can be achieved byFigures 3A to 3D Example embodiments achieve a lower parasitic inductance (stray inductance).

[0067] Reference Figure 3C shows a diagram of a combination of the structure of Figure 3B and the structure of Figure 3A That is, in the example of Figure 3C , Figure 3B The conductive spacers 322 and 323 of the structure of Figure 3C are respectively coupled to a portion 324a of the patterned metal layer 324 and pre-molded semiconductor modules 330a and 330b, as

[0068] As in Figure 2D , Figure 3C is illustrated as a perspective view in which the features inside the illustrated structure are visible in order to show the relative arrangement of the various elements of the illustrated components. However, in order not to confuse the illustrated arrangement, Figure 3C not all the features shown in Figure 3A and Figure 3C are shown. For example, Figure 3C Some edges of the substrate 310 are not shown in

[0069] Figure 3C also includes a line 3D-3D that corresponds to a cross-sectional view of the semiconductor device assembly 300 shown in Figure 3D . In this example, Figure 3D The view of Figure 3C illustrates the structure shown in Figure 3C after a molding operation and a curing operation to encapsulate and / or partially encapsulate the elements of the semiconductor device assembly 300, such as described herein. As Figure 3D shown, the line 3D-3D is not a straight line and changes its path through the illustrated components such that the line 3D-3D intersects various elements of the semiconductor device assembly 300 corresponding to the view shown in

[0070] As Figure 3D shown, the substrate 320 (e.g., a portion 324a of the patterned metal layer 324) is coupled to the conductive spacer 322 and the pre-molded semiconductor module 330a via a solder connection, for example. Also as Figure 3D shown, the illustrated conductive spacer 323 is coupled to the common drain connection 335a of the pre-molded semiconductor module 330a via a solder connection, and the illustrated signal connection 334a of the pre-molded semiconductor module 330a is coupled to the corresponding signal terminal extension of the portion 324b of the patterned metal layer 324, where the portion 324b extends outside the molding compound. As Figure 3DAs shown, portion 324b may have a thickness t1, which in some embodiments may be approximately 0.3 millimeters (mm).

[0071] In addition, as Figure 3D shown, the source connection 332a of the pre-molded semiconductor module 330a is also coupled to the substrate 320 (e.g., to portion 324a of the patterned metal layer 324). In this example, the pre-molded semiconductor module 330a and the conductive spacers 322 and 323 are encapsulated in the molding compound 370. In addition, the substrate 210, the substrate 320, the power terminal 340a, the output terminal 350, and portion 324b of the patterned metal layer 324 are partially encapsulated in the molding compound 370. For example, portion 324b is partially encapsulated and also extends out of the molding compound 370. Similarly, the surfaces of the metal layer of substrate 310 (e.g., metal layer 317) and the metal layer of substrate 320 (e.g., metal layer 319) are exposed by the molding compound 370, e.g., to facilitate attachment of a heat dissipation device (e.g., a heat sink and / or a fluid cooling jacket). Similar to Figure 3D the elements shown, other elements of the semiconductor device assembly 300 not shown in the Figure 3D cross-sectional view may be similarly encapsulated or partially encapsulated in the molding compound 370.

[0072] Figure 4 is an example of a flowchart of a method 400 for manufacturing a semiconductor device assembly such as Figures 2A to 2E the semiconductor device assembly illustrated. Accordingly, method 400 will be further described with reference to Figures 2A to 2E However, in some embodiments, method 400 may be used to manufacture other semiconductor components.

[0073] Method 400 includes performing a solder printing operation at block 410 on a first substrate (e.g., (bottom) substrate 220). The solder printing operation of block 410 can set solder on substrate 220 (e.g., on patterned metal layer 224) for the attachment of pre-molded semiconductor modules 230a and 230b and / or conductive spacers 222. In some embodiments, conductive spacers 222 can be coupled to substrate 210 prior to the solder printing operation of block 410. At block 420, method 400 includes attaching pre-molded semiconductor modules 230a and 230b and / or conductive spacers 222 to the solder of the printing operation at block 410. For example, the operation at block 420 of method 400 can include using an automated placement device (e.g., a pick and place device) to set pre-molded semiconductor modules 230a and 230b and / or conductive spacers 222 on the solder applied at block 410. At block 430, method 400 includes performing a reflow operation to physically and electrically couple pre-molded semiconductor modules 230a and 230b and / or conductive spacers 222 to patterned metal layer 224 of substrate 220.

[0074] At block 440, method 400 includes coupling output terminal 250 and power terminals 240a and 240b to patterned metal layer 224 of substrate 220. As discussed above, in some embodiments, output terminal 250 and power terminals 240a and 240b can be coupled to patterned metal layer 224 using laser welding. In other embodiments, output terminal 250 and power terminals 240a and 240b can be coupled to patterned metal layer 224 using solder (e.g., as part of the operations of blocks 410, 420, and 430, where the operation of block 440 is omitted).

[0075] At block 450, method 400 includes performing a solder printing operation on a second substrate (e.g., (top) substrate 210). The solder printing of block 450 can set solder on substrate 210 (e.g., on patterned metal layer 214) for attaching substrate 210 to substrate 220, e.g., to conductive spacers 222 and pre-molded semiconductor modules 230a and 230b. At block 460, method 400 includes attaching substrate 210 to substrate 220. For example, substrate 210 can be automatically placed on substrate 220 using, e.g., an automated pick and place device, e.g., vice versa, such that patterned metal layer 214 is disposed on conductive spacers 222 and pre-molded semiconductor modules 230a and 230b, e.g., as Figure 2D and Figure 2EAs shown. At block 470, method 400 includes performing a reflow operation to physically and electrically couple substrate 220 to substrate 210. For example, coupling patterned metal layer 214 to conductive spacer 222 and pre-molded semiconductor modules 230a and 230b.

[0076] At block 480, a molding operation and a post-molding curing operation may be performed to encapsulate semiconductor device assembly 200, such as Figure 2E As shown. In this example, since semiconductor device assembly 200 is produced without using a monomeric lead frame (e.g., is lead-frame-free), trimming and shaping operations are not required. This can increase manufacturing throughput. For example, compared to methods for producing semiconductor device assemblies having a lead-frame structure, the number of assemblies produced per hour is increased.

[0077] Figure 5 is an illustration of method 500 for producing a semiconductor device assembly such as Figures 3A to 3D the semiconductor device assembly illustrated. Thus, method 500 will be further described with reference to Figures 3A to 3D However, in some embodiments, method 500 may be used to produce other semiconductor components.

[0078] Method 500 includes performing a solder printing operation on a first substrate (e.g., substrate 320) at block 510. The solder printing operation of block 510 may deposit solder on substrate 320 (e.g., on portions 324a and 324b of patterned metal layer 324) for attachment of pre-molded semiconductor modules 330a and 330b. At block 520, method 500 includes attaching pre-molded semiconductor modules 330a and 330b to the solder of the printing operation at block 510. For example, the operation at block 520 of method 500 may include using an automated placement device (e.g., a pick-and-place device) to set pre-molded semiconductor modules 330a and 330b on the solder applied by the solder printing operation of block 510. At block 530, method 500 includes performing a reflow operation to physically and electrically couple pre-molded semiconductor modules 330a and 330b to patterned metal layer 324 of substrate 320.

[0079] At block 540, method 400 includes coupling output terminal 350, power terminals 340a and 340b, conductive spacer 322, and / or a conductive spacer to patterned metal layer 314 of substrate 210. As discussed above, in some embodiments, output terminal 350 and power terminals 340a and 340b may be coupled to patterned metal layer 314 using laser welding. In other embodiments, output terminal 350 and power terminals 340a and 340b may be coupled to patterned metal layer 324 along with conductive spacer 322 and conductive spacer 322 using solder (e.g., including a solder printing operation, an attachment (placement) operation, and a reflow operation at block 540).

[0080] At block 550, method 500 includes performing a solder printing operation on a second substrate (e.g., substrate 310). The solder printing of block 550 may dispose solder on conductive spacer 322 and conductive spacer 323 for attaching substrate 210 to substrate 220, e.g., to a portion 324a of patterned metal layer 324, and to pre-molded semiconductor modules 330a and 330b. At block 560, method 500 includes attaching substrate 310 to substrate 320. For example, substrate 310 (e.g., as Figure 3B shown) may be automatically placed on substrate 220, or vice versa, using, for example, an automated pick and place device, such that conductive spacer 322 and conductive spacer 323 are respectively disposed on portion 324a of patterned metal layer 324 and are disposed onto pre-molded semiconductor modules 330a and 330b, e.g., as Figure 3C and Figure 3D shown. At block 570, method 500 includes performing a reflow operation to physically and electrically couple substrate 310 to substrate 320, e.g., coupling conductive spacer 322 and conductive spacer 323 to portion 324a of patterned metal layer 324 and to pre-molded semiconductor modules 330a and 330b, respectively.

[0081] At block 580, a molding operation and a post-molding curing operation may be performed to encapsulate semiconductor device assembly 300, such as Figure 3D shown. In this example, since semiconductor device assembly 300 is produced without using a monomeric lead frame (e.g., is lead frame-less), trimming and forming operations are not required. This may increase manufacturing throughput, e.g., increasing the number of components produced per hour compared to methods for producing semiconductor device assemblies having a lead frame structure.

[0082] It should be understood that in the foregoing description, when an element such as a layer, region, or substrate is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element can be directly on the other element, connected or coupled to the other element, or there can be one or more intervening elements. In contrast, when an element is referred to as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there are no intervening elements or layers. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements shown as being directly located on, directly connected, or directly coupled can be referred to in such a manner. The claims of the present application can be amended to recite the exemplary relationships described in the specification or shown in the drawings.

[0083] As used in this specification, unless specifically stated otherwise in context, the singular forms can include the plural forms. Except for the orientations shown in the drawings, the spatial relative terms (e.g., above, on top of, over, below, under, beneath, at the top of, at the bottom of, etc.) are intended to cover different orientations of the device during use or operation. In some embodiments, the relative terms above and below can respectively include vertically above and vertically below. In some embodiments, the term adjacent can include laterally adjacent or horizontally adjacent.

[0084] Some embodiments can be implemented using various semiconductor processing and / or packaging techniques. Some embodiments can be implemented using various types of semiconductor processing techniques associated with a semiconductor substrate, which includes but is not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0085] Although certain features of the described embodiments have been illustrated as described herein, many modifications, alternative forms, variations, and equivalent forms will now occur to those skilled in the art. For example, the features and / or aspects illustrated with respect to one embodiment can also be included and / or applied to other embodiments, where appropriate. Accordingly, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail can be made. Except for mutually exclusive combinations, any part of the apparatus and / or method described herein can be combined in any combination. The embodiments described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A semiconductor device assembly (200), comprising: A first substrate (220), the first substrate comprising: a first dielectric layer (226); and A first patterned metal layer (224), the first patterned metal layer being disposed on a surface of the first dielectric layer (226); a pre-molded semiconductor device module (230a) having a first side disposed on and electrically coupled to the first patterned metal layer (224); and A second substrate (210), the second substrate comprising: a second dielectric layer; a second patterned metal layer (214) disposed on the first surface of the second dielectric layer, the second patterned metal layer (214) disposed on a second side of the pre-molded semiconductor device module (230a) opposite to the first side and electrically coupled to the second side; and A conductive via (216) is defined through the second dielectric layer, the conductive via (216) electrically coupling a signal terminal of the pre-molded semiconductor device module (230a) with a third patterned metal layer (217), the third patterned metal layer being disposed on a second surface of the second dielectric layer opposite to the first surface.

2. The semiconductor device assembly (200) according to claim 1, further comprising: at least one power terminal (240a, 240b), the at least one power terminal being welded to the first patterned metal layer (224); and An output signal terminal (250) is welded to the first patterned metal layer (224).

3. The semiconductor device assembly (200) according to claim 1, further comprising a plurality of conductive spacers (222), wherein the plurality of conductive spacers are respectively: coupled to the first patterned metal layer (224); and Coupled to the second patterned metal layer (214).

4. The semiconductor device assembly (200) according to claim 1, wherein the conductive via (216) is a first conductive via among a plurality of conductive vias (216) defined through the second dielectric layer, and the plurality of conductive vias (216) electrically couple corresponding signal terminals of the pre-molded semiconductor device module (230a) with corresponding portions (215) of the third patterned metal layer (217).

5. The semiconductor device assembly (200) of claim 1, wherein the pre-molded semiconductor device module (230a) is a first pre-molded semiconductor device module, the semiconductor device assembly further comprising: A second pre-molded semiconductor device module (230b), the second pre-molded semiconductor device module having: A first side disposed on the first patterned metal layer (224) and electrically coupled to the first patterned metal layer; and A second side opposite to the first side is disposed on the second patterned metal layer (214) and electrically coupled to the second patterned metal layer.

6. The semiconductor device assembly (200) of claim 5, wherein the conductive via (216) is a first conductive via, The second substrate (210) also includes a second conductive via (216) that electrically couples a signal terminal of the second pre-molded semiconductor device module (230b) with the third patterned metal layer (217).

7. The semiconductor device assembly (200) according to claim 6, wherein: The first conductive via (216) is included in a first plurality of conductive vias defined through the second dielectric layer, The second conductive via (216) is included in a second plurality of conductive vias defined through the second dielectric layer, The first plurality of conductive vias electrically couple corresponding signal terminals of the first pre-molded semiconductor device module (230a) to corresponding portions (215) of the third patterned metal layer (217), and The second plurality of conductive vias electrically couple corresponding signal terminals of the second pre-molded semiconductor device module (230b) to corresponding portions (215) of the third patterned metal layer (217).

8. The semiconductor device assembly (200) according to claim 7, further comprising a molding compound (270), wherein: encapsulating the first pre-molded semiconductor device module (230a), the second pre-molded semiconductor device module (230b), and a plurality of conductive spacers (222) coupled to the first patterned metal layer (224) and the second patterned metal layer (214), respectively; and The first substrate (220), the second substrate (210), an output signal terminal (250) welded to the first patterned metal layer (224), and a plurality of power supply terminals (240a, 240b) respectively welded to the first patterned metal layer (224) are partially encapsulated.

9. The semiconductor device assembly (200) of claim 8, wherein a surface of the third patterned metal layer (217) disposed on the second surface of the second dielectric layer is exposed through the molding compound (270).

10. The semiconductor device assembly (200) of claim 1, wherein an area of ​​the surface of the first dielectric layer (226) of the first substrate (220) is greater than an area of ​​the first surface of the second dielectric layer of the second substrate (210).

11. A semiconductor device assembly (300), comprising: A first substrate (320), the first substrate comprising: a first dielectric layer (326); and A first patterned metal layer (324), the first patterned metal layer comprising: a first portion (324a) disposed on a surface of the first dielectric layer (326); and a second portion (324b) extending away from the surface of the first dielectric layer (326); A pre-molded semiconductor device module (330a), the pre-molded semiconductor device module having a first side disposed on and electrically coupled to the first portion (324a) of the first patterned metal layer (324), the second portion (324b) of the first patterned metal layer (324) being electrically coupled to a signal terminal of the pre-molded semiconductor device module (330a) via the first portion (324a) of the first patterned metal layer (324); and A second substrate (310), the second substrate comprising: a second dielectric layer; and A second patterned metal layer (314) is disposed on a surface of the second dielectric layer, the second patterned metal layer (314) is disposed on a second side of the pre-molded semiconductor device module (330a) opposite to the first side and is electrically coupled to the second side.

12. The semiconductor device assembly (300) according to claim 11, further comprising: at least one power terminal (340a, 340b), the at least one power terminal being welded to the second patterned metal layer (314); and An output signal terminal (350) is welded to the second patterned metal layer (314).

13. The semiconductor device assembly (300) of claim 11, further comprising a conductive spacer (323) coupled to the pre-molded semiconductor device module (330a) and the second patterned metal layer (314).

14. The semiconductor device assembly (330) according to claim 11, further comprising a plurality of conductive spacers (322), wherein the plurality of conductive spacers are respectively: coupled to the first portion (324a) of the first patterned metal layer (324); and Coupled to the second patterned metal layer (314).

15. The semiconductor device assembly (300) of claim 11, wherein the second portion (324b) of the first patterned metal layer (324) includes a plurality of extensions electrically coupled to corresponding signal terminals of the pre-molded semiconductor device module (330a).

16. The semiconductor device assembly (330) of claim 11, wherein the pre-molded semiconductor device module (330a) is a first pre-molded semiconductor device module, the semiconductor device assembly further comprising: A second pre-molded semiconductor device module (330b), the second pre-molded semiconductor device module having: a first side disposed on the first patterned metal layer (324) and electrically coupled to the first patterned metal layer; and A second side opposite to the first side is disposed on the second patterned metal layer (324) and electrically coupled to the second patterned metal layer.

17. The semiconductor device assembly (300) of claim 16, wherein the second portion (324b) of the first patterned metal layer (324) comprises: a first plurality of extensions electrically coupled to corresponding signal terminals of the first pre-molded semiconductor device module (330a); and A second plurality of extensions are electrically coupled to corresponding signal terminals of the second pre-molded semiconductor device module (330b).

18. The semiconductor device assembly (300) of claim 17, further comprising a molding compound (370), wherein: encapsulating the first pre-molded semiconductor device module (330a), the second pre-molded semiconductor device module (330b), and a plurality of conductive spacers (322) coupled to the first patterned metal layer (324) and the second patterned metal layer (314), respectively; and The first substrate (320), the second substrate (310), an output signal terminal (350) welded to the second patterned metal layer (324), and a plurality of power supply terminals (340a, 340b) respectively welded to the second patterned metal layer (324) are partially encapsulated.

19. The semiconductor device assembly (300) of claim 18, wherein the molding compound (370): encapsulating the first portion (324a) of the first patterned metal layer (324), and Excluded from the second portion (324b) of the first patterned metal layer (324).

20. The semiconductor device assembly (300) of claim 11, wherein an area of ​​the surface of the first dielectric layer (326) of the first substrate (320) is greater than an area of ​​the surface of the second dielectric layer of the second substrate (310).

21. A method (400) for producing a semiconductor device assembly (200), the method (400) comprising: coupling a first side of a pre-molded semiconductor device module (230a) to a first patterned metal layer (224) disposed on a surface of a first dielectric layer (226) of a first substrate (220); coupling an output terminal (250) and at least one power supply terminal (240a, 240b) to the first patterned metal layer (224); coupling a second patterned metal layer (214) disposed on a first surface of a second dielectric layer of a second substrate (210) to a second side of the pre-molded semiconductor device module (230a), the second side being opposite to the first side, The second substrate (210) has a plurality of conductive vias (216) disposed through the second dielectric layer, the plurality of conductive vias (216) electrically coupling corresponding signal terminals of the at least one pre-molded semiconductor device module (230a) with corresponding portions (215) of a third patterned metal layer (217) disposed on a second surface of the second dielectric layer opposite to the first surface; and The second patterned metal layer (214): coupled to the pre-molded semiconductor device module (230a); and The first patterned metal layer (224) is coupled via a plurality of conductive spacers (222).

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