Potential generation circuit, countercurrent prevention circuit, and method for controlling potential generation circuit

Abstract

The invention relates to a potential generation circuit. The potential generation circuit includes: a first output circuit that outputs a first signal; a second output circuit outputting a second signal; and a control circuit that controls the first output circuit and the second output circuit so as to output a signal from either the first output circuit or the second output circuit in accordance with a combination of a magnitude relationship between a potential of the first signal and a first set potential and a magnitude relationship between a potential of the second signal and a second set potential.

Description

Technical Field

[0001] The present invention relates to a potential generation circuit, an anti-backflow circuit, and a control method for a potential generation circuit. Background Art

[0002] Conventionally, a potential generation circuit capable of generating a plurality of output potentials has been known.

[0003] Regarding this, in the specification of U.S. Patent No. 7,432,614, a circuit is disclosed that includes a plurality of output nodes, a plurality of switches connected to corresponding output nodes among the plurality of output nodes, and a control circuit that controls the timing of outputting a potential from each output node by controlling the on / off (ON / OFF) of the switches.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Specification of U.S. Patent No. 7,432,614 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] However, in the technology described in the specification of U.S. Patent No. 7,432,614, when there are differences in the loads connected to a plurality of output nodes, the more the output node connected to a large load, the more time it takes for the potential of the output node to reach the set potential, and furthermore, there is a problem that the potential of the output node is likely to drop. Also, in the technology described in the specification of U.S. Patent No. 7,432,614, there is a possibility of current flowing backward from the output side to the internal side of the circuit during the generation of a plurality of potentials.

[0009] The present invention has been made in view of such problems, and an object thereof is to provide a potential generation circuit and a control method for a potential generation circuit that can generate a specified set potential in a short time.

[0010] Means for Solving the Problems

[0011] To solve the above problems, the potential generation circuit according to the first aspect of the present invention includes: a first output circuit that outputs a first signal; a second output circuit that outputs a second signal different from the first signal; and a control circuit that controls the first output circuit and the second output circuit so that a signal is output from either the first output circuit or the second output circuit according to a combination of the magnitude relationship between the potential of the first signal and a first set potential and the magnitude relationship between the potential of the second signal and a second set potential.

[0012] In addition, in the potential generation circuit according to the second aspect of the present invention, when the potential of the first signal is equal to or higher than the first set potential and the potential of the second signal is lower than the second set potential, the control circuit sets the output mode to the fixed output mode and causes the second signal to be output from the second output circuit. When the potential of the second signal is equal to or higher than the second set potential and the potential of the first signal is lower than the first set potential, the control circuit sets the output mode to the fixed output mode and causes the first signal to be output from the first output circuit.

[0013] In addition, in the potential generation circuit according to the third aspect of the present invention, when the potential of the first signal is lower than the first set potential and the potential of the second signal is lower than the second set potential, the control circuit sets the output mode to the alternating output mode and alternately switches the output of the first signal by the first output circuit and the output of the second signal by the second output circuit at regular intervals.

[0014] In addition, in the potential generation circuit according to the fourth aspect of the present invention, when the output mode is the alternating output mode, when the potential of the first signal becomes equal to or higher than the first set potential or the potential of the second signal becomes equal to or higher than the second set potential, at the timing of switching the outputs of the first output circuit and the second output circuit, the control circuit switches the output mode from the alternating output mode to the fixed output mode.

[0015] In addition, a control method for a potential generation circuit according to a fifth aspect of the present invention is a control method for a potential generation circuit having a first output circuit and a second output circuit, and includes: the potential generation circuit determines whether a combination of a magnitude relationship between the potential of a first signal and a first set potential and a magnitude relationship between the potential of a second signal and a second set potential satisfies a specified condition; when the determination is affirmative, the potential generation circuit controls the first output circuit and the second output circuit so that a signal is output from one of the first output circuit and the second output circuit; and when the determination is negative, the potential generation circuit alternately switches the output of the first signal by the first output circuit and the output of the second signal by the second output circuit at regular intervals.

[0016] Moreover, the anti-backflow circuit of the sixth invention includes: an output circuit having a source terminal, a drain terminal, a gate terminal, and a back gate terminal, which operates in a first state where a first potential is supplied to the source terminal and a second state where a second potential higher than the first potential is supplied to the source terminal, and outputs from the drain terminal the potential supplied to the source terminal based on the potential of the gate terminal; and a control circuit connected to the gate terminal, the source terminal, and the back gate terminal, which in the first state controls the potential of the gate terminal so that the output circuit stops the output, and controls the potential of the back gate terminal to be the same as that of the drain terminal, and in the second state controls the potential of the back gate terminal to be the same as that of the source terminal.

[0017] In addition, in the anti-backflow circuit of the seventh invention, the output circuit has a first short-circuit control circuit and a second short-circuit control circuit. In the first state, both ends of the first short-circuit control circuit are short-circuited. In the second state, both ends of the first short-circuit control circuit are open. One end of the first short-circuit control circuit is connected to the back gate terminal, and the other end is connected to the drain terminal. In the first state, both ends of the second short-circuit control circuit are open. In the second state, both ends of the second short-circuit control circuit are short-circuited. One end of the second short-circuit control circuit is connected to the back gate terminal, and the other end is connected to the source terminal.

[0018] Advantages of the Invention

[0019] According to the first to fifth inventions, a specified set potential can be generated in a short time. According to the sixth to eighth inventions, backflow of the current in the output circuit can be prevented. Description of the Drawings

[0020] Figure 1 FIG. is an example diagram showing a power supply circuit.

[0021] Figure 2 FIG. is an example diagram showing an example of a potential generation circuit.

[0022] Figure 3 FIG. shows an example of the structure of the output circuit together with other circuits in the potential generation circuit.

[0023] Figure 4 FIG. is an example diagram showing an example of a constant voltage circuit.

[0024] Figure 5A FIG. is an example diagram showing an example of the operation in the first mode of the potential generation circuit.

[0025] Figure 5BThis is a diagram showing an example of the operation in the second mode of the potential generation circuit.

[0026] Figure 5C This is a diagram showing an example of the operation in the third mode of the potential generation circuit.

[0027] Figure 5D This is a diagram showing an example of the operation in the fourth mode of the potential generation circuit.

[0028] Figure 5E This is a diagram showing an example of the operation in the fifth mode of the potential generation circuit.

[0029] Figure 6A This is the first example of a timing diagram showing the state of the output of the potential generation circuit.

[0030] Figure 6B This is the second example of a timing diagram showing the state of the output of the potential generation circuit.

[0031] Figure 7 This is the first example of a timing diagram showing the transition of each signal in the potential generation circuit.

[0032] Figure 8 This is the second example of a timing diagram showing the transition of each signal in the potential generation circuit.

[0033] Figure 9 This is an example of a flowchart showing the flow of a series of processes of the potential generation circuit. Detailed Embodiments

[0034] Hereinafter, embodiments of the present invention (hereinafter referred to as "the present embodiments") will be described with reference to the accompanying drawings. For ease of understanding the description, the same reference numerals are given to the same components and steps as much as possible in the respective drawings, and repeated explanations are omitted.

[0035] <Structure>

[0036] Figure 1 This is a diagram showing an example of the power supply circuit 1 of the present embodiment. The power supply circuit 1 is mounted, for example, on an electronic device such as an active electrostatic stylus that can mount a storage battery and can be supplied with power from the outside, and supplies a potential to the circuit provided in the stylus.

[0037] Specifically, the power supply circuit 1 converts the power supplied from a primary battery such as a dry battery and a secondary battery such as a lithium-ion battery, and the power supplied from an external power supply path such as an AC (alternating current) adapter and a USB (Universal Serial Bus) into power corresponding to a digital circuit, an analog circuit, and an LC oscillation circuit, respectively. Then, the power supply circuit 1 supplies the converted power to the digital circuit, the analog circuit, and the LC oscillation circuit. In addition, the power supply circuit 1 charges a rechargeable secondary battery such as a lithium-ion battery mounted with the power supplied from the outside. The power supply circuit 1 is configured to include, for example, a potential generation circuit 10, a boost circuit 20, a constant voltage circuit 30, a constant voltage circuit 60, a constant voltage circuit 70, a constant voltage circuit 80, a charging circuit 40, and a bandgap circuit 50. It should be noted that the device equipped with the power supply circuit 1 is not limited to a stylus, and any device with a circuit can be used as long as it has a circuit.

[0038] The constant voltage circuit 30 is, for example, an LDO (Low Dropout) circuit, which converts the supplied potential into a constant potential of 4.0V and outputs it. Specifically, the constant voltage circuit 30 converts the potential VIN supplied from an external power supply path such as a USB into a specified potential VDD33 based on the reference potential VREF supplied from the bandgap circuit 50. The constant voltage circuit 30 supplies the converted potential VDD33 to the power supply line W_VDD33 via the switch SW1.

[0039] The switch SW1 is, for example, a transistor, a mechanical switch, etc., and shorts or opens the circuit between the constant voltage circuit 30 and the power supply line W_VDD33 based on the operation of the constant voltage circuit 30. Specifically, when the constant voltage circuit 30 supplies the potential VDD33 to the power supply line W_VDD33, the switch SW1 shorts the circuit between the constant voltage circuit 30 and the power supply line W_VDD33. In addition, when the constant voltage circuit 30 stops supplying the potential VDD33 to the power supply line W_VDD33, the switch SW1 opens the circuit between the constant voltage circuit 30 and the power supply line W_VDD33.

[0040] The charging circuit 40 is a circuit for supplying a potential to a lithium-ion battery for charging when a lithium-ion battery is used as the storage battery of the device equipped with the power supply circuit 1. Specifically, the charging circuit 40 converts the potential VDD33 supplied from the constant voltage circuit 30 via the power supply line W_VDD33 into a potential capable of charging the lithium-ion battery based on the reference potential VREF supplied from the bandgap circuit 50. The charging circuit 40 supplies the converted potential to the lithium-ion battery via a path not shown, thereby charging the lithium-ion battery.

[0041] The boost circuit 20 is, for example, a boost DC-DC converter that boosts the supplied potential and outputs it, or directly outputs the supplied potential. Specifically, when using a dry battery as the storage battery of the device equipped with the power supply circuit 1, the boost circuit 20 boosts the potential VBAT of about 0.95V to about 1.60V supplied from the dry battery to about 2.1V based on the reference potential VREF supplied from the bandgap circuit 50, and supplies the boosted potential as the potential VDD33 to the power supply line W_VDD33. In addition, when using a lithium-ion battery as the storage battery of the device equipped with the power supply circuit 1, the boost circuit 20 supplies the potential VBAT of about 2.80V to about 4.40V supplied from the lithium-ion battery directly as the potential VDD33 to the power supply line W_VDD33 without boosting.

[0042] The bandgap circuit 50 is a reference for operating each circuit provided in the power supply circuit 1, generates a reference potential VREF that is always constant regardless of temperature, power supply voltage, manufacturing process characteristics, etc., and supplies the generated reference potential VREF to each circuit. Specifically, the bandgap circuit 50 uses the potential VDD33 supplied from the constant voltage circuit 30 or the boost circuit 20 via the power supply line W_VDD33 as a power source, generates the reference potential VREF, and supplies the generated reference potential VREF to each circuit.

[0043] The potential generation circuit 10 is a DC-DC converter capable of generating multiple potentials. Based on the reference potential VREF output from the bandgap circuit 50, it generates a potential VDDD of about 1.4V, a potential VDD2 of about 2.1V, and a potential VR1 based on the potential VDD2 according to the potential VDD33 supplied from the power supply line W_VDD33. The potential generation circuit 10 supplies the generated potential VDDD to each digital circuit in the power supply circuit 1. In addition, the potential generation circuit 10 supplies the generated potential VDD2 to the constant voltage circuits 70 and 80. In addition, the potential generation circuit 10 supplies the generated potential VR1 to the constant voltage circuit 60.

[0044] The constant voltage circuit 60 is, for example, an LDO circuit that converts the supplied potential into a specified potential and outputs it. Specifically, the constant voltage circuit 60 compares the magnitude of the reference potential VREF supplied from the bandgap circuit 50 with the potential VR1 supplied from the potential generation circuit 10. When the potential of the reference potential VREF is equal to or higher than the potential of the potential VR1, the constant voltage circuit 60 generates a potential VDDD of 1.35V to 1.40V according to the potential VDD33 supplied via the power supply line W_VDD33. Then, the constant voltage circuit 30 supplies the generated potential VDDD to each digital circuit in the power supply circuit 1. In addition, when the potential of the reference potential VREF is less than the potential of the potential VR1, the constant voltage circuit 60 stops generating and outputting the potential VDDD.

[0045] The constant voltage circuits 70 and 80 are, for example, LDO circuits that convert the supplied potential into a specified potential and output it. Specifically, based on the reference potential VREF supplied from the bandgap circuit 50, the constant voltage circuit 70 converts the potential VDD2 supplied from the potential generation circuit 10 into a potential VDDA of approximately 1.85 V. The constant voltage circuit 70 supplies the converted potential VDDA to each analog circuit in the power supply circuit 1. In addition, based on the reference potential VREF supplied from the bandgap circuit 50, the constant voltage circuit 80 converts the potential VDD2 supplied from the potential generation circuit 10 into a potential VDDLC of approximately 1.74 V to 2.055 V. The constant voltage circuit 80 supplies the converted potential VDDLC to each LC oscillation circuit in the power supply circuit 1.

[0046] As described above, the operations of the respective circuits in the power supply circuit 1 have been explained. Next, the structure of the potential generation circuit 10 will be described. Figure 2 This is a diagram showing an example of the potential generation circuit 10. As Figure 2 shown, the potential generation circuit 10 is configured to include a control circuit 11, output circuits 12 to 14, amplifier circuits AMP1 to AMP4, buffer circuits BUF1 and BUF2, transistors TR1 to TR3, variable resistors R1 to R4, a constant voltage source V1, and a constant current source I1. In addition, an inductor element L1 having an inductance of about 22 μH is connected between terminals pA and pB of the potential generation circuit 10 via a signal line. It should be noted that a load capacitor C1 is connected to the terminal po1 of the potential generation circuit 10 as a load capacitor of a circuit, electrical component, etc. connected to the subsequent stage. In addition, a load capacitor C2 is connected to the terminal po2 of the potential generation circuit 10 as a load capacitor of a circuit, electrical component, etc. connected to the subsequent stage.

[0047] The amplifier circuits AMP1 and AMP2 are, for example, comparators that determine whether the potential input to the non-inverting input terminal + is equal to or higher than the potential input to the inverting input terminal -, and send the determination result to the control circuit 11. Specifically, under the control of the control circuit 11, the amplifier circuit AMP1 determines whether the reference potential VREF input to the non-inverting input terminal + via the terminal pi2 from the bandgap circuit 50 is equal to or higher than the potential VR2 that is the divided potential of the variable resistors R3 and R4 input to the inverting input terminal -. The amplifier circuit AMP1 sends the determination result to the control circuit 11. In addition, under the control of the control circuit 11, the amplifier circuit AMP2 determines whether the reference potential VREF input to the non-inverting input terminal + via the terminal pi2 from the bandgap circuit 50 is equal to or higher than the potential VR1 that is the divided potential of the variable resistors R1 and R2 input to the inverting input terminal -. The amplifier circuit AMP2 sends the determination result to the control circuit 11.

[0048] The control circuit 11 sends signals to the buffer circuits BUF1 and BUF2, and outputs the potential VA through the DC-DC converter formed by the buffer circuits BUF1 and BUF2 and the transistors TR1 and TR2, or stops the output of the potential VA.

[0049] In addition, the control circuit 11 causes the power supply circuit 1 to operate in any one of the first mode to the fifth mode. In the fourth mode, the control circuit 11 controls the output circuits 12 and 13 in such a way that a signal is output from either the output circuit 12 or 13, based on the combination of the magnitude relationship between the potential of the first signal SDDD output from the output circuit 12 and a predetermined first set potential, and the magnitude relationship between the potential of the second signal SDD2 output from the output circuit 13 and a predetermined second set potential. The control circuit 11 determines the magnitude relationship between the first signal SDDD and the first set potential based on the state of the output from the amplifier circuit AMP1. In addition, the control circuit 11 determines the magnitude relationship between the second signal SDD2 and the second set potential based on the state of the output from the amplifier circuit AMP2. It should be noted that the operation of the potential generation circuit 10 in each operation mode will be described later with reference to Figures 5A to 5E and thus its description is omitted here.

[0050] The buffer circuits BUF1 and BUF2 are, for example, buffer circuits configured to include MOS-FETs (metal-oxide-semiconductor field-effect transistors), and enhance the input signal while maintaining the logic state, and output the enhanced signal. Specifically, the buffer circuit BUF1 enhances the signal input from the control circuit 11 while maintaining the logic state, and outputs the enhanced signal to the gate terminal of the transistor TR1. In addition, the buffer circuit BUF2 enhances the signal input from the control circuit 11 with respect to the buffer circuit BUF2 while maintaining the logic state, and outputs the enhanced signal to the gate terminal of the transistor TR2.

[0051] The transistors TR1 and TR3 are, for example, P-type MOS-FETs. The transistors TR1 and TR3 supply the potential supplied to the source terminal to the drain terminal or stop the supply according to the signal input to the gate terminal. Specifically, when the state of the signal input to the gate terminal is in the low state, the transistors TR1 and TR3 supply the potential supplied to the source terminal to the drain terminal. On the other hand, when the potential of the signal input to the gate terminal is in the high state, the supply is stopped.

[0052] The gate terminal of transistor TR1 is connected to the output terminal of buffer circuit BUF1. The source terminal is connected to power supply line W_VDD33 via terminal pi1. The drain terminal is connected to one end of inductor element L1 via node no and terminal pA.

[0053] The gate terminal of transistor TR3 is connected to the output terminal for transistor TR3 of control circuit 11. The source terminal is connected to power supply line W_VDD33 via terminal pi1. The drain terminal is connected to the positive terminal of constant current source I1 and the inverting input terminal - of amplifier circuit AMP4.

[0054] Transistor TR2 is, for example, an N-type MOS-FET. Transistor TR2 draws out charge from the drain terminal toward the source terminal or stops the drawing out in accordance with the signal input to the gate terminal. Specifically, when the state of the signal input to the gate terminal is high, transistor TR2 draws out charge from the drain terminal toward the source terminal. On the other hand, when the state of the signal input to the gate terminal is low, the drawing out is stopped. The gate terminal of transistor TR2 is connected to the output terminal of buffer circuit BUF2. The source terminal is connected to ground line W_GND. The drain terminal is connected to one end of inductor element L1 via node no and terminal pA.

[0055] It should be noted that buffer circuits BUF1 and BUF2 and transistors TR1 and TR2 function as a DC-DC converter. Under the control of control circuit 11, this DC-DC converter generates potential VA by alternately switching between conduction and non-conduction between the drain terminal and the source terminal of transistors TR1 and TR2, and supplies the generated potential VA to node no. Specifically, during the period when the drain terminal and the source terminal of transistor TR1 are conducting and the drain terminal and the source terminal of transistor TR2 are non-conducting, potential VDD33 is supplied from power supply line W_VDD33 to node no via transistor TR1. In addition, during the period when the drain terminal and the source terminal of transistor TR1 are non-conducting and the drain terminal and the source terminal of transistor TR2 are conducting, potential is drawn out from node no to ground line W_GND via transistor TR2.

[0056] Constant voltage source V1 is a voltage source that generates a voltage such that the potential difference between the positive terminal and the negative terminal becomes a prescribed DC voltage and supplies the generated DC voltage. The positive terminal of constant voltage source V1 is connected to the non-inverting input terminal + of amplifier circuit AMP3. The negative terminal is connected to node no.

[0057] The constant current source I1 generates a direct current in a manner that a specified direct current flows from the positive terminal to the negative terminal under the control of the control circuit 11, and supplies the generated direct current. The positive terminal of the constant current source I1 is connected to the inverting input terminal - of the amplifier circuit AMP4 and the drain terminal of the transistor TR3, and the negative terminal is connected to the ground wire W_GND.

[0058] The amplifier circuit AMP3 is, for example, a comparator that performs a zero-crossing detection to detect the timing when the potential input to the non-inverting input terminal + exceeds or is lower than the ground potential GND input to the inverting input terminal -. Specifically, the amplifier circuit AMP3 determines, under the control of the control circuit 11, whether the potential input to the non-inverting input terminal + from the constant voltage source V1 is equal to or higher than the ground potential GND of the ground wire W_GND input to the inverting input terminal -. The amplifier circuit AMP3 sends the determination result to the control circuit 11.

[0059] The amplifier circuit AMP4 is, for example, a comparator that performs a peak current detection to detect the timing when the current flowing through the current path connected to the non-inverting input terminal + becomes equal to or higher than a specified current flowing through the current path connected to the inverting input terminal -. Specifically, the amplifier circuit AMP4 determines, under the control of the control circuit 11, whether the potential VA input to the non-inverting input terminal + from the drain terminals of the transistors TR1 and TR2 is equal to or higher than the potential of the drain terminal of the transistor TR3 and the positive terminal of the constant current source I1 input to the inverting input terminal -. The amplifier circuit AMP4 sends the determination result to the control circuit 11.

[0060] Based on the control of the control circuit 11, the output circuit 12 outputs the potential VB supplied from the terminal pB as the first signal SDDD or stops the output. It should be noted that the output circuit 12 operates in any one of the operation modes of the LDO mode, the DC-DC mode, and the standby mode. The details of the operation of the output circuit 12 in each operation mode will be described later with reference to Figures 5A - 5E and are thus omitted here.

[0061] Based on the control of the control circuit 11, the output circuit 13 outputs the potential VB supplied from the terminal pB as the second signal SDD2 or stops the output. The details of the operation of the output circuit 13 will be described later with reference to Figures 5A - 5E and are thus omitted here.

[0062] Based on the control of the control circuit 11, the output circuit 14 outputs the potential VDD33 supplied from the power supply line W_VDD33 as the second signal SDD2 or stops the output. It should be noted that the output circuit 14 operates in any one of the operation modes of current limit mode, through mode, DC-DC mode, and standby mode. Regarding the details of the operation of the output circuit 14 in each operation mode, refer to Figures 5A - 5E for description later, so the description thereof is omitted here.

[0063] The variable resistors R1 to R4 are resistor elements whose resistance values at both ends can be changed. The variable resistors R1 to R4 change their resistance values under the control of the control circuit 11.

[0064] The variable resistors R1 and R2 function as a voltage dividing circuit. The variable resistors R1 and R2 divide the potential VDDD output from the output circuit 12 using the resistance values of the variable resistors R1 and R2, output the divided potential VR1 to the inverting input terminal - of the amplifier circuit AMP2, and output the potential VR1 to the constant voltage circuit 60 via the terminal po3. One end of the variable resistor R1 is connected to the output terminal of the output circuit 12 and the terminal po1, and the other end is connected to one end of the variable resistor R2, the inverting input terminal - of the amplifier circuit AMP2, and the terminal po3. One end of the variable resistor R2 is connected to the other end of the variable resistor R1, the inverting input terminal - of the amplifier circuit AMP2, and the terminal po3, and the other end is connected to the ground wire W_GND.

[0065] The variable resistors R3 and R4 function as a voltage dividing circuit. The variable resistors R3 and R4 divide the potential VDD2 output from the output circuit 13 or 14 using the resistance values of the variable resistors R3 and R4, and output the divided potential VR2 to the inverting input terminal - of the amplifier circuit AMP1. One end of the variable resistor R3 is connected to the output terminal of the output circuit 13, the output terminal of the output circuit 14, and the terminal po2, and the other end is connected to one end of the variable resistor R4 and the inverting input terminal - of the amplifier circuit AMP1. One end of the variable resistor R4 is connected to the other end of the variable resistor R3 and the inverting input terminal - of the amplifier circuit AMP1, and the other end is connected to the ground wire W_GND.

[0066] Next, the structures of the output circuits 12 to 14 in the potential generation circuit 10 will be described. Figure 3 is a diagram showing an example of the structures of the output circuits 12 to 14 together with other circuits in the potential generation circuit 10. As Figure 3 shown, the control circuit 11 is configured to include, for example, an output control circuit 111 and a voltage control circuit 112.

[0067] The output control circuit 111 controls the output circuits 12 to 14 and the switch SW10. Specifically, the output control circuit 111 sends control signals CT121, CT122, CT124, and CT126 to the output circuit 12 to control the operation of the output circuit 12. In addition, the output control circuit 111 sends control signals CT131 and CT132 to the output circuit 13 to control the operation of the output circuit 13. In addition, the output control circuit 111 sends control signals CT142 to CT144 to the output circuit 14 to control the operation of the output circuit 14. In addition, the output control circuit 111 transmits an instruction to the voltage control circuit 112 to output the potential VA or stop the output.

[0068] The voltage control circuit 112 sends signals to the buffer circuits BUF1 and BUF2 of the DC-DC converter in accordance with the instruction transmitted from the output control circuit 111 so that the DC-DC converter formed by the buffer circuits BUF1 and BUF2 and the transistors TR1 and TR2 outputs the potential VA or stops the output.

[0069] The output circuit 12 is configured to include, for example, transistors TR121 to 127 and a buffer circuit BUF121. In addition, the output circuit 12 and the control circuit 11 together form an anti-backflow circuit 15.

[0070] The buffer circuit BUF121 is, for example, a buffer circuit configured to include MOS-FETs, enhances the signal while maintaining the logic state for the input signal, and outputs the enhanced signal. Specifically, the buffer circuit BUF121 enhances the control signal CT121 sent from the output control circuit 111 while maintaining the logic state, and outputs the enhanced signal to the gate terminal of the transistor TR121 and the source terminal of the transistor TR122.

[0071] The transistors TR121 to TR127, TR131 to TR133, TR141 to TR143, TR145, and TR146 are, for example, P-type MOS-FETs. The transistors TR121 to TR127, TR131 to TR133, TR141 to TR143, TR145, and TR146 supply the potential supplied to the source terminal to the drain terminal or stop the supply according to the signal input to the gate terminal. Specifically, the transistors TR121 to TR127, TR131 to TR133, TR141 to TR143, TR145, and TR146 supply the potential supplied to the source terminal to the drain terminal when the state of the signal input to the gate terminal is in the low state. On the other hand, when the potential of the signal input to the gate terminal is in the high state, the supply is stopped. It should be noted that the back gate terminals of the transistors TR122 to TR127, TR131 to TR133, TR141 to TR143, TR145, and TR146 other than the transistor TR121 are connected to the source terminal.

[0072] The gate terminal of the transistor TR121 is connected to the output terminal of the buffer circuit BUF121 and the source terminal of the transistor TR122. The source terminal is connected to the other end of the inductor element L1 via the terminal pB, and is also connected to the source terminal of the transistor TR124, the drain terminal of the transistor TR131, and one end of the switch SW10. In addition, the drain terminal of the transistor TR121 is connected to one end of the load capacitor C1 via the terminal po1, and is also connected to the source terminals of the transistors TR123 and TR127. The back gate terminal is connected to the source terminals of the transistors TR124 and TR126.

[0073] The gate terminal of the transistor TR122 is input with the control signal CT122 sent from the output control circuit 111. In addition, the source terminal of the transistor TR122 is connected to the gate terminal of the transistor TR121 and the output terminal of the buffer circuit BUF121, and the drain terminal is connected to the drain terminal of the transistor TR123.

[0074] The gate terminal of the transistor TR123 is input with the control signal CT122 sent from the output control circuit 111. In addition, the source terminal of the transistor TR123 is connected to one end of the load capacitor C1 via the terminal po1, and is also connected to the drain terminal of the transistor TR121 and the source terminal of the transistor TR127. The drain terminal is connected to the drain terminal of the transistor TR122.

[0075] The gate terminal of transistor TR124 is input with the control signal CT124 sent from the output control circuit 111. In addition, the source terminal of transistor TR124 is connected to the other end of the inductance element L1 via terminal pB, and is connected to the source terminal of transistor TR121, the drain terminal of transistor TR131, and one end of switch SW10. In addition, the drain terminal of transistor TR124 is connected to the drain terminal of transistor TR125. It should be noted that transistor TR124 and transistor TR125 together form the first short-circuit control circuit.

[0076] The gate terminal of transistor TR125 is input with the control signal CT124 sent from the output control circuit 111. In addition, the source terminal of transistor TR125 is connected to the back gate terminal of transistor TR121 and the source terminal of transistor TR126, and the drain terminal is connected to the drain terminal of transistor TR124. It should be noted that transistor TR125 and transistor TR124 together form the first short-circuit control circuit.

[0077] The gate terminal of transistor TR126 is input with the control signal CT126 sent from the output control circuit 111. In addition, the source terminal of transistor TR126 is connected to the back gate terminal of transistor TR121 and the source terminal of transistor TR125, and the drain terminal is connected to the drain terminal of transistor TR127. It should be noted that transistor TR126 and transistor TR127 together form the second short-circuit control circuit.

[0078] The gate terminal of transistor TR127 is input with the control signal CT126 sent from the output control circuit 111. In addition, the source terminal of transistor TR127 is connected to one end of the load capacitor C1 via terminal po1, and is connected to the drain terminal of transistor TR121 and the source terminal of transistor TR123, and the drain terminal is connected to the drain terminal of transistor TR126. It should be noted that transistor TR127 and transistor TR126 together form the second short-circuit control circuit.

[0079] The output circuit 13 is configured to include transistors TR131 to 133 and a buffer circuit BUF131, for example.

[0080] The buffer circuit BUF131 is a buffer circuit configured to include MOS-FETs, for example, and enhances the signal while maintaining the logic state of the input signal, and outputs the enhanced signal. Specifically, the buffer circuit BUF131 enhances the control signal CT131 sent from the output control circuit 111 while maintaining the logic state, and outputs the enhanced signal to the gate terminal of transistor TR131 and the source terminal of transistor TR132.

[0081] The gate terminal of transistor TR131 is connected to the output terminal of buffer circuit BUF131 and the source terminal of transistor TR132. In addition, the source terminal of transistor TR131 is connected to one end of load capacitor C2 via terminal po2, and is also connected to the source terminals of transistors TR133, TR141, and TR146. In addition, the drain terminal of transistor TR131 is connected to the other end of inductance element L1 via terminal pB, and is also connected to the source terminals of transistors TR121 and TR124 and one end of switch SW10.

[0082] The gate terminal of transistor TR132 is input with control signal CT132 sent from output control circuit 111. In addition, the source terminal of transistor TR132 is connected to the output terminal of buffer circuit BUF131 and the gate terminal of transistor TR131. In addition, the drain terminal of transistor TR132 is connected to the drain terminal of transistor TR133.

[0083] The gate terminal of transistor TR133 is input with control signal CT132 sent from output control circuit 111. In addition, the source terminal of transistor TR133 is connected to one end of load capacitor C2 via terminal po2, and is also connected to the source terminals of transistors TR131, TR141, and TR146. In addition, the drain terminal of transistor TR133 is connected to the drain terminal of transistor TR132.

[0084] Output circuit 14 is configured to include transistors TR141 to TR146, for example.

[0085] The gate terminal of transistor TR141 is connected to the source terminals of transistors TR144 and TR145. In addition, the source terminal of transistor TR141 is connected to one end of load capacitor C2 via terminal po2, and is also connected to the source terminals of transistors TR131, TR133, and TR146. In addition, the drain terminal of transistor TR141 is connected to the drain terminals of transistors TR142 and TR143.

[0086] The gate terminal of transistor TR142 is input with control signal CT142 sent from output control circuit 111. In addition, the source terminal of transistor TR142 is connected to power supply line W_VDD33 via terminal pi1, and is also connected to the source terminals of transistors TR1 and TR143. In addition, the drain terminal of transistor TR142 is connected to the drain terminals of transistors TR141 and TR143.

[0087] The gate terminal of transistor TR143 is input with the control signal CT143 sent from the output control circuit 111. Further, the source terminal of transistor TR143 is connected to the power supply line W_VDD33 via the terminal pi1 and is connected to the source terminals of transistors TR1 and TR142. Further, the drain terminal of transistor TR143 is connected to the drain terminals of transistors TR141 and TR142.

[0088] Transistor TR144 is, for example, an N-type MOS-FET. Transistor TR144 draws out charge from the drain terminal toward the source terminal or stops the drawing out in accordance with the signal input to the gate terminal. Specifically, when the state of the signal input to the gate terminal is high, transistor TR144 draws out charge from the drain terminal toward the source terminal, while when the state of the signal input to the gate terminal is low, the drawing out is stopped. Specifically, the gate terminal of transistor TR144 is input with the control signal CT144 sent from the output control circuit 111. Further, the source terminal of transistor TR144 is connected to the source terminal of transistor TR145 and the gate terminal of TR141. Further, the drain terminal of transistor TR144 is connected to the ground line W_GND.

[0089] The gate terminal of transistor TR145 is input with the control signal CT144 sent from the output control circuit 111. Further, the source terminal of transistor TR145 is connected to the source terminal of transistor TR144 and the gate terminal of TR141. Further, the drain terminal of transistor TR145 is connected to the drain terminal of transistor TR146.

[0090] The gate terminal of transistor TR146 is input with the control signal CT144 sent from the output control circuit 111. Further, the source terminal of transistor TR146 is connected to one end of the load capacitor C2 via the terminal po2 and is connected to the source terminals of transistors TR131, TR133, and TR144. Further, the drain terminal of transistor TR146 is connected to the drain terminal of transistor TR145.

[0091] Next, the structure of the constant voltage circuit 60 will be described. Figure 4 is a diagram showing an example of the constant voltage circuit 60. As Figure 4 shown, the constant voltage circuit 60 is configured to include, for example, an amplifier circuit AMP60 and a transistor TR60.

[0092] The amplifier circuit AMP60 is, for example, a comparator that determines whether the potential input to the non-inverting input terminal + is equal to or higher than the potential input to the inverting input terminal -, and outputs the determination result to the transistor TR60. Specifically, the amplifier circuit AMP60 determines whether the potential VR1 input to the non-inverting input terminal + from the potential generation circuit 10 is equal to or higher than the reference potential VREF input to the inverting input terminal - from the bandgap circuit 50. When the determination result is a positive determination, the amplifier circuit AMP60 outputs a high-state signal to the gate terminal of the transistor TR60. On the other hand, when the determination result is a negative determination, the amplifier circuit AMP60 outputs a low-state signal to the gate terminal of the transistor TR60.

[0093] The transistor TR60 is, for example, a P-type MOS-FET. The transistor TR60 makes the source terminal and the drain terminal conductive or non-conductive according to the potential input to the gate terminal. Specifically, when the state of the signal input to the gate terminal is in the low state, the transistor TR60 makes the source terminal and the drain terminal conductive. On the other hand, when the potential of the signal input to the gate terminal is in the high state, the transistor TR60 makes the source terminal and the drain terminal non-conductive. It should be noted that when the source terminal and the drain terminal of the transistor TR60 are conductive, a potential that has been decreased by the potential difference according to the source-drain resistance is supplied from the drain terminal with respect to the potential supplied to the source terminal.

[0094] The gate terminal of the transistor TR60 is connected to the output terminal of the amplifier circuit AMP60, the source terminal is connected to the power supply line W_VDD33, and the drain terminal is connected to the power supply line W_VDDD.

[0095] <Flow of a series of operations>

[0096] As described above, the structure of the power supply circuit 1 has been described. Next, the operations in each mode of the power supply circuit 1 will be described in detail. The output circuit 12 in the power supply circuit 1 operates in any one of the LDO mode, the DC-DC mode, and the standby mode. In addition, the output circuit 14 in the power supply circuit 1 operates in any one of the current limit mode, the through mode, the DC-DC mode, and the standby mode.

[0097] Moreover, the power supply circuit 1 switches its operation according to whether a dry battery or a lithium ion battery is mounted as a storage battery in the device on which the power supply circuit 1 is mounted. A case where a dry battery mode is mounted in the device on which the power supply circuit 1 is mounted will be described. After the power supply circuit 1 is started, the output circuit 12 first operates in the LDO mode, and then operates in the DC-DC mode. In addition, after the power supply circuit 1 is started, the output circuit 14 first operates in the current limit mode, and then operates in the through mode. In addition, when the device on which the power supply circuit 1 is mounted is in a sleep state or the like, the output circuits 12 to 14 operate in the standby mode.

[0098] A case where a lithium ion battery is mounted as a storage battery in the device on which the power supply circuit 1 is mounted will be described. After the power supply circuit 1 is started, the output circuit 12 first operates in the LDO mode, and then operates in the DC-DC mode. In addition, after the power supply circuit 1 is started, the output circuit 14 operates in the current limit mode for a specified time, and then operates in the through mode while the output circuit 12 operates in the LDO mode. In addition, when the output circuit 12 switches its operation mode from the LDO mode to the DC-DC mode, the power supply circuit 1 switches the operation mode of the output circuit 14 from the through mode to the DC-DC mode, and causes the output circuit 14 to operate in the DC-DC mode. In addition, when the device on which the power supply circuit 1 is mounted is in a sleep state or the like, the output circuits 12 to 14 operate in the standby mode.

[0099] The operation of each circuit in the power supply circuit 1 in the case where a dry battery is mounted as a storage battery in the device on which the power supply circuit 1 is mounted and the power supply circuit 1 operates in the first mode in which the output circuit 12 operates in the LDO mode will be described. Figure 5A This is a diagram showing an example of the operation of the potential generation circuit 10 in the first mode. Note that, in the present embodiment, a state in which the source terminal and the drain terminal of a transistor are conducting is referred to as an ON state, and a state in which the source terminal and the drain terminal of a transistor are non-conducting is referred to as an OFF state. In the first mode, the voltage control circuit 112 in the control circuit 11 controls the operation of the DC-DC converter formed by the transistors TR1 and TR2 and the buffer circuits BUF1 and BUF2 so as to stop the generation of the potential VA. In addition, the output control circuit 111 changes the potential of the terminal pB to the ground potential GND by performing short-circuit control on the switch SW10.

[0100] In the first mode, the output control circuit 111 in the control circuit 11 sends a control signal CT121 to the buffer circuit BUF121 in such a way that the state of the signal output from the buffer circuit BUF121 becomes a high-impedance state. In addition, the output control circuit 111 sends a control signal CT122 in a low state to the gate terminals of the transistors TR122 and TR123, setting the transistors TR122 and TR123 to an on state. In addition, the output control circuit 111 sends a control signal CT126 in a low state to the gate terminals of the transistors TR126 and TR127, setting the transistors TR126 and TR127 to an on state. In addition, the output control circuit 111 sends a control signal CT124 in a high state to the gate terminals of the transistors TR124 and TR125, setting the transistors TR124 and TR125 to an off state.

[0101] In the first mode, along with the states set for the transistors TR122 to TR127, the transistor TR121 supplies the gate terminal with the potential VDDD from the constant voltage circuit 60 via the on-state transistors TR122 and TR123 and the terminal po1. In addition, in the first mode, the transistor TR121 supplies the source terminal with the ground potential GND via the switch SW10. In addition, in the first mode, the transistor TR121 supplies the drain terminal with the potential VDDD from the constant voltage circuit 60 via the terminal po1. Furthermore, the transistor TR121 supplies the back gate terminal with the potential VDDD from the constant voltage circuit 60 via the on-state transistors TR126 and TR127 and the terminal po1.

[0102] In the first mode, the transistor TR121 becomes an off state along with the states of the transistors TR122 to TR127. In addition, in the first mode, the back gate terminal of the transistor TR121 is connected to the drain terminal via the transistors TR126 and TR127, thereby forming a parasitic diode from the source terminal via the back gate terminal toward the drain terminal. In the first mode, the transistor TR121 conducts with respect to the direction from the source terminal toward the drain terminal side, while it does not conduct with respect to the direction from the drain terminal toward the source terminal.

[0103] Thus, in the first mode, the anti-backflow circuit 15 including the output circuit 12 and the control circuit 11 becomes a first state in which the ground potential GND is supplied to the source terminal.

[0104] In the first state, for the anti-backflow circuit 15, although the parasitic diode conducts in the direction from the input side of the output circuit 12 towards the output side, since the potential of the terminal po1 as the output side is higher than the potential of the terminal pB as the input side, current is prevented from flowing from the input side of the output circuit 12 to the output side. Additionally, in the first state, for the anti-backflow circuit 15, since the parasitic diode does not conduct in the direction from the output side of the output circuit 12 towards the input side, current is prevented from flowing back from the output side to the input side.

[0105] In the first mode, the output control circuit 111 in the control circuit 11 sends a control signal CT131 to the buffer circuit BUF131 in such a way that the state of the signal output from the buffer circuit BUF131 becomes a high impedance state. Additionally, the output control circuit 111 sends a control signal CT132 in a low state to the gate terminals of the transistors TR132 and TR133, setting the transistors TR132 and TR133 to an on state.

[0106] In the first mode, the gate terminal of the transistor TR131 is supplied with the potential VDD2 from the output circuit 14 via the on-state transistors TR132 and TR133. Additionally, in the first mode, the source terminal of the transistor TR131 is supplied with the potential VDD2 from the output circuit 14. Additionally, in the first mode, the drain terminal of the transistor TR131 is supplied with the ground potential GND via the switch SW10.

[0107] In the first mode, the transistor TR131 becomes an off state along with the states of the transistors TR132 and TR133. Additionally, the back-gate terminal of the transistor TR131 is connected to the source terminal, thus forming a parasitic diode from the drain terminal towards the source terminal via the back-gate terminal. The transistor TR131 conducts with respect to the direction from the drain terminal towards the source terminal, while it does not conduct with respect to the direction from the source terminal towards the drain terminal.

[0108] As a result, in the first mode, for the output circuit 13, although the parasitic diode conducts in the direction from the input side towards the output side, since the potential of the terminal po2 as the output side is higher than the potential of the terminal pB as the input side, current is prevented from flowing from the input side of the output circuit 13 to the output side. Additionally, in the first mode, for the output circuit 13, the parasitic diode does not conduct with respect to the direction from the output side towards the input side, so current is prevented from flowing back from the output side to the input side.

[0109] In the first mode, the output control circuit 111 in the control circuit 11 sends a control signal CT144 in a high state to the gate terminals of the transistors TR144 to TR146, sets the transistor TR144 to the on state, and sets the transistors TR145 and TR146 to the off state. In the first mode, along with the states set for the transistors TR144 to TR146, the gate terminal of the transistor TR141 is supplied with the ground potential GND via the on-state transistor TR144 and the ground wire W_GND, and becomes the on state. It should be noted that the transistor TR146 is connected to the source terminal through the back gate terminal, and in the first mode, it prevents current from flowing in the direction from the source terminal to the drain terminal.

[0110] In addition, when the power supply circuit 1 is in the first mode and the output circuit 14 is in the current limit mode, the output control circuit 111 sends a control signal CT142 in a high state to the gate terminal of the transistor TR142 and sets the transistor TR142 to the off state. In addition, when the power supply circuit 1 is in the first mode and the output circuit 14 is in the current limit mode, the output control circuit 111 sends a control signal CT143 in a low state to the gate terminal of the transistor TR143 and sets the transistor TR143 to the on state.

[0111] Along with this, when the power supply circuit 1 is in the first mode and the output circuit 14 is in the current limit mode, the output circuit 14 outputs the potential VDD2 from the power supply line W_VDD33 via the on-state transistors TR143 and TR141 in a manner substantially the same as the potential VDD33 of the power supply line W_VDD33. For the output circuit 14, since the on-resistance of the transistor TR143 is larger than that of the transistor TR142, in the current limit mode, the output current is made smaller than in the case of operating in the through mode, and the potential VDD2 is output to the terminal po2.

[0112] In addition, when the power supply circuit 1 is in the first mode and the output circuit 14 is in the through mode, the output control circuit 111 sends a control signal CT142 in a low state to the gate terminal of the transistor TR142 and sets the transistor TR142 to the on state. In addition, when the power supply circuit 1 is in the first mode and the output circuit 14 is in the through mode, the output control circuit 111 sends a control signal CT143 in a high state to the gate terminal of the transistor TR143 and sets the transistor TR143 to the off state.

[0113] Concurrently, when the power supply circuit 1 is in the first mode and the output circuit 14 is in the through mode, the output circuit 14 outputs a potential VDD2 from the power supply line W_VDD33 via the turned-on transistors TR142 and TR141 in a manner substantially the same as the potential VDD33 of the power supply line W_VDD33. For the output circuit 14, since the on-resistance of the transistor TR142 is smaller than the on-resistance of the transistor TR143, in the through mode, the output current is more than that in the case of operating in the current limit mode, and the potential VDD2 is output to the terminal po2.

[0114] The operation of each circuit in the power supply circuit 1 will be described when a dry battery is mounted as a storage battery in a device equipped with the power supply circuit 1 and the power supply circuit 1 operates in the second mode in which the output circuit 12 operates in the DC-DC mode. Figure 5B This is a diagram showing an example of the operation of the potential generation circuit 10 in the second mode. In the second mode, the voltage control circuit 112 in the control circuit 11 controls the operation of the DC-DC converter formed by the transistors TR1 and TR2 and the buffer circuits BUF1 and BUF2 to generate the potential VA. In addition, the output control circuit 111 opens the switch SW10 to disconnect the terminal pB from the ground wire W_GND.

[0115] In the second mode, the output control circuit 111 in the control circuit 11 sends a control signal CT121 to the buffer circuit BUF121 to make the state of the signal output from the buffer circuit BUF121 a low state. In addition, the output control circuit 111 sends a high-state control signal CT122 to the gate terminals of the transistors TR122 and TR123 to set the transistors TR122 and TR123 to the off state. In addition, the output control circuit 111 sends a high-state control signal CT126 to the gate terminals of the transistors TR126 and TR127 to set the transistors TR126 and TR127 to the off state. In addition, the output control circuit 111 sends a low-state control signal CT124 to the gate terminals of the transistors TR124 and TR125 to set the transistors TR124 and TR125 to the on state.

[0116] In the second mode, along with the set states of transistors TR122 to TR127, a low-state signal is input from buffer circuit BUF121 to the gate terminal of transistor TR121, making it in the on state. Also, in the second mode, output circuit 12 supplies potential VB to the source terminal of transistor TR121 via terminal pB, and outputs a first signal SDDD from the drain terminal of transistor TR121 such that potential VDDD becomes a first set potential (e.g., 1.4 V). Thus, in the second mode, anti-backflow circuit 15 including control circuit 11 and output circuit 12 becomes a second state in which potential VB is supplied to the source terminal. In the second state, for anti-backflow circuit 15, the back-gate terminal of transistor TR121 is connected to the source terminal via transistors TR124 and TR125, thereby forming a parasitic diode from the drain terminal in transistor TR121 via the back-gate terminal toward the source terminal.

[0117] In the second mode, output control circuit 111 in control circuit 11 sends control signal CT131 to buffer circuit BUF131 in such a way that the state of the signal output from buffer circuit BUF131 becomes high. Also, output control circuit 111 sends a high-state control signal CT132 to the gate terminals of transistors TR132 and TR133, setting transistors TR132 and TR133 to the off state.

[0118] In the second mode, a high-state signal is input to the gate terminal of transistor TR131 from buffer circuit BUF131. Also, in the second mode, potential VDD2 is supplied to the source terminal of transistor TR131 from output circuit 14. Also, in the second mode, the potential of terminal pB is supplied to the drain terminal of transistor TR131.

[0119] In the second mode, transistor TR131 becomes in the off state along with the states of transistors TR132 and TR133. Also, the back-gate terminal of transistor TR131 is connected to the source terminal, thus forming a parasitic diode from the drain terminal via the back-gate terminal toward the source terminal. Transistor TR131 conducts in the direction from the drain terminal toward the source terminal, while it does not conduct in the direction from the source terminal toward the drain terminal.

[0120] Thus, in the second mode, for output circuit 13, although the parasitic diode conducts in the direction from the input side toward the output side, since the potential of terminal po2 as the output side is higher than the potential of terminal pB as the input side, current flowing from the input side of output circuit 13 to the output side is prevented. Also, in the second mode, for output circuit 13, the parasitic diode does not conduct in the direction from the output side toward the input side, thus preventing current from flowing backward from the output side to the input side.

[0121] In the second mode, the output control circuit 111 in the control circuit 11 sends a control signal CT144 in a high state to the gate terminals of the transistors TR144 to TR146, sets the transistor TR144 to an on state, and sets the transistors TR145 and TR146 to an off state. In addition, the output control circuit 111 sends a control signal CT142 in a low state to the gate terminal of the transistor TR142, and sets the transistor TR142 to an on state. In addition, the output control circuit 111 sends a control signal CT143 in a high state to the gate terminal of the transistor TR143, and sets the transistor TR143 to an off state. Along with this, in the second mode, the output circuit 14 outputs the second signal SDD2 from the power supply line W_VDD33 via the on-state transistors TR142 and TR141 such that the potential VDD2 is substantially the same as the potential VDD33 of the power supply line W_VDD33. It should be noted that the transistor TR146 is connected to the source terminal through the back gate terminal, and in the second mode, it prevents current from flowing in the direction from the source terminal to the drain terminal.

[0122] The operation of each circuit in the power supply circuit 1 when the device equipped with the power supply circuit 1 is equipped with a lithium-ion battery as a storage battery and the power supply circuit 1 operates in the LDO mode in the third mode will be described. Figure 5C It is a diagram showing an example of the operation of the potential generation circuit 10 in the third mode. In the third mode, the voltage control circuit 112 in the control circuit 11 controls the operation of the DC-DC converter formed by the transistors TR1 and TR2 and the buffer circuits BUF1 and BUF2 so as to generate the potential VA. In addition, the output control circuit 111 opens the switch SW10 to disconnect the terminal pB from the ground wire W_GND.

[0123] In the third mode, the output control circuit 111 in the control circuit 11 sends a control signal CT121 to the buffer circuit BUF121 so that the state of the signal output from the buffer circuit BUF121 becomes a high state. In addition, the output control circuit 111 sends a control signal CT122 in a high state to the gate terminals of the transistors TR122 and TR123, and sets the transistors TR122 and TR123 to an off state. In addition, the output control circuit 111 sends a control signal CT126 in a high state to the gate terminals of the transistors TR126 and TR127, and sets the transistors TR126 and TR127 to an off state. In addition, the output control circuit 111 sends a control signal CT124 in a low state to the gate terminals of the transistors TR124 and TR125, and sets the transistors TR124 and TR125 to an on state.

[0124] In the third mode, along with the states set for transistors TR122 to TR127, a high-state signal is input to the gate terminal of transistor TR121 from buffer circuit BUF121. Further, in the third mode, the source terminal of transistor TR121 is supplied with potential VB via terminal pB. Additionally, in the third mode, the drain terminal of transistor TR121 is supplied with potential VDDD from constant voltage circuit 60 via terminal po1. Furthermore, the back-gate terminal of transistor TR121 is supplied with potential VB via the turned-on transistors TR124 and TR125 and terminal pB.

[0125] In the third mode, transistor TR121 becomes in an off state along with the states of transistors TR122 to TR127. Additionally, in the third mode, the back-gate terminal of transistor TR121 is connected to the source terminal via transistors TR124 and TR125, thereby forming a parasitic diode from the drain terminal via the back-gate terminal toward the source terminal. In the third mode, transistor TR121 conducts in the direction from the drain terminal toward the source terminal side, while it does not conduct in the direction from the source terminal toward the drain terminal.

[0126] Accordingly, in the third mode, the anti-backflow circuit 15 including the control circuit 11 and the output circuit 12 becomes the second state in which potential VB is supplied to the source terminal. In the second state of the third mode, for the anti-backflow circuit 15, although the parasitic diode conducts in the direction from the output side of the output circuit 12 toward the input side, since the potential of terminal pB as the input side is higher than the potential of terminal po1 as the output side, current flowing from the output side of the output circuit 12 to the input side is prevented. Additionally, in the second state of the third mode, for the anti-backflow circuit 15, since the parasitic diode does not conduct in the direction from the input side of the output circuit 12 toward the output side, backflow of current from the input side to the output side is prevented.

[0127] In the third mode, the output control circuit 111 in the control circuit 11 sends control signal CT131 to buffer circuit BUF131 in such a manner that the state of the signal output from buffer circuit BUF131 becomes high. Additionally, the output control circuit 111 sends a high-state control signal CT132 to the gate terminals of transistors TR132 and TR133, setting transistors TR132 and TR133 in an off state. It should be noted that since the operation of the output circuit 13 in the third mode is the same as that in the second mode, its description is omitted.

[0128] In the third mode, the output control circuit 111 in the control circuit 11 sends a control signal CT144 in a high state to the gate terminals of transistors TR144 to TR146, sets transistor TR144 to an on state, and sets transistors TR145 and TR146 to off states.

[0129] In addition, when the power supply circuit 1 is in the third mode and the output circuit 14 is in the current limit mode, the output control circuit 111 sends a control signal CT142 in a high state to the gate terminal of transistor TR142, setting transistor TR142 to an off state. In addition, when the power supply circuit 1 is in the third mode and the output circuit 14 is in the current limit mode, the output control circuit 111 sends a control signal CT143 in a low state to the gate terminal of transistor TR143, setting transistor TR143 to an on state.

[0130] In addition, when the power supply circuit 1 is in the third mode and the output circuit 14 is in the through mode, the output control circuit 111 sends a control signal CT142 in a low state to the gate terminal of transistor TR142, setting transistor TR142 to an on state. In addition, when the power supply circuit 1 is in the third mode and the output circuit 14 is in the through mode, the output control circuit 111 sends a control signal CT143 in a low state to the gate terminal of transistor TR143, setting transistor TR143 to an off state. It should be noted that transistor TR146 is connected to the source terminal through the back gate terminal, and in the first mode, it prevents current from flowing in the direction from the source terminal to the drain terminal. In addition, regarding the operation of the output circuit 14 in the third mode, since it is the same as in the first mode, its description is omitted.

[0131] The operation of each circuit in the power supply circuit 1 when the power supply circuit 1 mounted in a device is operating in the fourth mode with a lithium-ion battery mounted as a storage battery and the output circuit 12 operating in the DC-DC mode will be described. Figure 5D This is a diagram showing an example of the operation of the potential generation circuit 10 in the fourth mode. In the fourth mode, the voltage control circuit 112 in the control circuit 11 controls the operation of the DC-DC converter formed by transistors TR1 and TR2 and buffer circuits BUF1 and BUF2 to generate potential VA. In addition, the output control circuit 111 opens the switch SW10 to disconnect the terminal pB from the ground wire W_GND.

[0132] In the fourth mode, the output control circuit 111 in the control circuit 11 sends a control signal CT121 to the buffer circuit BUF121 in such a manner that the state of the signal output from the buffer circuit BUF121 becomes a low state. In addition, the output control circuit 111 sends a control signal CT122 in a high state to the gate terminals of the transistors TR122 and TR123, setting the transistors TR122 and TR123 to an off state. In addition, the output control circuit 111 sends a control signal CT126 in a high state to the gate terminals of the transistors TR126 and TR127, setting the transistors TR126 and TR127 to an off state. In addition, the output control circuit 111 sends a control signal CT124 in a low state to the gate terminals of the transistors TR124 and TR125, setting the transistors TR124 and TR125 to an on state. It should be noted that the states of the transistor TR121, the output circuit 12, and the anti-backflow circuit 15 in the fourth mode are the same as those in the second mode, so their descriptions are omitted.

[0133] In the fourth mode, the output control circuit 111 in the control circuit 11 sends a control signal CT131 to the buffer circuit BUF131 in such a manner that the state of the signal output from the buffer circuit BUF131 becomes a low state. In addition, the output control circuit 111 sends a control signal CT132 in a high state to the gate terminals of the transistors TR132 and TR133, setting the transistors TR132 and TR133 to an off state.

[0134] In the fourth mode, a signal in a low state is input from the buffer circuit BUF131 to the gate terminal of the transistor TR131, making it an on state. In addition, in the fourth mode, the output circuit 13 supplies the potential VB of the terminal pB to the drain terminal of the transistor TR131, and a second signal SDD2 with a potential of VDD2 is output from the source terminal of the transistor TR131 via the terminal po2.

[0135] In the fourth mode, the output control circuit 111 in the control circuit 11 sends a control signal CT144 in a low state to the gate terminals of the transistors TR144 to TR146, setting the transistor TR144 to an off state and setting the transistors TR145 and TR146 to an on state. In addition, the output control circuit 111 sends a control signal CT142 in a high state to the gate terminal of the transistor TR142, setting the transistor TR142 to an off state. In addition, the output control circuit 111 sends a control signal CT143 in a high state to the gate terminal of the transistor TR143, setting the transistor TR143 to an off state. It should be noted that the transistors TR142 to TR144 are connected to the source terminal through the back gate terminal, and in the fourth mode, current flow in the direction from the source terminal to the drain terminal is prevented.

[0136] In the fourth mode, the gate terminal of transistor TR141 is supplied with the potential VDD from terminal po2 via transistors TR145 and TR146 in the on state. In the fourth mode, when the potential of VDD2 is lower than the potential of the drain terminal of transistor TR141, transistor TR141 becomes in the on state. In the fourth mode and when transistor TR141 is in the on state, since the conduction direction of the parasitic diode is from the drain terminal towards the source terminal, transistors TR142 and TR143 prevent current from flowing from power supply line W_VDD33 via transistor TR141 in the on state towards terminal po2.

[0137] In addition, in the fourth mode, when the potential of VDD2 is higher than the potential of the drain terminal of transistor TR141, transistor TR141 becomes in the off state. In the fourth mode and when transistor TR141 is in the off state, since the conduction direction of the parasitic diode is from the drain terminal towards the source terminal, transistor TR141 prevents current from flowing from terminal po2 via the parasitic diodes of transistors TR142 and TR143 towards power supply line W_VDD33.

[0138] The operations of the respective circuits in the power supply circuit 1 when the power supply circuit 1 operates in the fifth mode in which the output circuits 12 to 14 in the power supply circuit 1 operate in the standby mode will be described. Figure 5E This is a diagram showing an example of the operation of the potential generation circuit 10 in the fifth mode. In the fifth mode, the voltage control circuit 112 in the control circuit 11 controls the operation of the DC-DC converter formed by transistors TR1 and TR2 and buffer circuits BUF1 and BUF2 so as to stop the generation of potential VA. In addition, the output control circuit 111 changes the potential of terminal pB to the ground potential GND which is the potential of the ground wire W_GND by performing short-circuit control on switch SW10.

[0139] In the fifth mode, the output control circuit 111 in the control circuit 11 sends a control signal CT121 to the buffer circuit BUF121 in such a way that the state of the signal output from the buffer circuit BUF121 becomes a high impedance state. In addition, the output control circuit 111 sends a control signal CT122 in a low state to the gate terminals of the transistors TR122 and TR123, setting the transistors TR122 and TR123 to the on state. In addition, the output control circuit 111 sends a control signal CT126 in a low state to the gate terminals of the transistors TR126 and TR127, setting the transistors TR126 and TR127 to the on state. In addition, the output control circuit 111 sends a control signal CT124 in a high state to the gate terminals of the transistors TR124 and TR125, setting the transistors TR124 and TR125 to the off state.

[0140] In the fifth mode, along with the states set for the transistors TR122 to TR127, the gate terminal of the transistor TR121 is supplied with the potential VDDD from the constant voltage circuit 60 via the on-state transistors TR122 and TR123 and the terminal po1. In addition, in the fifth mode, the source terminal of the transistor TR121 is supplied with the ground potential GND via the switch SW10. In addition, in the fifth mode, the drain terminal of the transistor TR121 is supplied with the potential VDDD from the constant voltage circuit 60 via the terminal po1. Furthermore, the back-gate terminal of the transistor TR121 is supplied with the potential VDDD via the on-state transistors TR126 and TR127 and the terminal po1. It should be noted that the states of the transistor TR121 and the anti-backflow circuit 15 in the fifth mode are the same as those in the first mode, so their descriptions are omitted.

[0141] In the fifth mode, the output control circuit 111 in the control circuit 11 sends a control signal CT131 to the buffer circuit BUF131 in such a way that the state of the signal output from the buffer circuit BUF131 becomes a high impedance state. In addition, the output control circuit 111 sends a control signal CT132 in a low state to the gate terminals of the transistors TR132 and TR133, setting the transistors TR132 and TR133 to the off state.

[0142] In the fifth mode, the gate terminal of the transistor TR131 is supplied with the potential VDD2 from the output circuit 14 via the on-state transistors TR132 and TR133. In addition, in the fifth mode, the source terminal of the transistor TR131 is supplied with the potential VDD2 from the terminal po2. In addition, in the fifth mode, the drain terminal of the transistor TR131 is supplied with the ground potential GND via the switch SW10. It should be noted that the operation of the output circuit 13 in the fifth mode is the same as that in the first mode, so its description is omitted.

[0143] In the fifth mode, the output control circuit 111 in the control circuit 11 sends a control signal CT144 in a low state to the gate terminals of the transistors TR144 to TR146, sets the transistor TR144 to an off state, and sets the transistors TR145 and TR146 to an on state. In addition, the output control circuit 111 sends a control signal CT142 in a high state to the gate terminal of the transistor TR142, and sets the transistor TR142 to an off state. In addition, the output control circuit 111 sends a control signal CT143 in a high state to the gate terminal of the transistor TR143, and sets the transistor TR143 to an off state.

[0144] The transistors TR142 to TR144 are connected to the source terminal through the back gate terminal. In the fifth mode, it is possible to prevent current from flowing in the direction from the source terminal to the drain terminal. In addition, the operation of the output circuit 14 in the fifth mode is the same as that in the fourth mode, and thus the description thereof is omitted.

[0145] <Flow of a series of operations>

[0146] As described above, the operation of the potential generation circuit 10 in each operation mode has been described. Next, the transition of the potential of each signal in the potential generation circuit 10 will be described in detail. Figure 6A is the first example of a timing chart showing the state of the output of the potential generation circuit 10. In addition, Figure 6B is the second example of a timing chart showing the state of the output of the potential generation circuit 10. In Figure 6A and Figure 6B the control circuit 11 sets the operation mode of the power supply circuit 1 to the fourth mode, sets the first set potential to 1.4 V, and sets the second set potential to 2.1 V. In Figure 6A the control circuit 11 sets the operation mode of the power supply circuit 1 to the fourth mode, sets the first set potential to 1.4 V, and sets the second set potential to 2.1 V.

[0147] As Figure 6A shows, in the fourth mode, when the potential VDDD output by the output circuit 12 is less than the first set potential and the potential VDD2 output by the output circuit 13 is less than the second set potential, the control circuit 11 controls the states of the control signals CT121 and CT131 so that the output circuits 12 and 13 alternately output at regular intervals.

[0148] As Figure 6BAs shown, in the fourth mode, when the potential VDDD output by the output circuit 12 is less than the first set potential and the potential VDD2 output by the output circuit 13 is equal to or higher than the second set potential, the control circuit 11 controls the states of the control signals CT121 and CT131 so as to stop the output by the output circuit 13 and output from the output circuit 12.

[0149] Note that, although not shown, in the fourth mode, when the potential VDDD output by the output circuit 12 is equal to or higher than the first set potential and the potential VDD2 output by the output circuit 13 is less than the second set potential, the control circuit 11 controls the states of the control signals CT121 and CT131 so as to stop the output by the output circuit 12 and output from the output circuit 13. Further, when the potential VDDD is equal to or higher than the first set potential and the potential VDD2 is equal to or higher than the second set potential, the control circuit 11 controls the states of the control signals CT121 and CT131 so as to output from only one of the output circuits 12 and 14.

[0150] Figure 7 is the first example of a timing chart showing the transitions of the respective signals in the potential generation circuit 10. In Figure 7 a dry battery is mounted as a storage battery in the device equipped with the power supply circuit 1, and the power supply circuit 1 operates while switching among the first mode, the second mode, and the fifth mode. Note that, in Figure 7 the first set potential is set to 1.4V. Further, in Figure 7 the second set potential is set to 2.1V.

[0151] At time t70, the control circuit 11 sets the operation mode of the power supply circuit 1 to the first mode and sets the output circuit 14 to the current limit mode. Specifically, the control circuit 11 sets the states of the control signals CT121 and CT131 to the high impedance state. Further, the control circuit 11 sets the states of the control signals CT122, CT126, CT132, CT142, and CT144 to the high state. Further, the control circuit 11 sets the states of the control signals CT124 and CT143 to the low state. The control circuit 11 outputs the respective control signals with the set states.

[0152] At time t70, the output circuit 12 operates in the LDO mode and stops the output of the potential VDDD. The terminal po1 is supplied with a potential through the constant voltage circuit 60, and thus the potential VDDD starts to transition to 1.4V, which is the first set potential.

[0153] At time t70, the output circuit 13 stops outputting the potential VDD2. In addition, the output circuit 14 operates in a current limit mode, suppresses the inrush current, and outputs the potential of the power supply line W_VDD33 to the terminal po2. The potential VDD2 of the terminal po2 starts to change to 2.1V as the second set potential.

[0154] At time t71, the control circuit 11 sets the output circuit 14 to the through mode. Specifically, the states of the control signals CT132 and CT142 are changed to the low state. In addition, the control circuit 11 changes the state of the control signal CT143 to the high state.

[0155] At time t71, the output circuit 12 operates in the LDO mode and stops outputting the potential VDDD. The terminal po1 is supplied with a potential through the constant voltage circuit 60, and the potential VDDD reaches 1.4V as the first set potential.

[0156] At time t71, the output circuit 13 stops outputting the potential VDD2. In addition, the output circuit 14 operates in the through mode and outputs the potential of the power supply line W_VDD33 to the terminal po2 in a state where a large current flows. The potential VDD2 of the terminal po2 reaches 2.1V as the second set potential.

[0157] At time t72, the control circuit 11 sets the operation mode of the power supply circuit 1 to the second mode. Specifically, the control circuit 11 sets the states of the control signals CT121, CT122, and CT142 to the low state. In addition, the control circuit 11 sets the states of the control signals CT131, CT132, CT124, CT143, and CT144 to the high state. The control circuit 11 outputs each control signal with the set state.

[0158] At time t72, the output circuit 12 operates in the DC-DC mode and outputs the potential VDDD. The terminal po1 is supplied with the potential by the output circuit 12, and the potential VDDD maintains the first set potential of 1.4V.

[0159] At time t72, the output circuit 13 stops outputting the potential VDD2. In addition, the output circuit 14 operates in the through mode and outputs the potential of the power supply line W_VDD33 to the terminal po2 in a state where a large current flows. The potential VDD2 of the terminal po2 maintains 2.1V as the second set potential.

[0160] At time t73, the control circuit 11 sets the operation mode of the power supply circuit 1 to the fifth mode. Specifically, the control circuit 11 sets the states of the control signals CT121 and CT131 to the high-impedance state. In addition, the control circuit 11 sets the states of the control signals CT122, CT142, and CT143 to the high state. In addition, the control circuit 11 sets the states of the control signals CT124, CT132, and CT144 to the low state. The control circuit 11 outputs each control signal with the set state.

[0161] At time t73, the output circuit 12 operates in the standby mode and stops the output of the potential VDDD. The supply of the potential to the terminal po1 from the output circuit 12 and the constant voltage circuit 60 is cut off, and the potential gradually decreases.

[0162] At time t73, the output circuit 13 stops the output of the potential VDD2. In addition, the output circuit 14 operates in the standby mode and stops the output of the potential VDD2 to the terminal po2. The supply of the potential VDD2 to the terminal po2 is cut off, and the potential gradually decreases.

[0163] At time t74, the control circuit 11 sets the operation mode of the power supply circuit 1 to the first mode and sets the output circuit 14 to the through mode. The operation of the control circuit 11 at time t74 is the same as that at time t71, so its description is omitted.

[0164] At time t74, the output circuit 12 operates in the LDO mode and stops the output of the potential VDDD. The terminal po1 is supplied with the potential through the constant voltage circuit 60, and the transition of the potential VDDD to 1.4 V as the first set potential starts.

[0165] At time t74, the output circuit 13 stops the output of the potential VDD2. In addition, the output circuit 14 operates in the through mode and outputs the potential of the power supply line W_VDD33 to the terminal po2 in a state where a large current flows. The potential VDD2 of the terminal po2 starts to transition to 2.1 V as the second set potential.

[0166] At time t75, the control circuit 11 sets the operation mode of the power supply circuit 1 to the second mode. The operations of the control circuit 11 and the output circuits 12 to 14 at time t75 are the same as those at time t72, so their descriptions are omitted.

[0167] Figure 8 It is the second example of the timing chart showing the transition of each signal in the potential generation circuit 10. In Figure 8 In, a lithium-ion battery is mounted as a storage battery in the device equipped with the power supply circuit 1, and the power supply circuit 1 operates while switching among the third mode, the fourth mode, and the fifth mode. It should be noted that in Figure 8Among them, the first set potential is set to 1.4V. In addition, in Figure 8 Among them, the second set potential is set to 2.1V.

[0168] At time t80, the control circuit 11 sets the operation mode of the power supply circuit 1 to the third mode and sets the output circuit 14 to the current limit mode. Specifically, the control circuit 11 sets the states of the control signals CT121, CT122, CT126, CT131, CT132, CT142, and CT144 to the high state. In addition, the control circuit 11 sets the states of the control signals CT124 and CT143 to the low state. The control circuit 11 outputs each control signal with the set state.

[0169] At time t80, the output circuit 12 operates in the LDO mode and stops the output of the potential VDDD. The terminal po1 is supplied with a potential through the constant voltage circuit 60, and the potential VDDD starts to change to 1.4V, which is the first set potential.

[0170] At time t80, the output circuit 13 stops the output of the potential VDD2. In addition, the output circuit 14 operates in the current limit mode, suppresses the inrush current, and outputs the potential of the power supply line W_VDD33 to the terminal po2. The potential VDD2 of the terminal po2 starts to change to 2.1V, which is the second set potential.

[0171] At time t81, the control circuit 11 sets the output circuit 14 to the through mode. Specifically, the control circuit 11 changes the state of the control signal CT142 to the low state. In addition, the control circuit 11 changes the state of the control signal CT143 to the high state.

[0172] At time t81, the output circuit 12 operates in the LDO mode and stops the output of the potential VDDD. The terminal po1 is supplied with a potential through the constant voltage circuit 60, and the potential VDDD reaches 1.4V, which is the first set potential.

[0173] At time t81, the output circuit 13 stops the output of the potential VDD2. In addition, the output circuit 14 operates in the through mode and outputs the potential of the power supply line W_VDD33 to the terminal po2 in a state where a large current flows. The potential VDD2 of the terminal po2 reaches 4.2V, which is the second set potential.

[0174] At time t82, the control circuit 11 sets the operation mode of the power supply circuit 1 to the fourth mode. Specifically, the control circuit 11 determines whether the potential VDDD of the terminal po1 is equal to or higher than the first set potential, and whether the potential VDD2 of the terminal po2 is equal to or higher than the second set potential. The control circuit 11 determines that the potential VDDD of the terminal po1 is equal to or higher than the first set potential and the potential VDD2 of the terminal po2 is less than the second set potential. The control circuit 11 sets the states of the control signals CT121 and CT124 to the low state, and sets the state of the control signal CT142 to the high state. The control circuit 11 outputs each control signal with the set state.

[0175] At time t82, the output circuit 12 operates in the DC-DC mode and outputs the potential VDDD. The terminal po1 is supplied with the potential by the output circuit 12, and the potential VDDD is maintained at the first set potential of 1.4V.

[0176] At time t82, the output circuit 13 stops outputting the potential VDD2 to the terminal po2. In addition, the output circuit 14 operates in the DC-DC mode and stops outputting the potential to the terminal po2. The potential VDD2 of the terminal po2 is cut off from the supply of the potentials from the output circuits 13 and 14, and the potential gradually decreases.

[0177] At time t83, the control circuit 11 sets the operation mode of the power supply circuit 1 to the fifth mode. Specifically, the control circuit 11 sets the states of the control signals CT121 and CT131 to the high impedance state. In addition, the control circuit 11 sets the state of the control signal CT124 to the high state. In addition, the control circuit 11 sets the states of the control signals CT122, CT126, and CT132 to the low state. The control circuit 11 outputs each control signal with the set state.

[0178] At time t83, the output circuit 12 operates in the standby mode and stops outputting the potential VDDD. The terminal po1 is cut off from the supply of the potentials from the output circuit 12 and the constant voltage circuit 60, and the potential gradually decreases.

[0179] At time t83, the output circuit 13 stops outputting the potential VDD2. In addition, the output circuit 14 operates in the standby mode and stops outputting the potential VDD2 to the terminal po2. The potential VDD2 of the terminal po2 is cut off from the supply of the potential, and the potential gradually decreases.

[0180] At time t84, the control circuit 11 sets the operation mode of the power supply circuit 1 to the third mode and sets the output circuit 14 to the through mode. The operation of the control circuit 11 at time t78 is the same as that at time t81, so the description thereof is omitted.

[0181] At time t84, the output circuit 12 operates in the LDO mode and stops the output of the potential VDDD. The terminal po1 is supplied with a potential through the constant voltage circuit 60, and the transition of the potential VDDD to 1.4 V as the first set potential starts.

[0182] At time t84, the output circuit 13 stops the output of the potential VDD2. In addition, the output circuit 14 operates in the through mode and outputs the potential of the power supply line W_VDD33 to the terminal po2 in a state where a large current flows. The potential VDD2 of the terminal po2 starts to transition to 2.1 V as the second set potential.

[0183] At time t85, the control circuit 11 sets the operation mode of the power supply circuit 1 to the fourth mode. Specifically, the control circuit 11 determines whether the potential VDDD of the terminal po1 is equal to or higher than the first set potential and whether the potential VDD2 of the terminal po2 is equal to or higher than the second set potential. When the potential VDDD of the terminal po1 is equal to or higher than the first set potential and the potential VDD2 of the terminal po2 is less than the second set potential, the control circuit 11 sets the state of the control signal CT121 to the high state and sets the state of the control signal CT131 to the low state. In addition, when the potential VDDD of the terminal po1 is less than the first set potential and the potential VDD2 of the terminal po2 is equal to or higher than the second set potential, the control circuit 11 sets the state of the control signal CT121 to the low state and sets the state of the control signal CT131 to the high state. At time t85, the control circuit 11 outputs each control signal with the set state. Note that after time t85, the potential VDDD of the terminal po1 is near the first set potential and the potential VDD2 of the terminal po2 is near the second set potential, so the control signals CT121 and CT131 alternate with each other.

[0184] At time t85, the output circuit 12 operates in the DC-DC mode and outputs the potential VDDD according to the state of the control signal CT121. The terminal po1 is supplied with a potential by the output circuit 12, and the potential VDDD maintains 1.4 V as the first set potential.

[0185] At time t85, the output circuit 13 outputs the potential VDD2 according to the state of the control signal CT131. In addition, the output circuit 14 operates in the DC-DC mode and stops outputting the potential to the terminal po2. The potential VDD2 of the terminal po2 is supplied with a potential through the output circuit 13, and the potential VDD2 maintains 2.1 V as the second set potential.

[0186] The transition of the potential of each signal in the potential generation circuit 10 has been described above. Next, the flow of a series of processes of the potential generation circuit 10 will be described in detail. Figure 9This is an example of a flowchart showing a series of processes of the potential generation circuit 10. In Figure 9 a device equipped with the power supply circuit 1, a lithium-ion battery is installed as a storage battery, and the power supply circuit 1 operates in the fourth mode.

[0187] (Step SP10)

[0188] The potential generation circuit 10 acquires the output potentials of terminals po1 and po2. Specifically, the potential generation circuit 10 divides the potential VDDD of terminal po1 by variable resistors R1 and R2 to obtain the divided potential VR1. In addition, the potential generation circuit 10 divides the potential VDD2 of terminal po2 by variable resistors R3 and R4 to obtain the divided potential VR2. Then, the process proceeds to the process of step SP12.

[0189] (Step SP12)

[0190] The potential generation circuit 10 determines whether the combination of the magnitude relationship between the potential VDDD and the first set potential and the magnitude relationship between the potential VDD2 and the second set potential satisfies a specified condition. Specifically, the potential generation circuit 10 determines whether the potential VDDD of terminal po1 is equal to or higher than the first set potential (e.g., 1.4 V) and the potential VDD2 of terminal po2 is less than the second set potential (e.g., 2.1 V), or whether the potential VDDD of terminal po1 is less than the first set potential and the potential VDD2 of terminal po2 is equal to or higher than the second set potential. Moreover, when this determination is an affirmative determination, the process proceeds to the process of step SP14, and when this determination is a negative determination, the process proceeds to the process of step SP16.

[0191] (Step SP14)

[0192] The potential generation circuit 10 switches the output mode to the fixed output mode in such a way that a potential is output only from the output circuit that outputs a potential lower than a set potential. Specifically, in the fixed output mode, when the potential VDDD at the terminal po1 is less than the first set potential and the potential VDD2 at the terminal po2 is equal to or higher than the second set potential, the potential generation circuit 10 outputs the potential VDDD from the output circuit 12 and stops the output of the potential VDD2 from the output circuit 13. Further, in the fixed output mode, when the potential VDDD at the terminal po1 is equal to or higher than the first set potential and the potential VDD2 at the terminal po2 is less than the second set potential, the potential generation circuit 10 stops the output of the potential VDDD from the output circuit 12 and outputs the potential VDD2 from the output circuit 13. It should be noted that when the potential VDDD becomes equal to or higher than the first set potential or the potential VDD2 becomes equal to or higher than the second set potential, the potential generation circuit 10 switches the output mode from the alternate output mode to the fixed output mode at the timing of switching the outputs of the output circuits 12 and 13. Then, the process proceeds to the process of step SP18.

[0193] (Step SP16)

[0194] The potential generation circuit 10 switches the output mode to the alternate output mode in such a way that potentials are alternately output from the output circuits 12 and 13 at regular intervals. Specifically, in the alternate output mode, the potential generation circuit 10 alternately outputs the potential VDDD from the output circuit 12 and the potential VDD2 from the output circuit 13 at regular intervals. Then, the process proceeds to the process of step SP18.

[0195] (Step SP18)

[0196] The potential generation circuit 10 outputs a potential from the output circuit based on the output mode. Specifically, in the fixed output mode, the potential generation circuit 10 outputs a potential from one of the output circuits 12 and 13 and stops the output of the potential from the other. Further, in the alternate output mode, the potential generation circuit 10 outputs a potential from one of the output circuits 12 and 13 while alternately switching the outputs of the output circuits 12 and 13 at regular intervals. Then, Figure 9 the flow of the series of processes shown ends.

[0197] <Effect>

[0198] As described above, in the present embodiment, the potential generation circuit 10 includes: an output circuit 12 (first output circuit) that outputs a first signal SDDD; an output circuit 13 (second output circuit) that outputs a second signal SDD2 different from the first signal SDDD; and a control circuit 11 that controls the output circuits 12 and 13 in such a manner that a signal is output from one of the output circuits 12 and 13 according to a combination of the magnitude relationship between the potential VDDD of the first signal SDDD and a first set potential and the magnitude relationship between the potential VDD2 of the second signal SDD2 and a second set potential.

[0199] According to this configuration, the potential generation circuit 10 determines the switching of the outputs of the output circuits 12 and 13 based on the magnitude relationship of the potentials of the signals, and thus can generate a specified set potential in a short time.

[0200] In addition, in the present embodiment, when the potential VDDD of the first signal SDDD is equal to or higher than the first set potential and the potential VDD2 of the second signal SDD2 is less than the second set potential, the control circuit 11 sets the output mode to a fixed output mode and outputs the second signal SDD2 from the output circuit 13. When the potential VDD2 of the second signal SDD2 is equal to or higher than the second set potential and the potential VDDD of the first signal SDDD is less than the first set potential, the control circuit 11 sets the output mode to the fixed output mode and outputs the first signal SDDD from the output circuit 12.

[0201] According to this configuration, the potential generation circuit 10 preferentially outputs a signal from the output circuit that has not reached the set potential, and thus can generate a specified set potential with low power consumption and high efficiency (for example, a power conversion efficiency of 70.0% or more).

[0202] Further, in the present embodiment, when the potential VDDD of the first signal SDDD is less than the first set potential and the potential VDD2 of the second signal SDD2 is less than the second set potential, the control circuit 11 sets the output mode to an alternate output mode and alternately switches the output of the first signal SDDD by the output circuit 12 and the output of the second signal SDD2 by the output circuit 13 at regular intervals.

[0203] According to this configuration, since the potential generation circuit 10 alternately outputs signals from the output circuits 12 and 13 when the signals output from the output circuits 12 and 13 have not reached the set potential, it is possible to make the potentials of a plurality of signals change toward a specified set potential evenly while suppressing deviation.

[0204] In addition, in the present embodiment, when the output mode is the alternate output mode, when the potential VDDD of the first signal SDDD becomes equal to or higher than the first set potential, or when the potential VDD2 of the second signal SDD2 becomes equal to or higher than the second set potential, the control circuit 11 switches the output mode from the alternate output mode to the fixed output mode at the timing of switching the outputs of the output circuits 12 and 13.

[0205] According to this configuration, since the potential generation circuit 10 switches the output mode at the timing of switching the outputs of the output circuits 12 and 13, it is possible to suppress the generation of overcurrent accompanying the switching of the output mode.

[0206] In addition, in the present embodiment, the anti-backflow circuit 15 includes: an output circuit 12 having a source terminal, a drain terminal, a gate terminal, and a back gate terminal, which operates in a first state in which a ground potential GND (first potential) is supplied to the source terminal and a second state in which a potential VB (second potential) higher than the ground potential GND is supplied to the source terminal, and outputs the potential supplied to the source terminal from the drain terminal based on the potential of the gate terminal; and a control circuit 11 connected to the gate terminal, the source terminal, and the back gate terminal, which in the first state controls the potential of the gate terminal so that the output circuit 12 stops outputting, and controls the potential of the back gate terminal to be the same as the potential of the drain terminal, and in the second state controls the potential of the back gate terminal to be the same as the potential of the source terminal.

[0207] According to this configuration, in the anti-backflow circuit 15, when the potential of the source terminal is low, the back gate terminal is connected to the drain terminal, and when the potential of the source terminal may become high, the back gate terminal is connected to the source terminal, so that it is possible to prevent the backflow of current in the output circuit.

[0208] In addition, in the present embodiment, the output circuit 12 includes: a first short-circuit control circuit that is short-circuited at both ends in the first state and open at both ends in the second state, with one end connected to the back gate terminal and the other end connected to the drain terminal; and a second short-circuit control circuit that is open at both ends in the first state and short-circuited at both ends in the second state, with one end connected to the back gate terminal and the other end connected to the source terminal.

[0209] According to this configuration, the anti-backflow circuit 15 controls the connection destination of the back gate terminal of the output circuit 12 according to the state of the short-circuit control circuit, so that it is possible to easily control the anti-backflow of current in the output circuit 12.

[0210] --Modification example—

[0211] It should be noted that the present invention is not limited to the above-described embodiments. That is, as long as the features of the present invention are possessed, the embodiments obtained by appropriately making design changes to the above-described embodiments by those skilled in the art are also included in the scope of the present invention. In addition, the elements possessed by the above-described embodiments and the following modified examples can be combined as much as possible technically, and as long as the features of the present invention are included, the combinations thereof are also included in the scope of the present invention.

[0212] For example, in the above-described embodiment, the output circuit 14 controls the conduction and non-conduction between the gate terminal of the transistor TR142 and the terminal po2 through the transistors TR145 and TR146. However, it is not limited thereto, and the conduction and non-conduction between the gate terminal of the transistor TR142 and the terminal po2 may also be controlled only by the transistor TR146 after removing the transistor TR145.

[0213] According to this structure, the output circuit 14 can operate with a smaller number of components, so that the potential generation circuit 10 can generate a prescribed set potential at low cost and in a short time.

[0214] In addition, although in the above-described embodiment, the potential generation circuit 10 generates two potentials VDDD and VDD2 through two output circuits 12 and 13, it is not limited thereto. The potential generation circuit 10 may also generate three or more potentials through three or more output circuits. When the potential generation circuit 10 generates three or more potentials, it controls each output circuit in such a manner that a signal is output from the output circuit that outputs a potential not reaching the set potential prescribed in advance for each potential. When there are a plurality of output circuits that output signals, the potential generation circuit 10 causes these output circuits to output signals alternately at regular intervals.

[0215] According to this structure, the potential generation circuit 10 can generate three or more prescribed set potentials in a short time.

[0216] Description of Reference Numerals

[0217] 10... potential generation circuit, 11... control circuit, 12... output circuit (first output circuit), 13... output circuit (second output circuit), 15... anti-backflow circuit.

Claims

1. A potential generation circuit, comprising: A first output circuit that outputs a first signal; A second output circuit that outputs a second signal different from the first signal; and A control circuit that controls the first output circuit and the second output circuit in such a way that a signal is output from one of the first output circuit and the second output circuit according to a combination of the magnitude relationship between the potential of the first signal and a first set potential and the magnitude relationship between the potential of the second signal and a second set potential.

2. The potential generation circuit according to claim 1, wherein: When the potential of the first signal is equal to or higher than the first set potential and the potential of the second signal is less than the second set potential, the control circuit sets the output mode to a fixed output mode and causes the second signal to be output from the second output circuit. When the potential of the second signal is equal to or higher than the second set potential and the potential of the first signal is less than the first set potential, the control circuit sets the output mode to the fixed output mode and causes the first signal to be output from the first output circuit.

3. The potential generation circuit according to claim 2, wherein: When the potential of the first signal is less than the first set potential and the potential of the second signal is less than the second set potential, the control circuit sets the output mode to an alternating output mode and alternately switches the output of the first signal by the first output circuit and the output of the second signal by the second output circuit at regular intervals.

4. The potential generation circuit according to claim 3, wherein: When the output mode is the alternating output mode, when the potential of the first signal becomes equal to or higher than the first set potential or the potential of the second signal becomes equal to or higher than the second set potential, at the timing of switching the outputs of the first output circuit and the second output circuit, the control circuit switches the output mode from the alternating output mode to the fixed output mode.

5. A control method for a potential generation circuit, the potential generation circuit having a first output circuit and a second output circuit, wherein, The control method of the potential generation circuit includes: The potential generation circuit determines whether a combination of the magnitude relationship between the potential of the first signal and the first set potential and the magnitude relationship between the potential of the second signal and the second set potential satisfies a specified condition; When this determination is an affirmative determination, the potential generation circuit controls the first output circuit and the second output circuit in such a way that a signal is output from one of the first output circuit and the second output circuit; When this determination is a negative determination, the potential generation circuit alternately switches the output of the first signal by the first output circuit and the output of the second signal by the second output circuit at regular intervals.

6. A reverse current prevention circuit, comprising: An output circuit having a source terminal, a drain terminal, a gate terminal, and a back gate terminal, operating in a first state in which a first potential is supplied to the source terminal and a second state in which a second potential higher than the first potential is supplied to the source terminal, and outputting from the drain terminal a potential supplied to the source terminal based on the potential of the gate terminal; and A control circuit connected to the gate terminal, the source terminal, and the back gate terminal, controlling the potential of the gate terminal in the first state so that the output circuit stops the output, and controlling the potential of the back gate terminal to be the same as the potential of the drain terminal, and controlling the potential of the back gate terminal to be the same as the potential of the source terminal in the second state.

7. The anti-backflow circuit according to claim 6, wherein the output circuit has a first short-circuit control circuit and a second short-circuit control circuit, in the first state, both ends of the first short-circuit control circuit are short-circuited, in the second state, both ends of the first short-circuit control circuit are open, one end of the first short-circuit control circuit is connected to the back gate terminal and the other end is connected to the drain terminal, in the first state, both ends of the second short-circuit control circuit are open, in the second state, both ends of the second short-circuit control circuit are short-circuited, one end of the second short-circuit control circuit is connected to the back gate terminal and the other end is connected to the source terminal.

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