Continuous high-precision pulse width measurement method and system based on high-speed serdes

Abstract

The present invention discloses a continuous high-precision pulse width measurement method and system based on high-speed Serdes, which relates to the field of electronic measurement technology. The method includes S1, sending a matching calibration signal; S2, selecting and copying the calibration signal; S3, setting an initial delay value; S4, receiving data and performing template comparison to complete initial calibration; S5, setting the phase offset of multiple links; S6, delay adjusting the link; S7, accurately delay calibrating link data; S8, measurement accuracy analysis; S9, selecting and copying the measured signal; S10, parallel interleaved sampling and outputting sampling data; S11, calculating the pulse width value; S12, calculating the compensated pulse width value according to the compensation coefficient; the method can achieve a time resolution of ≤10ps and a maximum throughput of >300M event / s; support channel expansion to improve the interleaved sampling rate: the performance can be improved by using a delay chip with higher resolution as a delay adjustment module.

Description

Technical Field

[0001] The present invention relates to the field of electronic measurement technology, and in particular to a continuous high-precision pulse width measurement method and system based on high-speed serdes. Background Art

[0002] Many applications, such as laser ranging, particle physics experiments, and communication signal processing, place high demands on the accuracy and continuity of time measurement. Traditional time measurement methods rely primarily on time-to-digital converters (TDCs) or high-speed analog-to-digital converters (ADCs) for sampling, which have the following limitations:

[0003] 1. Commercial time-to-digital converter (TDC) chips have a limited number of channels, making it difficult to implement multi-channel parallel measurement.

[0004] 2. The sampling rate of the analog-to-digital converter (ADC) is limited by the device process and is usually less than 10GSps, resulting in insufficient time resolution.

[0005] 3. Existing interleaved sampling schemes require complex clock tree design, resulting in poor system stability.

[0006] 4. There is a dead time during continuous measurement, which makes it impossible to capture high-frequency events and continuously collect multiple pulse signals.

[0007] 5. Some implementations of delay taps using carry chains in field-programmable logic gate arrays (FPGAs) have low accuracy and difficulty in calibration due to differences in layout and routing when implementing programmable devices, making them difficult to apply in practical scenarios. Summary of the Invention

[0008] The purpose of the present invention is to design a continuous high-precision pulse width measurement method and system based on high-speed serdes in order to solve the above problems.

[0009] The present invention achieves the above-mentioned purpose through the following technical solutions:

[0010] Continuous high-precision pulse width measurement method based on high-speed serdes, including:

[0011] S1, the serial deserializer SerDes transmitter cyclically sends the feature template pattern;

[0012] S2. The selection module selects the calibration signal as the input signal, and the fan-out driver module copies the input signal to obtain signals of multiple links;

[0013] S3, multi-path interleaving calibration module adjusts and sets the initial delay value of each link , the initial delay value of each link is the same value, and the delay adjustment module adjusts the delay of the signals of multiple links according to the initial delay value of each link;

[0014] S4, the serial deserializer SerDes receiving end receives data, which is the signal after the delay of each link is adjusted. The multi-channel interleaving calibration module analyzes the received data and compares it with the characteristic template pattern to obtain the initial delay setting for the delay adjustment module receiving end of each link to stably receive data. 、 、 、… , complete the initial calibration;

[0015] S5. Set the phase offset of multiple links, where the phase offset is the sampling period Tclk / N, where N is the total number of links;

[0016] S6. The delay adjustment module adjusts the delay of each link so that the sampling points of each link are evenly distributed, obtains the unit interval UI, and determines the arrangement order of the signals of each link;

[0017] S7. Using the phase adjustment algorithm, the delay adjustment module performs accurate delay calibration of each link data according to the phase offset;

[0018] S8. Performing measurement accuracy analysis on the sampled data obtained by sampling the SerDes receiving end using a frequency offset adjustment algorithm;

[0019] S9, the selection module selects the measured signal as the input signal, and the fan-out driver module copies the input signal to obtain signals of multiple links;

[0020] S10, multiple serial deserializer (SerDes) receivers perform parallel interleaving sampling on the signals of multiple links and output sampled data, and a temperature collector collects the operating temperature of the system;

[0021] S11, a multi-parallel pulse width time measurement module extracts the pulse signal of the sampled data through an edge processing circuit and calculates the pulse width value through a parallel summing circuit;

[0022] S12. Determine a compensation coefficient at the operating temperature, and calculate a compensated pulse width value based on the compensation coefficient.

[0023] Continuous high-precision pulse width measurement system based on high-speed serdes, including:

[0024] At least two input modules; the input modules are used for inputting calibration signals or measured signals;

[0025] Selection module: The selection module is used to select a signal input by an input module;

[0026] The fan-out driver module is used to copy the input signal into signals of multiple links, and the signal output end of the selection module is connected to the signal input end of the fan-out driver module;

[0027] Multiple delay adjustment modules; one delay adjustment module is used to adjust the delay of the signal of a link,

[0028] The signal output terminals of the fan-out driving module are respectively connected to the signal input terminals of the multi-channel delay adjustment modules;

[0029] Temperature measurement module; the temperature measurement module is used to detect the temperature of the working environment of the measurement system;

[0030] FPGA chip; the signal output ends of the multiple delay adjustment modules and the signal output ends of the temperature measurement module are connected to the signal input end of the FPGA chip, the FPGA chip is provided with a serial deserializer SerDes, and the serial deserializer SerDes transmitting end is used to send a calibration signal to the input module;

[0031] Storage module; the storage module stores temperature compensation data;

[0032] FPGA chips include:

[0033] Multiple serial deserializers (SerDes); sampling the multiple parallel signals after delay conditioning to the corresponding multiple parallel serial deserializers (SerDes) receiving ends to obtain sampled data;

[0034] First-in-first-out data buffer FIFO; data buffer FIFO is used to synchronize clock processing of sampled data;

[0035] Multi-channel interleaving calibration module: The multi-channel interleaving calibration module determines the sampling phase of each channel of sampled data after synchronization based on the multi-channel interleaving algorithm, and evenly distributes the sampling clock phases of multiple SerDes receivers within a sampling period through the phase adjustment function of the SerDes receiver and the delay settings of each link. After calibration is completed, it outputs multiple parallel quantized data streams of interleaved samples.

[0036] Multi-parallel pulse width time measurement module; the multi-parallel pulse width time measurement module performs high-precision pulse width time calculation on multiple parallel quantized data streams through a pulse width retrieval circuit.

[0037] The beneficial effects of the present invention are: the method can achieve a time resolution of ≤10ps and a maximum throughput of >300M event / s; support channel expansion to improve the interleaved sampling rate: by using a delay chip with higher resolution as a delay adjustment module, the performance can be linearly improved by increasing the number of parallel Serdes; the inherent serial-to-parallel conversion structure of the serial deserializer (Serdes) is utilized to achieve seamless acquisition of continuous measurement with zero dead zone; it has a system self-calibration function, which can realize system accuracy self-calibration; it can perform multi-channel parallel operation: the selected devices and peripheral circuits are simple, the implementation volume is small, and multi-channel parallel high-precision acquisition can be performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is the architectural block diagram of a continuous high-precision pulse width measurement system based on high-speed serdes;

[0039] Figure 2 It is the hardware circuit block diagram;

[0040] Figure 3 is the calibration algorithm flow chart;

[0041] Figure 4 It is a multi-channel interleaved sampling relationship diagram;

[0042] Figure 5 It is the phase adjustment diagram of multi-channel interleaved sampling;

[0043] Figure 6 is the temperature calibration compensation graph;

[0044] Figure 7 is a schematic diagram of propagation delay;

[0045] Figure 8 It is a schematic diagram of sampling of interleaved sampling channels;

[0046] Figure 9 It is a schematic diagram of data segmentation;

[0047] Figure 10 It is a schematic diagram for measurement accuracy analysis; DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present invention. It should be understood that the described embodiments are only a portion of the embodiments of the present invention, not all of them. Generally, the components of the embodiments of the present invention described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

[0049] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0050] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0051] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. These are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0052] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, terms such as "disposed" and "connected" should be understood in a broad sense. For example, "connected" can mean a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can also mean internal communication between two components. Those skilled in the art will be able to understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0053] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0054] Continuous high-precision pulse width measurement method based on high-speed serdes, including:

[0055] S1. The serial deserializer (SerDes) transmitter cyclically sends a matching calibration signal as a characteristic template pattern. The pulse start characteristics of the characteristic template pattern satisfy the time relationship, which is expressed as: ,in is the period of the feature template pattern, It is the signal propagation delay, including the completion of data reception from the calibration signal input to the internal FPGA chip. After the input feature template pattern is synchronously sent to the FPGA chip multi-channel serial deserializer SerDes receiving end, each link receiving end can sample and align the same pulse edge to prevent the received data from deviating from the period during alignment due to a too small signal period. By controlling the pulse width of the calibration signal, the pulse width of each link receiving end can be verified to be correct.

[0056] The SerDes transmitter transmits data using a specific signature code. This signature code must have a pulse start characteristic and meet the aforementioned sampling delay requirements. The design uses 128-bit hexadecimal data: FF55AA00_00000000_00000000_00000000 as the matching code pattern. The transmitter cyclically transmits this signature code as the signature template pattern.

[0057] S2. The selection module selects the calibration signal as the input signal, controls the transmitting end of the serial deserializer (SerDes) in the FPGA chip, and sends out a pulse signal with a known period and pulse width. The fan-out driver module copies the input signal to obtain signals of multiple links.

[0058] S3, multi-path interleaving calibration module adjusts and sets the initial delay value of each link , the initial delay value of each link is the same value, and the delay adjustment module adjusts the delay of the signals of multiple links according to the initial delay value of each link; when returning from S404 to S3, the multi-path interleaving calibration module adjusts the initial delay value of each link according to the minimum adjustment step value of the delay adjustment module The adjustment range is 0~sampling period. For example, if the sampling rate of each link is 25Gsps, the adjustment range is initial value~initial value+40ps.

[0059] S4. The serial deserializer (SerDes) receiving end receives data. The received data is the signal after delay adjustment of each link. The multi-channel interleaving calibration module analyzes the received data and compares it with the characteristic template pattern to obtain the initial delay setting for the delay adjustment module receiving end of each link to stably receive data. 、 、 、… , complete the initial calibration; specifically including:

[0060] S401, a serial deserializer (SerDes) receiving end receives data;

[0061] S402, the multi-channel interleaving calibration module shifts the data under the main clock of the serial deserializer SerDes;

[0062] S403. Compare the collected data under each data master clock. If a rising edge appears, determine whether the 128-bit received data starting from the current beat is consistent with the feature template pattern. If they are consistent, the match is successful, output the matching success status of each link, and enter S405; otherwise, set m=m+1 and enter S404; where m is a positive integer;

[0063] S404, determine whether m is greater than the preset number of cycles, if so, return to S3; otherwise, shift the data by bitslip and return to S401; the preset number of cycles is 128 times;

[0064] S405: During the recording adjustment process, each link can stably receive the link delay setting of the feature template pattern, and take the intermediate delay value that each link can stably match as the initial delay setting of each link. 、 、 、… , after completing the initial calibration, it can be considered that the different propagation delays of all links have been aligned by adjusting the initial delay settings, such as Figure 7 shown.

[0065] S5. Set the phase offset of N links. The phase offset is the sampling period Tclk / N, where N is the total number of links. The sampling rate of each link is 25 Gsps. When N is 4, the corresponding offset is 10 ps.

[0066] S6, the delay adjustment module adjusts the delay of each link through the digital control and voltage control of the delay line, so that the sampling points of each link are evenly distributed, and the unit interval UI is obtained, which is 10ps. Figure 8 As shown, the receiving end of the multi-channel serial deserializer SerDes outputs the interleaved sampled data frames in parallel, and determines the arrangement order of the multi-channel data according to the delay setting relationship of each link.

[0067] S7. Using the phase adjustment algorithm, the delay adjustment module performs precise delay calibration of each link data according to the phase offset; specifically, the following steps are included:

[0068] S701. Adjust the transmit clock phase of the SerDes transmitter according to the phase offset to obtain a calibration signal with a fixed frequency and continuously changing phase delay. Specifically, the TXPIPPM controller for the SerDes phase adjustment can be used to manually adjust the TX phase interpolation PI controller of the SerDes transmitter, which can establish a controllable phase relationship between the reference clock and the transmitter output of the GTH transceiver. Determine whether the transmitter TX phase is advanced or retarded by setting the register port TXPIPPMSTEPSIZE, and then adjust TXPIPPMSTEPSIZE [3:0] according to the formula to obtain the appropriate step size. , expressed as: ; In this mode, TXPIPPMEN should generate a pulse of two TXUSRCLK cycles, so that the phase interpolation controller steps one level; TXPIPPMSTEPSIZE [3:0] is the configurable phase step control value set to 8, TXOUT_DIV is the clock division coefficient TXOUT_DIV can be set to 1, 2, 4, 8, 16, here it is 16, and the STEP_SIZE (UI) is 2.8125°. After 32 steps, the data transmission generates a 90° delay.

[0069] S702, the serial deserializer SerDes receiving end performs parallel interleaving sampling and outputs sampled data;

[0070] S703: In the parallel interleaved sampling data obtained by the SerDes receiving end, the rising edge is expected to be postponed from the first sampling point in the parallel link to the second sampling point, and the sampling data is judged to be correct. If not, the analog delay fine adjustment end of the delay adjustment module is adjusted to ensure that the delay phase is within the range of 90°±45°, thereby achieving the calibration parameters of the delay of each link.

[0071] S8. Performing measurement accuracy analysis on the sampled data obtained by sampling at the receiving end of the serial deserializer (SerDes) using a frequency offset adjustment algorithm; specifically, the following steps are included:

[0072] S801, the serial deserializer (SerDes) transmitter changes the frequency offset of the transmit clock through frequency deviation adjustment to obtain a standard signal with a periodic change; specifically, the serial deserializer (SerDes) transmitter TX output is controlled to operate at a frequency with a fixed ppm offset from the reference clock, and a continuous PI code update mode is used to change the output clock period. Figure 10 The frequency adjustment shown is used in scenarios where data may be received at one frequency and then retransmitted at a different frequency without the need for an additional external clock source.

[0073] The frequency offset can be generated by setting TXPIPPMSTEPSIZE[4] = 1 to adjust in incrementing mode, setting TXPIPPMSTEPSIZE[4] = 0 to decrement the counter, and setting TXPIPPMSTEPSIZE[3:0] according to the formula to determine the desired offset. , expressed as: TXOUT_DIV can be set to 1, 2, 4, 8, or 16, TXPI_SYNFREQ_PPM can be set to 1 to 7, and TXPIPPMSTEPSIZE can be set to 0 to 15.

[0074] By changing the transmit clock frequency offset of the serial deserializer (SerDes) transmitter, a periodically varying calibration signal is obtained.

[0075] S802. At a certain frequency, count the pulse widths of multiple interleaved samples and analyze the measurement results to generate an analysis curve. The analysis of the measurement results specifically includes finding the maximum and minimum values, calculating the maximum deviation, and calculating the RMS value, which is then subtracted from the transmitter TX signal. The horizontal axis represents the linear increase in the transmitter TX input pulse width, while the vertical axis represents the corresponding measurement value, to generate a corresponding measurement result analysis curve.

[0076] Temperature error compensation is specifically:

[0077] After completing the above measurement accuracy calculation, change the ambient temperature of the system, obtain the corresponding system operating temperature through the temperature measurement device, and draw an error-temperature curve with temperature as the horizontal axis and measurement deviation as the vertical axis, as shown in the figure below: Figure 6 As shown in the figure, the measurement error compensation values at different temperatures are obtained by measuring the deviation at different temperatures and stored in the system. When the system is working, the operating temperature is obtained in real time, and the corresponding compensation coefficient is queried to perform temperature compensation.

[0078] The system's operating temperature range is 0-40°C, and temperature calibration is performed every degree Celsius. Place the system in a constant temperature test chamber and set the corresponding operating temperature, Temp. After thermal engine and temperature equilibrium are achieved, the control system enters calibration mode and outputs a calibration signal with a known pulse width, Tcal. Obtain the system's measurement result, Tmea. After 1000 measurements, take the root mean square (RMS) value to obtain Tmea_rms. The error compensation value under this Temp condition is Temp_com = Tcal - Tmea_rms.

[0079] Perform piecewise linear fitting on the compensation value at the corresponding temperature. When measuring the pulse width, add the corresponding error compensation value to the original measurement value to obtain the corrected measurement result.

[0080] S9, the selection module selects the measured signal as the input signal, and the fan-out driver module copies the input signal to obtain signals of multiple links;

[0081] S10, multiple serial deserializer (SerDes) receivers perform parallel interleaving sampling on the signals of multiple links, output sampled data, and determine the arrangement order of the multiple sampled data according to the delay setting relationship of each link. The temperature collector collects the operating temperature of the system;

[0082] S11, the multi-parallel pulse width time measurement module extracts the pulse signal of the sampled data through the edge processing circuit, and performs data segmentation on the interleaved sampled signal, such as Figure 9 As shown, the pulse width value is calculated by a parallel summing circuit; specifically including:

[0083] S1101, extracting a pulse signal of an interleaved sampling signal through an edge processing circuit;

[0084] S1102. Split the pulse signal into multiple data groups, retaining the last bit of the previous group in each data group. Data segmentation is intended to reduce the difficulty of data processing, reduce the number of logical processing levels, and mitigate the timing implementation risks associated with multi-carry chains. Split the parallel large-bit-width sampled data into multiple data groups, each with a bit width of no more than 16 bits. Furthermore, to determine the first pulse of each group, the last bit of the previous group must be retained in each data group to determine the exact pulse start location.

[0085] S1103. Distinguish whether each set of data is in a rising edge state or a falling edge state. Specifically, two adjacent values in each set of data are determined. If the sample values are in a 0-1 sequence, it is considered a rising edge; if the sample values are in a 1-0 sequence, it is considered a falling edge. Each bit is set according to the determined position to obtain the rising edge state and falling edge state of each 16-bit set.

[0086] S1104. Sum the rising edge states of a preset number of groups bit by bit to obtain the total number of rising edges of a clock Rise_sum; sum the falling edge states of a preset number of groups bit by bit to obtain the total number of falling edges of a clock Fall_sum; the preset number of groups is 20; the statistical results are shown in Table 1;

[0087] S1105: Analyze the pulse width based on the total number of rising edges of a clock and the total number of falling edges of a clock; specifically:

[0088] As shown in Table 1, set the positive pulse width counter pos_pulse_cnt and the negative pulse width counter neg_pulse_cnt;

[0089] No. 1: When the total number of rising edges of a clock Rise_sum and the total number of falling edges of a clock Fall_sum are both 0, the positive pulse width counter pos_pulse_cnt is counted by 1 when the signal is all 1, and the negative pulse width counter neg_pulse_cnt is counted by 1 when the signal is all 0;

[0090] No. 2: When the total number of rising edges of a clock, Rise_sum, is 0 and the total number of falling edges of a clock, Fall_sum, is 1, the corresponding positive and negative pulse width values are mapped according to the determined falling edge one-hot code, and the sum is calculated with the corresponding positive and negative pulse width counters to obtain the corresponding pulse width;

[0091] No. 3: When the total number of rising edges of a clock (Rise_sum) is 1 and the total number of falling edges of a clock (Fall_sum) is 0, the corresponding positive and negative pulse width values are mapped according to the determined rising edge one-hot code, and the sum is calculated with the corresponding positive and negative pulse width counters to obtain the corresponding pulse width;

[0092] No. 4: When the total number of rising edges (Rise_sum) and the total number of falling edges (Fall_sum) of a clock are both 1, the pulse width is determined based on the order of the rising and falling edges. If the rising edge comes first, the pulse width is positive. The positive pulse width is obtained by subtracting the rising edge position from the falling edge position. If the falling edge comes first, the pulse width is negative. The negative pulse width is obtained by subtracting the falling edge position from the rising edge position.

[0093] No. 5: When the total number of rising edges of a clock (Rise_sum) is 2 and the total number of falling edges of a clock (Fall_sum) is 1, the corresponding acquisition code value and the corresponding sampling time are stored in the data buffer FIFO, and the second rising edge position is recorded at the same time. The positive pulse width length is calculated in conjunction with the subsequent positive pulse width counter pos_pulse_cnt;

[0094] No. 6: When the total number of rising edges of a clock Rise_sum is 1 and the total number of falling edges of a clock Fall_sum is 2, the corresponding acquisition code value and the corresponding sampling time are stored in the data buffer FIFO, and the second falling edge position is recorded at the same time. The negative pulse width is calculated in conjunction with the subsequent negative pulse width counter neg_pulse_cnt;

[0095] Sequence number 7: When the total number of rising edges of a clock Rise_sum and the total number of falling edges of a clock Fall_sum are both greater than or equal to 2, the corresponding acquisition code value and the corresponding sampling time are stored in the data buffer FIFO;

[0096] By adding an offset to each set of parallel data, the specific location of the corresponding rising and falling edges in the parallel data is determined. When there is only one pulse per FPGA master clock cycle, or when the pulse period is greater than the FPGA master clock cycle, the corresponding pulse width measurement result can be obtained at each clock cycle. If there are multiple pulse periods per FPGA master clock cycle, the data buffer FIFO can be read and analyzed channel by channel to determine the width of each pulse and its corresponding occurrence time. The analysis method reads the parallel data from the data buffer FIFO and converts it into a single data channel. The rising and falling edges of the data in this data channel are determined, and the corresponding pulse width information is obtained by calculating the bit difference between the rising and falling edges. When the FPGA master clock is 312.5MHz, at least one pulse width measurement result can be obtained at each master clock cycle, with a maximum throughput of >300M events / s.

[0097] S12. Determine a compensation coefficient at the operating temperature, and calculate a compensated pulse width value based on the compensation coefficient.

[0098] Table 1

[0099] Serial number Rise_sum value Fall_sum value illustrate 1 0 0 Data all 0 or all 1 2 0 1 Data falling edge 3 1 0 Data rising edge 4 1 1 According to the order of judgment, positive pulse or negative pulse 5 2 1 Short positive pulse and long positive pulse 6 1 2 Short negative pulse and long negative pulse 7 ≥2 ≥2 Multiple positive / negative pulses

[0100] Continuous high-precision pulse width measurement system based on high-speed serdes, such as Figure 1 、 Figure 2 Shown, including:

[0101] At least two input modules; the input modules are used for inputting calibration signals or measured signals;

[0102] Selection module: The selection module is used to select a signal input by an input module;

[0103] The fan-out driver module is used to copy the input signal into signals of multiple links, and the signal output end of the selection module is connected to the signal input end of the fan-out driver module;

[0104] Multiple delay adjustment modules; one delay adjustment module is used to adjust the delay of the signal of a link,

[0105] The signal output terminals of the fan-out driving module are respectively connected to the signal input terminals of the multi-channel delay adjustment modules;

[0106] Temperature measurement module; the temperature measurement module is used to detect the temperature of the working environment of the measurement system;

[0107] FPGA chip; the signal output ends of the multiple delay adjustment modules and the signal output ends of the temperature measurement module are connected to the signal input end of the FPGA chip, the FPGA chip is provided with a serial deserializer SerDes, and the serial deserializer SerDes transmitting end is used to send a calibration signal to the input module;

[0108] Storage module; the storage module stores temperature compensation data;

[0109] FPGA chips include:

[0110] Multiple serial deserializers (SerDes); sampling the multiple parallel signals after delay conditioning to the corresponding multiple parallel serial deserializers (SerDes) receiving ends to obtain sampled data;

[0111] Data buffer FIFO; Data buffer FIFO is used to synchronize clock processing of sampled data;

[0112] Multi-channel interleaving calibration module: The multi-channel interleaving calibration module determines the sampling phase of each channel of sampled data after synchronization based on the multi-channel interleaving algorithm, and evenly distributes the sampling clock phases of multiple SerDes receiving ends within a sampling period through the phase adjustment function of the SerDes transmitter and the delay settings of each link. After the calibration is completed, it outputs multiple parallel quantized data streams of interleaved samples.

[0113] Multi-parallel pulse width time measurement module; the multi-parallel pulse width time measurement module performs high-precision pulse width time calculation on multiple parallel quantized data streams through a pulse width retrieval circuit.

[0114] The measurement system also includes an input buffer driver module, which converts single-ended input signals to differential form via an ultra-wideband fixed-gain fully differential amplifier and adjusts the common-mode level of the output differential signal. The input signal can be single-ended or differential. Passing the input signal through the ultra-wideband fixed-gain fully differential amplifier converts the single-ended input signal to differential form and adjusts the common-mode level of the output differential signal. This device leverages its excellent bandwidth and low distortion to minimize signal transmission impedance and enhance the signal's drive capability for subsequent circuits.

[0115] The calibration signal is generated using the FPGA chip's built-in high-speed serial deserializer (SerDes) transmitter Tx port, capable of generating high-speed differential signals up to 32.75 Gbps and supporting DC coupling. High and low pulse signals of varying pulse widths can be configured, and the output signal phase can be fine-tuned using the clock phase adjustment function. During the calibration process, the clock offset can be adjusted to generate output signals of varying rates, generating calibration signals and testing multi-channel parallel phase calibration.

[0116] The selection module uses a high-speed analog multiplexer to select the signal to be measured. During the calibration phase, the transmitter Tx signal of the serial deserializer (SerDes) is selected for calibration of the multi-channel parallel system; during the measurement phase, the signal to be measured is selected for input calibration.

[0117] The fan-out driver module utilizes a multi-channel signal fan-out circuit and an ultra-low additive jitter differential clock buffer to achieve multi-channel signal fan-out, driving subsequent delay adjustment circuits. It also features output level adjustment, enabling flexible adaptation to various electrical standards. Its ultra-low jitter, at the femtosecond level, prevents the introduction of large jitter errors into the entire measurement system, potentially affecting measurement accuracy.

[0118] The delay adjustment module is a parallel multi-channel delay adjustment circuit that uses a high-precision adjustable delay chip to precisely adjust the delay of each signal. This device features programmable step delay adjustment and continuous delay adjustment controlled by analog voltage. Through step coarse adjustment and continuous fine adjustment, the delay of each line can be precisely controlled. Programmable fine adjustment is achieved through FPGA chip control, and analog voltage adjustment is achieved using a high-precision DAC with multiple outputs. The parallel multi-channel delay adjustment circuit, equipped with a multi-channel interleaving calibration algorithm, can achieve high-precision sampling phase adjustment, achieving uniform interleaving of the sampling moments of multiple signals. Accurately controlling the phase delay of multiple parallel signals is key to achieving multi-channel interleaving to improve the system sampling rate and time resolution accuracy.

[0119] The FPGA chip completes the high-speed acquisition of various signals, the output of calibration signals, the implementation of the multi-channel interleaved calibration algorithm, the sampling and quantization of the measured signals, the pulse width calculation of the high-resolution data, the error correction of the calculated results, and the control and communication. This is achieved using an FPGA chip with a high-performance serializer / deserializer (SerDes).

[0120] Throughout the hardware design, power supply noise suppression, transmission line signal integrity control, and clock system accuracy are addressed to reduce the jitter of the measured signal and improve the system's stability and accuracy.

[0121] Strictly follow the voltage range requirements in the device manual, use a separate linear regulator to power the high-speed interface power supplies MGTAVCC, MGTAVTT, and MGTVCCAUX, control the power ripple to less than 10mVpp, and use a combination of 4.7uF and 0.1uF capacitors to decouple and stabilize the power supply.

[0122] The reference clock transmission uses AC coupling and a 0.1uF capacitor for AC coupling to reduce the possibility of low-frequency noise coupling. The unused reference clock input terminal is connected to GND to reduce the impact of spatial electromagnetic interference on clock quality. During PCB design, the differential traces between each link are guaranteed to have a spacing of more than 3 times, and vias are evenly and alternately distributed along the signal routing path to prevent the impact of crosstalk from adjacent lines on signal edges.

[0123] A filtering circuit is used at the output end of the crystal oscillator to reduce the crystal's external electromagnetic radiation; a metal shield is used to isolate the crystal oscillator circuit; a separate linear regulated power supply is used to power the crystal oscillator to prevent noise interference from coupling to other circuits; a high-precision temperature-compensated crystal oscillator is used as a clock reference to ensure the system's clock accuracy.

[0124] The entire system has a small number of peripheral circuits, and the core components include drivers, analog multiplexers, signal fan-outs, delay adjustment chips, and core FPGAs. The circuit design is simple and easy to use.

[0125] Multi-channel interleaved sampling calibration algorithm process:

[0126] Designed by Figure 3 The following flow is used to perform the initial clock phase calibration of the sampling clock:

[0127] Set the SerDes (Serial Deserializer) transmitter (TX) to send a matching calibration signal: Use the transmitter's TX interface to output a signal encoding a signature pattern. The signature pattern signal period is the data clock period after the SerDes's receiver (RX) interface performs serial-to-parallel conversion on the data. For example, if the SerDes's receiver (RX) interface converts 25 Gbps data into 80-bit data at 312.5 MHz, the transmitter's TX signal period is 80 bits. Furthermore, the minimum repetition period of the digital signal sent by the SerDes's transmitter (TX) is 80 bits, meaning every 80 bits repeat.

[0128] Input selection is transmitter TX calibration signal input: Select calibration signal input to proceed with subsequent calibration process.

[0129] Set the delay of each link to the same initial value: Set the delay of each delay link to the same initial value. This delay value should be set within a reasonable range so that the delay of each link can be adjusted within the range of the initial value to 5 sampling clock cycles. For example, when the sampling rate of each link is 25Gbps, each link can be adjusted within a range of 40ps × 5, or 200ps.

[0130] The receiving end (RX) receives data and performs signature pattern matching: The receiving end (RX) of the SerDes (Serializer-Deserializer) samples data and compares the sampled data with the signature pattern of the transmitted data. If the received data differs from the transmitted data, the receiving end first adjusts the data cyclic shift (bitslip) to make adjustments, and then performs the matching again. If the signature pattern still fails after performing several bitslips in parallel (for example, 80 times), the delay of that line is adjusted using the step delay control. After adjusting the delay, the matching process is repeated. Since the transmitting end (TX) transmits data at the same sampling rate and reference clock, the receiving end (RX) can correctly receive the corresponding signature pattern after adjusting the signal delay, provided the hardware circuit is functioning properly. After receiving the signature pattern, it is necessary to continuously monitor the receiving end for a certain number of cycles to ensure stable operation of the transmitting and receiving ends under large amounts of data. After completion, the initial delay value of each line is recorded.

[0131] Precise positioning of multi-channel sampling phase: For each link, after stable sampling, the precise relationship between its sampling clock phase and the calibration signal cannot be confirmed. By increasing the delay of each link, the acquired data can be shifted backward. Gradually increase the delay of each link. When the acquired sampling result is shifted backward by 1 bit as a whole, record the delay value dly_1bit at this time; continue to increase the delay. When the acquired sampling structure is shifted backward by 2 bits as a whole, record the delay value dly_2bit at this time; calculate the average value of dly_1bit and dly_2bit to obtain the starting delay value dly_start of the sampling, as shown in the following example: Figure 4 shown.

[0132] Phase adjustment of multi-channel interleaved sampling: Calculate the corresponding sampling period Tsample based on the sampling rate Sample_lane of each link. Based on the principle of multi-channel interleaved parallel sampling, calculate the phase adjustment delay value dly_phase_add that needs to be added to each link. Add the sampling start delay value dly_start of each link to the phase adjustment delay value dly_phase_add to obtain the delay value setting of the link. Update the corresponding delay value to each link, such as Figure 5 shown.

[0133] Verifying Interleaved Sampling Results: After setting the delay for interleaved sampling, the interleaved sampling results must be tested and verified. By adjusting the transmit clock frequency of the transmitter (TX), the corresponding frequency deviation is set to adjust the data rate. The transmitter (TX) transmits a fixed-code signal. As the data rate changes, the corresponding high and low pulse durations also change. When the transmit frequency decreases, the signal period increases; when the transmit frequency increases, the signal period decreases.

[0134] The relationship between the transmission frequency, signal period and pulse width can be obtained through calculation.

[0135] The correctness of the interleaved sampling can be verified by calculating the high and low pulse widths of the high-speed data stream obtained by the interleaved sampling.

[0136] Interleaved sampling temperature compensation algorithm: When the system operating temperature changes, the crystal oscillator frequency can cause temperature drift in the system's measurements. A temperature sensor is included in the design to obtain real-time system operating temperature. A standard pulse width signal is input via an external, highly stable, constant-temperature crystal oscillator. The measurement results at different temperatures are fitted using the least squares method to obtain the corresponding temperature compensation coefficients, which are stored in non-volatile memory. During system operation, the operating temperature is read in real time to find the corresponding compensation coefficients. The original results obtained by the FPGA chip are then compared with the compensation coefficients to obtain accurate compensated results.

[0137] The technical solution of the present invention is not limited to the above-mentioned specific embodiments. Any technical variations made according to the technical solution of the present invention fall within the protection scope of the present invention.

Claims

1. A continuous high-precision pulse width measurement method based on high-speed serdes, characterized in that: include: S1, the serial deserializer SerDes transmitter cyclically sends the matching calibration signal as the characteristic template pattern; S2. The selection module selects the calibration signal as the input signal, and the fan-out driver module copies the input signal to obtain signals of multiple links; S3, multi-path interleaving calibration module adjusts and sets the initial delay value of each link , the initial delay value of each link is the same value, and the delay adjustment module adjusts the delay of the signals of multiple links according to the initial delay value of each link; S4, the serial deserializer SerDes receiving end receives data, which is the signal after the delay of each link is adjusted. The multi-channel interleaving calibration module analyzes the received data and compares it with the characteristic template pattern to obtain the initial delay setting for the delay adjustment module receiving end of each link to stably receive data. 、 、 、… , complete the initial calibration; S5. Set the phase offset of multiple links, where the phase offset is the sampling period Tclk / N, where N is the total number of links; S6. The delay adjustment module adjusts the delay of each link so that the sampling points of each link are evenly distributed, obtains the unit interval UI, and determines the arrangement order of the signals of each link; S7. Using the phase adjustment algorithm, the delay adjustment module performs accurate delay calibration of each link data according to the phase offset; S8. Performing measurement accuracy analysis on the sampled data obtained by sampling the SerDes receiving end using a frequency offset adjustment algorithm; S9, the selection module selects the measured signal as the input signal, and the fan-out driver module copies the input signal to obtain signals of multiple links; S10, multiple serial deserializer (SerDes) receivers perform parallel interleaving sampling on the signals of multiple links and output sampled data, and a temperature collector collects the operating temperature of the system; S11, a multi-parallel pulse width time measurement module extracts the pulse signal of the sampled data through the edge processing circuit and calculates the pulse width value through the parallel summing circuit; specifically including: S1101, extracting a pulse signal of an interleaved sampling signal through an edge processing circuit; S1102, dividing the pulse signal into multiple groups of data, retaining the last bit of the previous group of data in each group of data; S1103, distinguish whether each set of data is in a rising edge state or a falling edge state; S1104, performing bitwise summation on the rising edge states of a preset number of groups to obtain a total number of rising edges of a clock Rise_sum; performing bitwise summation on the falling edge states of a preset number of groups to obtain a total number of falling edges of a clock Fall_sum; S1105, analyzing the pulse width according to the total number of rising edges of a clock and the total number of falling edges of a clock; S12. Determine a compensation coefficient at the operating temperature, and calculate a compensated pulse width value based on the compensation coefficient.

2. The continuous high-precision pulse width measurement method based on high-speed serdes according to claim 1 is characterized in that: In S1, the pulse start feature of the feature template pattern satisfies the time relationship, which is expressed as: ,in is the period of the feature template pattern, is the propagation delay of the signal.

3. The continuous high-precision pulse width measurement method based on high-speed serdes according to claim 1 is characterized in that: Included in S4: S401, a serial deserializer (SerDes) receiving end receives data; S402, the multi-channel interleaving calibration module shifts the data under the master clock of the serial deserializer SerDes receiving end; S403. Compare the collected data under each data master clock. If a rising edge appears, determine whether the received data starting from the current beat is consistent with the feature template pattern. If they are consistent, the match is successful, output the matching success status of each link, and enter S405; otherwise, set m=m+1 and enter S404; where m is a positive integer; S404, determine whether m is greater than the preset number of cycles, if so, return to S3; otherwise, shift the data by bitslip and return to S401; S405: During the recording adjustment process, each link can stably receive the link delay setting of the feature template pattern, and take the intermediate delay value that each link can stably match as the initial delay setting of each link. 、 、 、… , complete the initial calibration.

4. The method for continuous high-precision pulse width measurement based on high-speed serdes according to claim 3, characterized in that: When returning from S404 to S3, the multi-path interleaving calibration module adjusts the initial delay value of each link according to the minimum adjustment step value. .

5. The continuous high-precision pulse width measurement method based on high-speed serdes according to claim 1 is characterized in that: Specifically in S7: S701, adjusting the transmit clock phase of the SerDes transmitter according to the phase offset to obtain a calibration signal with a fixed frequency and continuously varying phase delay; S702, the serial deserializer SerDes receiving end performs parallel interleaving sampling and outputs sampled data; S703: Determine whether the sampled data is correct. If not, adjust the analog delay fine adjustment terminal of the delay adjustment module to achieve calibration parameters for each link delay.

6. The method for continuous high-precision pulse width measurement based on high-speed serdes according to claim 1, characterized in that: Included in the S8: S801, the serial deserializer (SerDes) transmitter changes the frequency offset of the transmission clock through frequency deviation adjustment to obtain a standard signal with periodic variation; S802: Count the pulse widths of multiple interleaved samples, and analyze the measurement results to obtain an analysis curve.

7. The method for continuous high-precision pulse width measurement based on high-speed serdes according to claim 1, characterized in that: Specifically in S1105: setting the positive pulse width counter pos_pulse_cnt and the negative pulse width counter neg_pulse_cnt; When the total number of rising edges of a clock Rise_sum and the total number of falling edges of a clock Fall_sum are both 0, the positive pulse width counter pos_pulse_cnt is counted by 1 when the signal is all 1, and the negative pulse width counter neg_pulse_cnt is counted by 1 when the signal is all 0; When the total number of rising edges of a clock Rise_sum is 0 and the total number of falling edges of a clock Fall_sum is 1, the corresponding positive and negative pulse width values are mapped according to the determined falling edge one-hot code, and the sum is calculated with the corresponding positive and negative pulse width counters to obtain the corresponding pulse width; When the total number of rising edges of a clock Rise_sum is 1 and the total number of falling edges of a clock Fall_sum is 0, the corresponding positive and negative pulse width values are mapped according to the determined rising edge one-hot code, and the sum is calculated with the corresponding positive and negative pulse width counters to obtain the corresponding pulse width; When the total number of rising edges of a clock (Rise_sum) and the total number of falling edges of a clock (Fall_sum) are both 1, the rising edge and the falling edge are judged according to their order. If the rising edge comes first, it is a positive pulse width. The corresponding positive pulse width output is obtained by subtracting the rising edge position from the falling edge position. If the falling edge comes first, it is a negative pulse width. The corresponding negative pulse width output is obtained by subtracting the falling edge position from the rising edge position. When the total number of rising edges of a clock Rise_sum is 2 and the total number of falling edges of a clock Fall_sum is 1, the corresponding acquisition code value and the corresponding sampling time are stored in the data buffer FIFO, and the second rising edge position is recorded at the same time, and the positive pulse width length is calculated in conjunction with the subsequent positive pulse width counter pos_pulse_cnt; When the total number of rising edges of a clock Rise_sum is 1 and the total number of falling edges of a clock Fall_sum is 2, the corresponding acquisition code value and the corresponding sampling time are stored in the data buffer FIFO, and the second falling edge position is recorded at the same time, and the negative pulse width length is calculated in conjunction with the subsequent negative pulse width counter neg_pulse_cnt; When the total number of rising edges of a clock Rise_sum and the total number of falling edges of a clock Fall_sum are both greater than or equal to 2, the corresponding acquisition code value and the corresponding sampling time are stored in the data buffer FIFO; By adding an offset to each set of parallel data, the specific position of the corresponding rising and falling edges in the parallel data is obtained. When there is only one pulse in each FPGA master clock cycle, or when the pulse period is greater than the FPGA master clock cycle, the corresponding pulse width measurement result can be obtained at each clock. If there are multiple pulse cycles within each FPGA master clock cycle, the data buffer FIFO can be read and analyzed through the channel to obtain the width of each pulse and the corresponding occurrence time.

8. A high-speed serdes-based continuous high-precision pulse width measurement system, used to implement the high-speed serdes-based continuous high-precision pulse width measurement method according to any one of claims 1 to 7, characterized in that: include: At least two input modules; The input module is used to input the calibration signal or the measured signal; Select the module; The selection module is used to select a signal input by an input module; The fan-out driver module is used to copy the input signal into signals of multiple links, and the signal output end of the selection module is connected to the signal input end of the fan-out driver module; Multiple delay adjustment modules; A delay adjustment module is used to adjust the delay of the signal of a link. The signal output terminals of the fan-out driving module are respectively connected to the signal input terminals of the multi-channel delay adjustment modules; Temperature measurement module; the temperature measurement module is used to detect the temperature of the working environment of the measurement system; FPGA chip; The signal output ends of the multiple delay adjustment modules and the signal output ends of the temperature measurement module are connected to the signal input end of the FPGA chip. The FPGA chip is provided with a serial deserializer (SerDes). The serial deserializer (SerDes) transmitting end is used to send a calibration signal to the input module. Storage module; The storage module stores temperature compensation data; FPGA chips include: Multiple serial deserializers (SerDes); sampling the multiple parallel signals after delay conditioning to the corresponding multiple parallel serial deserializers (SerDes) receiving ends to obtain sampled data; Data buffer FIFO; Data buffer FIFO is used to synchronize clock processing of sampled data; Multi-channel interleaving calibration module: The multi-channel interleaving calibration module determines the sampling phase of each channel of sampled data after synchronization based on the multi-channel interleaving algorithm, and evenly distributes the sampling clock phases of multiple SerDes receivers within a sampling period through the phase adjustment function of the SerDes receiver and the delay settings of each link. After calibration is completed, it outputs multiple parallel quantized data streams of interleaved samples. Multi-parallel pulse width time measurement module; the multi-parallel pulse width time measurement module performs high-precision pulse width time calculation on multiple parallel quantized data streams through a pulse width retrieval circuit.

9. The high-speed serdes-based continuous high-precision pulse width measurement system according to claim 8, characterized in that: The measurement system also includes an input buffer driver module, which converts the single-ended input measured signal into a differential form through an ultra-wideband fixed-gain fully differential amplifier and adjusts the common-mode level of the output differential signal.

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