Onboard automatic triggering method and device for dynamic acquisition of inverter state

Abstract

The invention discloses an onboard automatic triggering method and device for dynamic acquisition of an inverter state, and belongs to the technical field of inverters. The onboard automatic triggering comprises configurable triggering and configurable acquisition; the configurable trigger captures a dynamic signal of an inverter switching tube, the capturing condition of the dynamic parameter comprises jump trigger and stable trigger, the jump trigger comprises linkage jump trigger and independent jump trigger, and the stable trigger comprises high level trigger and low level trigger; configurable data acquisition is carried out after configurable triggering, the configurable acquisition carries out parameterization configuration on channel selection, acquisition length and acquisition precision, and finally real-time synchronous acquisition and storage of a specific number of channel data are realized; any triggering and collecting requirements can be met through parameterized configuration, capturing and triggering of specified events under the complex control time sequence of the inverter are achieved, data are accurately collected and stored, and accurate data basis and reference are provided for inverter fault diagnosis and health assessment.

Description

Technical Field

[0001] The present invention relates to the technical field of inverters, and in particular to an on-board automatic triggering method and device for dynamically collecting inverter states. Background Art

[0002] As an important component of the electric drive system, the inverter undertakes the function of energy conversion and output, converting DC electrical energy into AC power with fixed frequency, fixed voltage or variable frequency, variable voltage, which is used to drive the motor to achieve motion control or energy conversion. Under the action of multi-physical field stresses in the working profile of the inverter power switch, aging of parts such as the inside of the chip, package bonding, and pins will cause a series of failure problems. Minor inverter failures will cause equipment shutdown or loss of equipment functions, affecting the normal development of production manufacturing and equipment tasks, resulting in decreased efficiency and increased costs. Severe failures may lead to serious consequences such as equipment or equipment out of control, fire, and burnout.

[0003] The switching tube is the core device and the weak link in the inverter. The correct acquisition of the switching tube state data is the technical prerequisite and foundation for online real-time monitoring and diagnosis of the inverter. Due to the limited size of the on-board storage resources, the acquisition of transient data of the switching tubes in the inverter needs to accurately capture the effective timing window. Due to the diverse triggering conditions and the large number of switching tubes in the inverter, it is difficult for the on-board circuit area to meet the needs of all monitoring. How to flexibly solve the dynamic triggering and acquisition of inverter monitoring plays a key role, which will provide strong support for accurately predicting the performance of all switching tubes in the inverter and evaluating the comprehensive performance of the entire inverter.

[0004] There are many types of inverters. The present invention can be applied to a three-phase full-bridge inverter in a servo drive system, which is composed of three half-bridges formed by six IGBT (Insulated Gate Bipolar Transistor) switching devices, as Figure 1 shown. They are VT1-VT6 respectively, where VT1 and VT4 are defined as phase a, VT3 and VT6 are defined as phase b, VT5 and VT2 are defined as phase c. The a, b, and c output terminals are connected to the three-phase windings (equivalent to coils) of the motor. The combination of 6 IGBTs (the signals of the upper and lower half-bridges of the same bridge arm are opposite) has 8 safe switching states, as Figure 2 shown. Among them, 000 and 111 represent the switching states of the three upper bridge arms. When the state of a certain IGBT in the three-phase full-bridge inverter circuit changes, the on and off bring changes in Vce and Ic currents. When the switching pulse jumps from high level to low level, it means that the IGBT is turned off, and the voltage drop of its Vce recovers from the saturation voltage drop to the value obtained by subtracting the saturation voltage drop from the bus voltage. Conversely, after the IGBT is turned on, the voltage drop of its Vce drops from the bus voltage to the saturation voltage drop.

[0005] The working mode of the inverter is a process of converting direct current into a specific alternating current voltage for external output through precise control of internal switching devices. The realization of this process depends on the state combination and switching use of internal three-phase bipolar switching tubes. Since it is a mode of combined use of multiple tubes, to capture and collect the dynamic waveforms at the moment of single-tube switching, it is necessary to accurately capture the moment of state jump.

[0006] Currently, the discovery of inverter faults in the electric drive system usually involves testing the U / V / W three-phase signals at the output end of the inverter bridge. If any one of the switching tubes in any one phase fails, the effective value of the phase voltage will show a significant drop. By using the open-phase waveform to judge whether there are faults caused by the open circuit of single or multiple switching tubes, it belongs to the fault discovery and location technology after the occurrence of electric drive failure, referring to the system-level signals of the electric drive inverter, and it is impossible to track the failure evolution process of internal switching tubes and detect problems in advance. With the help of special instruments such as oscilloscopes, the switching tubes of the inverter can be tested and analyzed, but it requires in-depth disassembly and grafting of test points, and the operation is complex. In practical engineering applications, it is often not possible to disassemble the switching tubes from the circuit board for testing and then solder them back for continued use, and other reliability problems will also be introduced. Currently, there is no on-board solution that can achieve general flexible triggering, automatic acquisition and transmission through configuration. Summary of the Invention

[0007] To solve the above technical problems, the present invention proposes an on-board automatic triggering method and device for dynamic acquisition of inverter states, belonging to the technical field of inverters. The on-board automatic triggering includes configurable triggering and configurable acquisition; the configurable triggering captures the dynamic signals of the inverter switching tubes, and the capture conditions for dynamic parameters include jump triggering and stable triggering; the jump triggering includes linked jump triggering and independent jump triggering; the stable triggering includes high-level triggering and low-level triggering; after the configurable triggering, configurable data acquisition is performed. The configurable acquisition parametrically configures the channel selection, acquisition length, and acquisition accuracy, and finally realizes the real-time synchronous acquisition and storage of data for a specific number of channels; through parametric configuration, it can be adapted to any triggering and acquisition requirements, realizing the capture triggering of specified events, accurate data acquisition and storage under the complex control timing of the inverter, and providing an accurate data basis and reference for inverter fault diagnosis and health assessment.

[0008] An on-board automatic triggering method that can realize dynamic acquisition of inverter states includes the following steps:

[0009] Step 1, obtain the differential control signal of the inverter switching tube: The differential control signal of the IGBT (Insulated Gate Bipolar Transistor) switching tube is the gate G and the collector E;

[0010] Step 2: Input the differential control signal into the isolation conversion circuit for amplitude conditioning and optoelectronic isolation conversion to obtain a single-ended pulse signal. The amplitude conditioning includes proportional scaling and biasing.

[0011] Step 3: Input the single-ended pulse signal into the threshold conversion circuit for specific threshold feature recognition and filtering anti-interference to obtain a dual-threshold comparison trigger pulse.

[0012] Step 4: Transmit the dual-threshold comparison trigger pulse as a basic event to the event capture unit, and the event capture unit performs timing recognition on the switching tube to obtain a trigger signal.

[0013] Step 5: Input the trigger signal into the controller (ARM), and the controller starts acquisition after being triggered by an external interrupt.

[0014] Furthermore, in Step 2, the number of isolation conversion circuits is the same as the number of switching tubes. The isolation conversion circuit sequentially includes four parts: a differential amplification module, a voltage biasing module, a linear optoelectronic isolation module, and a voltage amplification and follower module.

[0015] The differential amplification module includes operational amplifier U89, proportional setting resistors, capacitor C219, and ports. The port voltages are Vin+ and Vin- respectively. The operational amplifier U89 includes U89A and U89B. The proportional setting resistors include resistors R323, R324, R333, R334, R343, and R349, and satisfy R323 + R324 = R333 + R334, R343 = R349. The port voltage Vin+ is sequentially connected in series with R323 and R324, and after being superimposed with the bias voltage Vbias, it is connected to the positive input terminal of U89A. The positive power input terminal of U89A is simultaneously connected in series with capacitor C219 and then grounded. The port voltage Vin- is sequentially connected in series with R333 and R334, and after passing through resistor R334, it is divided into two paths. One path is connected to the negative input terminal of operational amplifier U89A, and the negative terminal of the operational amplifier U89A is grounded. The other path is connected to the output terminal of operational amplifier U89A after being connected in series with resistor R349 to form a negative feedback loop.

[0016] The voltage biasing module includes resistors R341 and R347. One end of resistor R341 is connected to one end of resistor R347. The other end of resistor R341 is connected to +5V, and the other end of resistor R347 is grounded. After voltage division, it is connected to the positive input terminal of operational amplifier U89B. The output terminal and the negative input terminal of U89B are interconnected to form a voltage follower. Operational amplifier U89B shares the positive and negative power input terminals with U89A.

[0017] The linear opto-isolation module includes an isolation device U85, a resistor R327, a resistor R339, a capacitor C223, and a capacitor C227. The pins of the isolation device U85 include a positive input terminal IN+, a negative input terminal IN-, a positive output terminal OUT+, a negative output terminal OUT-, a voltage matching region VDD1, a voltage matching region VDD2, a ground isolation region GNG1, and a ground isolation region GND2. One end of the resistor R327 is connected in series with one end of the resistor R339. The other end of the resistor R327 is connected to the output terminal of the operational amplifier U89A. The other end of the resistor R339 is connected to the digital ground. After secondary voltage division, it is grounded in parallel with the capacitor C223 and is also connected to the positive input terminal IN+ of the isolation device U85. The negative input terminal IN- of the isolation device U85, the other end of the capacitor C223, and the ground isolation region GNG1 are all connected to the digital ground. The voltage matching region VDD1 is connected to one end of the capacitor C227, and the other end of the capacitor C227 is connected to the digital ground.

[0018] The voltage amplification and follower module includes an operational amplifier U90A, configuration resistors, a capacitor C228, a capacitor C233, and a low-pass filter circuit. The configuration resistors include R329, R337, R344, and R351, and satisfy R329 = R337, R344 = R351. The low-pass filter circuit includes a capacitor C225 and a resistor R331. One end of the resistor R329 is connected to the positive output terminal OUT+ of the isolation device U85. The other end of the resistor R329 is connected to the positive input terminal of the operational amplifier U90A. The other end of the resistor R329 is grounded after being connected in series with R344, which is equivalent to setting the bias voltage to 0. The positive power input terminal of the operational amplifier U90A is grounded after being connected in series with the capacitor C233 at the same time. One end of the resistor R337 is connected to the negative output terminal OUT- of the isolation device U85. The other end of the resistor R337 is connected to the negative input terminal of the operational amplifier U90A, and is connected to the output terminal of the operational amplifier U90A after being connected in series with the resistor R351 at the same time, forming a feedback path. The negative power input terminal of the operational amplifier U90A is grounded at the same time. One end of the R331 is connected to the output terminal of the operational amplifier U90A. The other end of the R331 is grounded after being connected in series with the capacitor C225, and the output voltage Vout is output at the same time.

[0019] The isolation conversion circuit processes the differential control signal as follows:

[0020] Step 2.1, the port receives the differential control signal of the switching tube and converts the differential control signal into a single-ended signal. The operational amplifier U89A reduces the voltage of the single-ended signal by a ratio of β1. The reduced voltage range is -1.2 to 2V, and the reduction ratio β1 = R349 / (R323 + R324).

[0021] Step 2.2, the voltage biasing function is achieved by setting resistors R341 and R347. The biased voltage range is 0.05V to 3.25V, and the bias voltage Vbias = 5 * (R341 / (R341 + R347));

[0022] Step 2.3, the biased single - ended signal is first scaled down by a ratio β2 by setting resistors R327 and R339 while ensuring the driving ability. The scaled - down voltage range is 0.025V to 1.625V; then it is input to the isolation device U85 for linear opto - isolation. The input range of the isolation device U85 is 0V - 2V; the scaling ratio β2 = R327 / (R327 + R339);

[0023] Step 2.4, the single - ended signal after linear opto - isolation is amplified, restored, and followed by the operational amplifier U90A by a ratio β3. The amplified voltage range is 0.05V to 3.25V; the amplification ratio β3 = R351 / R329; The voltage amplification and following module cancels the scaling ratio before entering the linear opto - isolation module on one hand and improves the current driving ability to the threshold transformation circuit on the other hand, ensuring that the current consumption of multiple threshold transformation branches will not cause waveform distortion;

[0024] Step 2.5, the output voltage Vout of the isolation change circuit = (Vbias + ((Vin+) - (Vin -)) * β1) * β2 * β3, and the range of Vout is 0.05V to 3.25V.

[0025] Further, in step 3, the threshold transformation circuit realizes signal threshold feature recognition through configurable comparison voltages to obtain dual - threshold comparison trigger pulses;

[0026] The number of the threshold transformation circuits is the same as the number of inverter switching tubes; The threshold change circuit successively includes a multi - channel DAC (Digital - to - Analog Converter), a buffer, a high - speed comparator, and a high - speed opto - coupler; There are 2 high - speed opto - couplers, and the 2 high - speed opto - couplers are the same; The high - speed comparator includes high - speed comparator A and high - speed comparator B. High - speed comparator A is used to realize the comparison trigger of the rising edge, and high - speed comparator B is used to realize the comparison trigger of the falling edge;

[0027] The controller controls the output voltage of the multi - channel DAC through the IIC (Inter - Integrated Circuit) bus, so that the output voltage range is 0V - 3V; The output voltage of the multi - channel DAC is the reference voltage after passing through the buffer, and the reference voltage is used to compare with the single - ended signal;

[0028] The single-ended signals at the output end of the isolation change circuit are input in parallel to the negative terminal of the high-speed comparator A and the positive terminal of the high-speed comparator B respectively; the reference voltages are input to the positive terminal of the high-speed comparator A and the negative terminal of the high-speed comparator B respectively; when the voltages at the positive terminals of the high-speed comparator A and the high-speed comparator B are both greater than the voltages at the negative terminals, the threshold transformation circuit outputs a high level, otherwise it outputs a low level;

[0029] The output signal of the high-speed comparator A is input to one of the high-speed optocouplers, and the output signal of the high-speed comparator B is input to the other high-speed optocoupler. After the signals are filtered and anti-interfered by the high-speed optocouplers, dual-threshold comparison trigger pulses are obtained; the function of the high-speed optocouplers is to isolate and protect the event capture unit to avoid timing misjudgment caused by signal crosstalk in the event capture unit in a harsh electromagnetic environment.

[0030] Furthermore, in step 4, the event capture unit is implemented based on a programmable logic device (FPGA) for event capture;

[0031] The event capture unit includes an SPI communication interface module (SPI slave), a read / write control timing module, a configuration register module, a status register module, and a logic recognition module;

[0032] The SPI communication interface module is interconnected with the controller through a synchronous clock Clk, a data line MISO, and a data line MOSI; the SPI communication interface module provides a data read / write interface to the controller as a slave device of SPI. Under the beat of the synchronous clock Clk of the controller, it serially receives read / write commands, and the read / write commands include read / write identifiers, operation addresses, and operation data information; while responding to the SPI serial communication protocol of the controller, the SPI communication interface module controls the read / write control timing module to address and read / write the configuration register module and the status register module. The read / write control timing module is interconnected with the configuration register module and the status register module in an asynchronous read / write mode. The asynchronous read / write mode interconnection form includes an asynchronous clock, a 32-bit data bus, and an 8-bit address bus; the configuration register module and the status register module are implemented in the form of a dual-port running memory (RAM). The configuration register module and the status register module simultaneously provide read / write interface data to the read / write control timing module and the logic recognition module respectively; the logic recognition module writes operation status flags and data into the status register module for the read / write control timing module to read and then send to the controller through the SPI communication interface, forming a two-way data interaction;

[0033] The SPI communication interface module interacts with the SPI Master (the master device of SPI) interface of the controller, and the interaction information includes the contents of reading / writing the configuration register and the status register;

[0034] The configuration register module is used to save the configuration parameters of the controller for the event capture logic. The configuration parameters include trigger enable, mode selection, and event customization;

[0035] The status register module latches the recognition status and count of multiple events of the logic recognition module. The status register provides an interface for both the logic recognition module and the read / write control timing module to read and write. The logic recognition module and the read / write control timing module each occupy one read / write bus of the dual-port RAM of the status register. The logic recognition module writes the event markers triggered in real time by the differential control signal of the switch tube, and the read / write control timing module writes the clear and manual trigger markers of the controller; The clear of the controller is used to clear the original trigger status, wait for the writing of the new trigger status and hold it; The manual trigger marker is only used in the debug mode, and the forced trigger is realized by the controller actively writing the status flag for acquisition and testing; The priority of the manual trigger is higher than that of the trigger of the logic recognition module, and the switching of the manual trigger mode is determined by the manual mode control bit of the configuration register; When the manual mode control bit of the configuration register enables the manual trigger mode, the trigger result of the logic recognition module will be masked, and no write operation to the status register module will occur;

[0036] The logic recognition module performs timing recognition based on the dual-threshold trigger pulse of the switch tube to capture various events of the switch tube, and the captured event results are latched into the status register module; The combined output logic of the logic recognition module outputs a trigger interrupt signal to the controller according to the event markers in the current status register module, combined with the trigger enable, mode, and event customization source configuration in the configuration register module.

[0037] Further, the timing recognition includes single-tube timing recognition and multi-tube combined timing recognition;

[0038] The single-tube timing recognition first generates a basic event waveform based on the dual-threshold trigger pulse of a single switch tube, and then realizes the event recognition of the single-tube jump trigger and stable trigger according to the rising edge and falling edge of the basic event waveform of the single-ended signal; The multi-tube combined timing recognition is based on multiple single-tube timing recognitions. Based on the jump trigger and stable trigger events of the multi-tube basic event waveform, a state machine is used for strict timing discrimination to realize the triggering of complex events that meet the multi-tube timing conditions;

[0039] Step 4.1, the single-tube timing recognition process is as follows:

[0040] First, the basic event waveform generation:

[0041] The dual-threshold comparison trigger pulse of a single tube is input to the logic recognition module. The dual-threshold comparison trigger pulse includes the first trigger pulse VH and the second trigger pulse VL; The basic event waveform is generated by a finite element state machine;

[0042] The finite element state machine uses asynchronous reset and is set to the idle state;

[0043] When the finite element state machine is in the idle state, the basic event waveform is at a low level; when there is a transition from low to high level of VH, the finite element state machine changes to state 1, otherwise it remains unchanged;

[0044] When the finite element state machine is in state 1, the basic event waveform is at a high level. When there is a transition from low to high level of VL, the finite element state machine changes to state 0, otherwise it remains unchanged;

[0045] When the finite element state machine is in state 0, the basic event waveform is at a low level. When there is a transition from low to high level of VH, the finite element state machine changes to state 1, otherwise it remains unchanged;

[0046] Secondly, single switch tube event recognition:

[0047] The high-speed clock is used to distinguish the basic event waveform. In each cycle of the high-speed clock, the current state now_state is temporarily stored in the previous state pre_state, and then the current basic event waveform level is read out and assigned to pre_state to identify the rising edge transition, falling edge transition and stable state of high and low levels of the basic event waveform;

[0048] The rising edge transition trigger:

[0049] If pre_state is at a low level and now_state is at a high level, the rising edge transition flag bit of the single tube in the state register module is set to 1 and remains so until the controller clears it through SPI;

[0050] The falling edge transition trigger:

[0051] If pre_state is at a high level and now_state is at a low level, the falling edge transition flag bit of the single tube in the state register module is set to 1 and remains so until the controller clears it through SPI;

[0052] The high and low level trigger:

[0053] If now_state is at a high level, the single tube level flag bit in the state register module is set to 1;

[0054] If now_state is at a low level, the single tube level flag bit in the state register module is set to 0;

[0055] Step 4.2, the multi-tube combined timing recognition process is as follows:

[0056] First, establish a general timing recognition framework. The general timing recognition framework includes the following general variables:

[0057] The maximum multi-tube timing state length max_state_len is a constant; the effective multi-tube timing state length use_state_len is defined in the configuration register module; max_state_len signal variables signal[max_state_len] are defined in the configuration register; a total of use_state_len single-tube events from signal[0] to signal[use_state_len - 1] represent a multi-tube event, occurring in sequence according to the order of signal[0] to signal[use_state_len - 1]. The coordinates index of the single-tube events stored in signal[0] to signal[use_state_len - 1], and Status_register is the single-switch-tube status register in the status register module;

[0058] Then, write the effective multi-tube timing state length to use_state_len in the configuration register through the SPI communication bus of the controller, and write the single-tube event index to signal[0] to signal[use_state_len - 1] in sequence to complete the definition of the multi-tube event;

[0059] Finally, adopt a finite state machine as the multi-tube event recognition state machine, and the multi-tube event recognition state machine uses asynchronous reset; set the multi-tube event recognition state machine to the idle state, define an event traversal count variable len_temp to count the number of state transitions, and assign an initial value of 0;

[0060] In the idle state: If len_temp is greater than use_state_len, the trigger condition is met and a trigger signal is output; if Status_register[signal[0]] corresponding to signal[0] is equal to 1, the recognition state machine of the multi-tube event is set to state 1, and len_temp = len_temp + 1; otherwise, it remains unchanged;

[0061] In state 1: If len_temp is greater than use_state_len, the trigger condition is met and a trigger signal is output; if Status_register[signal[1]] corresponding to signal[1] is equal to 1, the recognition state machine of the multi-tube event is set to state 2, and len_temp = len_temp + 1; otherwise, it remains unchanged;

[0062] And so on until len_temp is greater than use_state_len, ultimately achieving the triggering of multi-tube events through the timing combination of use_state_len single-tube events;

[0063] Step 4.3: Synchronize the single-tube event and multi-tube event markers to the status register. The output combinational logic in the logic recognition module reads the marker bits in the status register according to the event selection mode in the configuration register and generates an interrupt signal externally. The interrupt signal triggers the controller to start data acquisition.

[0064] An on-board automatic triggering device capable of realizing dynamic acquisition of inverter status. The on-board automatic triggering device includes an isolation conversion circuit, a threshold conversion circuit, an event capture logic unit, a controller, a memory, an analog switch module, an analog-to-digital conversion module (ADC), and a communication module. The isolation conversion circuit, the threshold conversion circuit, and the number of inverter switching tubes are the same, and there are 6 inverter switching tubes. The differential control signal of each switching tube is converted into a single-ended signal through the isolation conversion circuit, and then a double-threshold comparison trigger pulse is obtained through the threshold conversion circuit. The double-threshold comparison trigger pulse is transmitted to the event capture unit as a basic event for timing recognition to obtain a trigger signal. The trigger signal is input to the controller, and the controller starts the acquisition after being triggered by an external interrupt. The memory is an on-chip storage unit mounted on the controller bus, and the memory is interconnected with the controller. The controller is interconnected with the analog-to-digital conversion module, and the analog-to-digital conversion module performs signal sampling, holding, quantization, and encoding output. The controller configures and reads data from the analog-to-digital conversion module and temporarily stores the data converted by the analog-to-digital conversion module in the buffer area of the memory. The output signal of the analog switch module is connected to the input end of the analog-to-digital conversion module, and the analog switch module switches different channels according to different trigger events to perform signal acquisition. The controller performs peripheral communication through the communication module.

[0065] Furthermore, the analog switch module includes 7 analog switch devices, and each analog switch device has a function of selecting 1 out of 8 channels. The input analog quantity of the analog switch device includes 29 signals of 6 switching tubes in the inverter. The 29 signals include 6 signals of the gate-emitter voltage Vge, 6 signals of the collector-emitter voltage Vc, 6 signals of the collector current Ice, 6 signals of the saturation voltage drop Vce_sat, 1 signal of the bus voltage, 1 signal of the bus current, 1 signal of the U-phase current Iu, 1 signal of the V-phase current Iv, and 1 signal of the W-phase current Iw. Connect the signal to be collected to the analog switch module to achieve data synchronization for multi-channel acquisition;

[0066] Furthermore, in step 5, before the controller receives the interrupt trigger input from the logic recognition module, the following process needs to be completed:

[0067] Step 5.1, the controller initializes itself. After the initialization is completed, it enters the Ethernet communication monitoring state; the initialization includes configuring the working modes of the main frequency, GPIO, interrupt, ADC, SPI, IIC, extended storage bus, and Ethernet interface.

[0068] Step 5.2, if a collection command and parameters are received from the host computer via Ethernet, first write to the asynchronous reset flag in the corresponding event capture register of all switch tubes through the SPI bus, stop all current event capture processes and be in the initial state.

[0069] Step 5.3, according to the collection parameters of the host computer, select the DAC in the switch tube configuration threshold transformation module corresponding to the host computer through IIC. Switch tubes not involved in the collection command do not need to be configured and are directly ignored.

[0070] Step 5.4, according to the collection parameters of the host computer, select the event capture unit of the switch tube corresponding to the host computer through the SPI bus, set the configuration register in the event capture unit, set the event capture unit to the disabled state, and further set the trigger mode and trigger event definition; switch tubes not involved in the collection command do not need to be configured and are directly ignored.

[0071] Step 5.5, clear the existing external interrupt flag of the controller and reset the external trigger working mode of the controller.

[0072] Step 5.6, according to the collection parameters of the host computer, configure the start mode of the analog-to-digital conversion module as external trigger, calculate the sampling rate, conversion accuracy, sampling channel parameters, and write register assignments.

[0073] Step 5.7, according to the collection parameters of the host computer, configure the channel selection of 7 analog switch devices in the analog switch module through the GPIO pin level of the controller.

[0074] Step 5.8, reset the read and write pointers of the data storage circular buffer, and configure the source address and target address of the DMA (Direct Memory Access) of the controller.

[0075] Step 5.9, configure the enable flag bit of the corresponding event capture unit configuration register of the switch tube through the SPI bus, and the event capture becomes the ready state, waiting for the trigger of the event to arrive.

[0076] Step 5.10, after the event trigger arrives, the data collection and storage will be automatically completed. After completion, enter the callback parameters and return the execution result status code.

[0077] Step 5.11, the controller starts to analyze and process the data. After obtaining the fault diagnosis conclusion, it sends the result data and the collected original waveform data to the host computer via Ethernet.

[0078] The controller enables the reception and transmission interrupts of Ethernet, maps the callback function, and after the Ethernet data reception interrupt is triggered, the callback function is used to receive and parse the acquisition commands and parameters of the host computer; the controller configures the registers in the event capture unit through SPI, configures the DAC parameters in the threshold transformation module through IIC, and configures the channel selection of the analog switch device through GPIO; and accepts the commands of the host computer.

[0079] The beneficial effects of the present invention are as follows:

[0080] Based on the on-line acquisition requirements of the dynamic signals of multiple switching tubes of the inverter, the technical solution of automatically triggering and on-line acquiring each switching tube under working conditions can solve the industry problem of difficult capture of dynamic signals for on-line diagnosis of inverter faults, and provide technical guarantee for improving the reliability of new energy products applying inverters;

[0081] The present invention saves costs. A small number of paths and circuits are used to cover the triggering and acquisition of all switching tubes of the inverter, and time-division multiplexing is adopted, which greatly saves costs and reduces the volume. The triggering conditions are programmable and configurable, with strong applicability and flexible use; to a certain extent, it can improve the cost performance and feasibility of the on-line test and evaluation scheme of the electric drive system, and has better market competitiveness;

[0082] The present invention selects the opening signals of the three-phase two-electrode switching tubes of the inverter as a reference, and realizes the multi-functional dynamic acquisition with configurable triggering conditions and selectable trigger sources of the inverter; it can flexibly capture various transient data of the inverter for fault diagnosis and tracking and analysis of the degradation degree, ensure the operation safety and predictive maintenance guarantee of the electric drive system, and has a small volume, adapts to various triggering conditions, and has the value of engineering transformation. Description of the Drawings

[0083] Figure 1 It is a schematic diagram of an inverter for servo drive;

[0084] Figure 2 It is the switching state of the inverter for servo drive;

[0085] Figure 3 It is a composition diagram of an on-line precise triggering and acquisition device for degradation monitoring and evaluation of the inverter switching tube;

[0086] Figure 4 It is a schematic diagram of the function of the isolation circuit transformation module;

[0087] Figure 5 It is a schematic diagram of the function of the threshold change circuit module;

[0088] Figure 6 It is a schematic diagram of the function of the event capture unit;

[0089] Figure 7 It is the logic state machine diagram for generating the basic event waveform;

[0090] Figure 8 It is the schematic diagram for dynamically assigning values to the monitoring signal;

[0091] Figure 9 It is the flowchart for dynamically assigning values to the monitoring signal;

[0092] Figure 10 It is the flowchart for event recognition of multiple tubes;

[0093] Figure 11 It is the flowchart for the main control automatic trigger acquisition. Specific implementation mode

[0094] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation modes.

[0095] As Figure 3 shown:

[0096] An on-board automatic trigger method capable of realizing dynamic acquisition of the inverter state includes the following steps:

[0097] Step 1, obtaining the differential control signal of the inverter switching tube: The differential control signal of the IGBT (Insulated Gate Bipolar Transistor) switching tube is the gate G and the collector E;

[0098] Step 2, inputting the differential control signal into the isolation conversion circuit for amplitude conditioning and optoelectronic isolation conversion processing to obtain a single-ended pulse signal; the amplitude conditioning includes proportional scaling and biasing;

[0099] Step 3, inputting the single-ended pulse signal into the threshold conversion circuit for specific threshold feature recognition and filtering anti-interference to obtain a dual-threshold comparison trigger pulse;

[0100] Step 4, transmitting the dual-threshold comparison trigger pulse as a basic event to the event capture unit, and the event capture unit performs timing recognition on the switching tube to obtain a trigger signal;

[0101] Step 5, inputting the trigger signal into the controller (ARM), and the controller starts the acquisition after being triggered by an external interrupt.

[0102] As Figure 4 shown:

[0103] Furthermore, in step 2, the number of the isolation conversion circuits is the same as the number of the switching tubes; the isolation conversion circuit sequentially includes four parts: a differential amplification module, a voltage biasing module, a linear optoelectronic isolation module, and a voltage amplification and follower module;

[0104] The differential amplification module includes an operational amplifier U89, proportional setting resistors, a capacitor C219, and ports. The port voltages are Vin+ and Vin- respectively. The operational amplifier U89 includes U89A and U89B. The proportional setting resistors include resistors R323, R324, R333, R334, R343, and R349, and R323 + R324 = R333 + R334, R343 = R349. The port voltage Vin+ is successively connected in series with R323 and R324, and after being superimposed with the bias voltage Vbias, it is connected to the positive input terminal of U89A. The positive power input terminal of U89A is simultaneously grounded after being connected in series with the capacitor C219. The port voltage Vin- is successively connected in series with R333 and R334, and after passing through the resistor R334, it is divided into two paths. One path is connected to the negative input terminal of the operational amplifier U89A, and the negative terminal of the operational amplifier U89A is grounded. The other path is connected to the output terminal of the operational amplifier U89A after being connected in series with the resistor R349, forming a negative feedback loop.

[0105] The voltage bias module includes resistors R341 and R347. One end of the resistor R341 is connected to one end of the resistor R347. The other end of the resistor R341 is connected to +5V, and the other end of the resistor R347 is grounded. After voltage division, it is connected to the positive input terminal of the operational amplifier U89B. The output terminal and the negative input terminal of U89B are interconnected to form a voltage follower. The operational amplifier U89B shares the positive and negative power input terminals with U89.

[0106] The linear opto-isolation module includes an isolation device U85, a resistor R327, a resistor R339, a capacitor C223, and a capacitor C227. The pins of the isolation device U85 include a positive input terminal IN+, a negative input terminal IN-, a positive output terminal OUT+, a negative output terminal OUT-, a voltage matching region VDD1, a voltage matching region VDD2, a ground isolation region GNG1, and a ground isolation region GND2. One end of the resistor R327 is connected in series with one end of the resistor R339. The other end of the resistor R327 is connected to the output terminal of the operational amplifier U89A. The other end of the resistor R339 is connected to the digital ground. After secondary voltage division, it is connected in parallel with the capacitor C223 to the ground and is also connected to the positive input terminal IN+ of the isolation device U85. The negative input terminal IN- of the isolation device U85, the other end of the capacitor C223, and the ground isolation region GNG1 are all connected to the digital ground. The voltage matching region VDD1 is connected to one end of the capacitor C227, and the other end of the capacitor C227 is connected to the digital ground.

[0107] The voltage amplification and follower module includes an operational amplifier U90A, configuration resistors, capacitor C228, capacitor C233, and a low-pass filter circuit; the configuration resistors include R329, R337, R344, and R351, and satisfy R329 = R337, R344 = R351; the low-pass filter circuit includes capacitor C225 and resistor R331; one end of resistor R329 is connected to the positive output terminal OUT+ of the isolation device U85, the other end of resistor R329 is connected to the positive input terminal of the operational amplifier U90A, and the other end of resistor R329 is grounded after being serially connected with R344, which is equivalent to setting the bias voltage to 0. The positive power input terminal of the operational amplifier U90A is grounded after being serially connected with capacitor C233 at the same time; one end of resistor R337 is connected to the negative output terminal OUT- of the isolation device U85, the other end of resistor R337 is connected to the negative input terminal of the operational amplifier U90A, and is connected to the output terminal of the operational amplifier U90A after being serially connected with resistor R351 at the same time, forming a feedback path. The negative power input terminal of the operational amplifier U90A is grounded at the same time. One end of R331 is connected to the output terminal of the operational amplifier U90A, and the other end of R331 is grounded after being serially connected with capacitor C225, and the output voltage Vout is output at the same time;

[0108] The isolation conversion circuit processes the differential control signal as follows:

[0109] Step 2.1: The port receives the differential control signal of the switching tube and converts the differential control signal into a single-ended signal. The operational amplifier U89A reduces the voltage of the single-ended signal by a ratio of β1. The reduced voltage range is -1.2 to 2V, and the reduction ratio β1 = R349 / (R323 + R324);

[0110] Step 2.2: The voltage biasing function is realized by setting resistors R341 and R347. The biased voltage range is 0.05V to 3.25V, and the bias voltage Vbias = 5*(R341 / (R341 + R347));

[0111] Step 2.3: By setting resistors R327 and R339, the biased single-ended signal is first reduced by a ratio of β2 and the driving ability is ensured. The reduced voltage range is 0.025V to 1.625V; then it is input to the isolation device U85 for linear opto-isolation. The input range of the isolation device U85 is 0V - 2V; the reduction ratio β2 = R327 / (R327 + R339);

[0112] Step 2.4, the single-ended signal after linear opto-isolation is amplified, restored, and followed by operational amplifier U90A according to the ratio β3, and the amplified voltage range is 0.05V to 3.25V; the amplification ratio β3 = R351 / R329; on the one hand, the voltage amplification and following module cancels the reduction ratio before entering the linear opto-isolation module, and on the other hand, it improves the current driving ability to the threshold transformation circuit to ensure that the current consumption of multiple threshold transformation branches will not cause waveform distortion;

[0113] Step 2.5, the output voltage of the isolation change circuit Vout = (Vbias + ((Vin+) - (Vin-)) * β1) * β2 * β3, and the range of Vout is 0.05V to 3.25V.

[0114] As Figure 5 shown:

[0115] Further, in step 3, the threshold transformation circuit realizes signal threshold feature recognition through configurable comparison voltages to obtain double-threshold comparison trigger pulses;

[0116] The number of the threshold transformation circuits is the same as the number of inverter switch tubes; the threshold change circuit successively includes a multi-channel DAC (Digital-to-Analog Converter), a buffer, a high-speed comparator, and a high-speed opto-coupler; there are 2 high-speed opto-couplers, and the 2 high-speed opto-couplers are the same; the high-speed comparator includes high-speed comparator A and high-speed comparator B, high-speed comparator A is used to realize the comparison trigger of the rising edge, and high-speed comparator B is used to realize the comparison trigger of the falling edge;

[0117] The controller controls the output voltage of the multi-channel DAC through the integrated circuit bus IIC to make the output voltage range from 0V to 3V; the output voltage of the multi-channel DAC is the reference voltage after passing through the buffer, and the reference voltage is used to compare with the single-ended signal;

[0118] The single-ended signals at the output end of the isolation change circuit are connected in parallel and respectively input to the negative terminal of high-speed comparator A and the positive terminal of high-speed comparator B; the reference voltage is respectively input to the positive terminal of high-speed comparator A and the negative terminal of high-speed comparator B; when the positive terminal voltages of high-speed comparator A and high-speed comparator B are both greater than the negative terminal voltages, the threshold transformation circuit outputs a high level, otherwise it outputs a low level;

[0119] The output signal of high-speed comparator A is input to one of the high-speed opto-couplers, and the output signal of high-speed comparator B is input to the other high-speed opto-coupler. After the signal filtering and anti-interference of the high-speed opto-coupler, double-threshold comparison trigger pulses are obtained; the function of the high-speed opto-coupler is to isolate and protect the event capture unit to avoid signal crosstalk in the event capture unit in a harsh electromagnetic environment from causing timing misjudgment.

[0120] As Figure 6 shown:

[0121] Further, in step 4, the event capture unit is implemented based on a Field-Programmable Gate Array (FPGA) for event capture;

[0122] The event capture unit includes an SPI communication interface module (SPI slave), a read / write control timing module, a configuration register module, a status register module, and a logic recognition module;

[0123] The SPI communication interface module is interconnected with the controller through a synchronous clock Clk, a data line MISO, and a data line MOSI; the SPI communication interface module provides a data read / write interface to the controller as a slave device of SPI. Under the beat of the controller's synchronous clock Clk, it serially receives read / write commands, which include read / write identifiers, operation addresses, and operation data information; while responding to the SPI serial communication protocol of the controller, the SPI communication interface module controls the read / write control timing module to address and read / write the configuration register module and the status register module. The read / write control timing module is interconnected with the configuration register module and the status register module in an asynchronous read / write mode. The form of the asynchronous read / write mode interconnection includes an asynchronous clock, a 32-bit data bus, and an 8-bit address bus; the configuration register module and the status register module are implemented in the form of a dual-port random access memory (RAM). The configuration register module and the status register module respectively provide read / write interface data to the read / write control timing module and the logic recognition module at the same time; the logic recognition module writes the running status flag and data into the status register module for the read / write control timing module to read and then send to the controller through the SPI communication interface, forming a two-way data interaction;

[0124] The SPI communication interface module exchanges information with the SPI Master (the master device of SPI) interface of the controller, and the exchanged information includes the content of reading / writing the configuration register and the status register;

[0125] The configuration register module is used to store the configuration parameters of the controller for the event capture logic, and the configuration parameters include trigger enable, mode selection, and event customization;

[0126] The state register module latches the recognition status and count of multiple events of the latch logic recognition module. The state register provides an interface for both the logic recognition module and the read / write control timing module to read and write simultaneously. The logic recognition module and the read / write control timing module each occupy one read / write bus of the dual-port RAM of the state register. The logic recognition module writes event tags triggered in real time by the differential control signal of the switch tube, and the read / write control timing module writes the clear and manual trigger tags of the controller. The clear of the controller is used to clear the original trigger state, wait for the writing of the new trigger state and hold it. The manual trigger tag is only used in the debug mode, and the forced trigger is achieved by actively writing the status flag by the controller for acquisition testing. The priority of the manual trigger is higher than that of the trigger of the logic recognition module, and the switching of the manual trigger mode is determined by the manual mode control bit of the configuration register. When the manual mode control bit of the configuration register enables the manual trigger mode, the trigger result of the logic recognition module will be masked, and no write operation to the state register module will occur.

[0127] The logic recognition module performs timing recognition based on the dual-threshold trigger pulse of the switch tube to capture various events of the switch tube, and the captured event results are latched into the state register module. The combined output logic of the logic recognition module outputs a trigger interrupt signal to the controller according to the event tags in the current state register module and in combination with the trigger enable, mode, and event customization source configuration in the configuration register module.

[0128] As Figure 7 shown:

[0129] Furthermore, the timing recognition includes single-tube timing recognition and multi-tube combined timing recognition;

[0130] The single-tube timing recognition first generates a basic event waveform based on the dual-threshold trigger pulse of a single switch tube, and then realizes the event recognition of the single-tube jump trigger and stable trigger according to the rising edge and falling edge of the basic event waveform of the single-ended signal. The multi-tube combined timing recognition is based on the single-tube timing recognition of multiple tubes. Based on the jump trigger and stable trigger events of the multi-tube basic event waveform, a state machine is used for strict timing discrimination to realize the triggering of complex events that meet the multi-tube timing conditions.

[0131] Step 4.1, the process of single-tube timing recognition is as follows:

[0132] First, the generation of the basic event waveform:

[0133] The dual-threshold comparison trigger pulse of the single tube is input to the logic recognition module. The dual-threshold comparison trigger pulse includes the first trigger pulse VH and the second trigger pulse VL. The basic event waveform is generated by a finite element state machine;

[0134] The finite element state machine uses asynchronous reset and sets the finite element state machine to the idle state;

[0135] When the finite element state machine is in the idle state, the basic event waveform is at a low level; when there is a transition from low to high level of VH, the finite element state machine changes to state 1, otherwise it remains unchanged;

[0136] When the finite element state machine is in state 1, the basic event waveform is at a high level. When there is a transition from low to high level of VL, the finite element state machine changes to state 0, otherwise it remains unchanged;

[0137] When the finite element state machine is in state 0, the basic event waveform is at a low level. When there is a transition from low to high level of VH, the finite element state machine changes to state 1, otherwise it remains unchanged;

[0138] Secondly, single switch tube event recognition:

[0139] The high-speed clock is used to distinguish the basic event waveform. In each cycle of the high-speed clock, the current state now_state is temporarily stored in the previous state pre_state, and then the current basic event waveform level is read out and assigned to pre_state to identify the rising edge transition, falling edge transition and stable state of high and low levels of the basic event waveform;

[0140] The rising edge transition trigger:

[0141] If pre_state is at a low level and now_state is at a high level, the rising edge transition flag bit of the single tube in the state register module is set to 1 and remains so until the controller clears it through SPI;

[0142] The falling edge transition trigger:

[0143] If pre_state is at a high level and now_state is at a low level, the falling edge transition flag bit of the single tube in the state register module is set to 1 and remains so until the controller clears it through SPI;

[0144] The high and low level trigger:

[0145] If now_state is at a high level, the single tube level flag bit in the state register module is set to 1;

[0146] If now_state is at a low level, the single tube level flag bit in the state register module is set to 0;

[0147] Step 4.2, the multi-tube combination timing recognition process is as follows:

[0148] First, establish a general timing recognition framework. The general timing recognition framework includes the following general variables:

[0149] The maximum multi-tube timing state length max_state_len is a constant; the effective multi-tube timing state length use_state_len is defined in the configuration register module; max_state_len signal variables signal[max_state_len] are defined in the configuration register; a total of use_state_len single-tube events from signal[0] to signal[use_state_len - 1] represent a multi-tube event, occurring in sequence according to the order of signal[0] to signal[use_state_len - 1]. The coordinates index of the single-tube events stored in signal[0] to signal[use_state_len - 1], and Status_register is the single-switch-tube status register in the status register module; each single-switch-tube event is defined according to the coordinate values in Table 1. For example, V T1 For a single-tube event triggered by a rising edge, index = 0, indicating that Status_register[0] corresponds to V T1 For a rising-edge trigger event, and so on for others;

[0150] Table 1 Coordinate definition of single-tube events

[0151]

[0152] Then, write the effective multi-tube timing state length to use_state_len in the configuration register through the SPI communication bus of the controller, and write the single-tube event index to signal[0] to signal[use_state_len - 1] in sequence to complete the definition of the multi-tube event, as Figure 8 shown;

[0153] Finally, use a finite state machine as the multi-tube event recognition state machine, and the multi-tube event recognition state machine uses asynchronous reset; set the multi-tube event recognition state machine to the idle state, define an event traversal count variable len_temp to count the number of state transitions, and assign an initial value of 0;

[0154] In the idle state: If len_temp is greater than use_state_len, the trigger condition is met and a trigger signal is output; if Status_register[signal[0]] corresponding to signal[0] is equal to 1, the recognition state machine of the multi-tube event is set to state 1, and len_temp = len_temp + 1; otherwise, it remains unchanged;

[0155] In state 1: If len_temp is greater than use_state_len, the trigger condition is met and a trigger signal is output; if the Status_register[signal[1]] corresponding to signal[1] is equal to 1, the recognition state machine of the multi-tube event is set to state 2, and len_temp = len_temp + 1; otherwise, it remains unchanged.

[0156] And so on until len_temp is greater than use_state_len, finally realizing the triggering of multi-tube events by the time sequence combination of use_state_len single-tube events.

[0157] Step 4.3: Synchronize the single-tube event and multi-tube event marks to the status register. The output combinational logic in the logic recognition module reads the mark bits in the status register according to the event selection mode in the configuration register and generates an interrupt signal externally. The interrupt signal triggers the controller to start data acquisition.

[0158] An on-board automatic trigger device capable of realizing dynamic acquisition of the inverter state. The on-board automatic trigger device includes an isolation conversion circuit, a threshold conversion circuit, an event capture logic unit, a controller, a memory, an analog switch module, an analog-to-digital conversion module (ADC), and a communication module; the isolation conversion circuit, the threshold conversion circuit, and the number of inverter switching tubes are the same, and there are 6 inverter switching tubes; the differential control signal of each switching tube is converted into a single-ended signal through the isolation conversion circuit, and then a dual-threshold comparison trigger pulse is obtained through the threshold conversion circuit. The dual-threshold comparison trigger pulse is transmitted to the event capture unit as a basic event for time sequence recognition to obtain a trigger signal; the trigger signal is input to the controller, and the controller starts acquisition after being triggered by an external interrupt; the memory is an on-chip storage unit mounted on the controller bus, and the memory is interconnected with the controller; the controller is interconnected with the analog-to-digital conversion module, and the analog-to-digital conversion module performs signal sampling, holding, quantization, and encoding output; the controller configures and reads data from the analog-to-digital conversion module, and temporarily stores the data converted by the analog-to-digital conversion module in the buffer area of the memory; the output signal of the analog switch module is connected to the input end of the analog-to-digital conversion module, and the analog switch module switches different channels according to different trigger events to perform signal acquisition; the controller performs peripheral communication through the communication module.

[0159] Further, the analog switch module includes 7 analog switch devices, and each analog switch device has the function of selecting 1 out of 8 channels; the input analog quantity of the analog switch device includes 29 signals of 6 switching tubes in the inverter; the 29 signals include 6 signals of gate-emitter voltage Vge, 6 signals of collector-emitter voltage Vc, 6 signals of collector current Ice, 6 signals of saturation voltage drop Vce_sat, 1 signal of bus voltage, 1 signal of bus current, 1 signal of U-phase current Iu, 1 signal of V-phase current Iv, and 1 signal of W-phase current Iw; the signal to be collected is connected to the analog switch module to realize data synchronization of multi-channel acquisition; the mapping relationship between the analog quantity and the analog switch device is shown in Table 2 below:

[0160] Table 2 Mapping Relationship between Analog Quantity and Analog Switch Device

[0161]

[0162] As Figure 11 shown:

[0163] Further, in step 5, before the controller receives the interrupt trigger input by the logic recognition module, the following processes need to be completed:

[0164] Step 5.1, the controller initializes itself and enters the Ethernet communication listening state after initialization; the initialization includes configuring the working modes of the main frequency, GPIO, interrupt, ADC, SPI, IIC, extended storage bus, and Ethernet interface;

[0165] Step 5.2, if the acquisition command and parameters sent by the host computer are received from the Ethernet, first write the asynchronous reset flag to the corresponding event capture register of all switching tubes through the SPI bus, stop all current event capture processes and be in the initial state;

[0166] Step 5.3, according to the acquisition parameters of the host computer, select the DAC in the switching tube configuration threshold transformation module corresponding to the host computer through IIC, and the switching tubes not involved in the acquisition command do not need to be configured and are directly ignored;

[0167] Step 5.4, according to the acquisition parameters of the host computer, select the event capture unit of the switching tube corresponding to the host computer through the SPI bus, set the configuration register in the event capture unit, set the event capture unit to the non-enabled state, and further set the trigger mode and trigger event definition; the switching tubes not involved in the acquisition command do not need to be configured and are directly ignored;

[0168] Step 5.5, clear the existing external interrupt flag of the controller and reset the external trigger working mode of the controller;

[0169] Step 5.6: According to the acquisition parameters of the host computer, configure the start mode of the analog-to-digital conversion module as external trigger, calculate the sampling rate, conversion accuracy, sampling channel parameters, and write register assignments.

[0170] Step 5.7: According to the acquisition parameters of the host computer, perform channel selection configuration on 7 analog switch devices in the analog switch module through the GPIO pin levels of the controller.

[0171] Step 5.8: Reset the read and write pointers of the data storage circular buffer, and configure the source address and destination address of the DMA (Direct Memory Access) of the controller.

[0172] Step 5.9: Configure the enable flag bit of the corresponding event capture unit configuration register of the switch tube through the SPI bus, the event capture becomes the ready state, and waits for the trigger of the event to arrive.

[0173] Step 5.10: After the event trigger arrives, the data acquisition and storage will be automatically completed. After completion, enter the callback parameters and return the execution result status code.

[0174] Step 5.11: The controller starts to analyze and process the data. After obtaining the fault diagnosis conclusion, it sends the result data and the collected original waveform data to the host computer through the Ethernet.

[0175] The controller enables the receive and transmit interrupts of the Ethernet, maps the callback function, and the callback function is used to receive and parse the acquisition commands and parameters of the host computer after the Ethernet receive data receive interrupt is triggered; the controller configures the registers in the event capture unit through the SPI, configures the DAC parameters in the threshold transformation module through the IIC, and configures the channel selection of the analog switch device through the GPIO; accepts the commands of the host computer.

Claims

1. An onboard automatic triggering method capable of realizing dynamic acquisition of inverter status, characterized in that: The onboard automatic triggering method comprises the following steps: Step 1, obtaining the differential control signal of the inverter switch tube: the differential control signal of the IGBT switch tube is the gate G and the collector E; Step 2, inputting the differential control signal into the isolation conversion circuit for amplitude conditioning and photoelectric isolation conversion processing to obtain a single-ended pulse signal; the amplitude conditioning includes scaling and offset; Step 3, inputting the single-ended pulse signal into a threshold conversion circuit for specific threshold feature recognition and filtering anti-interference, and obtaining a dual-threshold comparison trigger pulse; Step 4, transmitting the dual threshold comparison trigger pulse as a basic event to the event capture unit, and the event capture unit performs timing recognition on the switch tube to obtain a trigger signal; Step 5: Input the trigger signal to the controller, and the controller starts the acquisition after being triggered by an external interrupt.

2. The onboard automatic triggering method according to claim 1, characterized in that: In step 2, the number of the isolation conversion circuits is the same as the number of switch tubes; the isolation conversion circuit includes four parts in sequence: a differential amplifier module, a voltage bias module, a linear photoelectric isolation module and a voltage amplifier follower module; The differential amplifier module includes an operational amplifier U89, a proportional setting resistor, a capacitor C219 and a port, the port voltages are Vin+ and Vin- respectively, the operational amplifier U89 includes U89A and U89B, the proportional setting resistors include resistors R323, R324, R333, R334, R343 and R349, and satisfy R323+R324=R333+R334, R343=R349; the port voltage Vin+ is connected in series with R323 and R32 4 in series, and then superimposed with the bias voltage Vbias, connected to the positive input terminal of U89A. The positive input terminal of the power supply of U89A is connected in series with capacitor C219 and then grounded. The port voltage Vin- is connected in series with R333 and R334 in sequence, and then divided into two paths after resistor R334. One path is connected to the negative input terminal of the operational amplifier U89A, and the negative terminal of the operational amplifier U89A is grounded. The other path is connected in series with resistor R349 and then connected to the output terminal of the operational amplifier U89A, forming a negative feedback loop. The voltage bias module includes resistors R341 and R347; one end of the resistor R341 is connected to one end of the resistor R347, the other end of the resistor R341 is connected to +5V, the other end of the resistor R347 is grounded, and after voltage division, is connected to the positive input end of the operational amplifier U89B; the output end and the negative input end of U89B are interconnected to form a voltage follower, and the operational amplifier U89B and U89A share the positive and negative input ends of the power supply; The linear photoelectric isolation module includes an isolation device U85, a resistor R327, a resistor R339, a capacitor C223 and a capacitor C227; the pins of the isolation device U85 include a positive input terminal IN+, a negative input terminal IN-, a positive output terminal OUT+, a negative output terminal OUT-, a voltage matching area VDD1, a voltage matching area VDD2, a ground isolation area GNG1 and a ground isolation area GND2; one end of the resistor R327 is connected in series with one end of the resistor R339, the other end of the resistor R327 is connected to the output end of the operational amplifier U89A, the other end of the resistor R339 is connected to the digital ground, after secondary voltage division, it is connected to the ground after being connected in parallel with the capacitor C223, and is connected to the positive input terminal IN+ of the isolation device U85; the negative input terminal IN- of the isolation device U85, the other end of the capacitor C223, and the ground isolation area GNG1 are all connected to the digital ground; the voltage matching area VDD1 is connected to one end of the capacitor C227, and the other end of the capacitor C227 is connected to the digital ground; The voltage amplifier follower module includes an operational amplifier U90A, a configuration resistor, a capacitor C228, a capacitor C233 and a low-pass filter circuit; the configuration resistors include R329, R337, R344 and R351, and satisfy R329=R337, R344=R351; the low-pass filter circuit includes a capacitor C225 and a resistor R331; one end of the resistor R329 is connected to the positive output terminal OUT+ of the isolation device U85, and the other end of the resistor R329 is connected to the positive input terminal of the operational amplifier U90A, The other end of the resistor R329 is connected in series with R344 and then grounded, which is equivalent to setting the bias voltage to 0. The positive power input terminal of the operational amplifier U90A is connected in series with the capacitor C233 and then grounded; one end of the resistor R337 is connected to the negative output terminal OUT- of the isolation device U85, and the other end of the resistor R337 is connected to the negative input terminal of the operational amplifier U90A, and is connected in series with the resistor R351 and then connected to the output terminal of the operational amplifier U90A to form a feedback path. The negative power input terminal of the operational amplifier U90A is grounded at the same time, one end of R331 is connected to the output terminal of the operational amplifier U90A, and the other end of R331 is connected in series with the capacitor C225 and then grounded, and the output voltage Vout is output at the same time; The isolation conversion circuit processes the differential control signal in the following steps: Step 2.1, the port receives the differential control signal of the switch tube and converts the differential control signal into a single-ended signal. The operational amplifier U89A reduces the voltage of the single-ended signal by a ratio of β1. The reduced voltage range is -1.2 to 2V. The reduction ratio β1=R349 / (R323+R324); Step 2.2, realize the voltage bias function by setting the resistors R341 and R347, the biased voltage range is 0.05V to 3.25V, and the bias voltage Vbias=5*(R341 / (R341+R347)); Step 2.3, by setting the resistors R327 and R339, the biased single-ended signal is first reduced by a ratio of β2 and the driving capability is guaranteed. The reduced voltage range is 0.025V to 1.625V; then it is input to the isolation device U85 for linear photoelectric isolation. The input range of the isolation device U85 is 0V-2V; the reduction ratio β2=R327 / (R327+R339); Step 2.4, the single-ended signal after linear photoelectric isolation is amplified, restored and followed by the operational amplifier U90A at a ratio of β3, and the voltage range after amplification is 0.05V to 3.25V; the amplification ratio β3 = R351 / R329; the voltage amplification and following module offsets the reduction ratio before entering the linear photoelectric isolation module on the one hand, and improves the current driving capability to the threshold conversion circuit on the other hand, ensuring that multiple threshold conversion branches will not cause waveform distortion on current consumption; Step 2.5, the output voltage Vout of the isolation variation circuit is Vbias+((Vin+) - (Vin-))*β1)*β2*β3, and the range of Vout is 0.05V to 3.25V.

3. The onboard automatic triggering method according to claim 1, characterized in that: In step 3, the threshold conversion circuit realizes signal threshold feature recognition through a configurable comparison voltage to obtain a dual-threshold comparison trigger pulse; The number of the threshold conversion circuits is the same as the number of inverter switch tubes; the threshold change circuit includes a multi-channel DAC, a buffer, a high-speed comparator and a high-speed optocoupler in sequence; there are two high-speed optocouplers, and the two high-speed optocouplers are the same; the high-speed comparator includes a high-speed comparator A and a high-speed comparator B, the high-speed comparator A is used to realize the comparison trigger of the rising edge, and the high-speed comparator B is used to realize the comparison trigger of the falling edge; The controller controls the output voltage of the multi-channel DAC through the integrated circuit bus IIC, so that the output voltage range is 0V-3V; The output voltage of the multi-channel DAC is a reference voltage after passing through a buffer, and the reference voltage is used to compare with the single-ended signal; The single-ended signal at the output end of the isolation change circuit is input in parallel to the negative end of the high-speed comparator A and the positive end of the high-speed comparator B respectively; the reference voltage is input to the positive end of the high-speed comparator A and the negative end of the high-speed comparator B respectively; when the positive end voltages of the high-speed comparator A and the high-speed comparator B are both greater than the negative end voltages, the threshold conversion circuit outputs a high level, otherwise it outputs a low level; The output signal of high-speed comparator A is input to one of the high-speed optocouplers, and the output signal of high-speed comparator B is input to the other high-speed optocoupler. After the signal filtering and anti-interference of the high-speed optocoupler, a dual-threshold comparison trigger pulse is obtained; the function of the high-speed optocoupler is to isolate and protect the event capture unit to avoid timing misjudgment caused by signal crosstalk in the event capture unit in a harsh electromagnetic environment.

4. The onboard automatic triggering method according to claim 1, characterized in that: In step 4, the event capture unit realizes event capture based on a programmable logic device; The event capture unit includes an SPI communication interface module, a read-write control timing module, a configuration register module, a status register module and a logic identification module; The SPI communication interface module is interconnected with the controller through the synchronous clock Clk, the data line MISO and the data line MOSI; the SPI communication interface module, as a slave device of the SPI, provides a data read and write interface to the controller, and receives read and write commands in serial under the beat of the synchronous clock Clk of the controller, and the read and write commands include read and write identification, operation address and operation data information; while responding to the SPI serial communication protocol of the controller, the SPI communication interface module controls the read and write control timing module to address and read and write the configuration register module and the status register module, and the read and write control timing module is interconnected with the configuration register module and the status register module respectively in an asynchronous read and write mode, and the asynchronous read and write mode interconnection form includes an asynchronous clock, a 32-bit data bus and an 8-position address bus; the configuration register module and the status register module are implemented in a dual-port RAM manner, and the configuration register module and the status register module provide read and write interface data for the read and write control timing module and the logic identification module respectively at the same time; the logic identification module writes the operation status mark and data into the status register module, which are read by the read and write control timing module and then sent to the controller through the SPI communication interface to form a two-way data interaction; The SPI communication interface module exchanges information with the SPI Master interface of the controller, and the exchanged information includes reading and writing the contents of the configuration register and the status register; The configuration register module is used to store the configuration parameters of the controller for the event capture logic, and the configuration parameters include trigger enable, mode selection and event customization; The state register module latches the identification status and times of various events of the logic identification module. The state register provides an interface for the logic identification module and the read-write control timing module to read and write simultaneously. The logic identification module and the read-write control timing module each occupy a read-write bus of the state register dual-port RAM. The logic identification module writes the event mark triggered in real time by the differential control signal of the switch tube, and the read-write control timing module writes the controller's reset and manual trigger mark; the controller reset is used to clear the original trigger state, wait for the new trigger state to be written and maintained; the manual trigger mark is only used for the debugging mode, and the controller actively writes the state mark to achieve forced triggering, which is used for acquisition testing; the priority of manual triggering is higher than that of logic identification module triggering, and the switching of manual triggering mode is determined by the manual mode control bit of the configuration register; when the manual mode control bit of the configuration register is enabled in the manual triggering mode, the trigger result of the logic identification module will be shielded, and no write operation to the state register module will occur; The logic identification module performs timing identification according to the dual-threshold trigger pulse of the switch tube, realizes the capture of various events of the switch tube, and latches the captured event results into the status register module; The combinational output logic of the logic identification module outputs a trigger interrupt signal to the controller according to the event mark in the current status register module and in combination with the trigger enable, mode and event customized source configuration in the configuration register module.

5. The onboard automatic triggering method according to claim 4, characterized in that: The timing identification includes single-tube timing identification and multi-tube combination timing identification; The single-tube timing recognition first generates a basic event waveform based on a single switch tube double-threshold trigger pulse, and then realizes the event recognition of the jump trigger and stable trigger of the single tube according to the rising edge and falling edge of the basic event waveform of the single-ended signal; the multi-tube combination timing recognition is based on the jump trigger and stable trigger events of the multi-tube basic event waveform on the basis of multiple single-tube timing recognitions, and uses the state machine to perform strict timing identification to realize complex event triggering that meets the multi-tube timing conditions; Step 4.1, the single-tube timing identification process is as follows: First, the basic event waveform is generated: The dual-threshold comparison trigger pulse of a single tube is input to the logic recognition module, and the dual-threshold comparison trigger pulse includes VH and VL; the basic event waveform is generated through the finite element state machine; The finite element state machine adopts asynchronous reset, and sets the finite element state machine to an idle state; When the finite element state machine is idle, the basic event waveform is low level; when VH jumps from low to high level, the finite element state machine changes to state 1, otherwise it remains unchanged; When the finite element state machine is in state 1, the basic event waveform is at a high level. When VL jumps from a low level to a high level, the finite element state machine changes to state 0, otherwise it remains unchanged. When the finite element state machine is in state 0, the basic event waveform is at a low level. When VH jumps from a low level to a high level, the finite element state machine changes to state 1, otherwise it remains unchanged. Secondly, single switch event identification: A high-speed clock is used to distinguish the basic event waveform. In each cycle of the high-speed clock, now_state is temporarily stored in pre_state, and then the current basic event waveform level is read out and assigned to pre_state, and the rising edge jump, falling edge jump and high and low level stable state of the basic event waveform are identified; The rising edge transition trigger: If pre_state is low and now_state is high, the rising edge transition flag of the single tube in the status register module is set to 1 and remains set until the controller performs a clear operation through SPI; The falling edge transition trigger: If pre_state is high and now_state is low, the falling edge transition flag of the single tube in the status register module is set to 1 and remains until the controller performs a clear operation through SPI; The high and low level trigger: If now_state is high, the single-tube level flag in the status register module is set to 1; If now_state is low, the single-tube level flag in the status register module is set to 0; Step 4.2, the multi-tube combination timing identification process is as follows: First, a general time series recognition framework is established, which includes the following general variables: The maximum multi-tube timing state length max_state_len is a constant; the effective multi-tube timing state length use_state_len is defined in the configuration register module; max_state_len signal variables signal[max_state_len] are defined in the configuration register; signal[0] to signal[use_state_len-1], a total of use_state_len single-tube events, represent a multi-tube event, which occurs in the order of signal[0] to signal[use_state_len-1]. The coordinate index of the single-tube event stored in signal[0] to signal[use_state_len-1], Status_register is the single switch tube status register in the status register module; Then, write the valid multi-tube timing state length to the use_state_len in the configuration register through the controller's SPI communication bus, and write the single-tube event index to signal[0] to signal[use_state_len-1] in sequence to complete the definition of the multi-tube event; Finally, a finite element state machine is used as the multi-tube event recognition state machine, and the multi-tube event recognition state machine adopts asynchronous reset; Set the multi-channel event recognition state machine to the idle state, define the event traversal count variable len_temp to count the number of state transitions, and assign an initial value of 0; In idle state: if len_temp is greater than use_state_len, the trigger condition is met and a trigger signal is output; If Status_register[signal[0]] corresponding to signal[0] is equal to 1, the recognition state machine of the state multi-channel event is set to state 1, len_temp=len_temp+1; otherwise it remains unchanged; In state 1: if len_temp is greater than use_state_len, the trigger condition is met and a trigger signal is output; If Status_register[signal[1]] corresponding to signal[1] is equal to 1, the recognition state machine of the state multi-tube event is set to state 2, len_temp=len_temp+1; otherwise it remains unchanged; And so on, until len_temp is greater than use_state_len, and finally the multi-tube event triggering of use_state_len single-tube event timing combinations is realized; Step 4.3, synchronize the single-tube event and multi-tube event marks to the status register. The output combination logic in the logic recognition module reads the mark bit in the status register according to the event selection mode in the configuration register to generate an interrupt signal to the outside. The interrupt signal triggers the controller to start data collection.

6. The onboard automatic triggering method according to claim 1, characterized in that: In step 5, the controller needs to complete the following process before receiving the interrupt trigger input by the logic identification module: Step 5.1, the controller initializes itself, and enters the Ethernet communication monitoring state after completing the initialization; the initialization includes configuring the working mode of the main frequency, GPIO, interrupt, ADC, SPI, IIC, extended storage bus and Ethernet interface; Step 5.2: If the acquisition command and parameters are received from the host computer through Ethernet, firstly, the asynchronous reset flag in the event capturer configuration register corresponding to all switch tubes is written through the SPI bus to stop all current event capture processes and enter the initial state; Step 5.3, according to the acquisition parameters of the host computer, select the switch tube corresponding to the host computer through IIC to configure the DAC in the threshold conversion module. The switch tube not involved in the acquisition command does not need to be configured and is directly ignored; Step 5.4, according to the acquisition parameters of the host computer, select the event capture unit of the switch tube corresponding to the host computer through the SPI bus, set the configuration register in the event capture unit, set the event capture unit to the disabled state, further set the trigger mode, and trigger the event definition; the switch tube not involved in the acquisition command does not need to be configured and is directly ignored; Step 5.5, clear the existing external interrupt flag of the controller and reset the external trigger working mode of the controller; Step 5.6, according to the acquisition parameters of the host computer, configure the startup mode of the analog-to-digital conversion module to external trigger, calculate the sampling rate, conversion accuracy, sampling channel parameters and write register assignments; Step 5.7, according to the acquisition parameters of the host computer, the 7 analog switch devices in the analog switch module are configured for channel selection through the GPIO pin level of the controller; Step 5.8, reset the read and write pointers of the data storage ring buffer, and configure the controller's DMA (direct memory access) source address and destination address; Step 5.9, configure the enable flag bit of the event capture unit configuration register corresponding to the switch tube through the SPI bus, and the event capture becomes ready, waiting for the event to be triggered; Step 5.10: When the event is triggered, data collection and storage will be completed automatically. After completion, the callback parameters will be entered and the execution result status code will be returned. Step 5.11, the controller starts to analyze and process the data, and after obtaining the fault diagnosis conclusion, it sends the result data and the collected original waveform data to the host computer via Ethernet; The controller enables Ethernet reception and transmission interrupts, maps callback functions, and after Ethernet data reception interrupt is triggered, the callback function is used to receive and parse acquisition commands and parameters of the host computer; the controller configures registers in the event capture unit through SPI, configures DAC parameters in the threshold conversion module through IIC, and configures channel selection of the analog switch device through GPIO; and accepts commands from the host computer.

7. An onboard automatic triggering device for executing the method according to any one of claims 1 to 6, characterized in that: The onboard automatic trigger device includes an isolation conversion circuit, a threshold conversion circuit, an event capture logic unit, a controller, a memory, an analog switch module, an analog-to-digital conversion module and a communication module; the number of the isolation conversion circuit, the threshold conversion circuit and the inverter switch tubes is the same, and the inverter switch tubes have 6; the differential control signal of each switch tube is converted into a single-ended signal through the isolation conversion circuit, and then a dual-threshold comparison trigger pulse is obtained through the threshold conversion circuit. The dual-threshold comparison trigger pulse is transmitted to the event capture unit as a basic event for timing identification to obtain a trigger signal; the trigger signal is input to the controller, and the controller starts the acquisition after being triggered by an external interrupt; The memory is an on-chip storage unit mounted on the controller bus, and the memory is interconnected with the controller; the controller is interconnected with the analog-to-digital conversion module, and the analog-to-digital conversion module performs signal sampling, holding, quantization and encoding output; the controller configures the analog-to-digital conversion module and reads data, and temporarily stores the data converted by the analog-to-digital conversion module in the cache area of ​​the memory; the output signal of the analog switch module is connected to the input end of the analog-to-digital conversion module, and the analog switch module switches different channels according to different trigger events to perform signal acquisition; the controller performs peripheral communication through the communication module.

8. The onboard automatic triggering device according to claim 7, characterized in that: The analog switch module includes 7 analog switch devices, each of which has the function of selecting 1 out of 8 channels; the input analog quantity of the analog switch device includes 29 signals of 6 switch tubes in the inverter; The 29 signals include 6 signals of gate-emitter voltage Vge, 6 signals of collector-emitter voltage Vc, 6 signals of collector current Ice, 6 signals of saturation voltage drop Vce_sat, 1 signal of bus voltage, 1 signal of bus current, 1 signal of U-phase current Iu, 1 signal of V-phase current Iv and 1 signal of W-phase current Iw; The signal to be collected is connected to the analog switch module to achieve data synchronization of multi-channel collection.

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