Semiconductor test system, design method, test method and test device

Abstract

The invention discloses a semiconductor test system, a design method, a test method, a test device, test equipment and a computer readable storage medium. The semiconductor test system includes a plurality of semiconductor test devices. Each semiconductor test device includes a semiconductor field effect transistor and an antenna layer. The semiconductor field effect transistor includes a substrate and a gate disposed on the substrate. The antenna layer is connected with the grid. Structural designs of the plurality of semiconductor test devices are different, and the different structural designs include that positions of the antenna layers are different; and / or the antenna ratios of the antenna layers are different; and / or a protection diode is arranged between the grid electrode and the substrate. Thus, by systematically designing a plurality of semiconductor test devices of different structures, the source of the P2ID problem can be systematically positioned based on different positions of the plurality of semiconductor test devices, different positions of the antenna layers, and / or different antenna ratios of the antenna layers, and / or whether a protection diode is arranged between the grid electrode and the substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technologies, and particularly relates to a semiconductor testing system, a design method, a testing method, a testing device, a testing equipment, and a computer-readable storage medium. Background Art

[0002] In the process of semiconductor manufacturing, the plasma process plays a crucial role. Plasma is a mixed gas composed of ions and electrons, and is generally quasi-neutral. When a certain external interference disrupts the balance of the plasma, the plasma may generate a self-bias voltage or even an induced current, thereby causing damage to the manufactured device. The damage caused by the plasma process is simply referred to as P2ID (plasma-process induced damage).

[0003] The problem localization of P2ID is a very complex matter, involving multiple factors such as process manufacturing equipment, device design, process manufacturing control, and layout design. As the nanometer process becomes more and more advanced, the complexity of the process steps becomes higher and higher, the possibility of introducing P2ID becomes greater and greater, and the device size becomes smaller and smaller, and the tolerable P2ID dose level gradually decreases, resulting in the P2ID problem becoming more and more serious. At present, the source of the P2ID problem cannot be systematically located. Summary of the Invention

[0004] Embodiments of this application provide a semiconductor testing system, a design method, a testing method, a testing device, a testing equipment, and a computer-readable storage medium to solve at least one of the above-mentioned technical problems.

[0005] The semiconductor testing system according to the embodiments of this application, the semiconductor testing system includes a plurality of semiconductor testing devices, each of the semiconductor testing devices includes a semiconductor field-effect transistor and an antenna layer, the semiconductor field-effect transistor includes a substrate and a gate disposed on the substrate, and the antenna layer is connected to the gate;

[0006] The structural designs among the plurality of semiconductor testing devices are different, and the different structural designs include:

[0007] The positions of the antenna layers are different; and / or

[0008] The antenna ratios of the antenna layers are different; and / or

[0009] Whether a protection diode is disposed between the gate and the substrate.

[0010] In some embodiments, each of the semiconductor test devices further includes a plurality of metal layers and at least one dielectric layer, the plurality of metal layers are sequentially disposed on the semiconductor field effect transistor, and one of the dielectric layers is provided between two adjacent metal layers;

[0011] In each of the semiconductor test devices, the antenna layer is disposed on any one or more of the gate, the plurality of metal layers, and the at least one dielectric layer.

[0012] In some embodiments, in each of the semiconductor test devices, the antenna layer includes any one or more of a first type of antenna layer, a second type of antenna layer, and a third type of antenna layer, and the antenna structures of the first type of antenna layer, the second type of antenna layer, and the third type of antenna layer are different;

[0013] The first type of antenna layer is disposed on any one or more of the gate and the plurality of metal layers;

[0014] The second type of antenna layer is disposed on any one or more of the at least one dielectric layer;

[0015] The third type of antenna layer is disposed on any one or more of the gate and the plurality of metal layers.

[0016] In some embodiments, the first type of antenna layer is a planar structure antenna.

[0017] In some embodiments, the antenna ratio of the planar structure antenna is:

[0018]

[0019] where AR is the antenna ratio, L B is the length of the planar structure antenna, W B is the width of the planar structure antenna, N f is the number of gates, W is the width of the gate, and L is the length of the gate.

[0020] In some embodiments, the second type of antenna layer is a via structure antenna.

[0021] In some embodiments, the via structure antenna includes M rows and N columns of vias, and the antenna ratio of the via structure antenna is:

[0022]

[0023] where AR is the antenna ratio, M is the number of rows of the vias, N is the number of columns of the vias, W v is the side length of the via, N fN is the number of the gates, W is the width of the gates, and L is the length of the gates.

[0024] In some embodiments, the third type of antenna layer is a comb-shaped antenna.

[0025] In some embodiments, the comb-shaped antenna includes a comb handle portion and a plurality of comb teeth portions extending from the comb handle portion. The antenna ratio of the comb-shaped antenna is:

[0026]

[0027] where AR is the antenna ratio, t a is the thickness of the comb-shaped antenna, N is the number of the comb teeth portions, L b is the length of the comb teeth portions, W c is the width of the comb teeth portions, W b is the spacing between two adjacent comb teeth portions, N f is the number of the gates, W is the width of the gates, and L is the length of the gates.

[0028] The design method of the semiconductor test system according to the embodiments of the present application includes:

[0029] Fabricating a plurality of semiconductor test devices with different structural designs. Each semiconductor test device includes a semiconductor field effect transistor and an antenna layer. The semiconductor field effect transistor includes a substrate and a gate disposed on the substrate, and the antenna layer is connected to the gate. The different structural designs include:

[0030] The positions of the antenna layers are different; and / or

[0031] The antenna ratios of the antenna layers are different; and / or

[0032] Whether a protection diode is disposed between the gate and the substrate.

[0033] The test method according to the embodiments of the present application is applied to the semiconductor test system in any of the above embodiments. The test method includes:

[0034] Performing a plasma damage test on the plurality of semiconductor test devices;

[0035] Determining the plasma damage test results based on the different structural designs among the plurality of semiconductor test devices.

[0036] In some embodiments, performing the plasma damage test on the plurality of semiconductor test devices includes:

[0037] Applying a predetermined voltage to the gate of each semiconductor test device;

[0038] Obtain the leakage current of the gate;

[0039] Determining the plasma damage test result based on different structural designs among the multiple semiconductor test devices includes:

[0040] Based on different structural designs among the multiple semiconductor test devices, determine the plasma damage test result according to the leakage current.

[0041] The test device according to the embodiment of the present application is characterized in that it is applied to the semiconductor test system of any of the above embodiments, and the test device includes:

[0042] A test module for performing plasma damage tests on the multiple semiconductor test devices;

[0043] A determination module for determining the plasma damage test result based on different structural designs among the multiple semiconductor test devices.

[0044] The test equipment according to the embodiment of the present application, the test equipment includes one or more processors and a memory, the memory stores a computer program, and when the computer program is executed by the processor, the test method of any of the above embodiments is implemented.

[0045] The computer-readable storage medium according to the embodiment of the present application, on which a computer program is stored, and when the program is executed by a processor, the test method of any of the above embodiments is implemented.

[0046] In the semiconductor test system, design method, test method, test device, test equipment and computer-readable storage medium according to the embodiments of the present application, by systematically designing multiple semiconductor test devices with different structures, based on the different positions of the antenna layer, and / or different antenna ratios of the antenna layer, and / or whether a protection diode is provided between the gate and the substrate among the multiple semiconductor test devices, the source of the P2ID problem can be systematically located.

[0047] The additional aspects and advantages of the embodiments of the present application will be partially given in the following description, partially will become obvious from the following description, or will be understood through the practice of the embodiments of the present application. Description of the Drawings

[0048] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, where:

[0049] Figure 1 is a schematic diagram of the modules of the semiconductor test system of certain embodiments of the present application;

[0050] Figure 2 is a cross-sectional schematic diagram of a semiconductor test device according to some embodiments of the present application;

[0051] Figure 3 is a schematic diagram of a planar structure antenna provided in a semiconductor test device according to some embodiments of the present application;

[0052] Figure 4 is a schematic diagram of a hole structure antenna provided in a semiconductor test device according to some embodiments of the present application;

[0053] Figure 5 is a schematic diagram of a comb structure antenna provided in a semiconductor test device according to some embodiments of the present application;

[0054] Figure 6 is a schematic flow diagram of a test method according to some embodiments of the present application;

[0055] Figure 7 is a schematic flow diagram of a test method according to some embodiments of the present application;

[0056] Figure 8 is a schematic block diagram of a test device according to some embodiments of the present application;

[0057] Figure 9 is a schematic block diagram of a test equipment according to some embodiments of the present application;

[0058] Figure 10 is a schematic diagram of the connection state between a computer-readable storage medium and a processor according to some embodiments of the present application.

[0059] Description of reference numerals:

[0060] Semiconductor test system 1000, semiconductor test device 100, semiconductor field effect transistor 10, substrate 11, gate 12, source 13, drain 14, antenna layer 20, first type antenna layer 21, second type antenna layer 22, via 221, third type antenna layer 23, comb handle part 231, comb tooth part 232, protection diode 30, metal layer 40, dielectric layer 50, test device 200, test module 210, determination module 220, test equipment 300, processor 310, memory 320, computer-readable storage medium 400, computer program 410, processor 420. Detailed embodiments

[0061] The following further describes the embodiments of the present application with reference to the accompanying drawings. The same or similar reference numerals in the drawings denote the same or similar elements or elements having the same or similar functions throughout. Additionally, the embodiments of the present application described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application and should not be construed as a limitation of the present application.

[0062] In the semiconductor manufacturing process, the plasma process plays a crucial role. Plasma is a mixed gas composed of ions and electrons, which is generally quasi-neutral. When an external disturbance disrupts the balance of the plasma, the plasma may generate self-bias voltage and even induced current, thereby causing damage to the manufactured device. The damage caused by the plasma process is simply referred to as P2ID (plasma-process induced damage).

[0063] Through research, it has been found that the plasma process will cause great damage to the gate oxide layer of the device, resulting in serious harm. For a device, the lifetime of the gate oxide layer is one of the most important reliability indicators, and the defects caused by P2ID will have a great impact on the long-term reliability of small-sized devices. As the device size gets smaller and smaller, the damage caused by the plasma to the gate oxide layer becomes more and more serious. Plasma damage has become an important factor affecting the reliability of high-integration devices.

[0064] Through research, it has been found that there are mainly three plasma damage failure mechanisms: charging damage, edge damage, and electron shielding effect. Charging damage is caused by the movement of electrons and ions in the plasma to generate plasma current, which makes the gates at different positions have different electric potentials, thus causing a potential difference. Some parts of the wafer will have a large static charge accumulation. When the gate oxide layer breaks down, a tunneling current is generated, and electrons are injected from the substrate into the Si-SiO2 interface and the gate oxide layer, resulting in an increase in the threshold voltage, a decrease in the channel mobility, changes in the saturation drain current and linear leakage current, a decrease in the hot carrier lifetime and the TDDB time-dependent breakdown lifetime, and ultimately affecting the device reliability. Edge damage is caused by the fact that in the polysilicon etching process, the gate edge will be directly bombarded and irradiated by the plasma or ultraviolet rays, generating oxide layer traps and interface states, thus directly affecting the reliability of the gate oxide layer. The electron shielding effect is caused by the microloading effect when etching a relatively dense comb-shaped antenna. More reactants are consumed, resulting in the reactants not reaching the dense etching area in time, thereby reducing the etching rate in the dense area, and then continuously accumulating positive charges, causing charge accumulation damage.

[0065] Locating the problem of P2ID is a very complex matter, involving many factors such as process manufacturing equipment, device design, process manufacturing control, and layout design. As the nanotechnology becomes more and more advanced, the complexity of the process steps is getting higher and higher, the possibility of introducing P2ID is also getting greater and greater, and the device size is getting smaller and smaller, and the tolerable P2ID dose level is gradually decreasing, resulting in the P2ID problem becoming more and more serious. At present, it is impossible to systematically locate the source of the P2ID problem.

[0066] In view of this, embodiments of the present application provide a semiconductor test system, a test method, a test device, a test equipment, and a computer-readable storage medium.

[0067] Please refer to Figures 1 to 3 , the semiconductor test system 1000 of the embodiments of the present application includes a plurality of semiconductor test devices 100. Each semiconductor test device 100 includes a semiconductor field-effect transistor 10 and an antenna layer 20. The semiconductor field-effect transistor 10 includes a substrate 11 and a gate 12 disposed on the substrate 11. The antenna layer 20 is connected to the gate 12. The structural designs among the plurality of semiconductor test devices 100 are different. The different structural designs include: different positions of the antenna layer 20; and / or different antenna ratios of the antenna layer 20; and / or whether a protection diode 30 is disposed between the gate 12 and the substrate 11.

[0068] In the semiconductor test system 1000 of the embodiments of the present application, by systematically designing a plurality of semiconductor test devices 100 with different structures, based on the different positions of the antenna layer 20, and / or different antenna ratios of the antenna layer 20, and / or whether a protection diode 30 is disposed between the gate 12 and the substrate 11 among the plurality of semiconductor test devices 100, the source of the P2ID problem can be systematically located.

[0069] Specifically, the semiconductor test system 1000 includes a plurality of semiconductor test devices 100. The plurality in the embodiments of the present application refers to two or more. Each semiconductor test device 100 includes a semiconductor field-effect transistor 10 and an antenna layer 20.

[0070] The semiconductor field-effect transistor 10 may specifically be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS). The semiconductor field-effect transistor 10 includes a substrate 11, a gate 12, a source 13, and a drain 14. The gate 12, the source 13, and the drain 14 are all disposed on the substrate 11. Among them, the gate 12 is also a poly contact.

[0071] The antenna layer 20 is connected to the gate 12. The number of the antenna layers 20 may be one or more. The antenna layer 20 may be made of metal or other materials. By collecting electrons and ions, the antenna layer 20 can amplify or reduce the effect of plasma damage, so as to determine the plasma damage test result through the plasma damage test.

[0072] The structural designs among multiple semiconductor test devices 100 are different. For example, the positions of the antenna layer 20 are set differently among the multiple semiconductor test devices 100. At this time, the antenna ratio settings of the antenna layer 20 can be the same or different; a protection diode 30 can be provided or not provided between the gate 12 and the substrate 11, which is not limited herein.

[0073] For another example, the antenna ratio settings of the antenna layer 20 are different among the multiple semiconductor test devices 100. At this time, the positions of the antenna layer 20 can be the same or different; a protection diode 30 can be provided or not provided between the gate 12 and the substrate 11, which is not limited herein. Among them, when the antenna ratio of the antenna layer 20 is larger, the amplification effect on plasma damage is stronger.

[0074] For yet another example, in some semiconductor test devices 100, a protection diode 30 is provided between the gate 12 and the substrate 11; in some semiconductor test devices 100, a protection diode 30 is not provided between the gate 12 and the substrate 11. At this time, the positions of the antenna layer 20 can be the same or different; the antenna ratio settings of the antenna layer 20 can be the same or different, which is not limited herein. Among them, when a protection diode 30 is provided between the gate 12 and the substrate 11, the plasma can be discharged through the protection diode 30, reducing the risk of damage to the gate 12.

[0075] Please refer to Figure 2 , in some embodiments, each semiconductor test device 100 further includes a plurality of metal layers 40 and at least one dielectric layer 50. The plurality of metal layers 40 are sequentially provided on the semiconductor field effect transistor 10. A dielectric layer 50 is provided between two adjacent metal layers 40. In each semiconductor test device 100, the antenna layer 20 is provided on any one or more of the gate 12, the plurality of metal layers 40, and the at least one dielectric layer 50.

[0076] Specifically, taking each semiconductor test device 100 including four metal layers 40 as an example, as Figure 2 shown, each semiconductor test device 100 from bottom to top is in sequence: semiconductor field effect transistor 10, the 1st metal layer 40, the 1st dielectric layer 50, the 2nd metal layer 40, the 2nd dielectric layer 50, the 3rd metal layer 40, the 3rd dielectric layer 50, the 4th metal layer 40. Among them, other dielectric layers, gate oxide layers, etc. can be additionally provided between any two adjacent layers, which is not limited herein.

[0077] The bottom of the first metal layer 40 is connected to the semiconductor field effect transistor 10. The bottom of the second metal layer 40 is connected to the top of the first metal layer 40 through a via trace in the first dielectric layer 50. The bottom of the third metal layer 40 is connected to the top of the second metal layer 40 through a via trace in the second dielectric layer 50. The bottom of the fourth metal layer 40 is connected to the top of the third metal layer 40 through a via trace in the third dielectric layer 50.

[0078] In each semiconductor test device 100, the number of semiconductor field effect transistors 10 can be one or more. Correspondingly, the number of gates 12 is also one or more. When the number of semiconductor field effect transistors 10 is multiple, the metal layer 40 is disposed on multiple semiconductor field effect transistors 10.

[0079] In each semiconductor test device 100, the antenna layer 20 is disposed on any one or more of the gate 12, multiple metal layers 40, and at least one dielectric layer 50. For example, the antenna layer 20 is disposed on the gate 12; or, the antenna layer 20 is disposed on one of the metal layers 40; or, the antenna layer 20 is disposed on one of the dielectric layers 50; or, the antenna layer 20 is disposed on the gate 12, all metal layers 40, all dielectric layers 50, etc. Examples are not given one by one here.

[0080] Please refer to Figures 3 to 5 In some embodiments, in each semiconductor test device 100, the antenna layer 20 includes any one or more of the first type of antenna layer 21, the second type of antenna layer 22, and the third type of antenna layer 23. The antenna structures of the first type of antenna layer 21, the second type of antenna layer 22, and the third type of antenna layer 23 are different. The first type of antenna layer 21 is disposed on any one or more of the gate 12 and multiple metal layers 40. The second type of antenna layer 22 is disposed on any one or more of at least one dielectric layer 50. The third type of antenna layer 23 is disposed on any one or more of the gate 12 and multiple metal layers 40.

[0081] The embodiments of the present application design three different types of antenna structures (the first type of antenna layer 21, the second type of antenna layer 22, and the third type of antenna layer 23) based on different process objects (gate 12, dielectric layer 50, metal layer 40). It takes into account the P2ID impact during the manufacturing of the metal layers 40 at different levels, the P2ID impact during the via manufacturing of the dielectric layers 50 at different levels, and the P2ID impact during the manufacturing of the gate 12.

[0082] Specifically, in each semiconductor test device 100, the antenna layer 20 includes any one or more of a first type of antenna layer 21, a second type of antenna layer 22, and a third type of antenna layer 23. For example, the antenna layer 20 includes the first type of antenna layer 21; alternatively, the antenna layer 20 includes the second type of antenna layer 22; alternatively, the antenna layer 20 includes the third type of antenna layer 23; or the antenna layer 20 includes the first type of antenna layer 21, the second type of antenna layer 22, the third type of antenna layer 23, etc., and specific examples are not listed one by one here.

[0083] When the antenna layer 20 includes the first type of antenna layer 21, the first type of antenna layer 21 is disposed on any one or more of the gate 12 and the plurality of metal layers 40. At this time, the number of the first type of antenna layer 21 corresponds to one or more. When the antenna layer 20 includes the second type of antenna layer 22, the second type of antenna layer 22 is disposed on any one or more of at least one dielectric layer 50. At this time, the number of the second type of antenna layer 22 corresponds to one or more. When the antenna layer 20 includes the third type of antenna layer 23, the third type of antenna layer 23 is disposed on any one or more of the gate 12 and the plurality of metal layers 40. At this time, the number of the third type of antenna layer 23 corresponds to one or more.

[0084] It should be noted that in the embodiments of the present application, in each semiconductor test device 100, the position of the antenna layer 20 can be set arbitrarily, the antenna ratio of the antenna layer 20 can be set arbitrarily, and whether a protection diode 30 is disposed between the gate 12 and the substrate 11 can be set arbitrarily. However, among the plurality of semiconductor test devices 100, at least one of the position of the antenna layer 20, the antenna ratio of the antenna layer 20, and whether a protection diode 30 is disposed between the gate 12 and the substrate 11 is different, so that the structural designs of the plurality of semiconductor test devices 100 are different, and the plurality of semiconductor test devices 100 with different structures are used for testing to systematically locate from which link the P2ID problem is introduced.

[0085] Taking the semiconductor test device 100 including four metal layers 40 as an example, the following Table 1 is used to exemplarily describe the different structural designs among the plurality of semiconductor test devices 100. Among them, Poly represents the first type of antenna layer 21 disposed on the gate 12. M1 represents the third type of antenna layer 23 disposed on the first metal layer 40, M2 represents the third type of antenna layer 23 disposed on the second metal layer 40, M3 represents the third type of antenna layer 23 disposed on the third metal layer 40, and M4 represents the third type of antenna layer 23 disposed on the fourth metal layer 40. V1 represents the second type of antenna layer 22 disposed on the first dielectric layer 50, V2 represents the second type of antenna layer 22 disposed on the second dielectric layer 50, and V3 represents the second type of antenna layer 22 disposed on the third dielectric layer 50. Stack represents the case of multi-layer stacking combination. The minimum design rule for the antenna ratio is ARrule 。

[0086] For the semiconductor test device 100 with serial number 1, the first type of antenna layer 21 is disposed on the gate 12, and the antenna ratio of the first type of antenna layer 21 is set to 1.0×AR rule , and no protection diode 30 is disposed between the gate 12 and the substrate 11. For the semiconductor test device 100 with serial number 2, the first type of antenna layer 21 is disposed on the gate 12, and the antenna ratio of the first type of antenna layer 21 is set to 1.5×AR rule , and no protection diode 30 is disposed between the gate 12 and the substrate 11. For the semiconductor test device 100 with serial number 3, the first type of antenna layer 21 is disposed on the gate 12, and the antenna ratio of the first type of antenna layer 21 is set to 2.0×AR rule , and no protection diode 30 is disposed between the gate 12 and the substrate 11.

[0087] Thus, among the semiconductor test devices 100 with serial numbers 1 to 3, the antenna ratios of the antenna layer 20 are set differently.

[0088] For the semiconductor test device 100 with serial number 4, the first type of antenna layer 21 is disposed on the gate 12, and the antenna ratio of the first type of antenna layer 21 is set to 1.0×AR rule , and a protection diode 30 is disposed between the gate 12 and the substrate 11. For the semiconductor test device 100 with serial number 5, the first type of antenna layer 21 is disposed on the gate 12, and the antenna ratio of the first type of antenna layer 21 is set to 1.5×AR rule , and a protection diode 30 is disposed between the gate 12 and the substrate 11. For the semiconductor test device 100 with serial number 6, the first type of antenna layer 21 is disposed on the gate 12, and the antenna ratio of the first type of antenna layer 21 is set to 2.0×AR rule , and a protection diode 30 is disposed between the gate 12 and the substrate 11.

[0089] Thus, for the semiconductor test devices 100 with serial numbers 4 to 6, compared with the semiconductor test devices 100 with serial numbers 1 to 3, whether a protection diode 30 is disposed between the gate 12 and the substrate 11 is different.

[0090] For the semiconductor test devices 100 with serial numbers 7 to 12, the third type of antenna layer 23 is disposed on the first metal layer 40. For the semiconductor test devices 100 with serial numbers 13 to 18, the third type of antenna layer 23 is disposed on the second metal layer 40. For the semiconductor test devices 100 with serial numbers 19 to 24, the third type of antenna layer 23 is disposed on the third metal layer 40. For the semiconductor test devices 100 with serial numbers 25 to 30, the third type of antenna layer 23 is disposed on the fourth metal layer 40.

[0091] For semiconductor test device 100 with serial numbers from 31 to 36, the second type of antenna layer 22 is disposed on the first dielectric layer 50. For semiconductor test device 100 with serial numbers from 37 to 42, the second type of antenna layer 22 is disposed on the second dielectric layer 50. For semiconductor test device 100 with serial numbers from 43 to 48, the second type of antenna layer 22 is disposed on the third dielectric layer 50.

[0092] For semiconductor test device 100 with serial numbers from 49 to 54, the third type of antenna layer 23 is disposed on the first metal layer 40 and the second metal layer 40. For semiconductor test device 100 with serial numbers from 55 to 60, the third type of antenna layer 23 is disposed on the first metal layer 40, the second metal layer 40, and the third metal layer 40. For semiconductor test device 100 with serial numbers from 61 to 66, the third type of antenna layer 23 is disposed on the first metal layer 40, the second metal layer 40, the third metal layer 40, and the fourth metal layer 40.

[0093] For semiconductor test device 100 with serial numbers from 67 to 72, the second type of antenna layer 22 is disposed on the first dielectric layer 50 and the second dielectric layer 50. For semiconductor test device 100 with serial numbers from 73 to 78, the second type of antenna layer 22 is disposed on the first dielectric layer 50, the second dielectric layer 50, and the third dielectric layer 50. For semiconductor test device 100 with serial numbers from 79 to 86, the first type of antenna layer 21 is disposed on the gate 12, the third type of antenna layer 23 is disposed on the first metal layer 40, the second metal layer 40, the third metal layer 40, and the fourth metal layer 40, and the second type of antenna layer 22 is disposed on the first dielectric layer 50, the second dielectric layer 50, and the third dielectric layer 50.

[0094] It can be seen that for semiconductor test devices 100 with serial numbers from 7 to 12, from 13 to 18, from 19 to 24, from 25 to 30, from 31 to 36, from 37 to 42, from 43 to 48, from 49 to 54, from 55 to 60, from 61 to 66, from 67 to 72, from 73 to 78, and from 79 to 86, respectively, compared with semiconductor test device 100 with serial numbers from 1 to 6, the position settings of antenna layer 20 are different.

[0095] Table 1

[0096]

[0097]

[0098]

[0099]

[0100]

[0101]

[0102] Please refer to Figure 3 , in some embodiments, the first type of antenna layer 21 is a bulk structure antenna.

[0103] Specifically, the first type of antenna layer 21 can be made of metal or other materials. The first type of antenna layer 21 is a large-area integral block structure, such as a rectangular structure. The first type of antenna layer 21 is disposed on any one or more of the gate 12 and the plurality of metal layers 40, and is connected to the gate 12.

[0104] In some embodiments, the antenna ratio of the bulk structure antenna is:

[0105]

[0106] wherein, AR (Antenna Ratio) is the antenna ratio, L B is the length of the bulk structure antenna, W B is the width of the bulk structure antenna, N f is the number of gates 12, W is the width of the gate 12, and L is the length of the gate 12. It should be noted that the antenna ratio refers to the ratio of the antenna side area to the effective gate area of the semiconductor test device 100.

[0107] Through research, the present application embodiment obtains the antenna ratio calculation formula of the bulk structure antenna. Based on this calculation formula, the first type of antenna layer 21 with different antenna ratios can be designed, so as to design different semiconductor test devices 100, amplify or reduce the effect of plasma damage to different degrees, and determine the plasma damage test result through the plasma damage test.

[0108] Please refer to Figure 4 , in some embodiments, the second type of antenna layer 22 is a via structure antenna.

[0109] Specifically, the second type of antenna layer 22 can be made of metal or other materials. The second type of antenna layer 22 is provided with a via array, and each via corresponds to a via of the dielectric layer 50. The second type of antenna layer 22 is disposed on any one or more of at least one dielectric layer 50, and is connected to the gate 12.

[0110] In some embodiments, the via structure antenna includes M rows and N columns of vias 221. The antenna ratio of the via structure antenna is:

[0111]

[0112] Wherein, AR is the antenna ratio, M is the number of rows of via 221, N is the number of columns of via 221, and W v is the side length of via 221, and N f is the number of gates 12, W is the width of gate 12, and L is the length of gate 12. The total number of vias 221 is M * N.

[0113] In the embodiments of the present application, through research, the antenna ratio calculation formula of the hole structure antenna is obtained. Based on this calculation formula, the second type of antenna layer 22 with different antenna ratios can be designed, so as to design different semiconductor test devices 100, amplify or reduce the effect of plasma damage to different degrees, and determine the plasma damage test result through the plasma damage test.

[0114] Please refer to Figure 5 , in some embodiments, the third type of antenna layer 23 is a comb-shaped structure antenna.

[0115] Specifically, the third type of antenna layer 23 can be made of metal or other materials. The third type of antenna layer 23 is integrally in a comb-shaped structure. The third type of antenna layer 23 is disposed in any one or more of at least one dielectric layer 50 and is connected to the gate 12.

[0116] In some embodiments, the comb-shaped structure antenna includes a comb handle portion 231 and a plurality of comb tooth portions 232 extending from the comb handle portion 231. The antenna ratio of the comb-shaped structure antenna is:

[0117]

[0118] Wherein, AR is the antenna ratio, and t a is the thickness of the comb-shaped structure antenna, N is the number of comb tooth portions 232, L b is the length of the comb tooth portion 232, W c is the width of the comb tooth portion 232, W b is the distance between two adjacent comb tooth portions 232, N f is the number of gates 12, W is the width of gate 12, and L is the length of gate 12.

[0119] In the embodiments of the present application, through research, the antenna ratio calculation formula of the comb-shaped structure antenna is obtained. Based on this calculation formula, the third type of antenna layer 23 with different antenna ratios can be designed, so as to design different semiconductor test devices 100, amplify or reduce the effect of plasma damage to different degrees, and determine the plasma damage test result through the plasma damage test.

[0120] Please refer to Figures 1 to 3 , the design method of the semiconductor test system 1000 in the embodiments of the present application includes:

[0121] Multiple semiconductor test devices 100 with different structural designs are fabricated. Each semiconductor test device 100 includes a semiconductor field-effect transistor 10 and an antenna layer 20. The semiconductor field-effect transistor 10 includes a substrate 11 and a gate 12 disposed on the substrate 11. The antenna layer 20 is connected to the gate 12. Different structural designs include: different positions of the antenna layer 20; and / or different antenna ratios of the antenna layer 20; and / or whether a protection diode 30 is disposed between the gate 12 and the substrate 11.

[0122] In the design method of the semiconductor test system 1000 according to the embodiments of the present application, by systematically designing multiple semiconductor test devices 100 with different structures, based on the different positions of the antenna layer 20, and / or different antenna ratios of the antenna layer 20, and / or whether a protection diode 30 is disposed between the gate 12 and the substrate 11 among the multiple semiconductor test devices 100, the source of the P2ID problem can be systematically located.

[0123] In some embodiments, each semiconductor test device 100 further includes a plurality of metal layers 40 and at least one dielectric layer 50. The plurality of metal layers 40 are sequentially disposed on the semiconductor field-effect transistor 10. A dielectric layer 50 is disposed between two adjacent metal layers 40. In each semiconductor test device 100, the antenna layer 20 is disposed on any one or more of the gate 12, the plurality of metal layers 40, and the at least one dielectric layer 50.

[0124] In some embodiments, in each semiconductor test device 100, the antenna layer 20 includes any one or more of a first-type antenna layer 21, a second-type antenna layer 22, and a third-type antenna layer 23. The antenna structures of the first-type antenna layer 21, the second-type antenna layer 22, and the third-type antenna layer 23 are different. The first-type antenna layer 21 is disposed on any one or more of the gate 12 and the plurality of metal layers 40. The second-type antenna layer 22 is disposed on any one or more of the at least one dielectric layer 50. The third-type antenna layer 23 is disposed on any one or more of the gate 12 and the plurality of metal layers 40.

[0125] In some embodiments, the first-type antenna layer 21 is a planar structure antenna.

[0126] In some embodiments, the antenna ratio of the planar structure antenna is:

[0127]

[0128] where AR (Antenna Ratio) is the antenna ratio, L B is the length of the planar structure antenna, W B is the width of the planar structure antenna, N fis the number of gates 12, W is the width of gate 12, and L is the length of gate 12. It should be noted that the antenna ratio refers to the ratio of the antenna side area to the effective gate area of the semiconductor test device 100.

[0129] In some embodiments, the second type of antenna layer 22 is a via structure antenna.

[0130] In some embodiments, the via structure antenna includes M rows and N columns of vias 221. The antenna ratio of the via structure antenna is:

[0131]

[0132] where AR is the antenna ratio, M is the number of rows of vias 221, N is the number of columns of vias 221, W v is the side length of via 221, N f is the number of gates 12, W is the width of gate 12, and L is the length of gate 12. The total number of vias 221 is M * N.

[0133] In some embodiments, the third type of antenna layer 23 is a comb structure antenna.

[0134] In some embodiments, the comb structure antenna includes a comb handle portion 231 and a plurality of comb tooth portions 232 extending from the comb handle portion 231. The antenna ratio of the comb structure antenna is:

[0135]

[0136] where AR is the antenna ratio, t a is the thickness of the comb structure antenna, N is the number of comb tooth portions 232, L b is the length of the comb tooth portion 232, W c is the width of the comb tooth portion 232, W b is the spacing between adjacent two comb tooth portions 232, N f is the number of gates 12, W is the width of gate 12, and L is the length of gate 12.

[0137] It should be noted that the foregoing explanations of the semiconductor test system 1000 in the embodiments are equally applicable to the design method of the semiconductor test system 1000 in the embodiments of the present application, and will not be elaborated herein.

[0138] Please refer to Figure 1 and Figure 6 , the test method of the embodiments of the present application is applied to the semiconductor test system 1000 in any of the foregoing embodiments. The test method includes:

[0139] 010: Perform plasma damage tests on a plurality of semiconductor test devices 100;

[0140] 020: Determine the plasma damage test results based on different structural designs among multiple semiconductor test devices 100.

[0141] In the test method of the embodiments of the present application, by systematically designing multiple semiconductor test devices 100 with different structures, based on the differences among multiple semiconductor test devices 100, the position setting of the antenna layer 20 is different, and / or the antenna ratio of the antenna layer 20 is different, and / or whether a protection diode 30 is provided between the gate 12 and the substrate 11, the source of the P2ID problem can be systematically located.

[0142] Specifically, it takes into account the P2ID impact during the manufacturing of metal layers 40 at different levels, the P2ID impact during the via manufacturing of dielectric layers 50 at different levels, and the P2ID impact during the manufacturing of the gate 12. Different antenna structures are adopted according to the actual application scenarios. The antenna corresponding to the metal layer 40 adopts a comb-shaped structure antenna (or a planar structure antenna), the antenna corresponding to the dielectric layer 50 adopts a hole structure antenna, and the antenna corresponding to the gate 12 adopts a planar structure antenna (or a comb-shaped structure antenna), and the antenna ratio calculation formulas are given respectively. In addition, antenna structures with multiple sequences such as 0.5 times, 1 time, 1.5 times, and 2 times are designed for the same antenna structure, taking into account the impact of the antenna ratio on P2ID; considering the impact of whether a protection diode 30 is provided between the gate 12 and the substrate 11 on P2ID; at the same time, it also takes into account the single and multiple stacked combinations of the antennas corresponding to different levels. By comprehensively performing plasma damage tests on multiple semiconductor test devices 100, it is possible to determine whether there is an impact of P2ID on the semiconductor test devices 100. If there is an impact of P2ID on the semiconductor test devices 100, it is possible to accurately locate which level or levels introduce the P2ID problem, and it is also possible to measure the severity of the dose when P2ID appears, providing a strong discrimination basis for effectively evaluating the P2ID impact and design improvement.

[0143] Please refer to Figure 2 and Figure 7 , in some embodiments, performing a plasma damage test (i.e., 010) on multiple semiconductor test devices 100 includes:

[0144] 011: Apply a predetermined voltage to the gate 12 for each semiconductor test device 100;

[0145] 012: Obtain the leakage current of the gate 12;

[0146] Determining the plasma damage test results (i.e., 020) based on different structural designs among multiple semiconductor test devices 100 includes:

[0147] 021: Based on different structural designs among multiple semiconductor test devices 100, determine the plasma damage test results according to the leakage current.

[0148] Specifically, the predetermined voltage is a preset voltage with a relatively small value. For each semiconductor test device 100, apply the predetermined voltage to the gate 12 and obtain the leakage current of the gate 12. When there is plasma damage, the leakage current of the gate 12 will increase.

[0149] Due to the different structural designs among multiple semiconductor test devices 100, the corresponding rules satisfied by the leakage current of the gate 12 are also different. Based on the different structural designs among multiple semiconductor test devices 100, the plasma damage test results can be accurately determined according to the leakage current of the gate 12.

[0150] For example, under certain other conditions, the larger the antenna ratio of the antenna layer 20, the greater the possibility of plasma damage, and then the leakage current of the gate 12 is also correspondingly higher. If the leakage current of the gate 12 satisfies this rule, it indicates that there may be plasma damage. On the contrary, if it is found in the test that the leakage current of the gate 12 when the antenna ratio is large is smaller than the leakage current of the gate 12 when the antenna ratio is small, it indicates that it may not belong to plasma damage, and there may be other reasons, such as leakage, doping, contamination, etc.

[0151] Another example, under certain other conditions, when a protection diode 30 is provided between the gate 12 and the substrate 11, the leakage current of the gate 12 is usually small. If the leakage current of the gate 12 satisfies this rule, it indicates that there may be plasma damage and the protection diode 30 is effective. On the contrary, if it is found in the test that the leakage current of the gate 12 when the protection diode 30 is provided is greater than the leakage current of the gate 12 when the protection diode 30 is not provided, it indicates that it may not belong to plasma damage, or the protection diode 30 may fail.

[0152] In addition, if the position of the antenna layer 20 is set differently, the corresponding layer where the P2ID problem exists can be accurately located. For example, if the antenna layer 20 is provided on the gate 12, it can be used to determine whether there is a P2ID problem with the gate 12; another example, if the antenna layer 20 is provided on the metal layer 40, it can be used to determine whether there is a P2ID problem with the metal layer 40; yet another example, if the antenna layer 20 is provided on the dielectric layer 50, it can be used to determine whether there is a P2ID problem with the dielectric layer 50.

[0153] Please refer to Figure 8, the test device 200 of the embodiment of the present application is applied to the semiconductor test system 1000 of any of the above embodiments. The test device 200 includes a test module 210 and a determination module 220. The test module 210 is used to perform plasma damage tests on a plurality of semiconductor test devices 100. The determination module 220 is used to determine the plasma damage test results based on different structural designs among the plurality of semiconductor test devices 100.

[0154] In some embodiments, the test module 210 is specifically configured to: for each semiconductor test device 100, apply a predetermined voltage to the gate 12; obtain the leakage current of the gate 12. The determination module 220 is specifically configured to determine the plasma damage test results based on different structural designs among the plurality of semiconductor test devices 100 according to the leakage current.

[0155] It should be noted that the explanations of the test methods in the foregoing embodiments are equally applicable to the test device 200 of the embodiment of the present application, and will not be elaborated here.

[0156] Please refer to Figure 9 , the test equipment 300 of the embodiment of the present application includes one or more processors 310 and a memory 320, and the memory 320 stores a computer program. When the computer program is executed by the processor 310, the test method of any of the above embodiments is implemented.

[0157] For example, when the computer program is executed by the processor 310, the following test method is implemented:

[0158] 010: Perform plasma damage tests on a plurality of semiconductor test devices 100;

[0159] 020: Determine the plasma damage test results based on different structural designs among the plurality of semiconductor test devices 100.

[0160] Again, for example, when the computer program is executed by the processor 310, the following test method is implemented:

[0161] 011: For each semiconductor test device 100, apply a predetermined voltage to the gate 12;

[0162] 012: Obtain the leakage current of the gate 12;

[0163] 021: Determine the plasma damage test results based on different structural designs among the plurality of semiconductor test devices 100 according to the leakage current.

[0164] It should be noted that the explanations of the test methods in the foregoing embodiments are equally applicable to the test equipment 300 of the embodiment of the present application, and will not be elaborated here.

[0165] Please refer to Figure 10 a computer-readable storage medium 400 according to an embodiment of the present application, on which a computer program 410 is stored. When the program is executed by a processor 420, the testing method according to any one of the above embodiments is implemented.

[0166] For example, when the program is executed by the processor 420, the following testing method is implemented:

[0167] 010: Perform plasma damage testing on a plurality of semiconductor test devices 100;

[0168] 020: Determine the plasma damage test result based on different structural designs among the plurality of semiconductor test devices 100.

[0169] Again, for example, when the program is executed by the processor 420, the following testing method is implemented:

[0170] 011: Apply a predetermined voltage to the gate 12 for each semiconductor test device 100;

[0171] 012: Obtain the leakage current of the gate 12;

[0172] 021: Determine the plasma damage test result based on the leakage current according to different structural designs among the plurality of semiconductor test devices 100.

[0173] It should be noted that the explanations of the testing methods in the foregoing embodiments are equally applicable to the computer-readable storage medium 400 according to the embodiments of the present application, and will not be elaborated herein.

[0174] In summary, in the semiconductor testing system 1000, design method, testing method, testing device 200, testing equipment 300, and computer-readable storage medium 400 according to the embodiments of the present application, by systematically designing a plurality of semiconductor test devices 100 with different structures, based on the different positions of the antenna layer 20, and / or different antenna ratios of the antenna layer 20, and / or whether a protection diode 30 is provided between the gate 12 and the substrate 11 among the plurality of semiconductor test devices 100, the source of the P2ID problem can be systematically located.

[0175] Specifically, the P2ID impact during the fabrication of metal layers 40 at different levels is considered, the P2ID impact during the fabrication of vias in dielectric layers 50 at different levels is considered, and the P2ID impact during the fabrication of gate 12 is considered. Different antenna structures are adopted according to the actual application scenarios. The antenna corresponding to the metal layer 40 adopts a comb-shaped antenna (or planar antenna), the antenna corresponding to the dielectric layer 50 adopts a via antenna, and the antenna corresponding to the gate 12 adopts a planar antenna (or comb-shaped antenna), and the antenna ratio calculation formulas are given respectively. In addition, antenna structures with multiple sequences such as 0.5 times, 1 time, 1.5 times, and 2 times are designed for the same antenna structure, considering the impact of the antenna ratio on P2ID; the impact of whether a protection diode 30 is provided between the gate 12 and the substrate 11 on P2ID is considered; at the same time, the single and multiple stacked combinations of the antennas corresponding to different levels are considered. By comprehensively performing plasma damage tests on multiple semiconductor test devices 100, it is possible to determine whether there is an impact of P2ID on the semiconductor test devices 100. If there is an impact of P2ID on the semiconductor test devices 100, it is possible to accurately locate which level or levels introduce the P2ID problem, and the severity of the dose when P2ID occurs can also be measured, providing a strong discriminant basis for effectively evaluating the P2ID impact and design improvement.

[0176] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0177] Any process or method description shown in the flowchart or described in other ways herein can be understood as representing a module, segment, or part of the code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present application includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the art of the embodiments of the present application.

[0178] The logic and / or steps represented in the flowchart or otherwise described herein can, for example, be considered as a definable sequence of executable instructions for implementing logical functions, and can be embodied specifically in any computer-readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. For the purposes of this specification, a computer-readable storage medium can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection portion having one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable storage medium can even be paper or other suitable media on which the program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other suitable processing as necessary, and then storing it in a computer memory.

[0179] It should be understood that various parts of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well-known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having suitable combinational logic gate circuits, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

[0180] Those of ordinary skill in the art can understand that all or part of the steps carried out in implementing the above-described embodiment methods can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment. In addition, in each of the various embodiments of the present application, the functional units can be integrated into one processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the above-mentioned integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disc, etc.

[0181] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A semiconductor testing system, characterized in that: The semiconductor test system comprises a plurality of semiconductor test devices, each of the semiconductor test devices comprises a semiconductor field effect transistor and an antenna layer, the semiconductor field effect transistor comprises a substrate and a gate arranged on the substrate, and the antenna layer is connected to the gate; The plurality of semiconductor test devices have different structural designs, and the different structural designs include: The antenna layers are arranged at different positions; and / or The antenna ratios of the antenna layers are set differently; and / or Whether a protection diode is provided between the gate and the substrate.

2. The semiconductor testing system according to claim 1, characterized in that: Each of the semiconductor test devices further comprises a plurality of metal layers and at least one dielectric layer, wherein the plurality of metal layers are sequentially arranged on the semiconductor field effect transistor, and a dielectric layer is arranged between two adjacent metal layers; In each of the semiconductor test devices, the antenna layer is disposed on any one or more of the gate, the plurality of metal layers, and the at least one dielectric layer.

3. The semiconductor testing system according to claim 2, characterized in that: In each of the semiconductor test devices, the antenna layer includes any one or more of a first type antenna layer, a second type antenna layer, and a third type antenna layer, and the antenna structures of the first type antenna layer, the second type antenna layer, and the third type antenna layer are different; The first type of antenna layer is disposed on any one or more of the gate and the plurality of metal layers; The second type of antenna layer is disposed in any one or more of the at least one dielectric layer; The third type antenna layer is disposed on any one or more of the gate and the plurality of metal layers.

4. The semiconductor testing system according to claim 3, characterized in that: The first type of antenna layer is a planar structure antenna.

5. The semiconductor testing system according to claim 4, characterized in that: The antenna ratio of the planar structure antenna is: Where AR is the antenna ratio, L B is the length of the planar structure antenna, W B is the width of the planar structure antenna, N f is the number of the gates, W is the width of the gates, and L is the length of the gates.

6. The semiconductor testing system according to claim 3, characterized in that: The second type of antenna layer is a hole structure antenna.

7. The semiconductor testing system according to claim 6, characterized in that: The hole structure antenna includes M rows and N columns of via holes, and the antenna ratio of the hole structure antenna is: Wherein, AR is the antenna ratio, M is the number of rows of the vias, N is the number of columns of the vias, and W v is the side length of the via, N f is the number of the gates, W is the width of the gates, and L is the length of the gates.

8. The semiconductor testing system according to claim 7, characterized in that: The third type of antenna layer is a comb structure antenna.

9. The semiconductor testing system according to claim 8, characterized in that: The comb-shaped structure antenna comprises a comb handle and a plurality of comb teeth extending from the comb handle, and the antenna ratio of the comb-shaped structure antenna is: Where AR is the antenna ratio, t a is the thickness of the comb-shaped structure antenna, N is the number of the comb teeth, L b is the length of the comb teeth, W c is the width of the comb teeth, W b is the distance between two adjacent comb teeth, N f is the number of the gates, W is the width of the gates, and L is the length of the gates.

10. A method for designing a semiconductor test system, characterized in that: include: A plurality of semiconductor test devices with different structural designs are manufactured, wherein each of the semiconductor test devices comprises a semiconductor field effect transistor and an antenna layer, the semiconductor field effect transistor comprises a substrate and a gate disposed on the substrate, and the antenna layer is connected to the gate; the different structural designs include: The antenna layers are arranged at different positions; and / or The antenna ratios of the antenna layers are set differently; and / or Whether a protection diode is provided between the gate and the substrate.

11. A testing method, characterized in that: Applied to the semiconductor test system according to any one of claims 1 to 9, the test method comprising: performing a plasma damage test on the plurality of semiconductor test devices; Based on the different structural designs among the plurality of semiconductor test devices, a plasma damage test result is determined.

12. The testing method according to claim 11, characterized in that: The performing plasma damage test on the plurality of semiconductor test devices comprises: For each of the semiconductor test devices, applying a predetermined voltage to the gate; Obtaining a leakage current of the gate; The step of determining a plasma damage test result based on different structural designs among the plurality of semiconductor test devices comprises: Based on the different structural designs among the plurality of semiconductor test devices, the plasma damage test result is determined according to the leakage current.

13. A testing device, characterized in that: The semiconductor test system according to any one of claims 1 to 9, wherein the test device comprises: A test module, used for performing a plasma damage test on the plurality of semiconductor test devices; The determination module is used to determine the plasma damage test result based on the different structural designs among the plurality of semiconductor test devices.

14. A testing device, characterized in that: The testing device includes one or more processors and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the testing method according to claim 11 or 12 is implemented.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the testing method according to claim 11 or 12 is implemented.

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