Satellite-borne SAR simulation method based on FPGA heterogeneous platform

Abstract

The invention provides a satellite-borne SAR (Synthetic Aperture Radar) simulation method based on an FPGA (Field Programmable Gate Array) heterogeneous platform, the satellite-borne SAR simulation is realized based on a CPU (Central Processing Unit) and the FPGA heterogeneous platform, and the method comprises the following steps: calculating to obtain simulation echo intermediate parameters by a CPU end according to obtained simulation parameters; wherein the simulation echo intermediate parameters comprise a Doppler parameter at a simulation center moment, a plurality of fixed parameters, a simulation echo parameter changing along with azimuth moments and a simulation echo parameter changing along with a point target; the CPU end transmits the simulation echo intermediate parameters to the FPGA end for accelerated calculation by accessing a PCIe interface module in the FPGA, and linear frequency modulation signals are obtained; and the FPGA end transmits the linear frequency modulation signal back to the CPU end through the PCIe interface module for recalculation, and an echo file obtained through calculation and Doppler parameters at the simulation center moment are imaged to obtain a satellite-borne SAR image. According to the scheme, rapid simulation echo calculation of the spaceborne SAR can be realized.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of radar signal simulation, and particularly to a spaceborne SAR simulation method based on an FPGA heterogeneous platform. Background Art

[0002] In the fierce competition of high-level radar systems, synthetic aperture radar (SAR) has received great attention from researchers in related fields due to its many unique advantages. Moreover, with its excellent applications in civilian scenarios such as disaster observation and weather forecasting, as well as military fields such as ship monitoring and air defense warning, it has received strong development and support from the government and enterprises. Since the construction cost of a spaceborne synthetic aperture radar system is relatively high, it is necessary to conduct a preliminary evaluation test on the working conditions of the radar system before launch. Therefore, the echo signal simulation system has become an indispensable part of the entire engineering project.

[0003] However, with the rapid development of spaceborne SAR technology, researchers have increasingly higher requirements for the performance of the echo signal simulation system. As the image resolution and observation swath increase, the amount of simulated radar echo data increases accordingly, and the computational load borne by the simulation system also increases sharply, resulting in an extended simulation time. High-efficiency echo signal simulation is a difficult problem restricting engineering applications.

[0004] Therefore, there is an urgent need to provide a spaceborne SAR simulation method based on an FPGA heterogeneous platform. Summary of the Invention

[0005] To solve the problem of low efficiency in traditional spaceborne SAR simulation, the embodiments of the present invention provide a spaceborne SAR simulation method based on an FPGA heterogeneous platform.

[0006] In a first aspect, the embodiments of the present invention provide a spaceborne SAR simulation method based on an FPGA heterogeneous platform. The spaceborne SAR simulation is implemented based on a CPU and an FPGA heterogeneous platform. The method includes:

[0007] The CPU side calculates intermediate simulation echo parameters according to the obtained simulation parameters. Among them, the intermediate simulation echo parameters include Doppler parameters at the simulation center time, several fixed parameters, simulation echo parameters that change with the azimuth time, and simulation echo parameters that change with point targets.

[0008] The CPU side transmits the intermediate simulation echo parameters to the FPGA side through accessing the PCIe interface module in the FPGA for accelerated calculation to obtain a chirp signal.

[0009] The FPGA side transmits the chirp signal back to the CPU side through the PCIe interface module for re - calculation, and images the echo file obtained from the calculation with the Doppler parameters at the simulation center time to obtain the spaceborne SAR image.

[0010] An embodiment of the present invention provides a spaceborne SAR simulation method based on an FPGA heterogeneous platform. The spaceborne SAR simulation is implemented based on a heterogeneous platform of a CPU and an FPGA. First, the CPU side performs an initial calculation based on the obtained simulation parameters to obtain intermediate simulation echo parameters. Then, the CPU side transmits the intermediate simulation echo parameters obtained from the initial calculation to the FPGA side through the PCIe interface module for accelerated calculation to obtain a chirp signal. Finally, the FPGA side transmits the calculated chirp signal data back to the CPU side through the PCIe interface again for further calculation, and images the obtained echo file with the Doppler parameters at the simulation center time to generate the final spaceborne SAR image. In this solution, by dividing the calculation process of echo simulation into two parts and completing the process with higher computational complexity in the echo simulation code in the FPGA, thus, the fast simulation echo calculation of spaceborne SAR is realized with extremely high efficiency and high consistency relative to CPU calculation. Brief Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 It is a flowchart of a spaceborne SAR simulation method based on an FPGA heterogeneous platform provided by an embodiment of the present invention. Detailed Embodiments

[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0014] Traditional spaceborne SAR simulation systems are usually implemented based on traditional computer CPUs. However, as the image resolution and observation swath increase, the amount of radar echo data generated by simulation also increases, and the computational load borne by the simulation system increases sharply. At the same time, due to the serial computing characteristics of traditional computer CPUs, operations such as common matrix operations, convolution operations, and fast Fourier transforms consume a large amount of time, resulting in an extended simulation time and making it difficult to achieve high-efficiency echo signal simulation. Therefore, in the embodiments of the present invention, a heterogeneous platform composed of a CPU and an FPGA is considered for simulation. First, the simulation parameters are initially calculated in the CPU, and then they are input into the FPGA to complete the process with the highest computational complexity in the echo simulation code. Finally, the calculated echo file is transmitted back to the CPU for post-processing to obtain the final spaceborne SAR image. In this way, high-efficiency spaceborne SAR echo simulation is achieved.

[0015] The following describes the specific implementation manners of the above concepts.

[0016] Please refer to Figure 1 , embodiments of the present invention provide a spaceborne SAR simulation method based on an FPGA heterogeneous platform. The spaceborne SAR simulation is implemented based on a heterogeneous platform of a CPU and an FPGA. The method includes:

[0017] Step 100, the CPU side calculates intermediate simulation echo parameters according to the obtained simulation parameters. Among them, the intermediate simulation echo parameters include Doppler parameters at the simulation center time, several fixed parameters, simulation echo parameters that change with the azimuth time, and simulation echo parameters that change with point targets.

[0018] Step 102, the CPU side transmits the intermediate simulation echo parameters to the FPGA side through accessing the PCIe interface module in the FPGA for accelerated calculation to obtain a chirp signal.

[0019] Step 104, the FPGA side transmits the chirp signal back to the CPU side through the PCIe interface module for further calculation, and images the calculated echo file with the Doppler parameters at the simulation center time to obtain a spaceborne SAR image.

[0020] In the embodiment of the present invention, the spaceborne SAR simulation is implemented based on a heterogeneous platform of CPU and FPGA. First, the CPU side performs initial calculations based on the obtained simulation parameters to obtain intermediate parameters of the simulation echo. Then, the CPU side transmits the intermediate parameters of the simulation echo obtained from the initial calculations to the FPGA side through the PCIe interface module for accelerated calculations to obtain a chirp signal. Finally, the FPGA side transmits the calculated chirp signal data back to the CPU side through the PCIe interface again for further calculations, and performs imaging on the obtained echo file and the Doppler parameters at the simulation center time to generate the final spaceborne SAR image. In this solution, by dividing the calculation process of echo simulation into two parts and completing the processes with higher computational complexity in the echo simulation code in the FPGA, the fast simulation echo calculation of spaceborne SAR is achieved with extremely high efficiency and high consistency relative to CPU calculation.

[0021] Regarding step 100:

[0022] In some embodiments, the simulation parameters include earth parameters, satellite orbit parameters, and radar parameters.

[0023] In the embodiment of the present invention, the earth parameters include gravitational parameter, semi-major axis of the earth, semi-minor axis of the earth, average earth radius, earth's angular velocity of rotation, semi-major axis, orbital inclination, and argument of perigee; the satellite orbit parameters include right ascension of the ascending node of the satellite orbit, eccentricity, roll angle, pitch angle, yaw angle, yaw control parameter; the radar parameters include radar operating wavelength, antenna center view angle, antenna length, antenna width, signal sampling rate, signal bandwidth, pulse repetition frequency, pulse width, echo window delay, intermediate frequency signal carrier frequency, number of samples in the range direction, number of simulation pulses in the azimuth direction, latitude of the scene center, number of points in the azimuth direction, number of points in the range direction, azimuth point interval, range point interval, x coordinate of the receiving channel, y coordinate of the receiving channel, z coordinate of the receiving channel, whether to use a real SAR image, real SAR image data, real SAR image bit depth, and Doppler parameter file.

[0024] Before performing the calculations, corresponding memory is allocated on the CPU side first, including: memory space for storing echoes, memory space for storing scene data, memory space for storing scene coordinates, memory space for storing the distance between the satellite and the target, memory space for storing the azimuth off-axis angle between the satellite and the target, memory space for storing the azimuth antenna pattern, and memory space for storing the backscattering coefficient and random phase. Further, for reading the backscattering coefficient and setting the random phase, first select to use the actual scene or simulated points. If using actual scene data, read the data depth and select different data types to read the backscattering coefficient according to different data depths; if selecting to use simulated points, set the backscattering coefficient of all scene points to 1; generate random phase within a certain range by using the method of generating random numbers.

[0025] In some embodiments, the simulation echo parameters varying with the dot target include the coordinates of each simulation point in the simulation scenario;

[0026] The coordinates of each simulation point in the simulation scenario are calculated as follows:

[0027] According to the obtained simulation parameters, calculate the positions of the satellite, the point in the antenna coordinate system, the point where the antenna points to the ground, and the phase center in the corresponding coordinate systems at the simulation center time;

[0028] According to the positions of the satellite, the point in the antenna coordinate system, the point where the antenna points to the ground, and the phase center in the corresponding coordinate systems, solve the longitude and latitude of the center point of the simulation scenario;

[0029] Based on the longitude and latitude of the simulation scenario center, arrange the simulation points at a preset interval to form an n×n simulation dot matrix, and calculate the coordinates of each simulation point in the simulation scenario.

[0030] In the embodiments of the present invention, the positions of the satellite, the point in the antenna coordinate system, the point where the antenna points to the ground, and the phase center in the corresponding coordinate systems at the simulation center time are calculated through the following steps:

[0031] (1) First, calculate the simulation center time t in the following way:

[0032] Use the obtained earth parameters and satellite orbit parameters to calculate the angle between the sub-satellite point plane and the beam center intersection plane;

[0033] Use the satellite orbit parameters and the angle between the sub-satellite point plane and the beam center intersection plane to calculate the true anomaly corresponding to the simulation center time;

[0034] Use the true anomaly corresponding to the simulation center time to calculate the eccentric anomaly corresponding to the simulation center time;

[0035] Use the eccentric anomaly corresponding to the simulation center time to calculate the simulation center time, and the expression is:

[0036] t = (M - e*sinM) / w

[0037] Where t is the simulation center time, M is the eccentric anomaly corresponding to the simulation center time, e is the orbital eccentricity, and w is the mean motion angular velocity.

[0038] (2) Calculate the coordinates of the satellite in the orbital plane coordinate system at the simulation center time obtained as follows: First, calculate the mean anomaly from the simulation center time, then calculate the eccentric anomaly from the orbital parameters and the anomaly, next calculate the true anomaly from the eccentric anomaly, then calculate the satellite orbital radius from the true anomaly, and finally calculate the coordinates of the satellite in the orbital plane coordinate system at the simulation center time through the satellite orbital radius. The x coordinate of the satellite in the orbital plane is: x = r * cos(θ), the y coordinate is: y = r * sin(θ), and the z coordinate is 0, where; r represents the satellite orbital radius and θ represents the true anomaly.

[0039] (3) The position of the point (0, 1, 0) in the antenna coordinate system in the rotating geocentric coordinate system is first converted from the antenna coordinate system (Ea) to the satellite body coordinate system (Ee), then from the satellite body coordinate system (Ee) to the satellite platform coordinate system (Er), then from the satellite platform coordinate system (Er) to the orbital plane coordinate system (Ev), next from the orbital plane coordinate system (Ev) to the equatorial inertial coordinate system (Eo), and finally from the equatorial inertial coordinate system (Eo) to the rotating geocentric coordinate system (Eg). Among them, Ex represents the position vector in each coordinate system, and there is Ea = Aab · Eb, where Aab represents the coordinate transformation matrix and Eb is the vector. The coordinate transformation matrices of each coordinate system are as follows:

[0040]

[0041] Among them, Ago is the transformation matrix from the equatorial inertial coordinate system (Eo) to the rotating geocentric coordinate system (Eg), and H is the Greenwich hour angle;

[0042]

[0043] Among them, Aov is the transformation matrix from the orbital plane coordinate system (Ev) to the equatorial inertial coordinate system (Eo), a is the angle of counterclockwise rotation of the coordinate system around the Z axis, b is the angle of counterclockwise rotation of the coordinate system around the X axis, and c is the angle of counterclockwise rotation of the coordinate system around the Y axis. These three rotations need to be carried out in sequence;

[0044]

[0045] Among them, Avr is the transformation matrix from the satellite platform coordinate system (Er) to the orbital plane coordinate system (Ev), θ is the true anomaly of the satellite, and γ is the track angle of the satellite;

[0046]

[0047] Among them, Are is the transformation matrix from the satellite body coordinate system (Ee) to the satellite platform coordinate system (Er). a represents the angle of clockwise rotation of the coordinate system around the X-axis, b is the angle of clockwise rotation of the coordinate system around the Z-axis, and c is the angle of counterclockwise rotation of the coordinate system around the Y-axis. These three rotations need to be carried out in sequence;

[0048]

[0049] Among them, Aea is the transformation matrix from the antenna coordinate system (Ea) to the satellite body coordinate system (Ee). a' is the angle of counterclockwise rotation of the coordinate system around the X-axis. If the coordinate system needs to be transformed in the opposite direction, only the inverse matrix of the transformation matrix needs to be calculated to be used as the reverse transformation matrix.

[0050] (3) The position of the phase center in the rotating geocentric coordinate system. First, the x, y, and z coordinates of the receiving channel are transformed from the satellite body coordinate system to the satellite platform coordinate system, then from the satellite platform coordinate system to the orbital plane coordinate system, next from the orbital plane coordinate system to the equatorial inertial coordinate system, and finally from the equatorial inertial coordinate system to the rotating geocentric coordinate system. Among them, the specific transformation method is as shown in step (2).

[0051] (4) Simulate the position of the satellite in the rotating geocentric coordinate system at the central moment. First, the coordinates of the satellite at the simulation central moment are transformed from the orbital plane coordinate system to the equatorial inertial system, and then from the equatorial inertial system to the rotating geocentric coordinate system. Among them, the specific transformation method is as shown in step (2).

[0052] (5) The position of the point where the antenna points to the ground in the rotating geocentric coordinate system. First, determine the distance from the scene center to the antenna center at the simulation central moment, and then determine the coordinates of the point where the antenna points to the ground in the rotating geocentric coordinate system through the following equations: x tg = x1 * R ref + x, y tg = y1 * R ref + y, z tg = z1 * R ref + z, where, R ref is the distance from the scene center to the antenna center at the simulation central moment, x1, y1, z1 are the coordinates of the point (0, 1, 0) in the antenna coordinate system in the rotating geocentric coordinate system, and x, y, z are the coordinates of the satellite at the simulation central moment in the equatorial inertial system.

[0053] (6) The position of the point where the antenna points to the ground in the equatorial inertial coordinate system. From the distance from the scene center to the antenna center at the simulation central moment, determine the coordinates of the point where the antenna points to the ground in the equatorial inertial coordinate system through the following equations: x to = x to ’ * R ref + xvs +x eo ,y to = y to ’*R ref +y vs +y eo ,z to = z to ’*R ref +z vs +z eo ,where R ref is the distance from the scene center to the antenna center at the simulation center time, x vs ,y vs ,z vs are the coordinates of the satellite in the equatorial inertial system, x eo ,y eo ,z eo are the coordinates of the phase center in the equatorial inertial system, x to ’,y to ’,z to ’ are the coordinates of the point where the antenna pointed to the ground at the previous time in the equatorial inertial system.

[0054] After that, the following formula is used to calculate the longitude and latitude of the simulation center point:

[0055]

[0056] where Longitude is the longitude of the simulation center point, Latitude is the latitude of the simulation center point, x tg ,y tg ,z tg are the coordinates of the point where the antenna points to the ground in the rotating geocentric coordinate system.

[0057] Arrange the scene at preset intervals based on the longitude and latitude of the simulation scene center. Arrange the scene dot matrix to be simulated at the scene center determined by the scene longitude and latitude data to form an n×n dot matrix. First, calculate the longitude and latitude of each simulation point, and then calculate the coordinates of each simulation point in the simulation scene based on the longitude and latitude of each simulation point;

[0058] where the longitude and latitude of each simulation point are calculated by the following formula:

[0059]

[0060] where Latitudep is the longitude of one of the simulation points, Longtitudep is the latitude of one of the simulation points, x’, y’ are the relative positions of the point target in the ground dot matrix, For the r-th simulation point, longAxis is the semi-major axis of the Earth, shortAxis is the semi-minor axis of the Earth, and i1, j1 are values used to count the array;

[0061] The coordinates of each simulation point in the simulation scenario are calculated by the following formula:

[0062]

[0063] In some embodiments, the Doppler parameter at the simulation center time is calculated as follows:

[0064] Based on the Earth parameters and satellite orbit parameters, calculate the velocities and accelerations of the satellite and the simulation point target at the simulation center time respectively;

[0065] The velocity of the satellite at the simulation center time is: v xsat =-sin(θ), v ysat =e + cos(θ), v zsat =0, where θ is the true anomaly and e is the eccentricity; the acceleration is: a xsat =cos(θ), a ysat =sin(θ), a zsat =0, then transform the satellite velocity into the equatorial inertial system and transform the satellite acceleration into the equatorial inertial system;

[0066] The velocity of the simulation point target at the simulation center time is: v xtar =-y to *Earth_rev, v ytar =x to *Earth_rev, v ztar =0, where Earth_rev is the angular velocity of the Earth's rotation, and the acceleration of the simulation point target is: a xtar =-x to *Earth_rev*Earh_rev, a ytar =-y to *Earth rec *Earth rev , a ztar =0.

[0067] According to the velocities and relative accelerations of the satellite and the simulation point target at the simulation center time, calculate the relative velocity and relative acceleration between the satellite and the simulation point target;

[0068] The relative velocity between the satellite and the simulation point target is: v x =v xsat -v xtar , v y =v ysat -v ytar, v z = v zsat - v ztar ; The relative acceleration is: a x = a xsat - a xtar , a y = a ysat - a ytar , a z = a zsat - a ztar .

[0069] According to the relative velocity and relative acceleration between the satellite and the simulated point target, the distance between the satellite and the scene center at the simulation center time, and the relative velocity between the satellite and the scene center at the simulation center time, calculate the Doppler frequency and Doppler frequency modulation slope at the simulation center time respectively;

[0070] First, use the following formula to calculate the distance R between the satellite and the scene center at the simulation center time: where R x = x vs - x to , R y = y vs - y to , R z = z vs - z to ;

[0071] After that, use the following formula to calculate the relative velocity V between the satellite and the scene center at the simulation center time:

[0072] Finally, use the following formulas to calculate the Doppler frequency f d and the Doppler frequency modulation slope f r respectively:

[0073] f d = 2 * (v x * R x + v y * R y + v z * R z ) / (λ * R)

[0074]

[0075] where λ is the radar operating wavelength.

[0076] In some embodiments, the simulated echo parameters varying with the azimuth time include the coordinates of the satellite in the orbital plane, the yaw angle, and the difference between the true anomaly and the track angle at each azimuth time;

[0077] At each azimuth time, the following operations are performed:

[0078] Calculate the orbital eccentric anomaly and the true anomaly based on satellite parameters, radar parameters, and the simulation center time;

[0079] Calculate the coordinates of the satellite in the orbital plane according to the orbital eccentric anomaly, the true anomaly, and the radius vector;

[0080] Calculate the difference between the true anomaly and the track angle at each azimuth time according to the orbital eccentricity, the true anomaly, and the typical value of pi;

[0081] Process the yaw angle at each azimuth time based on the obtained satellite parameters to obtain the yaw angle.

[0082] In the embodiment of the present invention, the stpc, pitch, and roll at each azimuth time are all set to 0. Next, calculate the coordinates of the satellite in the orbital plane at each azimuth time. First, solve the mean anomaly M according to the following formula: M = w*(i' / PRF + t - ver_data / 2 / PRF), where w is the mean angular velocity, t is the simulation center time, PRF is the ideal repetition frequency, ver_data is the azimuth simulation pulse number, and i' is the i'th azimuth time; then, use the mean anomaly to solve the eccentric anomaly, and then use the eccentric anomaly to solve the true anomaly and the radius vector. Finally, solve the coordinates of the satellite in the orbital plane: x vs = r*cos(θ), y vs = r*sin(θ), z vs = 0, where r represents the radius vector and θ represents the true anomaly. Write the coordinates x vs , y vs , z vs of the satellite in the orbital plane obtained at each azimuth time into the data file to be transmitted to the FPGA. Assign the yaw angle corresponding to each azimuth time to the yaw angle read from the parameter file divided by 180 and write it into the data file to be transmitted to the FPGA. Finally, calculate the difference ds between the true anomaly and the track angle, ds = (θ - φ) / pi, where φ represents the track angle and is calculated from the orbital eccentricity and the true anomaly. Write the difference between the true anomaly and the track angle at each azimuth time into the data file to be transmitted to the FPGA. And form an array of the backscattering coefficients (all set to 1 in this example) and the random phases (all set to 0 in this example) of all simulated point targets and write it into the data file to be transmitted to the FPGA.

[0083] In some embodiments, 16 fixed parameters are calculated and written into the FPGA data file. The specific implementation is as follows:

[0084] para1 = Earth_rev / PRF / pi

[0085] para2 = Earth_rev * ver_data / 2 / PRF / pi

[0086] para3 = Antenna_Length / Wave_Length * pi

[0087] para4 = 1 / (pi * Antenna_Length / Wave_Length) / pi

[0088] para5 = Wave_Length / Antenna_Length / 2 * 0.886 / pi

[0089] para6 = 2 * R_ref

[0090] para7 = 1 / (t_interval / xx * c)

[0091] para8 = Valid_Rangnum * xx / 2 + hor_data * xx / 2

[0092] para9 = xx * hor_data

[0093] para10 = -4 / Wave_Length

[0094] para11 = Angle_W / 180

[0095] para12 = Angle_Inclination / 180

[0096] para13 = Angle_Omig / 180

[0097] para14 = Angle_Look / 180

[0098] para15 = 0

[0099] para16 = 0

[0100] Among them, Earth_rev is the angular velocity of the Earth's rotation, PRF is the ideal repetition frequency, pi is the typical value of pi, ver_data is the number of azimuth simulation pulses, Antenna_Length is the antenna length, Wave_Length is the operating wavelength, t_interval is the range sampling period, xx is the interpolation multiple 4, hor_data is the number of range sampling points, Angle_W is the argument of perigee, Angle_Inclination is the orbital inclination, Angle_Omig is the right ascension of the ascending node, Angle_Look is the antenna center viewing angle, R_ref is the distance from the scene center to the antenna center at the simulation center time, c is the speed of light, and Valid_Rangnum is the number of valid range points.

[0101] Therefore, in the embodiment of the present invention, the CPU is used to obtain simulation parameters and perform preliminary simple calculations based on these simulation parameters. Then, the Doppler parameters at the simulation center time, several fixed parameters, simulation echo parameters that change with the azimuth time, and simulation echo parameters that change with point targets obtained from the calculations are transmitted to the FPGA for complex echo operations. By combining the operation characteristics of spaceborne SAR simulation, different operation parts in spaceborne SAR simulation are allocated to the most suitable hardware resources. In this way, not only the utilization rate of hardware resources is maximized, but also the overall simulation efficiency is improved.

[0102] In the embodiment of the present invention, the host computer (CPU) uses the XDMA driver provided by Xilinx official in cooperation with the XDMA functional IP core on the FPGA to implement the DMA technology based on PCIe. The host computer accesses the FPGA board through the PCIe interface and transmits the simulation echo intermediate parameter file to the FPGA. After the host computer implants the XDMA driver provided by Xilinx official, the FPGA board, which is a slave device of the PCIe interface, is mapped to the address space in the memory. By using the DMA technology, data reading and writing can be performed efficiently. The DMA length is 128KB, and the data interaction function on the host computer side is realized by accessing the corresponding address space through the file writing and reading functions.

[0103] Regarding step 102:

[0104] In some embodiments, the PCIe interface module includes two groups of upstream interfaces, two groups of downstream interfaces, and an AXI_LITE_M interface. Among them, the upstream interfaces receive data from the user logic module through the AXI_STREAM interface and send the received data to the CPU side through the PCIe3.0 x8 interface. The downstream interfaces receive data from the CPU side and transmit the data to the FPGA side through the AXI_STREAM interface. The AXI_LITE_M interface is connected to the BRAM_CONTROLLER IP core for functional control of the FPGA.

[0105] In the embodiments of the present invention, the FPGA side adopts the XDMA function IP core provided by Xilinx official. By configuring the IP core, a PCIe interface module is formed. One side accesses the user logic through the AXI_STREAM interface, and the other side accesses the PCIe host, that is, the corresponding upper computer, through PCIe3.0x8. A total of two groups of upstream interfaces and two groups of downstream interfaces are designed. The protocol is axi_stream, and the data bit width is 256 bits. The AXI_LITE_M interface is enabled and connected to the IP core of the BRAM_CONTROLLER provided by Xilinx official. The output ports of this IP core are used to control 4 32-bit registers for realizing functional control, thereby realizing the data interaction function on the FPGA board side.

[0106] In some embodiments, the FPGA side includes a data receiving module, a calculation module, and a data feedback module. Among them, the data receiving module is connected to the downstream interface of the PCIe interface module, and is used to receive the intermediate parameters of the simulated echo transmitted from the CPU side and store them in the corresponding storage medium in sequence for later use. The calculation module is used to read the intermediate parameters of the simulated echo received by the data receiving module and perform acceleration calculation, and output the calculated chirp signal to the data feedback module. The data feedback module is connected to the upstream interface of the PCIe interface module and is used to feedback the chirp signal received from the calculation module to the CPU side in sequence.

[0107] In some embodiments, the storage medium includes on-chip RAM and off-chip DDR. The data receiving module includes an arbitration unit and a two-stage FIFO data buffer. After the intermediate parameters of the simulated echo transmitted from the CPU side enter the first-stage FIFO buffer, they are shunted. The arbitration unit determines the corresponding storage medium of the corresponding data according to the address of the intermediate parameters of the simulated echo. The simulated echo parameters changing with the azimuth time are stored in the on-chip RAM, and the simulated echo parameters changing with the point target enter the next-stage FIFO buffer and are stored in the off-chip DDR after passing through the second-stage FIFO buffer.

[0108] In the embodiments of the present invention, the data order in the simulation echo intermediate parameter data file transmitted by the host computer is pre-agreed. Therefore, in the FPGA, a counter method is used to generate the address of the input data and store it in order. The Doppler parameters, several fixed parameters, and the parameters varying with the azimuth time of the simulation center time transmitted by the host computer to the FPGA are stored in the RAM generated by the IP core for generating RAM provided by Xilinx official in the order of increasing address. It is located inside the FPGA and belongs to the on-chip storage resource; the simulation echo parameters varying with the point target transmitted by the host computer are stored in the off-chip DDR integrated on the FPGA board by the data receiving module of the FPGA. Because the data volume of the point target is large, it is not suitable to occupy the on-chip storage medium. Therefore, it is selected to be stored in the off-chip board-mounted DDR for later use.

[0109] In the data receiving module of the FPGA, an arbitration unit is used to judge which area the data transmitted by the host computer should be stored in, and before the FPGA starts to calculate, the data required for calculation is transmitted to the calculation module of the FPGA in order according to the data reading requirements. The arbitration module judges whether the corresponding data should be stored in the on-chip RAM or DDR by incrementing the address, and uses the official IP core provided by Xilinx to control the DDR, that is, uses MIG to control the DDR. MIG contains a memory controller and a PHY, which can be directly connected to the DDR4 chip on one side and directly connected to the user logic on the other side. The user interface can select the app mode.

[0110] Moreover, a two-level buffer design is adopted for the data stream, and two FIFOs are set as data buffers. All data are split after passing through the first FIFO. The Doppler parameters, several fixed parameters, and the simulation echo parameters varying with the azimuth time of the simulation center time enter the on-chip RAM, and the simulation echo parameters varying with the point target enter the next-level FIFO, and then the simulation echo parameters varying with the point target enter the DDR after passing through the second-level FIFO.

[0111] In summary, in the embodiments of the present invention, by adopting the above method, the Doppler parameters, several fixed parameters, and the simulation echo parameters varying with the azimuth time of the simulation center time, which have a small data volume, high real-time performance, and need to be accessed frequently and quickly, are stored in the on-chip RAM with a small capacity but a fast access speed, and the simulation echo parameters varying with the point target, which have a large data volume, a low access frequency, and a low real-time performance, are stored in the off-chip DDR with a low access speed but a large capacity, thereby realizing the high-efficiency calculation of data.

[0112] In some embodiments, the computing module includes a control sub-module and an echo calculation sub-module, where: the control sub-module controls data reading, data output, and the echo calculation process through a state machine, and the echo calculation sub-module is used to perform accelerated calculation based on the received intermediate parameters of the simulated echo to obtain a chirp signal.

[0113] In the embodiments of the present invention, the implementation manner of the control sub-module is as follows: The point_k_loop_ctrl module in the point_k_loop_top module that undertakes the echo data calculation task is the control sub-module of the entire echo generation process, and there is a state machine therein: idle, lp_being, initiation, data_read, data_clr, and data_write. The following is a detailed introduction to this control state machine.

[0114] idle: The idle state, initializes all data, and selects to enter initiation or lp_being according to the received command;

[0115] initiation: The initialization stage, waits for the system to complete initialization, that is, reads the parameter constants (16 fixed parameters), and the waiting duration is INT_DELAY (declared in point_k_loop_pkg). After sufficient waiting time, it enters data_read; when receiving h55, it enters idle;

[0116] lp_being: The waiting state, waits to enter initiation after the h2c_done_d signal (the read completion flag from axis_h2c_0 (effective after all relevant data in ctrl's ver_data is read) & axis_h2c_1 (effective after the addr in ctrl is full) is valid. This state is the state of waiting for the data in axis_h2c_1 to be read completely (reads the required data from the PCIe interface module to the buffer of axis_h2c_1));

[0117] data_read: The state of reading data, calculating and generating an echo, and storing it in the FIFO (reads data from the buffer of aixs_h2c_1 to the point_k_loop module, calculates and generates chirp_data, and puts it into the FIFO of axis_c2h). At each azimuth time, reads the data of each simulated point target, calculates and generates chirp_data, and then stores it in the FIFO of axis_c2h until all simulated point targets in this azimuth time are calculated and then enters data_write; when receiving h55, it enters idle;

[0118] data_write: If the azimuth time = the number of azimuth simulation pulses, it means that all azimuth time data have been read and the corresponding echo data have been generated and stored in the FIFO of axis_c2h or sent to h55, then it enters the idle state; after coming out of data_read, it starts to enter the loop of chirp_state, that is, the process of transmitting the echo data of an entire azimuth time back to the PCIe module through the FIFO in axis_c2h. After completing the upload of the echo data for one azimuth time, it returns to data_read to read the data for the next azimuth time, and the process of echo generation and writing to the FIFO.

[0119] Furthermore, in the embodiments of the present invention, chirp_state_FSM (the finite state machine of chirp_data) is nested in data_read and data_wtite. Thus, the state transition of chirp operations can be more centrally managed and controlled, thereby realizing a fast response to the data stream, and in some states, unnecessary data transmission can be reduced, saving bandwidth and processing time.

[0120] Specifically, chirp_state_FSM includes the following states: chirp_idle: the idle state, initializes relevant parameters, and then enters chirp_delay; chirp_delay: the state of writing data delay, enters chirp_read after the write data delay count is full; chirp_read: generates ram_sel and rd_en signals, controls the chirp_data_read module to perform RAM-related operations on chirp_data; chirp_clr: the state of clearing data, controls the chirp_data_gen module to clear data, and then enters chirp_done; chirp_done: indicates that the operations related to chirp_data are completed, and then returns to chirp_idle.

[0121] In some embodiments, in the FPGA program of the embodiments of the present invention, parametric design is carried out. Key parameters such as the number of point targets, the number of azimuth pulses, the number of range samples, the interpolation factor, and the read-write delay are declared in a parameter file. By calling this parameter file in each module of the FPGA code, the call of key parameters can be realized. Relying on these key parameters, the FPGA can generate simulation data with different point targets and different resolutions according to requirements.

[0122] In some embodiments, the echo calculation sub-module includes a coordinate conversion unit, a phase_gen unit, a chirp_data_gen unit, and a chirp_data_read unit, where: the coordinate conversion unit is configured to convert the positions of the received satellite and the simulated point target from the rotating geocentric coordinate system to the antenna coordinate system and input them into the phase_gen unit. The phase_gen unit calculates the antenna pattern, range gate number, and phase of each simulated point at each azimuth time using the input data and inputs them into the chirp_data_gen unit. The chirp_data_gen unit calculates the real and imaginary parts of the chirp signal using the input data and inputs them into the chirp_data_read unit. The chirp_data_read unit superimposes the chirp signals input at the current time and the previous time according to the range gate number and azimuth time and transmits them to the data feedback module.

[0123] In the embodiments of the present invention, the calculation functional unit of the point_k_loop_top module responsible for the echo data calculation task is point_k_loop, which integrates all the functional units of the entire chirp_data (chirp signal) calculation process. To improve the simulation efficiency, this module adopts a pipeline design and divides the entire simulation process into eight functional units, including: five are coordinate system conversion units (trans_Eg_Eo, trans_Eo_Ev, trans_Ev_Er, trans_Er_Ee, trans_Ee_Ea), a phase_gen unit, a chirp_data_gen unit, and a chirp_data_read unit. The specific implementation methods of each unit are explained below:

[0124] The implementation method of the trans_Eg_Eo unit is as follows: The function of this unit is to convert the coordinates from the rotating geocentric coordinate system to the equatorial inertial system: x o = cos(Earth_rev * t) * x g - sin(Earth_rev * t) * y g , y o = sin(Earth_rev * t) * x g + cos(Earth_rev * t) * y g , z o = z g ;

[0125] where Earth_rev represents the angular velocity of the Earth's rotation,

[0126] The implementation method of the trans_Eo_Ev unit is as follows: The function of this unit is to transform coordinates from the equatorial inertial system to the satellite orbit plane coordinate system. The specific implementation method is: First, rotate counterclockwise around the z-axis by the angle of the right ascension of the ascending node. The expression is as follows: x1 = cos(Angle_Omig * pi / 180) * x o + sin(Angle_Omig * pi / 180) * y o , y1 = -sin(Angle_Omig * pi / 180) * x o + cos(Angle_Omig * pi / 180) * y o , z1 = z o , where Angle_Omig is the right ascension of the ascending node;

[0127] Then, rotate counterclockwise around the x-axis by the angle of the orbital inclination. The expression is: x2 = x1, y2 = cos(Angle_Inclination * pi / 180) * y1 + sin(Angle_Inclination * pi / 180) * z1, z2 = -sin(Angle_Inclination * pi / 180) * y1 + cos(Angle_Inclination * pi / 180) * z1, where Angle_Inclination is the orbital inclination;

[0128] Finally, rotate counterclockwise around the z-axis by the angle of the argument of perigee. The expression is, x v = cos(Angle_W * pi / 180) * x2 + sin(Angle_W * pi / 180) * y2, y v = -sin(Angle_W * pi / 180) * x2 + cos(Angle_W * pi / 180) * y2, z v = z2, where Angle_W is the argument of perigee.

[0129] The implementation method of the trans_Ev_Er unit is as follows. The function of this unit is to transform coordinates from the satellite orbit plane coordinate system to the satellite platform coordinate system. The expression is: z r = z v , where θ is the true anomaly, is the track angle;

[0130] The implementation method of the trans_Er_Ee unit is as follows. The function of this unit is to transform coordinates from the satellite platform coordinate system to the satellite body coordinate system. The specific implementation method is: First, rotate the yaw angle around the y-axis, and the expression is: x1 = cos(yaw) * x r + sin(yaw) * z r , y1 = y r , z1 = -sin(yaw) * x r + cos(yaw) * z r , where yaw is the yaw angle; then rotate the pitch angle around the z-axis, and the expression is: x2 = cos(pitch) * x1 + sin(pitch) * y1, y2 = -sin(pitch) * x1 + cos(pitch) * y1, z2 = z1, where pitch is the pitch angle; finally, rotate the roll angle around the x-axis, and the expression is x e = x2, y e = cos(pitch) * y2 + sin(pitch) * z2, z e = -sin(pitch) * y2 + cos(pitch) * z2, where roll is the roll angle;

[0131] The implementation method of the trans_Ee_Ea unit is as follows. The function of this unit is to transform coordinates from the satellite body coordinate system to the antenna coordinate system. The expression is: x a = x e , y a = cos(Look_Angle * pi / 180) * y e - sin(Look_Angle * pi / 180) * z e , z a = sin(Look_Angle * pi / 180) * y e + cos(Look_Angle * pi / 180) * z e , where Look_Angle is the antenna center viewing angle.

[0132] Through the above conversion process, the conversion of the relative coordinate vector (R x , R y , R z ) from the rotating geocentric coordinate system to the antenna coordinate system is realized.

[0133] It should be noted that the multiplication, addition, and subtraction involved in the above coordinate conversion unit calculations are all implemented using the double-precision multiplication, addition, and subtraction IP cores provided by Xilinx official; the sine and cosine operations involved are implemented using a separate sine and cosine function operation module.

[0134] The specific implementation of the phase_gen unit is as follows:

[0135] First, calculate the slant range distance between the satellite and the target: distance

[0136]

[0137] where, R x , R y , R z are the relative coordinate vectors of the satellite and the target point;

[0138] Then, calculate the angle between the line connecting the satellite and the target point: sttphase = atan(R x / R y );

[0139] Then, calculate the antenna radiation pattern wa2: wa2 = sin(pi * Antenna_Length * sttphase / Wave_Length) / (pi * Antenna_Length * sttphase / Wave_Length), where Antenna_Length is the antenna length and Wave_Length is the operating wavelength;

[0140] Next, calculate the range gate number num_min: num_min = (2 * distance - 2 * R_ref) / (t_interval / xx * c) - Valid_Rangnum * xx / 2 + hor_data * xx / 2; where R_ref is the distance from the scene center to the antenna center at the simulation center time, t_interval is the range sampling period, xx is the interpolation factor, c is the speed of light, Valid_Rangnum is the number of points within a pulse width, and hor_data is the number of range samples;

[0141] Finally, calculate the phase phase: phase = -4 * distance / Wave_Length + cor[point].im, where cor[point].im is the backward random phase of the corresponding point target;

[0142] The multiplications, additions, and subtractions involved in the calculations are all implemented using the double-precision multiplication, square root, addition, and subtraction IP cores provided by Xilinx official; the sine and cosine operations involved are implemented using a separate sine and cosine function operation module; the arctangent function operation is implemented through the arctangent function IP core provided by Xilinx official;

[0143] The implementation method of the chirp_data_gen unit is as follows: This unit uses the antenna pattern (wa2), range gate number (num_min), and phase (phase) data input by the phase_gen unit to complete the calculation of the real part chirp_data[num_min].re and the imaginary part chirp_data[num_min].im of the chirp_data (chirp signal) and transmits them to the chirp_data_read module; the calculation method is as follows: chirp_data[num_min].re = cor[point].re * wa2 * cos(phase), chirp_data[num_min].im = cor[point].re * wa2 * sin(phase);

[0144] Among them, cor[point].re is the backscattering coefficient of the target corresponding to the simulation point.

[0145] The chirp_data_read unit will perform superposition processing on the chirp_data output by the chirp_data_gen unit according to the range gate number and azimuth time. After the final processing, it will transmit the superimposed chirp_data together with the address information (chirp_data_addr) to the data feedback module;

[0146] The real part and the imaginary part of the chirp_data are superimposed according to the range gate number in the following way:

[0147] chirp_data[num_min].re = chirp_data[num_min].re + chirp_data_new[num_min].re, chirp_data[num_min].im = chirp_data[num_min].im + chirp_data_new[num_min].im

[0148] Among them, chirp_data[num_min].re and chirp_data[num_min].im are the real and imaginary parts of chirp_data already stored in the corresponding positions, and chirp_data_new[num_min].re and chirp_data_new[num_min].im are the real and imaginary parts of the new chirp_data input from the phase_gen module. The existing chirp_data and the newly calculated and generated chirp_data are superimposed according to the consistency of the range gate number and the azimuth time, so as to generate the final chirp signal. After the superposition of the final chirp signal is completed, it is transmitted to the data feedback module.

[0149] In the embodiment of the present invention, in order to reduce the increased time consumption caused by the RAM read and write delay, the chirp_data_read unit adopts a ping-pong operation, and designs two single-port RAMs for temporarily storing the real part of chirp_data and two single-port RAMs for storing the imaginary part of chirp_data. These two RAMs are both generated by the RAM generator provided by Xilinx official, and are storage resources inside the FPGA. Their address signals are generated depending on the range gate number and the azimuth time input by the phase_gen unit.

[0150] In some embodiments, the echo calculation sub-module divides the calculated chirp signal into two parts, and writes them into two DDRs through two FIFOs respectively. The data feedback module reads the chirp signal from the two DDRs through a two-level FIFO structure of two channels and feeds it back to the CPU side.

[0151] In the embodiment of the present invention, the echo calculation sub-module divides the chirp signal into two parts through two-level FIFOs. The first half of the data is written into the first DDR through the first-level FIFO, and the second half of the data is written into the second DDR through the second-level FIFO; the FIFO is implemented by using the FIFO function IP core provided by Xilinx official. The two FIFOs have the same configuration, and the write data bit width is 160 bits, where the lower 128 bits are chirp_data and the higher 32 bits are address information. The read data source is the chirp_data_read module; the write data bit width is 640 bits, the higher 32 bits are address information, and the 0-127 bits, 160-287 bits, 320-447 bits, and 480-607 bits in the lower 608 bits are four chirp_data data, and the write data destination is the DDR corresponding to this FIFO.

[0152] When reading data from the DDR and sending it back to the host computer, the FPGA reads and transmits data through a two-level FIFO structure with two channels. The first-level FIFO is between the DDR interface and the user logic of the AXI_STREAM interface of the FPGA, which buffers the data. It is generated using the FIFO function IP core provided by Xilinx official. The write data width is 512 bits, and the write port is directly connected to the corresponding DDR. The read data width is 256 bits, and the read port is directly connected to the user interface in AXI_STREAM mode. An axi_stream_fifo is also designed between the user interface of AXI_STREAM and the upstream AXI_STREAM interface of the PCIe interface module. It is generated using the IP core of the axis_fifo function provided by Xilinx official. The write interface width is 256 bits and is connected to the user interface of AXI_STREAM, and the read interface width is 256 bits and is connected to the upstream AXI_STEAM interface of the PCIe interface module. Thus, the function of sending the chirp_data data stored in the DDR back to the host computer is realized.

[0153] In the embodiment of the present invention, adopting the above-mentioned dual-channel two-level FIFO design can not only provide necessary data buffering to ensure the continuity and stability of data transmission, but also efficiently complete the task of sending data back from the DDR memory to the host computer, ensuring data integrity and transmission speed.

[0154] Regarding step 104:

[0155] In some embodiments, the FPGA end sends the chirp signal back to the CPU end through the PCIe interface module for further calculation, including:

[0156] The CPU end reads a number of chirp signals sent back from the FPGA end into an array in sequence, and performs fast Fourier transform and inverse fast Fourier transform with a preset number of points in sequence;

[0157] Read the real and imaginary parts of hor_data (number of samples in the range direction) * xx chirp_data into an array in sequence, and then perform a fast Fourier transform (FFT) with n points on the chirp_data array, where n satisfies 2^n = hor_data;

[0158] Process the chirp_data that has undergone FFT as follows:

[0159] chirp_data[j].re = chirp_data[j].re * chirp_F[j].re - chirp_data[j].im * chirp_F[j].im, chirp_data[j].im = chirp_data[j].re * chirp_F[j].im + chirp_data[j].im * chirp_F[j].re

[0160] where chirp_F[j].re = cos(-pi * b * t * t), chirp_F[j].im = sin(-pi * b * t * t), b is the signal frequency modulation slope, t = (j - Valid_Rangnum * xx / 2) * t_interval / xx, where j is the incrementing count number not greater than Valid_Rangnum * xx; then perform IFFT with the same number of points on chirp_data;

[0161] Downsample the chirp signal after the inverse fast Fourier transform; the expression is: data[j] = chirp_data[xx * j + xx / 2], where j is the incrementing count number not greater than hor_data;

[0162] Perform frequency loading on the downsampled data to obtain the simulated echo file; the specific implementation method is as follows: t = (j - hor_data / 2) * t_interval + 2 * R_ref / c, phase = 2 * W_ref * t,

[0163] where W_ref is the carrier frequency of the intermediate frequency signal, data[j].re = data[j].re * cos(phase) - data[j].im * sin(phase), data[j].im = data[j].im * cos(phase) + data[j].re * sin(phase), j is the incrementing count number less than hor_data;

[0164] In the embodiment of the present invention, finally write the data data obtained after the frequency loading process into a specified file, that is, the simulated echo file, and input the simulated echo file together with the necessary imaging parameters (Doppler parameters at the simulation center time) into the strip imaging program to perform imaging, that is, finally simulate and generate the echo data.

[0165] To prove the effectiveness of the embodiment of the present invention, the following simulation tests were carried out: Let the heterogeneous platform based on FPGA and the traditional CPU platform generate echoes under the simulation parameters shown in Table 1, calculate the time consumption of each platform respectively, and compare the consistency of the echo data generated by the two platforms;

[0166] Table 1 Partial Simulation System Parameters

[0167]

[0168]

[0169] After measurement, the time taken to generate a chirp signal on the FPGA-based heterogeneous platform is 57 s, and the time taken to generate the final echo on the traditional CPU platform is 10339 s. Among them, the time taken to generate the echo signal by post-processing the chirp signal is 266 s. Thus, it can be seen that the time taken for the traditional CPU platform to generate only the chirp signal is 10073 s. It can be seen that the FPGA-based heterogeneous platform has a 177-fold improvement in execution efficiency in the task of generating chirp signals, with an extremely significant acceleration effect, achieving the engineering goal of the invention.

[0170] Furthermore, the correlation coefficient of the echo data generated by the two platforms is calculated. The result shows that the correlation coefficient reaches 0.986659, indicating that the two sets of echo data have a high degree of consistency. Thus, the correctness of the calculation results of the FPGA-based heterogeneous platform is verified, meeting the preset engineering requirements of the invention.

[0171] In summary, the embodiment of the present invention realizes the rapid generation of spaceborne SAR echo simulation on the FPGA-based heterogeneous platform, achieving a 177-fold efficiency improvement compared to the traditional CPU platform, and also obtaining a high correlation coefficient of 0.986659 in data consistency, achieving the preset engineering goal and having great engineering value.

[0172] The embodiment of the present invention also provides a computing device, including a memory and a processor. The memory is used to store the data calculated by the FPGA. When the processor, i.e., the FPGA, executes the program, it realizes the method described in any embodiment of this specification.

[0173] The embodiment of the present invention also provides a computer-readable storage medium, on which computer and FPGA programs are stored. When the computer program is executed on the computer and the FPGA program is burned into the corresponding FPGA through the corresponding development software, the computer and the FPGA jointly execute the method described in any embodiment of this specification.

[0174] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A spaceborne SAR simulation method based on FPGA heterogeneous platform, characterized in that: The spaceborne SAR simulation is implemented based on a CPU and FPGA heterogeneous platform, and the method includes: The CPU calculates the simulated echo intermediate parameters according to the obtained simulation parameters; wherein the simulated echo intermediate parameters include the Doppler parameters at the simulation center time, a number of fixed parameters, simulated echo parameters that change with the azimuth time, and simulated echo parameters that change with the point target; The CPU accesses the PCIe interface module in the FPGA to transmit the simulated echo intermediate parameters to the FPGA for accelerated calculation to obtain a linear frequency modulation signal; The FPGA end transmits the linear frequency modulation signal back to the CPU end through the PCIe interface module for recalculation, and images the calculated echo file with the Doppler parameters at the simulation center time to obtain a space-borne SAR image.

2. The method according to claim 1, characterized in that The simulation parameters include earth parameters, satellite orbit parameters and radar parameters; the simulation echo parameters that change with the azimuth moment include the coordinates of the satellite in the orbital plane, the yaw angle, and the difference between the true pericentric angle and the track angle at each azimuth moment; At each azimuth moment, the following operations are performed: Calculate orbital eccentricity and true pericentricity based on satellite parameters, radar parameters and simulation center time; Calculating the coordinates of the satellite in the orbital plane according to the orbital eccentricity angle, true pericentricity angle and radial vector; According to the typical values ​​of orbital eccentricity, true anomaly and pi, the difference between the true anomaly and the track angle at each azimuth is calculated; The yaw angle at each azimuth moment is processed based on the acquired satellite parameters to obtain the yaw angle.

3. The method according to claim 1, characterized in that The simulated echo parameters that vary with the point target include the coordinates of each simulated point in the simulation scene; The coordinates of each simulation point in the simulation scene are calculated as follows: According to the obtained simulation parameters, the satellite at the simulation center time, the point in the antenna coordinate system, the point where the antenna points to the ground, and the position of the phase center in the corresponding coordinate system are calculated; According to the points in the satellite and antenna coordinate systems, the points where the antenna points to the ground, and the positions of the phase center in the corresponding coordinate systems, the longitude and latitude of the center point of the simulation scene are solved; Based on the longitude and latitude of the center of the simulation scene, the simulation points are arranged at preset intervals to form an n×n simulation dot matrix, and the coordinates of each simulation point in the simulation scene are calculated.

4. The method according to claim 1, characterized in that: The Doppler parameters at the simulation center time are calculated as follows: Based on the earth parameters and satellite orbit parameters, the speed and acceleration of the satellite and the simulation point target at the simulation center time are calculated respectively; According to the speed and acceleration of the satellite and the simulation point target at the simulation center time, the relative speed and relative acceleration of the satellite and the simulation point target are calculated; The Doppler frequency and Doppler modulation slope at the simulation center time are calculated according to the relative speed and relative acceleration between the satellite and the simulation point target, the distance between the satellite and the scene center at the simulation center time, and the relative speed between the satellite and the scene center at the simulation center time.

5. The method according to claim 1, characterized in that The PCIe interface module includes two groups of upstream interfaces and two groups of downstream interfaces; the upstream interface receives data from the user logic module through the AXI_STREAM interface, and sends the received data to the CPU end through the PCIe3.0 x8 interface, the downstream interface receives data from the CPU end, and transmits the data to the FPGA end through the AXI_STREAM interface, and the AXI_LITE_M interface is connected to the BRAM_CONTROLLERIP core for functional control of the FPGA.

6. The method according to claim 5, characterized in that The FPGA end includes a data receiving module, a calculation module and a data return module; wherein the data receiving module is connected to the downlink interface of the PCIe interface module, and is used to receive the simulated echo intermediate parameters transmitted by the CPU end and store them in sequence in the corresponding storage medium for use; the calculation module is used to read the simulated echo intermediate parameters received by the data receiving module and perform accelerated calculation, and output the calculated linear frequency modulation signal to the data return module; the data return module is connected to the uplink interface of the PCIe interface module, and is used to return the linear frequency modulation signal received from the calculation module to the CPU end in sequence.

7. The method according to claim 6, characterized in that The storage medium includes on-chip RAM and off-chip DDR; The data receiving module includes an arbitration unit and a two-level FIFO data buffer. The simulated echo intermediate parameters transmitted by the CPU end enter the first-level FIFO buffer and are then diverted. The arbitration unit determines the storage medium corresponding to the corresponding data according to the address of the simulated echo intermediate parameters. The simulated echo parameters that change with the azimuth are stored in the on-chip RAM, and the simulated echo parameters that change with the point target enter the next-level FIFO buffer and are stored in the off-chip DDR after passing through the second-level FIFO buffer.

8. The method according to claim 6, characterized in that The calculation module includes a control submodule and an echo calculation submodule, wherein: The control submodule controls data reading and data output as well as the echo calculation process through a state machine, and the echo calculation submodule is used to perform accelerated calculation based on the received simulated echo intermediate parameters to obtain a linear frequency modulation signal; and / or The echo calculation submodule includes a coordinate conversion unit, a phase_gen unit, a chirp_data_gen unit and a chirp_data_read unit, wherein: The coordinate conversion unit is used to convert the positions of the received satellite and simulation point targets from the rotating geocentric coordinate system to the antenna coordinate system, and input it into the phase_gen unit. The phase_gen unit uses the input data to calculate the antenna radiation pattern, range gate number and phase of each simulation point at each azimuth moment, and inputs it into the chirp_data_gen unit. The chirp_data_gen unit uses the input data to calculate the real and imaginary parts of the linear frequency modulation signal, and inputs it into the chirp_data_read unit. The chirp_data_read unit superimposes the linear frequency modulation signals input at the current moment and the previous moment according to the range gate number and the azimuth moment, and transmits it to the data return module.

9. The method according to claim 6, characterized in that The echo calculation submodule divides the calculated linear frequency modulation signal into two parts, writes them into two DDRs through two FIFOs respectively, and the data return module reads the linear frequency modulation signal from the two DDRs through a two-stage FIFO structure of two channels and returns it to the CPU end.

10. The method according to claim 1, characterized in that The FPGA side transmits the linear frequency modulation signal back to the CPU side through the PCIe interface module for further calculation, including: The CPU reads several linear frequency modulation signals sent back from the FPGA into an array in order, and performs fast Fourier transform and inverse fast Fourier transform of preset points in turn; Downsampling the linear frequency modulation signal after inverse fast Fourier transformation; The downsampled data is loaded with frequency to obtain a simulated echo file.

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