Forwarding type SAR dot matrix target simulation system and method based on FPGA

Abstract

The invention discloses a forwarding type SAR dot matrix target simulation system and method based on an FPGA, and belongs to the field of synthetic aperture radar target simulation. The system comprises a microwave module, a baseband module, a power supply module, a display control module and a backboard, the baseband module comprises an ADC, a DAC and an FPGA chip, and the FPGA chip is used for performing target delay, Doppler frequency superposition and other processing to realize modulation of radar signals. The FPGA is adopted as a core processor, the parallel computing advantage of the FPGA is fully played, and compared with a scheme that a multi-piece high-speed DSP parallel architecture is adopted in traditional SAR echo simulation, the method has the advantages that the processing speed is remarkably increased, and the method can be flexibly applied to processing of complex tasks and is particularly suitable for meeting the high-speed processing requirement of broadband SAR signals. According to the method, under the condition that no actual target exists, various performance indexes of the SAR system can be accurately and efficiently tested and evaluated, and a reliable basis is provided for system optimization.

Description

Technical Field

[0001] The present invention relates to a forward-type SAR dot target simulation system and method based on FPGA, belonging to the field of synthetic aperture radar target simulation. Background Art

[0002] Synthetic Aperture Radar (SAR for short) is a high-resolution imaging radar. With its all-weather and all-time imaging capabilities, it is widely used in remote sensing, military reconnaissance, disaster monitoring and other fields.

[0003] During the development of SAR systems, forward-type SAR target simulators can be used to verify the performance of radar systems in different scenarios. By simulating different targets and environmental conditions, especially when real data is not easily available, the accuracy, resolution and stability of SAR systems can be tested, reducing the cost and time of actual measurements. SAR echo simulation requires a high resolution. To simulate a very high-precision image, a large number of time steps and spatial points need to be processed, resulting in a huge amount of computation and requiring very high computing resources.

[0004] In traditional SAR echo simulation implementation schemes, an architecture with multiple high-speed digital signal processors (DSPs) in parallel is generally adopted. However, this architecture has obvious limitations when dealing with complex tasks, mainly manifested in the lack of system flexibility and difficulty in adapting to the growing simulation requirements. With the continuous development of SAR technology, the limitations of this traditional implementation method have become more prominent, and it is urgent to explore more efficient and flexible solutions. Summary of the Invention

[0005] In order to improve the system flexibility and processing speed of SAR echo simulation, the present invention provides a forward-type SAR dot target simulation system and method based on FPGA. The technical solutions are as follows:

[0006] The present invention provides a forward-type SAR dot target simulation system, including: a microwave module, a baseband module, a power supply module, a display and control module, and a backplane;

[0007] The microwave module includes a down-conversion module, a frequency-agile local oscillator module, and an up-conversion module. The down-conversion module down-converts the radar transmit excitation signal to output an intermediate-frequency signal with a constant power; the frequency-agile local oscillator module generates the sampling reference clock required by the baseband module and the local oscillator signal required by the radio frequency module; the up-conversion module up-converts the intermediate-frequency signal output by the baseband module to output a radio frequency signal with the same frequency as the radar transmit excitation signal, and outputs it after power control;

[0008] The baseband module includes an ADC, a DAC, and an FPGA chip. The ADC realizes high-speed acquisition of the intermediate-frequency signal input to the baseband module; the DAC outputs the intermediate-frequency signal; the FPGA chip performs processing such as target delay and Doppler frequency superposition to realize the modulation of radar signals.

[0009] The power supply module is used for power supply.

[0010] The display and control module runs an operating system and is used for controlling target parameters, and controls the operation of the entire system through upper computer software.

[0011] The backplane is used to complete data exchange between various modules.

[0012] Optionally, the power supply module converts the externally input 28V power supply into +12V and -12V, and supplies power to all other modules through the backplane.

[0013] Optionally, the backplane is of a CPCIe / PXIe bus architecture.

[0014] The present invention provides a method for simulating a forward SAR dot target. The method is implemented based on the forward SAR dot target simulation system described in any one of the above, and includes:

[0015] Step 1: Receive a radar excitation signal, and output an intermediate-frequency signal through the down-conversion module.

[0016] Step 2: Sample the intermediate-frequency signal using the ADC of the baseband module, and convert it into two digital signals, I and Q, through down-conversion DDC.

[0017] Step 3: According to the radar system parameters and scene parameters set by the user, obtain the number of clock cycles for target delay and the Doppler frequency within the radar beam coverage area.

[0018] Step 4: Use the FIFO in the FPGA chip of the baseband module to receive the number of clock cycles for target delay and the Doppler frequency.

[0019] Step 5: At the rising edge of the pulse repetition frequency (PRF), use the RAM in the FPGA chip of the baseband module to realize the superposition of target delay information of the digital signal in Step 2, and use the Doppler superposition module to realize the superposition of target Doppler frequency.

[0020] Step 6: Up-convert the signal obtained in Step 5 through DUC, and output an intermediate-frequency signal through the DAC of the baseband module.

[0021] Step 7: Microwave up-convert the baseband signal with the superimposed dot target information to obtain the SAR echo signal.

[0022] Optionally, in step 1, the forward SAR target simulator host receives the radar excitation signal. The synthetic aperture radar emits an LFM signal, and its mathematical expression is:

[0023]

[0024] where A m is the scattering coefficient, f c is the carrier frequency, k r is the frequency modulation rate, M is the number of pulses, and τ is the instantaneous time.

[0025] Optionally, the number of clock delays for the dot matrix target in step 3 is expressed as:

[0026]

[0027] where (x i , y i , 0) is the target position, v is the flight speed of the carrier aircraft, H is the platform altitude, R t is the delay distance of the target information, c is the speed of light, t is the slow time, and F is the clock operating frequency of the FPGA chip in the baseband module;

[0028] The Doppler frequency is expressed as:

[0029]

[0030] where v r is the radial flight speed of the carrier aircraft, and f c is the carrier frequency.

[0031] Optionally, the Doppler superposition module uses DDS to multiply the generated Doppler sequence with the input IQ digital signal to obtain the echo signal with Doppler superimposed.

[0032] Optionally, the SAR echo signal is expressed as:

[0033]

[0034] where A0 is the target scattering coefficient, rect(·) is the pulse envelope, and T r is the pulse repetition period.

[0035] Optionally, the model of the FPGA chip is XCKU060.

[0036] Optionally, the model of the ADC in the baseband module is ADC083000.

[0037] Optionally, the model of the DAC in the baseband module is AD9739.

[0038] The beneficial effects of the present invention are:

[0039] The present invention designs a forward - type SAR dot - target simulation system and method based on FPGA. It uses FPGA as the core processor and fully exploits its parallel computing advantages. Compared with the traditional SAR echo simulation scheme that uses a parallel architecture of multiple high - speed DSPs, the present invention significantly improves the processing speed and can be flexibly applied to the processing of complex tasks, especially suitable for the high - speed processing requirements of broadband SAR signals. In addition, the reconfigurable characteristic of FPGA hardware resources makes the system have higher flexibility, and the processing architecture can be dynamically adjusted according to different simulation requirements, overcoming the problems of difficult firmware upgrade and limited function expansion in the traditional DSP scheme. Based on the multi - channel parallel processing mechanism of FPGA, the present invention realizes the efficient simulation of dot - array SAR echoes and significantly improves the overall throughput of the system.

[0040] Without actual targets, the present invention can accurately and efficiently test and evaluate various performance indicators of the SAR system, providing a reliable basis for system optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0042] Figure 1 It is the system design block diagram of the forward - type SAR dot - target simulation of the present invention.

[0043] Figure 2 It is the flowchart of the implementation method of the forward - type SAR dot - target simulation of the present invention.

[0044] Figure 3 It is the flowchart of the host - computer design of the forward - type SAR dot - target simulation of the present invention.

[0045] Figure 4 It is the flowchart of the base - band design of the forward - type SAR dot - target simulation of the present invention.

[0046] Figure 5 It is the simulation schematic diagram of the SAR dot - target simulation.

[0047] Figure 6 It is the imaging result diagram of the forward - type SAR dot - target simulation of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will further describe the embodiments of the present invention in detail with reference to the drawings.

[0049] Embodiment 1:

[0050] This embodiment provides a forwarding SAR dot target simulation system. Refer to Figure 1 , this system includes: a microwave module, a baseband module, a power supply module, a display and control module, and a backplane.

[0051] The microwave module includes a down-conversion module, a frequency-agile local oscillator module, and an up-conversion module. The down-conversion module down-converts the radar transmission excitation signal and outputs an intermediate-frequency signal with a constant power. The frequency-agile local oscillator module generates the sampling reference clock required by the baseband module and the local oscillator signal required by the radio frequency module. The up-conversion module up-converts the intermediate-frequency signal output by the baseband module, outputs a radio frequency signal with the same frequency as the radar transmission excitation signal, and outputs it after power control.

[0052] The baseband module includes an ADC, a DAC, and an FPGA chip. The ADC realizes high-speed acquisition of the intermediate-frequency signal input to the baseband module. The DAC outputs the intermediate-frequency signal. The FPGA chip performs processing such as target delay and Doppler frequency superposition to realize the modulation of the radar signal;

[0053] In this embodiment, the ADC chip model is ADC083000, which realizes high-speed acquisition of analog signals. ADC083000 (ADC) is a low-power, high-performance CMOS analog-to-digital converter that can digitize signals to 8-bit resolution with a sampling rate of up to 3.4 GSPS. The DAC chip model is AD9739, which realizes the output of high-speed DA signals. AD9739 (DAC) is a 14-bit, 2.5 GSPS high-performance radio frequency digital-to-analog converter that can synthesize broadband signals up to 3.0 GHz. The FPGA chip is a high-performance FPGA-XCKU060 of the Kintex UltraScale series of Xilinx. The board-mounted ARM realizes control and communicates with the host computer through the network. Realize processing such as target delay and Doppler frequency superposition.

[0054] In this embodiment, the power supply module converts the externally input 28V power supply into +12V and -12V, and powers all other modules through the PXIe backplane.

[0055] The display and control module in this embodiment is built with an Intel 3955U processor with a maximum main frequency of 2 GHz and a Windows 7 operating system. It provides 1 high-speed RS422 / 485 serial port with a baud rate support of 2 Mbps, which is used to control other modules of the simulator and external program control. The display and control module runs the operating system and controls the operation of the entire system through the host computer software.

[0056] The backplane in this embodiment is a CPCIe / PXIe bus architecture, which completes data exchange, fan control, etc. of each module.

[0057] Embodiment 2:

[0058] This embodiment provides a method for simulating a forward SAR dot target based on FPGA, which is implemented by using the system described in Embodiment 1, and includes the following steps:

[0059] Step 1: The host of the forward SAR target simulator receives the radar excitation signal and outputs an intermediate frequency signal after microwave down-conversion.

[0060] Step 2: The ADC of the baseband module samples the intermediate frequency signal and converts it into two digital signals of IQ through down-conversion DDC.

[0061] Step 3: According to the radar system parameters and scene parameters set by the user, obtain the number of clock cycles of the dot target delay in the radar beam coverage area and the Doppler frequency.

[0062] Step 4: Use the on-chip FIFO of the FPGA in the baseband module to receive the number of clock cycles of the target delay and the Doppler frequency.

[0063] Step 5: At the rising edge of the pulse repetition frequency PRF, use the on-chip RAM of the FPGA in the baseband module to implement the superposition of the target delay information of the digital signal in Step 2, and use the Doppler superposition module to implement the superposition of the target Doppler frequency.

[0064] Step 6: Up-convert the signal in Step 5 through DUC and output an intermediate frequency signal through DAC.

[0065] Step 7: Microwave up-convert the baseband signal with the superimposed dot target information to obtain the SAR echo signal.

[0066] Further, in Step 1, the host of the forward SAR target simulator receives the radar excitation signal. Generally, the synthetic aperture radar emits an LFM signal, and its mathematical expression is:

[0067]

[0068] where A m is the scattering coefficient, f c is the carrier frequency, k r is the frequency modulation rate, M is the number of pulses, and τ is the instantaneous time. The excitation signal is down-converted to an intermediate frequency signal through microwave to obtain the baseband signal.

[0069] Further, in step 2, the baseband module ADC samples the intermediate frequency signal and converts it into two digital signals, I and Q, through digital downconversion DDC. Among them, the ADC chip model is ADC083000, which is a low-power and high-performance CMOS analog-to-digital converter. It can digitize the signal to 8-bit resolution and has a sampling rate as high as 3.4 GSPS. In this embodiment, an LFM signal with a bandwidth of 140 MHz is sampled and becomes a digital signal after AD sampling. Through downmixing and filtering decimation, the IQ quadrature components of the signal are obtained.

[0070] Further, in step 3, according to the radar system parameters and scene parameters input on the simulator host interface, the host computer software program calculates to obtain the number of clock cycles of the dot target delay and the Doppler frequency within the radar beam coverage area. The target delay distance is expressed as (x i ,y i ,0) is the target position, v is the flight speed of the carrier aircraft, H is the platform altitude, and t is the slow time. The number of clock cycles N of the target delay can be obtained through the following formula:

[0071]

[0072] where R t is the delay distance of the target information, c is the speed of light, and F is the clock operating frequency of the FPGA in the baseband module. The target Doppler can be expressed as:

[0073]

[0074] where v r is the radial flight speed of the carrier aircraft, and f c is the carrier frequency.

[0075] Further, in step 4, the on-chip FIFO of the baseband module FPGA receives the dot target information. In this embodiment, the FPGA chip model is XCKU060, and the width of the on-chip FIFO buffer is set to the data bit width of the dot target information.

[0076] Further, in step 5, at the rising edge of the pulse repetition frequency PRF of the radar excitation signal, the RAM is used to read the number of pulse delays in the FIFO to achieve the superposition of the target delay information of the two digital signals, I and Q. A Doppler superposition module is built, and the DDS is used to generate a Doppler sequence and complex multiply it with the input IQ data to obtain the echo signal with Doppler superimposed.

[0077] Further, in step 6, the signal in step 5 is up-converted by DUC and output as an intermediate frequency signal through DAC. In this embodiment, the digital up-conversion DUC corresponds exactly to the digital down-conversion and consists of two parts: interpolation filtering and IQ modulation. In this example, the DAC chip model is AD9739, which is a high-performance radio frequency digital-to-analog converter with 14 bits and 2.5 GSPS, and can synthesize broadband signals up to 3.0 GHz.

[0078] Further, in step 7, the baseband signal with the overlaid dot matrix target information is up-converted by microwave to obtain the SAR echo signal. Taking a single pulse as an example, the SAR echo can be expressed as:

[0079]

[0080] where A0 is the target scattering coefficient, rect(·) is the pulse envelope, and T r is the pulse repetition period.

[0081] Next, the host computer and the baseband data processing flow of this embodiment will be further described.

[0082] As Figure 3 shown, the host computer data processing flow of the forward SAR dot matrix target simulation in this embodiment is as follows:

[0083] (1) According to the set radar status information, target position, and carrier position, prompt the user for the duration of the target within 1 frame, starting from the Nth PRF to the Mth PRF.

[0084] (2) Determine whether the baseband FIFO meets the write requirement, and calculate the number of PRF times to be simulated according to the FIFO write count returned by the current baseband module.

[0085] (3) Calculate the switches, distances, and Doppler frequencies of the empty dot matrix target points according to the PRF period and PRF sequence number, and send the target data to the baseband module through the serial port.

[0086] For example, in this embodiment, the host computer software sets 5 ground target positions, carrier altitude and speed, the carrier flying northward, beam azimuth angle and azimuth angle, PRF period and pulse width, and there are 16,000 PRF signals per frame. The host computer calculates the number of delay pulses and Doppler frequencies of the ground targets according to the positions of the targets covered by the radar beam angle.

[0087] As Figure 4 shown, the baseband data processing flow of this embodiment is as follows:

[0088] (1) Perform digital down-conversion DDC processing on the signal after ADC down-sampling and output it to a zero intermediate frequency signal.

[0089] (2) For the serial port data received according to FIFO, perform RAM delay processing on the received number of delay clocks, and perform complex multiplication and superposition on the received Doppler frequency.

[0090] (3) Perform digital up-conversion DUC processing on the signal superimposed with target information, and perform up-sampling through DAC to output an intermediate frequency signal.

[0091] For example, in this embodiment, the baseband module receives the intermediate frequency signal output by microwave down-conversion, the internal ADC chip samples the intermediate frequency signal, down-converts it to I and Q two-channel zero intermediate frequency signals through DDC, and then superimposes the number of delay pulses and Doppler frequency shift sent by the host computer serial port, up-converts it to the intermediate frequency signal through DUC, and performs up-sampling through DAC and outputs it to microwave up-conversion to achieve the output of the forward SAR target signal.

[0092] This embodiment designs a forward SAR dot target simulation system and method based on FPGA. It uses FPGA as the core processor and gives full play to its parallel computing advantages. Compared with the traditional SAR echo simulation scheme that uses a parallel architecture of multiple high-speed DSPs, this embodiment has a significant improvement in processing speed and can be flexibly applied to the processing of complex tasks, especially suitable for the high-speed processing requirements of broadband SAR signals. In addition, the reconfigurable characteristic of FPGA hardware resources makes the system have higher flexibility, and the processing architecture can be dynamically adjusted according to different simulation requirements, overcoming the problems of difficult firmware upgrade and limited function expansion in the traditional DSP scheme. Based on the multi-channel parallel processing mechanism of FPGA, this embodiment realizes the efficient simulation of dot SAR echo and significantly improves the overall throughput of the system.

[0093] This embodiment can accurately and efficiently test and evaluate various performance indicators of the SAR system without actual targets, providing a reliable basis for system optimization.

[0094] Some steps in the embodiments of the present invention can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk, etc.

[0095] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A forwarding SAR dot matrix target simulation system, characterized in that: The system includes: a microwave module, a baseband module, a power module, a display and control module and a backplane; The microwave module includes a down-conversion module, an agile frequency local oscillator module, and an up-conversion module. The down-conversion module down-converts the radar transmission excitation signal and outputs an intermediate frequency signal with constant power; the agile frequency local oscillator module generates a sampling reference clock required by the baseband module and a local oscillator signal required by the radio frequency module; the up-conversion module up-converts the intermediate frequency signal output by the baseband module, outputs an radio frequency signal consistent with the frequency of the radar transmission excitation signal, and outputs it after power control; The baseband module includes an ADC, a DAC and an FPGA chip. The ADC realizes high-speed acquisition of the intermediate frequency signal input to the baseband module; the DAC outputs the intermediate frequency signal; the FPGA chip performs target delay, Doppler frequency superposition and other processing to realize modulation of the radar signal; The power module is used for supplying power; The display and control module runs an operating system for controlling target parameters and controls the operation of the entire system through the host computer software; The backplane is used to complete data exchange among various modules.

2. The forwarding SAR dot matrix target simulation system according to claim 1, characterized in that: The power module converts the external input 28V power into +12V and -12V, and supplies power to all other modules through the backplane.

3. The forwarding SAR dot matrix target simulation system according to claim 1, characterized in that: The backplane is a CPCIe / PXIe bus architecture.

4. A method for simulating a forwarding SAR dot matrix target, characterized in that: The method is implemented based on the forwarding SAR dot matrix target simulation system according to any one of claims 1 to 3, and includes: Step 1: receiving a radar excitation signal, and outputting an intermediate frequency signal through the down-conversion module; Step 2: Sample the intermediate frequency signal using the ADC of the baseband module, and convert it into two-way IQ digital signals through down-conversion DDC; Step 3: According to the radar system parameters and scene parameters set by the user, obtain the number of delayed clocks and Doppler frequency of the dot matrix target in the radar beam coverage area; Step 4: Receive the target delay clock number and Doppler frequency using the FIFO in the FPGA chip of the baseband module; Step 5: At the rising edge of the pulse repetition period PRF, the target delay information superposition of the digital signal in step 2 is realized by using the RAM in the FPGA chip of the baseband module, and the target Doppler frequency superposition is realized by using the Doppler superposition module; Step 6: Up-convert the signal obtained in step 5 through DUC, and output the intermediate frequency signal through the DAC of the baseband module; Step 7: Perform microwave up-conversion on the baseband signal with superimposed dot matrix target information to obtain the SAR echo signal.

5. The method for simulating a forwarding SAR dot matrix target according to claim 4, characterized in that: In step 1, the host of the forwarding SAR target simulator receives the radar excitation signal, and the synthetic aperture radar transmits the LFM signal, whose mathematical expression is: Among them A m is the scattering coefficient, f c is the carrier frequency, k r is the modulation frequency, M is the number of pulses, and τ is the instantaneous time.

6. The method for simulating a forwarding SAR dot matrix target according to claim 4, characterized in that: The number of lattice target delay clocks in step 3 is expressed as: Among them, (x i ,y i ,0) is the target position, v is the aircraft flight speed, H is the platform height, R t is the delay distance of the target information, c is the speed of light, t is the slow time, and F is the clock operating frequency of the baseband module FPGA chip; The Doppler frequency is expressed as: Among them, v r is the radial flight speed of the carrier aircraft, f c is the carrier frequency.

7. The method for simulating a forwarding SAR dot matrix target according to claim 4, characterized in that: The Doppler superposition module uses DDS to generate a Doppler sequence and multiplies the input IQ digital signal to obtain an echo signal superimposed with Doppler.

8. The method for simulating a forwarding SAR dot matrix target according to claim 4, characterized in that: The SAR echo signal is expressed as: Where A0 is the target scattering coefficient, rect(·) is the pulse envelope, T r is the pulse repetition period.

9. The method for simulating a forwarding SAR dot matrix target according to claim 4, characterized in that: The model of the FPGA chip is XCKU060.

10. The method for simulating a forwarding SAR dot matrix target according to claim 4, characterized in that: The ADC model of the baseband module is ADC083000.

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