Radar detection receiver-oriented loosely coupled FPGA and DSP architecture time sequence control method and radar detection receiver-oriented loosely coupled FPGA and DSP architecture time sequence control device

Abstract

The invention discloses a time sequence control method and device for a loosely coupled FPGA and DSP architecture of a radar detection receiver, and relates to the field of radar detection signal processing. The problems of complex time sequence control, low data interaction efficiency and the like of the existing FPGA and DSP architecture are solved. According to the method, the DSP is controlled to work according to the strict working rhythm by relying on the overall time sequence management of the FPGA and combining the interrupt mode, the advantages of the FPGA hardware parallelism and the real-time performance are utilized, the DSP is only used as a processor for sequential execution, the mode balances the real-time performance and the calculation efficiency in a radar detection receiver, and the real-time performance and the calculation efficiency of the radar detection receiver are improved. And when the algorithm function needs to be expanded subsequently, the number of DSP chips can be directly increased, and only the interruption issuing of the FPGA needs to be modified in time sequence control, so that the coupling degree between DSPs is reduced, and the expansibility and the flexibility of the system are improved. The method is also suitable for the field of optimizing the real-time performance and resource allocation efficiency of a signal processing task in a radar detection system.

Description

Technical Field

[0001] The present invention relates to the technical field of radar detection signal processing, and in particular to a timing control method and device for a loose-coupled FPGA and DSP architecture for a radar detection receiver. Background Art

[0002] To meet the target identification requirements in a high-density signal environment, a radar detection system needs to have the ability to parallelly analyze multi-source signals, which are specifically manifested as core indicators such as wide-bandwidth coverage, high spectral resolution, and large dynamic range. At the same time, a real-time stream processing architecture needs to be configured to cope with the sorting challenges of millisecond-level time-domain overlapping signals. It should be noted that traditional radar reconnaissance receivers implement signal capture based on an analog processing architecture, and its technical bottlenecks are becoming increasingly prominent in broadband signal processing scenarios. As radar systems evolve towards ultra-wideband waveforms and frequency agility, analog receivers are limited by the physical characteristics of discrete devices, including large volume and weight, poor channel consistency, and high maintenance complexity. Against this background, benefiting from the breakthrough progress of large-scale integrated circuits, a digital intermediate frequency architecture with a high-speed analog-to-digital converter (ADC) as the core, combined with the development of digital signal processing technology, reconnaissance receivers have begun to transform towards a digital and software-based processing paradigm. Radar detection captures electromagnetic radiation sources through a broadband receiver, and finally completes the demodulation and analysis of signal characteristics through adaptive gain control and digital channelization processing.

[0003] Current radar technology is undergoing generational leaps. Advanced radar systems with low-observability designs, such as multi-polarized digital array radars and active electronically scanned array radars, have been widely applied, and their signal characteristics are characterized by high frequency, frequency agility, and complex modulation, which are difficult to process by traditional radar reconnaissance receivers. Currently, in the architecture of radar detection receivers, a pure DSP architecture has too high a delay due to its serial computing mode in multi-channel signal processing. Although the FPGA architecture can achieve high-speed signal capture, such as digital down-conversion and channelization splitting, its floating-point operation ability is insufficient to support high-order parameter estimation algorithms. Against this background, a cooperative architecture based on FPGA and DSP has become the key path to break through technical bottlenecks due to its complementary advantages of parallel processing ability and complex algorithm flexibility.

[0004] The software radio implementation of digital channelized receivers began in the 1990s. In its initial stage, the technical path adopted a distributed architecture of discrete analog-to-digital converters and digital anti-aliasing filters to achieve spectrum segmentation. The prior art discloses the construction of a reconfigurable channelized kernel based on a pipelined frequency transformation architecture, which can achieve the processing capacity of 1024 parallel channels within an FPGA. The research process of the software radio implementation of domestic digital channelized receivers has been gradually advancing since the beginning of the 21st century. The prior art discloses the construction of a dual-signal broadband digital down-conversion processing system based on an FPGA platform, laying a key technical foundation for engineering implementation. The prior art also discloses the development of a 7-channel 16-way uniform channelized architecture based on an FPGA and the integration of a DSP-assisted signal sorting system.

[0005] From the above development status, it can be seen that the implementation of radar detection receivers based on the software radio concept mostly relies on FPGAs, which is also related to the parallelism and real-time performance of FPGAs themselves. At the same time, it can be noted that for some complex algorithms such as signal sorting, researchers will choose to implement them in DSPs to make full use of their computing power. Therefore, the FPGA+DSP architecture is very suitable for the requirements of radar detection channelized receivers. However, the FPGA and DSP architectures have problems such as complex timing control and low data interaction efficiency. Therefore, it is very necessary to design a timing control scheme based on the heterogeneous architecture of FPGA+DSP to ensure the respective advantages of FPGAs and DSPs are exerted and the coupling degree is reduced as much as possible while increasing the scalability. Summary of the Invention

[0006] The present invention aims to solve the problems existing in the existing FPGA and DSP architectures, such as complex timing control and low data interaction efficiency.

[0007] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0008] Solution 1: The present invention proposes a timing control method for a loosely coupled FPGA and DSP architecture for a radar detection receiver. The radar detection receiver includes detecting and processing a specified frequency band, and the detection and processing include a first detection mode and a second detection mode. The radar detection receiver uses an FPGA and DSP architecture for processing, and the EMIF interface of the DSP realizes fast communication between the DSP and the FPGA. The method includes the following steps:

[0009] S1. The FPGA receives commands from the central management unit and outputs them to the first DSP through an interrupt method, and completes the response under the control of the first DSP.

[0010] S2. After the FPGA is loaded, it outputs a first interrupt pulse to the first DSP.

[0011] S3. After the first DSP responds to measuring the first interrupt pulse, it outputs control information to the FPGA through the EMIF;

[0012] S4. Under the control of the first DSP, the FPGA completes digital channelization, time-domain energy detection, and frequency-domain measurement. In the second detection mode, when the FPGA completes the frequency-domain measurement of each signal, it outputs a measurement interrupt pulse to the second DSP;

[0013] S5. After the second DSP responds to measuring the second interrupt pulse, it reads the signal data and parameter information of the FPGA through the EMIF, and performs extended measurement. After the measurement is completed, it writes the updated parameters into the FPGA;

[0014] S6. After the FPGA updates the extended parameters of all signals, it sends a measurement first interrupt pulse to the first DSP;

[0015] S7. In the case of the second detection mode, after the first DSP responds to measuring the first interrupt pulse, it reads the signal parameters to be sorted in the FPGA, performs signal sorting work, and saves the parameter set of the maximum energy signal, realizing high-precision execution of modulation type identification, parameter measurement, and signal sorting.

[0016] Further, a preferred implementation is provided. A high-precision clock network is set in the FPGA to directly generate synchronous timing signals, that is, periodically measure the first interrupt pulse, and implement time window constraint through hardware logic, that is, the LD signal takes effect after LD_delay after the interruption.

[0017] Further, a preferred implementation is provided. The first detection mode is: according to the central management unit instruction, data is collected through the ADC in each channel of a specific frequency band, 8-channel digital channelization processing is performed, basic parameter measurement is sequentially performed on the detected signals, and after all signals are processed, the parameter set of the maximum energy signal is saved and then enter the next channel.

[0018] Further, a preferred implementation is provided. The basic parameter measurement in the first detection mode includes pulse width and frequency.

[0019] Further, a preferred implementation is provided. The second detection mode is: according to the central management unit instruction, data is collected through the ADC in each channel of a specific frequency band, after 8-channel digital channelization processing, basic parameter measurement, extended measurement, and signal sorting are performed, after all signals are processed, the parameter set of the maximum energy signal is saved, and then enter the next channel.

[0020] Further, a preferred implementation is provided. The extended measurement in the second detection mode is modulation type identification and parameter measurement.

[0021] Further, a preferred implementation is provided. The method for the radar detection receiver to detect and process a specified frequency band in the first detection mode is as follows:

[0022] The working beats are all synchronized by measuring the first interrupt pulse of the FPGA. After the data processing FPGA is successfully loaded, LD_delay measures the first interrupt pulse and periodically initiates DSPINT_T to the DSP software.

[0023] The LD signal is generated internally by the FPGA and becomes valid after LD_delay of measuring the first interrupt pulse. After the LD signal becomes valid, the FPGA starts to receive signals for data processing.

[0024] Further, a preferred implementation is provided. The timing control method further includes the step of dividing the functions of the radar detection receiver according to the requirements of the first detection mode and the second detection mode.

[0025] Further, a preferred implementation is provided. The FPGA is respectively connected to the first DSP, the second DSP, and a DDR3. The ADC is connected to the FPGA. The central management unit is used to issue instructions and is connected to the FPGA through the RS422 interface.

[0026] Solution 2: A timing control device for a loosely coupled FPGA and DSP architecture of a radar detection receiver. The radar detection receiver includes detecting and processing a specified frequency band, and the detection processing modes include a first detection mode and a second detection mode. The radar detection receiver adopts an FPGA and DSP architecture for processing, and the EMIF interface of the DSP realizes fast communication between the DSP and the FPGA. The device includes:

[0027] An acquisition module, which is used for the FPGA to receive the communication command of the central management unit and output it to the first DSP through the interrupt mode, and complete the response under the control of the first DSP.

[0028] A timing control module, which is used to output the measurement of the first interrupt pulse to the first DSP after the FPGA is loaded.

[0029] A transmission module, which is used to output control information to the FPGA through the EMIF after the first DSP responds to the measurement of the first interrupt pulse.

[0030] An interaction module, which is used for the FPGA to complete digital channelization, time-domain energy detection, and frequency-domain measurement work under the control of the first DSP. In the second detection mode, after the FPGA completes the frequency-domain measurement of each signal, it outputs the measurement of the second interrupt pulse to the second DSP.

[0031] An update module, which is used for the second DSP to read the signal data and parameter information of the FPGA through the EMIF after responding to the measurement of the second interrupt pulse, perform extended measurement, and write the updated parameters into the FPGA after the measurement is completed;

[0032] A summary module, which is used for sending a measurement of the first interrupt pulse to the first DSP after the FPGA has updated the extended parameters of all signals;

[0033] An execution module, which is used in the case of the second detection mode. After the first DSP responds to the measurement of the first interrupt pulse, it reads the signal parameters to be sorted in the FPGA, performs signal sorting work, saves the parameter set of the maximum energy signal, and realizes high-precision execution of modulation type recognition, parameter measurement, and signal sorting.

[0034] The beneficial effects of the present invention are as follows:

[0035] The timing control method and device of a loosely coupled FPGA and DSP architecture for a radar detection receiver according to the present invention manage the overall timing of the FPGA, and combine the interrupt method to control the DSP to work according to a strict working rhythm. This timing control method utilizes the advantages of the hardware parallelism and real-time performance of the FPGA. The DSP is only used as a sequentially executing processor. This method balances the real-time performance and computational efficiency in the radar detection receiver. And when it is necessary to expand the algorithm function in the future, the number of DSP chips can be directly increased. In terms of timing control, only the interrupt issued by the FPGA needs to be modified, reducing the coupling degree between the DSPs and improving the system scalability and flexibility.

[0036] The timing control method and device of a loosely coupled FPGA and DSP architecture for a radar detection receiver according to the present invention have high real-time performance: that is, the interrupt-driven architecture reduces idle waiting, avoiding resource waste and timing jitter caused by polling;

[0037] The timing control method and device of a loosely coupled FPGA and DSP architecture for a radar detection receiver according to the present invention have strong scalability and maintainability, that is, it supports adding new DSP chips or algorithm upgrades without reconstructing the core logic; system maintenance is more convenient, and the module with problems can be maintained separately.

[0038] The timing control method and device of a loosely coupled FPGA and DSP architecture for a radar detection receiver according to the present invention have a low coupling degree, that is, there is no data interaction between the DSPs, the interfaces are clear, that is, there is only the EMIF interface between the FPGA and the two DSPs, and each component is developed and tested independently; the dependence between components is low, and the upgrade is relatively easy; when a certain component has a problem, the impact on the system is small.

[0039] The present invention is also applicable to the field of optimizing the real-time performance and resource allocation efficiency of signal processing tasks in a radar detection system. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Schematic diagram of the hardware structure of a radar detection receiver in a timing control device with a loosely coupled FPGA and DSP architecture for the tenth embodiment.

[0041] Figure 2 Schematic diagram of the functional division of a timing control device with a loosely coupled FPGA and DSP architecture for a radar detection receiver for the tenth embodiment.

[0042] Figure 3 Schematic diagram of the processing flow of the first detection mode for the first embodiment.

[0043] Figure 4 Schematic diagram of the processing flow of the second detection mode for the first embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application.

[0045] Embodiment 1. This embodiment proposes a timing control method for a loosely coupled FPGA and DSP architecture for a radar detection receiver. The radar detection receiver includes detecting and processing a specified frequency band, where the detection and processing include a first detection mode and a second detection mode. The loosely coupled FPGA and DSP architecture is used for processing in the radar detection receiver, and the EMIF interface of the DSP realizes fast communication between the DSP and the FPGA. The method includes the following steps:

[0046] S1. The FPGA receives a command from the central management unit and outputs it to the first DSP through an interrupt mode, and completes the response under the control of the first DSP;

[0047] S2. After the FPGA is loaded, it outputs a measurement first interrupt pulse to the first DSP;

[0048] S3. After the first DSP responds to the measurement first interrupt pulse, it outputs control information to the FPGA through the EMIF;

[0049] S4. Under the control of the first DSP, the FPGA completes digital channelization, time-domain energy detection, and frequency-domain measurement work. In the second detection mode, when the FPGA completes the frequency-domain measurement of each signal, it outputs a measurement interrupt pulse to the second DSP;

[0050] S5. After the second DSP responds to the measurement of the second interrupt pulse, it reads the signal data and parameter information of the FPGA through the EMIF, performs extended measurement, and writes the updated parameters into the FPGA after the measurement is completed;

[0051] S6. After the FPGA updates the extended parameters of all signals, it sends a measurement of the first interrupt pulse to the first DSP;

[0052] S7. In the case of the second detection mode, after the first DSP responds to the measurement of the first interrupt pulse, it reads the signal parameters to be sorted in the FPGA, performs signal sorting work, saves the parameter set of the maximum energy signal, and realizes the high-precision execution of modulation type recognition, parameter measurement, and signal sorting.

[0053] Embodiment 2. This embodiment further limits the timing control method of the loose-coupling FPGA and DSP architecture for a radar detection receiver described in Embodiment 1. A high-precision clock network is set in the FPGA to directly generate synchronous timing signals, that is, periodically measure the first interrupt pulse, and implement time window constraints through hardware logic, that is, the LD signal takes effect after LD_delay after the interruption.

[0054] Embodiment 3. This embodiment further limits the timing control method of the loose-coupling FPGA and DSP architecture for a radar detection receiver described in Embodiment 1. The first detection mode is: according to the central management unit instruction, data is collected through the ADC in each channel of a specific frequency band, 8-channel digital channelization processing is performed, basic parameter measurements are sequentially performed on the detected signals, and after all signals are processed, the parameter set of the maximum energy signal is saved and then the next channel is entered.

[0055] Embodiment 4. This embodiment further limits the timing control method of the loose-coupling FPGA and DSP architecture for a radar detection receiver described in Embodiment 3. The basic parameter measurements in the first detection mode include pulse width and frequency.

[0056] Embodiment 5. This embodiment further limits the timing control method of the loose-coupling FPGA and DSP architecture for a radar detection receiver described in Embodiment 1. The second detection mode is: according to the central management unit instruction, data is collected through the ADC in each channel of a specific frequency band, after 8-channel digital channelization processing, basic parameter measurement, extended measurement and signal sorting are performed, after all signals are processed, the parameter set of the maximum energy signal is saved, and then the next channel is entered.

[0057] Embodiment Six: This embodiment further defines the timing control method for the loosely coupled FPGA and DSP architecture for a radar detection receiver described in Embodiment Five. The extended measurement in the second detection mode is modulation type identification and parameter measurement.

[0058] Embodiment Seven: This embodiment further defines the timing control method for the loosely coupled FPGA and DSP architecture for a radar detection receiver described in Embodiment Five. The method for the radar detection receiver to detect and process a specified frequency band in the first detection mode is as follows:

[0059] The working beats are all synchronized by the first measurement interrupt pulse of the FPGA. The first measurement interrupt pulse is initiated to the DSP software periodically as DSPINT_T after the LD_delay when the data processing FPGA is successfully loaded.

[0060] The LD signal is generated internally by the FPGA and becomes valid after LD_delay of the first measurement interrupt pulse. After the LD signal becomes valid, the FPGA starts to receive signals for data processing.

[0061] Embodiment Eight: This embodiment further defines the timing control method for the loosely coupled FPGA and DSP architecture for a radar detection receiver described in Embodiment Five. The timing control method further includes the step of dividing the functions of the radar detection receiver according to the requirements of the first detection mode and the second detection mode.

[0062] Embodiment Nine: This embodiment further defines the timing control method for the loosely coupled FPGA and DSP architecture for a radar detection receiver described in Embodiment Five. The FPGA is respectively connected to the first DSP, the second DSP, and a DDR3. The ADC is connected to the FPGA. The central management unit is used to issue instructions and is connected to the FPGA through an RS422 interface.

[0063] Embodiment Ten: This embodiment proposes a timing control device for the loosely coupled FPGA and DSP architecture for a radar detection receiver. The radar detection receiver includes detecting and processing a specified frequency band, and the detection processing modes include the first detection mode and the second detection mode. The radar detection receiver adopts the FPGA and DSP architecture for processing, and the EMIF interface of the DSP realizes fast communication between the DSP and the FPGA. The device includes:

[0064] An acquisition module, which is used for the FPGA to receive the communication command of the central management unit and output it to the first DSP in an interrupt manner to complete the response under the control of the first DSP.

[0065] The timing control module is used to output a measurement first interrupt pulse to the first DSP after the FPGA loading is completed;

[0066] The transmission module is used to output control information to the FPGA through the EMIF after the first DSP responds to the measurement first interrupt pulse;

[0067] The interaction module is used to complete digital channelization, time-domain energy detection, and frequency-domain measurement work on the FPGA under the control of the first DSP. In the second detection mode, after the FPGA completes the frequency-domain measurement of each signal, it outputs a measurement second interrupt pulse to the second DSP;

[0068] The update module is used to read the signal data and parameter information of the FPGA through the EMIF after the second DSP responds to the measurement second interrupt pulse, and perform extended measurement. After the measurement is completed, the updated parameters are written into the FPGA;

[0069] The summary module is used to send a measurement first interrupt pulse to the first DSP after the FPGA updates the extended parameters of all signals;

[0070] The execution module is used in the case of the second detection mode. After the first DSP responds to the measurement first interrupt pulse, it reads the signal parameters to be sorted in the FPGA, performs signal sorting work, and saves the parameter set of the maximum energy signal, realizing high-precision execution of modulation type recognition, parameter measurement, and signal sorting.

[0071] Embodiment XI. This embodiment is proposed to explain Embodiments 1 to 10 above. The specific content of this embodiment is as follows:

[0072] Refer to Figure 1 and Figure 4 To describe this embodiment, this embodiment proposes a timing control method for a loose-coupled FPGA and DSP architecture based on interrupt control for a digital channelized receiver of a radar detection system. In this embodiment, the radar detection receiver device can detect radar signals with high sensitivity and measure their time-frequency domain parameter information. The device can detect and process a specified frequency band in a time-sharing manner, and the detection modes include the first detection mode and the second detection mode.

[0073] (1) The first detection mode: According to the instruction, data is collected through the ADC in each channel of a specific frequency band, and 8-channel digital channelization processing is performed. Then, basic parameter measurements (pulse width and frequency) are sequentially performed on the detected signals. After all signals are processed, the parameter set of the signal with the maximum energy is saved, and then the next channel is entered;

[0074] (2) Second detection mode: According to the instruction, data is collected through the ADC for each channel in a specific frequency band, and 8-channel digital channelization processing is performed. Then, basic parameter measurement, extended measurement (modulation type identification and parameter measurement), and signal sorting are carried out. After all signals are processed, the signal parameter set with the maximum energy is saved, and then the next channel is entered.

[0075] It is necessary to divide the functions of the radar signal reconnaissance receiver according to the above requirements. Several principles need to be followed, including giving priority to real-time performance, optimizing resource allocation, and algorithm-hardware cooperation. Specifically: According to real-time requirements, high-throughput tasks (such as signal detection and channelization demultiplexing) are assigned to the FPGA to ensure microsecond-level response; based on the pipeline and parallel computing architecture of the FPGA, the need for multi-channel signal synchronous processing is met; combined with the floating-point operation advantages of the DSP, high-precision execution of complex algorithms (such as modulation type identification, parameter measurement, and signal sorting) is achieved. The hardware structure diagram is as Figure 1 shown.

[0076] The FPGA is connected to two DSPs and one DDR3. The ADC chip is connected to the FPGA, and the central management unit is responsible for issuing instructions and is connected to the FPGA through the RS422 interface. The RF combination provides the working clock for the FPGA and the ADC, and is also responsible for down-converting the RF signal to the intermediate frequency for ADC sampling. The RF combination will perform channel sweeping in the frequency band of 1-10 GHz according to the starting and ending channel numbers. Designing to connect two DSPs is considered because there are many complex algorithms (modulation type identification, parameter measurement, signal sorting) to be implemented in the second detection mode, and the resources of a single DSP are relatively tight. At the same time, the implementation of these algorithms by two DSPs together also provides a basis for the subsequent function expansion and improves the scalability of the system.

[0077] The overall functional division design of the receiver software is as Figure 2 . It can be seen that the FPGA is mainly responsible for the digital channelization of the original ADC-acquired data, signal detection, and preliminary measurement of frequency-domain parameters, and controls the first DSP and the second DSP to read data as needed through interrupts; the first DSP is mainly responsible for signal sorting and the judgment of the working mode; the second DSP is mainly responsible for modulation type identification and extended parameter measurement. Data is exchanged between the FPGA and the DSP through the EMIF interface.

[0078] The working process described in this embodiment is as follows:

[0079] (1) The FPGA receives the communication command from the central management unit and outputs it to the first DSP through the interrupt mode, and completes the response under the control of the first DSP;

[0080] (2) After the FPGA is loaded, it outputs a measurement interrupt pulse to the first DSP;

[0081] (3) After the DSP responds to the measurement interrupt pulse, it outputs control information to the FPGA through the EMIF;

[0082] (4) Under the control of the first DSP, the FPGA completes tasks such as digital channelization, time-domain energy detection, and frequency-domain measurement. In the second detection mode, after the FPGA completes the frequency-domain measurement of each signal, it outputs a measurement second interrupt pulse to the second DSP;

[0083] (5) After the second DSP responds to the measurement second interrupt pulse, it reads the signal data and parameter information of the FPGA through the EMIF, then performs extended measurement, and writes the updated parameters into the FPGA after the measurement is completed;

[0084] (6) After the FPGA updates the extended parameters of all signals, it sends a measurement first interrupt pulse to the DSP;

[0085] (7) In the case of the second detection mode, after the first DSP responds to the measurement first interrupt pulse, it reads the signal parameters to be sorted in the FPGA, performs signal sorting work, and then saves the parameter set of the maximum energy signal.

[0086] The core part of this embodiment is a timing control method based on interrupt control of FPGA and DSP. In this embodiment, the FPGA and DSP need to work in strict timing coordination, and at the same time, the timing control accuracy directly affects the real-time performance of the signal processing link. And it is more convenient to perform timing control in the FPGA. The FPGA has a built-in high-precision clock network, which can directly generate synchronous timing signals (such as the periodic measurement first interrupt pulse), and implement time window constraints through hardware logic (such as the LD signal takes effect after LD_delay after the interrupt). The clock of the DSP depends on the external crystal oscillator, and the timing management at the software level is easily interfered by task scheduling, making it difficult to ensure timing determinacy. And the two DSPs work in a sequential order in time. The data processed by DSP1 is after being processed by the second DSP. If data transfer timing is directly performed between the two DSPs, it is easy to make mistakes. Therefore, in this design, the FPGA is used as the timing management center, and deterministic timing control is realized by using hardware parallelism. The two DSPs are guaranteed to be strictly synchronized through interrupt control; the DSP mainly performs complex calculations, focuses on algorithms, and gives full play to its floating-point operation advantages. The timing processing pipeline of the two modes is introduced in detail below.

[0087] When the device works in the first detection mode, the processing flow timing is as Figure 3 shown.

[0088] The working beats are all synchronized by measuring the first interrupt pulse of the FPGA. After the data processing FPGA is successfully loaded, the LD_delay measures the first interrupt pulse and periodically (DSPINT_T) initiates it to the DSP software. The LD signal is generated internally by the FPGA and becomes valid after LD_delay when measuring the first interrupt pulse. After the LD signal becomes valid, the FPGA starts to receive signals for data processing. The following details the specific work of each part in the processing pipeline shown in the figure.

[0089] Output instruction: At the nth beat, the DSP software outputs the working mode control information for the nth beat;

[0090] Execution instruction: When it is DSPINT_T - LD_delay after the nth beat and LD_delay before the (n + 1)th beat, the device starts to execute the working mode control information for the nth beat;

[0091] FPGA calculation: When it is DSPINT_T - LD_delay after the nth beat and LD_delay before the (n + 1)th beat, the FPGA processes the data in the working mode of the nth beat;

[0092] DSP1 calculation: No DSP1 data processing (radar signal sorting);

[0093] DSP2 calculation: No DSP2 data processing;

[0094] (2) When the device is working in the second detection mode, the processing pipeline timing of multiple channels in a specific frequency band is as Figure 4 .

[0095] When the device is in the second detection mode, the LD signal becomes valid after the data processing FPGA and the DSP jointly complete all signal extended parameter measurements and sorting functions and the signal parameter set with the maximum energy is saved. The following details the specific work of each part in the processing pipeline shown in the figure.

[0096] Output instruction: At the nth beat, the DSP software outputs the working mode control information for the nth beat;

[0097] Execution instruction: At the nth beat when the LD signal is valid, the device starts to execute the working mode control information for the nth beat;

[0098] FPGA calculation: At the nth beat when the LD signal is valid, the FPGA processes the data in the working mode of the nth beat, mainly including: acquisition and processing of initial ADC data, and saving and processing of the results sent back by the DSP;

[0099] Second DSP calculation: At the nth beat, the FPGA sends multiple measurement second interrupt pulses to the DSP. After each measurement second interrupt pulse, the DSP reads a signal and parameter set processed by the FPGA at the current beat and performs a second detection mode calculation. After the DSP measurement is completed, an enable signal is set, and the updated parameter set is output to the FPGA. Then the FPGA continues to send measurement second interrupt pulses to the DSP until all the signal and parameter sets at the current beat are updated and saved in the DSP and then in the FPGA, and the FPGA stops sending measurement second interrupt pulses to the DSP;

[0100] First DSP calculation: At the (n + 1)th beat, the FPGA sends a measurement first interrupt pulse to the DSP. The DSP reads the parameters to be sorted of the FPGA at the nth beat, and then the DSP performs sorted data processing. After the processing is completed, the signal parameter set with the maximum energy is output to the FPGA.

[0101] It can be seen from the control timings of each working mode that the working mode control information output by the first DSP and the DSP1 calculation (radar signal sorting) in this working mode differ by one beat, and are in the same beat as the second DSP calculation in this working mode.

[0102] The present invention relies on the overall timing management of the FPGA and combines the interrupt mode to control the DSP to work according to a strict working beat. This timing control method utilizes the advantages of the hardware parallelism and real-time performance of the FPGA. The DSP is only used as a sequentially executing processor. This method balances the real-time performance and computational efficiency in the radar detection receiver. And when it is necessary to expand the algorithm function subsequently, the number of DSP chips can be directly increased. In terms of timing control, only the interrupt distribution of the FPGA needs to be modified, reducing the coupling degree between the DSPs and improving the scalability and flexibility of the system.

[0103] Those skilled in the art can understand that the above description is only the preferred embodiment of the present invention. The features recorded in each embodiment and / or claim of the present disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly recorded in the present disclosure. It is not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0104] Although the preferred embodiments of the present invention have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they learn of the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present invention. Obviously, those skilled in the art can make various changes and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A timing control method for a loosely coupled FPGA and DSP architecture for a radar detection receiver, characterized in that: The radar detection receiver includes a detection process for a frequency band of a specified frequency band, wherein the detection process includes a first detection mode and a second detection mode, the radar detection receiver uses an FPGA and DSP architecture for processing, and the EMIF interface of the DSP realizes fast communication between the DSP and the FPGA, and the method includes the following steps: S1, FPGA receives the command from the central management unit and outputs it to the first DSP through interruption, and completes the response under the control of the first DSP; S2, after the FPGA is loaded, output the first interrupt pulse to the first DSP for measurement; S3, after the first DSP responds to and measures the first interrupt pulse, it outputs control information to the FPGA through the EMIF; S4. Under the control of the first DSP, the FPGA completes digital channelization, time domain energy detection, and frequency domain measurement. In the second detection mode, when the FPGA completes the frequency domain measurement of each signal, it outputs a measurement interrupt pulse to the second DSP. S5, after the second DSP responds to and measures the second interrupt pulse, it reads the signal data and parameter information of the FPGA through the EMIF, and performs extended measurement, and writes the updated parameters into the FPGA after the measurement is completed; S6. After the FPGA completes updating the extended parameters of all signals, a first interrupt pulse for measuring is sent to the first DSP; S7. In the second detection mode, after the first DSP responds to and measures the first interrupt pulse, it reads the signal parameters to be sorted in the FPGA, performs signal sorting, and saves the parameter set of the maximum energy signal, thereby achieving high-precision execution of modulation type recognition, parameter measurement, and signal sorting.

2. The timing control method of loosely coupled FPGA and DSP architecture for radar detection receiver according to claim 1, characterized in that: The FPGA is provided with a high-precision clock network for directly generating a synchronous timing signal, that is, periodically measuring the first interrupt pulse, and implementing a time window constraint through hardware logic, that is, the LD signal LD_delay takes effect after the interruption.

3. The timing control method of loosely coupled FPGA and DSP architecture for radar detection receiver according to claim 1, characterized in that: The first detection mode is: according to the instructions of the central management unit, data is collected through the ADC in each channel of a specific frequency band, 8-channel digital channelization processing is performed, basic parameters of the detected signals are measured in turn, and when all signals are processed, the signal parameter set with the maximum energy is saved and then the next channel is entered.

4. The timing control method of loosely coupled FPGA and DSP architecture for radar detection receiver according to claim 3, characterized in that: The basic parameters measured in the first detection mode include pulse width and frequency.

5. The timing control method of loosely coupled FPGA and DSP architecture for radar detection receiver according to claim 1, characterized in that: The second detection mode is: according to the instructions of the central management unit, data is collected through the ADC in each channel of a specific frequency band, and basic parameter measurement, extended measurement and signal sorting are performed after 8-channel digital channelization processing. After all signals are processed, the signal parameter set with the maximum energy is saved, and then the next channel is entered.

6. The timing control method of loosely coupled FPGA and DSP architecture for radar detection receiver according to claim 5, characterized in that: The extended measurements in the second detection mode are modulation type identification and parameter measurement.

7. The timing control method of loosely coupled FPGA and DSP architecture for radar detection receiver according to claim 1, characterized in that: The method for the radar detection receiver to detect and process the frequency band of the specified frequency band in the first detection mode is: The working beats are all synchronized by the first interrupt pulse measurement of the FPGA. After the data processing FPGA is successfully loaded, the first interrupt pulse measurement LD_delay is initiated periodically DSPINT_T to the DSP software; The LD signal is generated inside the FPGA. After measuring the first interrupt pulse, LD_delay is valid. After the LD signal is valid, the FPGA starts receiving signals for data processing.

8. The timing control method of loosely coupled FPGA and DSP architecture for radar detection receiver according to claim 1, characterized in that: The timing control method further comprises the step of dividing the functions of the radar detection receiver according to the requirements of the first detection mode and the second detection mode.

9. The timing control method of loosely coupled FPGA and DSP architecture for radar detection receiver according to claim 1, characterized in that: The FPGA is connected to the first DSP, the second DSP and a DDR3 respectively, the ADC is connected to the FPGA, and the central management unit is used for issuing instructions and is connected to the FPGA through an RS422 interface.

10. A timing control device for a loosely coupled FPGA and DSP architecture for a radar detection receiver, characterized in that: The radar detection receiver includes a detection process for a frequency band of a specified frequency band, wherein the detection process mode includes a first detection mode and a second detection mode, the radar detection receiver adopts FPGA and DSP architecture for processing, and the EMIF interface of the DSP realizes fast communication between the DSP and the FPGA, and the device includes: The acquisition module is used for the FPGA to receive the communication command of the central management unit, and output it to the first DSP through an interrupt mode, and complete the response under the control of the first DSP; A timing control module is used to output a first interrupt pulse to the first DSP after the FPGA is loaded; A transmission module, used for outputting control information to the FPGA through the EMIF after the first DSP responds to and measures the first interrupt pulse; The interactive module is used to enable the FPGA to complete digital channelization, time domain energy detection, and frequency domain measurement under the control of the first DSP. In the second detection mode, when the FPGA completes the frequency domain measurement of each signal, it outputs a second interrupt pulse to the second DSP for measurement; An update module is used for reading the signal data and parameter information of the FPGA through the EMIF after the second DSP responds to and measures the second interrupt pulse, and performing extended measurement, and writing the updated parameters into the FPGA after the measurement is completed; A summary module, used for sending a first interrupt pulse for measurement to the first DSP after the FPGA completes updating the extended parameters of all signals; The execution module is used in the second detection mode. After the first DSP responds to and measures the first interrupt pulse, it reads the signal parameters to be sorted in the FPGA, performs signal sorting, and saves the parameter set of the maximum energy signal, thereby realizing high-precision execution of modulation type recognition, parameter measurement, and signal sorting.

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