Interleaved write control for dual interlock cells

Abstract

The invention relates to interleaved write control for dual interlock cells. Systems and methods include a memory device including a dual interlock cell (DICE) latch and upstream circuitry coupled to the DICE latch and including a common node configured to receive a control signal for operation of the DICE latch. The upstream circuitry also includes a first divided control path coupled to a common node and configured to generate a first divided control signal from the control signal. The upstream circuitry includes a second divided control path coupled to the common node and configured to generate a second divided control signal from the control signal. The second divided control path includes a delay configured to delay the second divided control signal to interleave propagation of potential neutron impacts from the DICE latch at or upstream of the common node.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 614,995, filed Dec. 27, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to memory devices. More specifically, embodiments of the present disclosure relate to memory devices using dual-interlocked cells. Background Art

[0004] Typically, a computing system may include an electronic device that transfers information via electrical signals during operation. For example, a computing system may include a processor communicatively coupled to an integrated circuit device, such as a dynamic random access memory (DRAM) device, a ferroelectric random access memory (FeRAM) device, another random access memory (RAM) device, and / or other integrated circuit devices incorporating dual-interlocked cell (DICE) latches. A DICE latch may include an inverter circuit and redundant nodes. A DICE latch may be resistant to single neutron strikes. However, their tolerance to double neutron strikes may be much lower and they may not recover from neutron strikes, resulting in DICE latch failure (e.g., data corruption). Additionally, a single neutron strike at some location upstream of a DICE latch may cause a downstream failure, where the upstream neutron strike mimics the behavior of a double strike at the DICE latch itself due to the separated control paths.

[0005] Embodiments of the present disclosure may address one or more of the problems set forth above. Summary of the Invention

[0006] In one aspect, the present disclosure provides a memory device including: a dual-interlocked cell (DICE) latch; and an upstream circuitry coupled to the DICE latch and including: a common node configured to receive a control signal for operation of the DICE latch; a first partitioned control path coupled to the common node and configured to generate a first partitioned control signal from the control signal; and a second partitioned control path coupled to the common node and configured to generate a second partitioned control signal from the control signal, wherein the second partitioned control path includes a delay configured to delay the second partitioned control signal to stagger the propagation of a potential neutron strike at or upstream of the common node from the DICE latch.

[0007] In another aspect, the present disclosure further provides a method for operating a memory device, the method comprising: receiving a control signal for a dual-interlocked cell (DICE) latch; dividing the control signal into a first divided control signal on a first divided control path and a second divided control signal on a second divided control path; delaying the second divided control signal using a delay element in the second divided control path to stagger the propagation of potential neutron strikes affecting the control signal upstream of the DICE latch; providing the first divided control signal to the DICE latch; and providing the delayed second divided control signal to the DICE latch.

[0008] In yet another aspect, the present disclosure further provides a memory device, the memory device comprising: a dual-interlocked cell (DICE) latch; and an upstream circuitry coupled to the DICE latch and configured to receive a control signal for an operation in the DICE latch and provide a first divided control signal and a second divided control signal to the DICE latch, the upstream circuitry comprising: a first divided control path configured to receive the control signal and generate the first divided control signal from the control signal; and a second divided control path configured to generate the second divided control signal from the control signal, wherein the second divided control path includes a delay configured to delay the second divided control signal to stagger the propagation of potential neutron strikes affecting the control signal upstream of the second divided control path, and staggering the propagation includes staggering the propagation of the potential neutron strikes via the first divided control signal and the second divided control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a memory device utilizing a dual-interlocked cell (DICE) latch according to an embodiment of the present disclosure;

[0010] Figure 2 is a circuit diagram of a DICE latch having critical nodes according to an embodiment of the present disclosure Figure 1 of;

[0011] Figure 3 is according to an embodiment of the present disclosure Figure 2 graph of neutron strikes and the effects of neutron strikes at critical nodes of a DICE latch of;

[0012] Figure 4 is a circuit diagram of an upstream circuitry for controlling the operation of a DICE latch using divided control signals according to an embodiment of the present disclosure;

[0013] Figure 5 is a circuit diagram of a DICE latch configured to receive a partitioned control signal from an upstream circuit system according to an embodiment of the present disclosure; Figure 4 of the upstream circuit system;

[0014] Figure 6 is a circuit diagram of an upstream circuit system configured to generate an interleaved and partitioned control signal and drive an operation of a DICE latch according to an embodiment of the present disclosure; and Figure 5 of the DICE latch; and

[0015] Figure 7 is a timing diagram showing the response of a DICE latch according to an embodiment of the present disclosure when a neutron strike occurs in an upstream circuit system of Figure 4 and when a neutron strike occurs in an upstream circuit system of Figure 6 and when a neutron strike occurs in an upstream circuit system of Figure 5 of the DICE latch. DETAILED DESCRIPTION

[0016] One or more specific embodiments will be described below. To provide a concise description of these embodiments, all features of the actual implementation are not described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the specific goals of the developer, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. In addition, it should be understood that this development work may be complex and time-consuming, but will still be a routine for those of ordinary skill in the art who benefit from the present disclosure in design, fabrication, and manufacturing.

[0017] As previously discussed, although dual-interlocked cell (DICE) latches are robust against a single neutron strike on the DICE latch, they are more vulnerable to simultaneous dual neutron strikes. One mechanism for implementing this susceptibility is to provide a separate control path for the DICE latch. However, a neutron strike at a location upstream of a DICE latch with a separate control path may result in a failure at a level similar to a dual neutron strike on the DICE itself. As discussed below, interleaving signals that may encounter neutron strikes upstream of the DICE latch can enable the DICE latch to recover from the propagation of consecutive rather than simultaneous neutron strikes, since the propagation of a single neutron strike in a separate control path mimics a dual neutron strike, and the simultaneous propagation may cause unrecoverability, which may lead to data failure.

[0018] Turning now to the figures, Figure 1 is a simplified block diagram showing certain features of a memory device 10. Specifically, Figure 1The block diagram is a functional block diagram showing certain functionality of the memory device 10. According to one embodiment, the memory device 10 may be a Double Data Rate Type Five Synchronous Dynamic Random Access Memory (DDR5 SDRAM) device. Compared with previous generations of DDR SDRAM, various features of DDR5 SDRAM achieve reduced power consumption, more bandwidth, and larger storage capacity.

[0019] The memory device 10 may include a number of memory banks 12. For example, the memory banks 12 may be DDR5 SDRAM memory banks. The memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) arranged on a Dual In-line Memory Module (DIMM). It should be understood that each DIMM may include a number of SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip may include one or more memory banks 12. The memory device 10 represents a part of a single memory chip (e.g., SDRAM chip) having a number of memory banks 12. For DDR5, the memory banks 12 may be further arranged to form bank groups. For example, for an 8 Gigabyte (Gb) DDR5 SDRAM, the memory chip may include 16 memory banks 12 arranged in 8 bank groups, with each bank group containing 2 memory banks. For a 16 Gb DDR5 SDRAM, the memory chip may, for example, include 32 memory banks 12 arranged in 8 bank groups, with each bank group containing 4 memory banks. Depending on the application and design of the overall system, various other configurations, organizations, and sizes of the memory banks 12 on the memory device 10 may be utilized.

[0020] The memory bank 12 and / or the bank control block 22 includes Dual Interlocked Cell (DICE) latches 13. As previously described, DICE latches can be used to store information in a manner that is robust against single neutron strikes but may be vulnerable to double neutron strikes.

[0021] The memory device 10 may include a command interface 14 and an Input / Output (I / O) interface 16. The command interface 14 is configured to provide a number of signals (e.g., signal 15) from an external (e.g., host) device (not shown), such as a processor or a controller. The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transmission and reception of data to be written to or read from the memory device 10.

[0022] As will be appreciated, command interface 14 may include several circuits, such as a clock input circuit 18 and a command address input circuit 20, to ensure, for example, proper handling of signal 15. Command interface 14 may receive one or more clock signals from an external device. Typically, a double data rate (DDR) memory utilizes a differential pair of system clock signals: a true clock signal Clk_t and an inverted / complementary clock signal Clk_c. The positive clock edge of DDR refers to the point where the rising true clock signal Clk_t crosses the falling complementary clock signal Clk_c, while the negative clock edge indicates the transition of the falling true clock signal Clk_t and the rising of the complementary clock signal Clk_c. Commands (e.g., read commands, write commands, activate commands, precharge commands, etc.) are typically input on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0023] The clock input circuit 18 receives the true clock signal Clk_t and the complementary clock signal Clk_c, and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay locked loop (DLL) circuit 30. The DLL circuit 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, the I / O interface 16 and is used as a timing signal for determining the output timing of the read data. In some embodiments, the clock input circuit 18 may include circuitry for splitting the clock signal into multiple (e.g., 4) phases. The clock input circuit 18 may also include phase detection circuitry for detecting which phase receives the first pulse when pulse bursts occur too frequently so that the clock input circuit 18 can reset between pulse bursts.

[0024] The internal clock signal / phase CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to the command decoder 32. The command decoder 32 may receive command signals from the command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide the command signals to the DLL circuit 30 via the bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. The phase-controlled internal clock signal LCLK may be used, for example, to time data via the IO interface 16.

[0025] In addition, the command decoder 32 can decode commands such as read commands, write commands, mode register set commands, activate commands, precharge commands, etc., and provide access to a specific memory bank 12 corresponding to the command via the bus path 40. As will be appreciated, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory bank 12. In one embodiment, each memory bank 12 includes a bank control block 22 that provides the necessary decoding (e.g., row decoder and column decoder) and other features such as timing control and data control to facilitate the execution of commands to and from the memory bank 12.

[0026] The memory device 10 performs operations such as read commands and write commands based on command / address signals received from an external device such as a processor. In one embodiment, the command / address bus may be a 14-bit bus to accommodate the command / address signals (CA<13:0>). The command / address signals are timed into the command interface 14 using clock signals (Clk_t and Clk_c). The command interface may include a command address input circuit 20 configured to receive and transmit commands via, for example, the command decoder 32 to provide access to the memory bank 12. In addition, the command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables the memory device 10 to process commands on the incoming CA<13:0> bus. Access to a specific bank 12 within the memory device 10 is encoded by the command on the CA<13:0> bus.

[0027] In addition, the command interface 14 may be configured to receive several other command signals. For example, a command / address on-die termination (CA_ODT) signal may be provided to facilitate proper impedance matching within the memory device 10. For example, a reset command (RESET_n) may be used to reset the command interface 14, status register, state machine, etc. during power-up. The command interface 14 may also receive a command / address inversion (CAI) signal, which may be provided to invert the state of the command / address signals CA<13:0> on the command / address bus, for example, depending on the command / address routing of the specific memory device 10. A mirror MIR signal may also be provided to facilitate the mirroring function. Based on the configuration of multiple memory devices in a specific application, the MIR signal may be used to multiplex signals such that the signals can be swapped to achieve a certain routing of the signals to the memory device 10. Various signals may also be provided to facilitate testing of the memory device 10, such as a test enable (TEN) signal. For example, the TEN signal may be used to place the memory device 10 in a test mode for connectivity testing.

[0028] The command interface 14 can also be used to provide a warning signal (ALERT_n) to the system processor or controller for certain errors that may be detected. For example, the warning signal (ALERT_n) can be emitted from the memory device 10 in the event of a detected cyclic redundancy check (CRC) error. Other warning signals can also be generated. In addition, the bus and pins used to emit the warning signal (ALERT_n) from the memory device 10 can be used as input pins during certain operations, such as the connectivity test mode performed using the TEN signal as described above.

[0029] The commands and timing signals discussed above can be utilized to send data to and from the memory device 10 by transmitting and receiving data signals 44 via the IO interface 16. More specifically, data can be sent to or retrieved from the memory bank 12 via a data path 46 that includes a plurality of bidirectional data buses. Data IO signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For certain memory devices, such as DDR5 SDRAM memory devices, the IO signals can be divided into upper and lower bytes. For example, for a x16 memory device, the IO signals can be divided into upper and lower IO signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to the upper and lower bytes of the data signal, respectively.

[0030] To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices, can utilize data strobe signals, commonly referred to as DQS signals. The DQS signal is driven by an external processor or controller to send data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is actually an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal is used as a clock signal to capture the corresponding input data. Similar to the clock signals (Clk_t and Clk_c), the DQS signal can be provided as a differential pair (DQS_t and DQS_c) of data strobe signals to provide differential pair signaling during both read and write operations. For certain memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals can be divided into upper and lower data strobe signals (e.g., UDQS_t / and UDQS_c; LDQS_t / and LDQS_c) corresponding to the upper and lower bytes of the data sent to and from the memory device 10, respectively.

[0031] The impedance (ZQ) calibration signal can also be provided to the memory device 10 via the IO interface 16. The ZQ calibration signal can be provided to a reference pin and is used to tune the output driver and ODT values by adjusting the pull-up and pull-down resistors of the memory device 10 through changes in process, voltage, and temperature (PVT) values. Since PVT characteristics can affect the ZQ resistor value, the ZQ calibration signal can be provided to the ZQ reference pin to adjust the resistance and thus calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor serves as a reference for adjusting the drive strength of the internal ODT and IO pins.

[0032] In addition, the loopback data signal (LBDQ) and the loopback strobe signal (LBDQS) can be provided to the memory device 10 via the IO interface 16. The loopback data signal and the loopback strobe signal can be used during the test or debug phase to set the memory device 10 into a mode in which the signal is looped back through the memory device 10 via the same pin. For example, the loopback signal can be used to set the memory device 10 to test the data output (DQ) of the memory device 10. The loopback can include both LBDQ and LBDQS or may include only the loopback data pin. This is typically intended for monitoring the data captured by the memory device 10 at the IO interface 16. LBDQ can indicate the data operation of the target memory device (such as the memory device 10), and thus can be analyzed to monitor (e.g., debug and / or perform diagnostics on) the data operation of the target memory device. In addition, LBDQS can indicate the strobe operation (e.g., the timing of the data operation) of the target memory device (such as the memory device 10), and thus can be analyzed to monitor (e.g., debug and / or perform diagnostics on) the strobe operation of the target memory device.

[0033] As will be appreciated, various other components such as a power supply circuit (for receiving external VDD and VSS signals), a mode register (for defining various modes of programmable operation and configuration), a read / write amplifier (for amplifying signals during read / write operations), a temperature sensor (for sensing the temperature of the memory device 10), etc. can also be incorporated into the memory device 10. Accordingly, it should be understood that the Figure 1 block diagram provided is only to highlight certain functional characteristics of the memory device 10 to assist in the subsequent detailed description. In addition, although the memory device 10 has been described above as a DDR5 device, the memory device 10 can be any suitable device in which DICE latches can be deployed (e.g., a low-power double data rate (LPDDR) device, a double data rate type 4 DRAM (DDR4) device, another DRAM type, or a combination of different types of devices).

[0034] Figure 2Is a circuit diagram of an embodiment of the DICE latch 13. The illustrated embodiment of the DICE latch 13 receives a first signal 98 at a first terminal of an n-channel metal oxide semiconductor (NMOS) transistor 100. For example, the first signal 98 may be a signal for assisting in capturing data via the NMOS transistor 100 (e.g., its gate terminal). A second terminal of the NMOS transistor 100 is coupled to a gate terminal of a p-channel metal oxide semiconductor (PMOS) transistor 102. A first terminal of the PMOS transistor 102 is coupled to a supply voltage 104 (e.g., VPERI), and a second terminal of the PMOS transistor 102 is coupled to a first terminal of an NMOS transistor 106. A second terminal of the NMOS transistor 106 is coupled to ground (e.g., VSS). A second terminal of the PMOS transistor 102 and a first terminal of the NMOS transistor 106 are coupled to a gate terminal of an NMOS transistor 108. A first terminal of the NMOS transistor 108 is coupled to ground, and a second terminal of the NMOS transistor 108 is coupled to a first terminal of a PMOS transistor 110. A second terminal of the PMOS transistor 110 is coupled to the supply voltage 104.

[0035] The illustrated embodiment of the DICE latch 13 also receives a second signal 112 at the first terminal of the NMOS transistor 114. For example, the second signal 112 can be a signal for assisting in capturing data via the NMOS transistor 114 (e.g., its gate terminal). The second terminal of the NMOS transistor 114 is coupled to the gate terminal of the PMOS transistor 116. The gate terminal of the PMOS transistor 116 is also coupled to the gate terminal of the NMOS transistor 106. The first terminal of the PMOS transistor 116 is coupled to the supply voltage 104, and the second terminal of the PMOS transistor 116 is coupled to the first terminal of the NMOS transistor 118. The second terminal of the NMOS transistor 118 is coupled to ground (e.g., VSS). The gate terminal of the NMOS transistor 118 is coupled to the gate terminal of the PMOS transistor 102. The second terminal of the PMOS transistor 116 and the first terminal of the NMOS transistor 118 are coupled to the gate terminal of the NMOS transistor 120. The gate terminal of the NMOS transistor 120 is coupled to the gate terminal of the PMOS 110. The first terminal of the NMOS transistor 120 is coupled to ground, and the second terminal of the NMOS transistor 120 is coupled to the first terminal of the PMOS transistor 122. The second terminal of the PMOS transistor 122 is coupled to the supply voltage 104. The gate terminal of the PMOS transistor 122 is coupled to the gate of the NMOS transistor 108. The DICE latch 13 can have an output Q 124 and an output QF 126. The output QF 126 is complementary to the output Q 124. The DICE latch 13 can also have an output Q1 128 and an output Q1F 130. The output Q1F130 is complementary to the output Q1 128.

[0036] As previously described, if a neutron strike occurring at a node of the DICE latch 13 (e.g., output Q 124 or output Q1 128) is below a relatively high threshold (e.g., 100+ picocoulombs (pC)) of current injection (as negative noise), the DICE latch 13 is able to recover from the strike. However, if two nodes are struck, the DICE latch 13 may fail above a certain Qcrit threshold, which is much lower than the relatively high threshold. For example, Figure 3Graph 150 showing the voltage at nodes in response to different amounts of energy (e.g., current) injected during neutron strikes. Graph 150 includes line 152 corresponding to the voltage at a first node (e.g., output Q1 24) and line 154 corresponding to the voltage at a second node (e.g., output Q1 128). Graph 150 includes line 156 corresponding to the energy / current injected by neutron strikes. At an initial time 157, data is stored as logic high at the first and second nodes. At time 158, noise (e.g., negative noise) is injected in a certain amount (e.g., 5 femtocoulombs (fC)), and the first and second nodes recover from the noise and maintain the logic at the first and second nodes. An example of fC is shown in Graph 160, which shows that fC is equal to the amount of energy injected by a pulse having a duration 162 of 100 picoseconds (ps) and an amplitude of 10 microamperes (μA) or some other equivalent amount of energy having a different duration or amplitude. At times 166 and 168, the first and second nodes recover from the respective noise levels (e.g., 6 fC, 7 fC). However, at time 170, noise (e.g., 8 fC) causes the first and second nodes to flip from logic high to logic low. This value is designated as Qcrit, where the logic fails due to double neutron strikes. Similarly, if the stored value is logic high when double neutron strikes occur, any one of the noise levels (e.g., 9 fC, 10 fC, 11 fC, 12 fC, 13 fC, or 14 fC) at times 174, 176, 178, 180, or 182 can cause the logic values at the first and second nodes to flip. As previously mentioned, even when the injected current exceeds 100 pC, the DICE latch 13 can resist single neutron strikes. However, double neutron strikes with a portion of the single strike energy (e.g., less than 1 / 10,000 or 10 fC) may cause the stored data to fail. To address this weakness, the DICE latch 13 can be deployed with a layout that provides a relatively large distance (e.g., 0.5 μm) between critical nodes (e.g., Q output 124 and Q1 output 128) so that the two critical nodes are less likely to be struck simultaneously. Another mechanism for providing more robust protection includes separating access transistors (e.g., NMOS transistors 100 and 114), gate signals, and data input signals to the DICE latch 13.

[0037] Figure 4It is a circuit diagram of an upstream circuit system 200 that includes a separate control path (e.g., access transistors, gate signals, data input signals, etc.) to the DICE latch 13. The upstream circuit system 200 receives a fuseLoad signal 202 at an inverter 204, and the fuseLoad signal can serve as a control signal for the DICE latch 13, and the control signal is a control signal for enabling an operation (e.g., a data write operation). The output of the inverter 204 is input to an inverter 206 to generate a first instance or a first divided control signal of the separate control signal (i.e., the fuseLoadb0 signal 208). The fuseLoadb0 signal 208 is sent to an inverter 210 to generate a fuseLoadb0F signal 212 that is complementary to the fuseLoadb0 signal 208.

[0038] An inverter 216 generates a second instance or a second divided control signal of the separate control signal (i.e., the fuseLoadb1 signal 218) from a node 214 between the inverter 204 and the inverter 206. The fuseLoadb1 signal 218 is inverted in an inverter 220 to generate a fuseLoadb1F signal 222 that is complementary to the fuseLoadb1 signal 218. In some embodiments, at least some of the various inverters can be inverter amplifiers that are configured to amplify the signals inverted in the respective inverters.

[0039] Figure 5 It is a circuit diagram of the DICE latch 13 in an embodiment where a separate control path is configured to be coupled to the upstream circuit system. The illustrated embodiment of the DICE latch 13 receives an Efusedata signal 232 (data signal), the fuseLoadb0F signal 212, and the fuseLoadb0 signal 208 at a complementary metal-oxide-semiconductor (CMOS) 234. The illustrated embodiment of the DICE latch 13 also receives an Efusedata1 signal 236 (data signal), the fuseLoadb1F signal 222, and the fuseLoadb1 signal 218 at a CMOS 238.

[0040] The CMOS 234 is coupled to the gate terminal of a PMOS transistor 240. The first terminal of the PMOS transistor 240 is coupled to a VPERI 242. The CMOS 234 is also coupled to the gate terminal of an NMOS transistor 244. The first terminal of the NMOS transistor 244 is coupled to a VSS 246.

[0041] CMOS234 is further coupled to the first terminal of PMOS transistor 248. The second terminal of PMOS transistor 248 is coupled to the first terminal of PMOS transistor 250, and the gate terminal of PMOS transistor 248 is coupled to the second terminal of NMOS transistor 244. PMOS transistor 250 has a second terminal coupled to VPERI 242 and a gate terminal coupled to the fuseLoadb0 signal 208. The gate terminal of PMOS transistor 248 is also coupled to the gate terminal of NMOS transistor 252, and the first terminal of the NMOS transistor is coupled to the first terminal of NMOS transistor 254. The second terminal of NMOS transistor 254 is coupled to VSS246, and the gate terminal of NMOS transistor 254 is coupled to the fuseLoadb0F signal 212.

[0042] CMOS238 is coupled to the gate terminal of PMOS transistor 256. The first terminal of PMOS transistor 256 is coupled to VPERI 242, and the second terminal of PMOS transistor 256 is coupled to the second terminal of NMOS transistor 244. CMOS238 is also coupled to the gate terminal of NMOS transistor 258. The first terminal of NMOS transistor 258 is coupled to VSS246, and the second terminal of NMOS transistor 258 is coupled to the second terminal of PMOS transistor 240.

[0043] CMOS238 is further coupled to the first terminal of PMOS transistor 260. The second terminal of PMOS transistor 260 is coupled to the first terminal of PMOS transistor 262, and the gate terminal of PMOS transistor 260 is coupled to the second terminal of NMOS transistor 258. The second terminal of PMOS transistor 262 is coupled to VPERI 242, and the gate terminal is coupled to the fuseLoadb1 signal 218. The gate terminal of PMOS transistor 260 is coupled to the gate terminal of NMOS transistor 264, and the first terminal of the NMOS transistor is coupled to the first terminal of NMOS transistor 266. The second terminal of NMOS transistor 264 is coupled to the first terminal of PMOS transistor 248. The second terminal of NMOS transistor 266 is coupled to VSS246, and the gate terminal of NMOS transistor 266 is coupled to the fuseLoadb0F signal 212.

[0044] The DICE latch 13 further includes critical node Q0 270 at or between: the first terminal of PMOS transistor 260, the second terminal of NMOS transistor 252, the gate terminal of PMOS transistor 256, the gate terminal of NMOS transistor 258, and / or CMOS 238. The complementary node Q0F 272 may be located at or between the second terminal of PMOS transistor 240, the second terminal of NMOS transistor 258, the gate terminal of PMOS transistor 260, and / or the gate terminal of NMOS transistor 264. The DICE latch 13 further includes critical node Q1 274 at or between: the second terminal of NMOS transistor 264, the first terminal of PMOS transistor 248, the gate terminal of PMOS transistor 240, the gate terminal of NMOS transistor 244, and / or CMOS 234. The complementary node Q1F 276 may be located at or between the second terminal of NMOS transistor 244, the second terminal of PMOS transistor 256, the gate terminal of PMOS transistor 260, and / or the gate terminal of NMOS transistor 264.

[0045] Physically separating the critical nodes of the DICE latch 13 can increase the rigidity to resist double neutron strikes on the DICE latch 13 itself. Additionally, in addition to the DICE latch 13 itself, Figure 4 and 5 the separate control paths of can also provide rigidity against neutron strikes on the fuseLoadb0 signal 208, fuseLoadb0F signal 212, fuseLoadb1 signal 218, or fuseLoadb1F signal 222. However, as previously described, if a single neutron strike occurs upstream of the DICE latch 13, noise can propagate via paths that affect the separation of the DICE latch 13. For example, at Figure 4 a single neutron strike at the fuseLoad signal 202 or node 214 of can propagate along two paths and propagate to the DICE latch 13, resulting in the propagation effects of the neutron strike overlapping at the critical nodes, potentially causing the stored data value to flip logic incorrectly. To address this overlap or simultaneous propagation that can mimic a double neutron strike, one of the control paths can be delayed. For example, Figure 6 shows a circuit diagram of the upstream circuitry 300, which may be similar to Figure 4The upstream circuit system 200, only the upstream circuit system 300 includes a delay 302 in the second divided control path. The inclusion of the delay 302 is to stagger the propagation of any upstream neutron strike (e.g., at node 214). In some embodiments, the delay 302 can have a duration sufficient to allow the DICE latch to recover at least partially from the propagation of a neutron strike via one control path (e.g., via the fuseLoadb0 signal 208, etc.) before the neutron strike propagates via another control path. In some embodiments, the duration (e.g., 100 - 200 ps) can be at least the length of the total recovery of the DICE latch 13 from a neutron strike of a given intensity (e.g., 100 ps). In some embodiments, the delay element of the delay 302 can be adjusted using a metal option display unit. The additional delay can increase the area of the delay element, but the trade-off is to increase reliability. Additionally, in some embodiments, the delay 302 may not affect the timing of the write operation to the DICE latch 13 because the write timing margin for staggered write control may not be a problem.

[0046] Figure 7 A timing diagram 320 showing the operation (e.g., write operation) of the DICE latch 13. The timing diagram 320 includes a line 322 corresponding to a current injection generated by a neutron strike upstream of the DICE latch 13. For example, the current injection can occur at node 214 where the control path forks for the DICE latch 13 or upstream of node 214 from the DICE latch 13. Lines 324, 326, and 328 correspond to embodiments of the DICE latch 13 that do not include the delay 302 for staggering the propagation through the divided control path. Lines 330, 332, and 334 correspond to embodiments of the DICE latch 13 that include the delay 302 for staggering the propagation through the divided control path. Specifically, line 324 corresponds to Figure 4 the fuseLoadb0F signal 212 of the upstream circuit system 200, and line 326 corresponds to the fuseLoadb1F signal 222 of the upstream circuit system. Line 326 corresponds to being stored in the DICE latch 13, for example, in one of the critical nodes (e.g., Figure 5As shown, when current is injected as indicated by the pulse shown on line 322 at time 336, both the fuseLoadb0F signal 212 indicated by line 324 and the fuseLoadb1F signal 222 indicated by line 326 propagate noise at least partially simultaneously (i.e., with some overlap), causing both of them to drop from logic high to logic low at time 338. This at least partially simultaneous propagation and drop causes the logic value stored at the critical node to flip, as indicated by the drop of line 328 at time 338, where the logic value remains at logic low without recovering from the propagated noise / neutron strike.

[0047] Line 330 corresponds to Figure 6 The fuseLoadb0F signal 212 of the upstream circuit system 300, and line 332 corresponds to the fuseLoadb1F signal 222 with a delay that causes the fuseLoadb1F signal 222 to occur at Figure 6 The propagation of potential neutron strikes / noise upstream of the DICE latch 13 of the upstream circuit system 300 is staggered. Line 334 corresponds to the propagation of potential neutron strikes / noise upstream of the DICE latch 13, such as at one of the key nodes (e.g., Figure 5 340). As shown, when current is injected as indicated by the pulse shown on line 322 at time 336, only the fuseLoadb0F signal 212 indicated by line 330 propagates noise before time 340. Neutron strikes / noise are prevented from propagating to the fuseLoadb1F signal 222 until after time 340 to stagger the charge injection in the DICE latch 13 via the control path. The amount of delay in delay 302 corresponds to the time difference between time 338 and time 340. By delaying the propagation of the fuseLoadb1F signal 222, the voltage at the critical node indicated by line 334 is able to recover within time 342 and not switch logic values. Therefore, the staggering of the control path using delay 302 enables the DICE latch 13 to be more robust against neutron strikes, even when they occur upstream of the DICE latch 13 and node 214.

[0048] Although the present disclosure allows for various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. In fact, the present disclosure is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present disclosure defined by the appended claims.

[0049] Reference is made to the technology set forth and claimed herein, and the technology is applied to substantial objects and specific instances having a practical nature, which substantial objects and specific instances demonstrably improve the technical field of the present invention and are thus not abstract, intangible, or purely theoretical. Further, if any claim appended to this specification contains one or more elements designated as "means for [performing]... [function]" or "step for [performing]... [function]", it is intended that such elements be construed in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements will not be construed in accordance with 35 U.S.C. 112(f).

Claims

1. A memory device, comprising: Dual interlock unit DICE latch; as well as an upstream circuit system coupled to the DICE latch and comprising: a common node configured to receive a control signal for operation of the DICE latch; a first divided control path coupled to the common node and configured to generate a first divided control signal from the control signal; and a second partitioned control path coupled to the common node and configured to generate a second partitioned control signal from the control signal, wherein the second partitioned control path includes a delay configured to delay the second partitioned control signal to stagger propagation of a potential neutron strike at or upstream of the common node from the DICE latch.

2. The memory device of claim 1, wherein the operation comprises a write operation to the DICE latch.

3. The memory device of claim 1 , wherein the delay has a duration of a length of time configured to enable the DICE latch to recover from propagation of the potential neutron strike via the first partitioned control path prior to propagating the neutron strike via the second partitioned control path.

4. The memory device of claim 1, wherein the second divided control path is connected in parallel with the first divided control path between the common node and the DICE latch.

5. The memory device of claim 1, wherein the DICE latch comprises a first complementary metal oxide semiconductor (CMOS) configured to receive the first divided control signal from the upstream circuitry at the DICE latch.

6. The memory device of claim 5, wherein the DICE latch comprises a second CMOS configured to receive the second divided control signal at the DICE latch from the upstream circuitry.

7. The memory device of claim 1 , wherein the delay is configured to prevent propagation of the potential neutron strike from simulating a double neutron strike due to at least partial simultaneous propagation through the first control path and the second control path by staggering the propagation of the potential neutron strike in the first control path and the second control path.

8. The memory device of claim 1, wherein the first divided control path comprises a first plurality of inverting amplifiers configured to: generating the first divided control signal; generating a first complementary divided control signal complementary to the first divided control signal; as well as The first divided control signal and the first complementary divided control signal are transmitted to the DICE latch.

9. The memory device of claim 8, wherein the second divided control path comprises a second plurality of inverting amplifiers configured to: generating the second divided control signal; generating a second complementary divided control signal complementary to the second divided control signal; and The second divided control signal and the second complementary divided control signal are transmitted to the DICE latch.

10. The memory device of claim 1, wherein the delay is configured to enable the DICE latch to at least partially recover from propagation of a potential neutron strike via the first divided control signal prior to propagation of the potential neutron strike via the second divided control signal.

11. A method for operating a memory device, comprising: receiving a control signal for a dual interlock unit DICE latch; dividing the control signal into a first divided control signal on a first divided control path and a second divided control signal on a second divided control path; delaying the second divided control signal using a delay element in the second divided control path to stagger the propagation of potential neutron strikes affecting the control signal upstream of the DICE latch; providing the first divided control signal to the DICE latch; as well as The delayed second divided control signal is provided to the DICE latch. 12 . The method of claim 11 , wherein the first divided control path and the second divided control path are coupled in parallel between a common node that divides the control signal and the DICE latch.

13. The method of claim 11, wherein the control signal is configured to enable a write operation to the DICE latch.

14. The method of claim 11, wherein providing the first divided control signal comprises providing the first divided control signal without a delay element in the first divided control path.

15. The method of claim 11, wherein the delay length of the delay element is set to a recovery duration that provides time for the DICE latch to at least partially recover from propagation of the potential neutron strike via the first partitioned control path before propagating the potential neutron strike via the second partitioned control path.

16. The method of claim 15, wherein the recovery duration comprises a complete length of recovery after the potential neutron strike propagates via the first partitioned control path.

17. A memory device comprising: Dual interlock unit DICE latch; as well as an upstream circuit system coupled to the DICE latch and configured to receive a control signal for an operation in the DICE latch and to provide a first divided control signal and a second divided control signal to the DICE latch, the upstream circuit system comprising: a first divided control path configured to receive the control signal and generate the first divided control signal from the control signal; as well as and a second divided control path configured to generate the second divided control signal from the control signal, wherein the second divided control path includes a delay configured to delay the second divided control signal to stagger the propagation of potential neutron strikes affecting the control signal upstream of the second divided control path, and staggering the propagation includes staggering the propagation of the potential neutron strikes via the first divided control signal and the second divided control signal.

18. The memory device of claim 17, wherein the first divided control path comprises a first plurality of inverting amplifiers configured to: generating the first divided control signal; generating a first complementary divided control signal complementary to the first divided control signal; as well as The first divided control signal and the first complementary divided control signal are transmitted to the DICE latch.

19. The memory device of claim 17, wherein the second divided control path comprises a second plurality of inverting amplifiers configured to: generating the second divided control signal; generating a second complementary divided control signal complementary to the second divided control signal; and The second divided control signal and the second complementary divided control signal are transmitted to the DICE latch.

20. The memory device of claim 17, wherein the duration of the delay is of a length sufficient to allow the DICE latch to at least partially recover from propagation of the potential neutron strike via the first partitioned control path prior to propagating the neutron strike via the second partitioned control path.

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