Chip program issuing system and method based on FPGA

Abstract

The invention provides a chip program issuing system and method based on an FPGA, and belongs to the technical field of FPGA semiconductor tests.The method comprises the steps that a single-chip microcomputer downloading board is designed, and IO pins of the single-chip microcomputer downloading board are connected with a tested FPGA and a testing machine; developing a corresponding test program according to a test requirement, and generating a bit program file; a test mother board and a daughter board of the test machine are designed according to the requirements of the test machine, a downloading pin of the tested FPGA is connected with a downloading main control board of the single-chip microcomputer, and test resources corresponding to the test machine are connected to the tested FPGA through the mother board or the combination of the daughter board and the mother board; and development of a test program of the ate is carried out. According to the chip program issuing system and method based on the FPGA, the automatic testing process for testing the FPGA is simplified, and the problems that a downloader is externally hung and downloading needs to be conducted with the help of a development environment are solved. And the test efficiency and the automation degree are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA semiconductor testing, and particularly to a chip program downloading system and method based on FPGA. Background Art

[0002] The existing FPGA semiconductor testing based on ATE test program development has the following problems:

[0003] In terms of test program development:

[0004] High development difficulty: The functions of FPGA chips are complex. Developing test programs requires in-depth understanding of the FPGA architecture and functional characteristics, and at the same time, mastering relevant test theories and methods, so the development difficulty is relatively large.

[0005] Long development cycle: Due to the high development difficulty of FPGA test programs, the development cycle is relatively long. Especially for complex FPGA chips, the development cycle may be even longer.

[0006] Poor maintainability and scalability of test programs: As the functions of FPGA chips continue to increase and change, test programs need to be continuously maintained and extended. However, due to the complexity of test programs, their maintainability and scalability are often poor, which brings great challenges to the testing work.

[0007] In terms of test equipment and environment:

[0008] High equipment cost: ATE test equipment is expensive, especially for high-end FPGA test equipment, its cost is even higher, which is a great burden for some small test institutions and enterprises.

[0009] Fast equipment update: With the continuous development of FPGA technology, ATE test equipment also needs to be continuously updated to meet new test requirements. However, equipment update requires a large amount of capital investment, which is a great challenge for some test institutions and enterprises.

[0010] Complex test environment setup: FPGA testing requires setting up a complex test environment, including test equipment, test software, test fixtures, etc. This requires testers to have rich test experience and professional knowledge. At the same time, setting up the test environment also requires a large amount of time and effort, which brings great challenges to the testing work.

[0011] In terms of test result analysis and processing:

[0012] Difficult test result analysis: FPGA test results often contain a large amount of data and information. How to accurately analyze whether the performance and functions of the chip meet the requirements from these data and information is a great challenge.

[0013] Low efficiency in processing test results: Due to the great difficulty in analyzing test results, the efficiency of processing test results is relatively low. Especially for large-scale FPGA tests, the processing of test results may take a lot of time and effort. To test different configuration files of FPGAs with existing ate test machines, different file switches need to be performed through the FPGA development environment and downloaders, which cannot achieve automated testing and takes a long time.

[0014] Difficulty in visualizing test results and generating reports: How to visually display test results in an intuitive manner and generate detailed test reports is a great challenge. This requires testers to have certain programming and data processing capabilities, and also requires the use of some professional test result visualization and report generation tools.

[0015] Therefore, there is an urgent need in the art for a technical solution that can solve one or more of the above problems.

[0016] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0017] The purpose of the present invention is to provide a technical solution for FPGA automated testing.

[0018] To achieve the above purpose, the present invention provides the following solution:

[0019] A chip program downloading system based on FPGA, comprising:

[0020] A single-chip microcomputer download board, the IO pins of which are connected to the FPGA under test and the test machine;

[0021] The main control board includes a main control chip, DDR3, and QSPI FLASH; the main control board includes 1 gigabit Ethernet interface, 1 UART serial interface, 1 SD card interface, 1 JTAG download interface, 2 100PIN connector interfaces, a BNAK power voltage switching interface, and several button LEDs;

[0022] The main control chip has a main frequency of 866 MHz and supports 200 I / Os at the HR end and 120 I / Os at the HP end as signal input and output channels; the main control chip includes a processing system composed of a dual-core ARM Cortex-A9 as the core and a programmable logic part equivalent to one FPGA.

[0023] The FPGA includes programmable input / output units, basic programmable logic units, embedded block RAMs, several routing resources, underlying embedded functional units, and embedded dedicated hardcore.

[0024] A method for downloading a chip program based on an FPGA includes:

[0025] Design a single-chip microcomputer download board, and connect the IO pins of the single-chip microcomputer download board to the FPGA under test and the tester.

[0026] Develop corresponding test programs according to test requirements and generate bit program files.

[0027] Design a test motherboard and daughter board for the tester according to the requirements of the test machine platform, connect the download pins of the FPGA under test to the main control board of the single-chip microcomputer download, and connect the corresponding test resources of the test machine platform to the FPGA under test through the motherboard or a combination of the motherboard and daughter board.

[0028] Develop the test program for ate.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The chip program downloading system and method based on FPGA provided by the present invention simplifies the automated test process for testing FPGAs, solves the problems of external downloaders and the need to download with the aid of a development environment, solves the problem of how to automatically switch test configuration files during testing, and improves the test efficiency and automation level. Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0032] Figure 1 It is a schematic diagram of the main control chip structure provided by the embodiment of the present invention.

[0033] Figure 2 It is a circuit diagram of the pins of the resource 500 area block provided by the embodiment of the present invention

[0034] Figure 3 It is a circuit diagram of the pins of the resource 501 area block provided by the embodiment of the present invention.

[0035] Figure 4 It is a circuit diagram of the pins of the resource 502 area block provided by the embodiment of the present invention.

[0036] Figure 5 Pin circuit diagram of the resource 13 area block provided by an embodiment of the present invention.

[0037] Figure 6 Pin circuit diagram of the resource 34 area block provided by an embodiment of the present invention.

[0038] Figure 7 Pin circuit diagram of the resource 35 area block provided by an embodiment of the present invention. Detailed implementation manners

[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0040] The purpose of the present invention is to provide a technical solution that can be used for FPGA automated testing.

[0041] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0042] Embodiment 1:

[0043] This embodiment provides a chip program downloading system and method based on FPGA. By cooperating with the developed download board and various test machine programs, the test machine can download the developed FPGA configuration file through the existing instructions without relying on the FPGA development environment and downloader, so as to realize various automated tests. Through the FPGA download board, the developed FPGA configuration file can be downloaded through the program of the single-chip microcomputer. The ate test machine program only needs to send serial port instructions to the single-chip microcomputer, and the single-chip microcomputer program can automatically download the corresponding FPGA configuration program to the FPGA, realizing automatic switching of the downloaded file and improving the download efficiency.

[0044] 1. Design a single-chip microcomputer download board and connect the IO pins of the single-chip microcomputer download board to the FPGA under test and the test machine.

[0045] The main control board is mainly composed of a minimum system of ZYNQ7020 + 2 DDR3s + 1 QSPI FLASH.

[0046] ZYNQ7020 uses the XC7Z020_2CLG400I chip of Xilinx Corporation, as Figure 1-7As shown in the figure, the ZYNQ7020 chip can be divided into the processor system (PS) and the programmable logic (PL). Two DDR3 chips are mounted on the PS of the ZYNQ7020 chip, each with a capacity of up to 2Gbit, allowing the ARM system to independently process and store data. A 32M QSPI FLASH on the PS side is used to statically store the operating system, file system and user data.

[0047] The main control board has a wealth of peripheral interfaces, including 1 Gigabit Ethernet interface, 1 UART serial port interface, 1 SD card interface, 1 JTAG download interface, 2 100PIN connector interfaces, BNAK power supply voltage switching interface and some key LEDs. The main control board includes multiple area blocks such as resource 500 area block, resource 501 area block, resource 502 area block, resource 13 area block, resource 34 area block and resource 35 area block.

[0048] The main control chip ZYNQ on the board uses the embedded chip XC7Z020_2CLG484I with a main frequency of 866MHz. The chip core is ARM's Cortex-A9 core. It has rich on-chip resources and supports 200 HR-side and 120 HP-side I / Os as signal input and output channels.

[0049] ZYNQ is composed of two main parts: a (PL, Programmable Logic) part. The simplified model of the ZYNQ architecture is shown in the figure below: a processing system (PS, Processing System) composed of dual-core ARM Cortex-A9 as the core, and a programmable logic equivalent to an FPGA.

[0050] On ZYNQ, the core ARM Cortex-A9 is an application-level processor that can run operating systems like Linux, while the programmable logic is based on the Xilinx 7 series FPGA architecture. The ZYNQ architecture implements the industry-standard AXI interface, which enables high-bandwidth, low-latency connections between the two parts of the chip. This means that the processor and logic parts can each play their best role without incurring the interface overhead between two discrete devices. At the same time, the benefits of simplifying the system to a single chip can be obtained, including reductions in physical size and overall cost.

[0051] The PS part has a fixed architecture and contains the processor and system memory. The PL part is flexible and gives designers a "blank canvas" to create custom peripherals.

[0052] The simplified basic structure of the FPGA consists of six parts, namely programmable input / output units, basic programmable logic units, embedded block RAMs, rich wiring resources, underlying embedded functional units, and embedded dedicated hardcore, etc.

[0053] The highlight of the Zynq-7000 series is that it includes a complete ARM processor system, and the processor system integrates a memory controller and a large number of peripherals, enabling the Cortex-A9 processor to be completely independent of the programmable logic unit. In ZYNQ, the power supply circuits of the PL and PS parts are independent, so if the PS or PL part is not used, it can be powered off.

[0054] 2. FPGA engineers develop corresponding test programs according to the test requirements and generate bit program files. They only need to put these bit files into the corresponding SD cards, develop the test machine program. The test machine issues corresponding instructions through the serial port, and then calls the corresponding bit files in the SD card to send them to the FPGA under test, and runs the test program to perform functional tests on the FPGA under test.

[0055] 3. Design the test mother board and daughter board of the test machine according to the requirements of the test machine. Connect the download pins of the FPGA under test to the single-chip microcomputer download main control board, and connect the corresponding test resources of the test machine to the FPGA under test through the mother board or a combination of the mother board and daughter board.

[0056] Equipment: General ate test machines, such as J750, V93000, UltraFlex, etc.

[0057] 4. Develop the test program of ate. First, complete the communication with the single-chip microcomputer main control board. Secondly, download the FPGA program under test through the main control board. Finally, set different incentives for the test resources of the ate test machine according to the functional test requirements and then collect the test results.

[0058] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description in the method part.

[0059] In this article, specific examples are used to elaborate on the principles and implementation methods of the present invention. The descriptions of the above embodiments are only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, based on the idea of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A chip program distribution system based on FPGA, characterized in that: include: MCU download board, the IO pins of the MCU download board are connected to the FPGA under test and the test machine; The main control board includes the main control chip, DDR3 and QSPI FLASH; The main control board includes 1 Gigabit Ethernet interface, 1 UART serial port interface, 1 SD card interface, 1 JTAG download interface, 2 100PIN connector interfaces, BNAK power supply voltage switching interface and several key LEDs; The main control chip has a main frequency of 866MHz and supports 200 I / Os on the HR side and 120 I / Os on the HP side as signal input and output channels; the main control chip includes a processing system composed of a dual-core ARM Cortex-A9 as the core and a programmable logic part equivalent to an FPGA; FPGA includes programmable input / output units, basic programmable logic units, embedded block RAM, several wiring resources, bottom-level embedded functional units and embedded dedicated hard cores.

2. A chip program distribution method based on FPGA, characterized in that: include: Design the MCU download board and connect the IO pins of the MCU download board to the FPGA under test and the test machine; Develop the corresponding test program according to the test requirements and generate the bit program file; Design the test motherboard and daughterboard of the test machine according to the requirements of the test machine, connect the download pins of the FPGA under test with the MCU download control board, and connect the corresponding test resources of the test machine to the FPGA under test through the motherboard or the combination of the motherboard and daughterboard; Develop test procedures for ate.

Images