Standby replacement in memory systems

Abstract

The invention relates to spare replacement in a memory system. As part of background operation, a controller may assign bits to replace bits of a codeword and store an indication of assignment of the spare bits in a memory array. The codeword may include a set of bits each corresponding to a respective minimum substitution region (MSR) within a memory medium holding the codeword. The MSR corresponding to the bit to be replaced may include a number of error bits relative to a threshold. During a read operation, the controller may identify the spare bits in a first portion of the codeword, determine the bits to be replaced based on accessing the memory array, and replace the bits with the spare bits concurrently with receiving a second portion of the codeword.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of the patent application for invention titled "Spare Substitution in a Memory System" with the application date of July 23, 2019, application number "201980055576.9".

[0003] Cross-reference

[0004] This patent application claims the priority of PCT Application No. PCT / US2019 / 043050, titled "Spare Substitution in Memory System", filed by Pawlowski on July 23, 2019. The PCT application claims the priority of U.S. Patent Application No. 16 / 516,916, titled "Spare Substitution in Memory System", filed by Pawlowski on July 19, 2019, and U.S. Provisional Patent Application No. 62 / 702,808, titled "Spare Substitution in Memory System", filed by Pawlowski on July 24, 2018. Each of the applications is assigned to the present assignee and is hereby incorporated by reference in its entirety. Technical Field

[0005] This technical field relates to spare substitution in a memory system. Background Art

[0006] The following generally relates to operating a memory subsystem or a memory system, and more particularly, to spare substitution in a memory system.

[0007] A computing system may include a memory subsystem or a memory system that includes various memory devices and controllers coupled to one or more buses to manage information among numerous electronic devices such as computers, wireless communication devices, the Internet of Things, cameras, digital displays, etc. Memory devices are widely used to store information in such electronic devices. Information is stored by programming different states of the memory devices. For example, a binary device has two logic states typically labeled as logic "1" or logic "0". In other systems, more than two states may be stored in the memory device. To access the stored information, components of the electronic device may read or sense the stored states in the memory device. To store information, components of the electronic device may write or program the states in the memory device.

[0008] There are different types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, non-AND (NAND) memory, phase change memory (PCM), etc. The memory device can be volatile or non-volatile. A non-volatile memory cell can maintain its logical state for a long time even without an external power supply. A volatile memory device such as DRAM can lose its stored state when disconnected from an external power supply.

[0009] An improved computing system can include enhancing the performance of a memory system, such as reducing power consumption, increasing memory capacity and reliability, increasing read / write speed, providing non-volatility by using a permanent memory medium, or reducing the manufacturing cost at a certain performance point, and other metrics. SUMMARY OF THE INVENTION

[0010] Disclosed is a method. In some instances, the method can include: receiving a first portion of a codeword from a memory medium, the codeword including a set of bit fields indicating a plurality of data bursts across a plurality of channels; identifying spare bits in the first portion of the codeword to replace a bit field of the set at least partially based on receiving the first portion of the codeword; determining the bit field of the set to be replaced by the spare bits at least partially based on identifying the spare bits; receiving a second portion of the codeword at least partially based on determining the bit field of the set to be replaced by the spare bits; and replacing the bit field of the set in the second portion of the codeword with the spare bits simultaneously with receiving the second portion of the codeword.

[0011] Disclosed is a method. In some instances, the method can include: reading a codeword from a memory medium including a set of minimum substitution regions (MSRs), the codeword including a plurality of bits each corresponding to a respective MSR of the set; identifying a number of error bits in the codeword using an error control operation at least partially based on a size of one or more MSRs of the set; setting a value of a counter associated with the MSRs of the set corresponding to the number of error bits at least partially based on identifying the number of error bits in the codeword; determining the value of the counter relative to a threshold at least partially based on the value of the counter; and assigning spare bits of the codeword to the number of error bits at least partially based on the value of the counter relative to the threshold.

[0012] Describe a method. In some instances, the method may include: reading a codeword from a memory medium including a plurality of minimum substitution regions (MSRs), the codeword including a set of bit fields indicating a plurality of channels associated with the memory medium, wherein each bit field of the set corresponds to a respective one of the plurality of MSRs associated with a counter; identifying, at least in part based on reading the codeword, a first number of counters associated with a channel among the plurality of channels, each of the first number of counters having a value equal to or greater than a first threshold; determining, at least in part based on identifying the first number of counters, that the first number is equal to or greater than a second threshold; and assigning, at least in part based on determining that the first number is equal to or greater than the second threshold, a spare channel of the codeword to the channel among the plurality of channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Illustrate examples of a computing system that supports spare substitution in a memory system in accordance with aspects disclosed herein.

[0014] Figure 2 Illustrate examples of a computing system that supports spare substitution in a memory system in accordance with aspects disclosed herein.

[0015] Figure 3 Illustrate examples of a codeword format that supports spare substitution in a memory system in accordance with aspects disclosed herein.

[0016] Figure 4 Illustrate examples of the configuration of a memory die and the configuration of a memory medium that support spare substitution in a memory system in accordance with aspects disclosed herein.

[0017] Figure 5 Show a block diagram of an apparatus that supports spare substitution in a memory system in accordance with aspects disclosed herein.

[0018] Figures 6 to 8 Describe one or more methods that support spare substitution in a memory system in accordance with aspects disclosed herein. DETAILED DESCRIPTION

[0019] The performance of a computing system (e.g., a server including a memory system or subsystem) can depend on various factors, such as supplying reliable information to the computing system with low latency (e.g., load-to-use latency). In the context of a computing system or subsystem, data carrying information can be referred to as a codeword. In some cases, a codeword can include a certain amount of user data and other bits carrying various information (e.g., bits supporting error control operations) to provide reliable user data with low latency. A codeword can be associated with an element of the computing system (e.g., a memory medium of a memory system or subsystem), and the codeword can be transmitted and received during one or more access operations or background operations or both. A background operation in a computing system can refer to a processing program that runs without user intervention (e.g., an access command from a host device).

[0020] In some cases, the memory cells of one or more memory dies in a memory medium can support a limited number of access operations (e.g., read cycles or write cycles or both) before becoming unreliable or having problems. When a memory cell is unreliable, the information generated by the memory cell can become erroneous or invalid, and such a memory cell (or the information generated by the memory cell) can be referred to as an error bit. When a certain number of memory cells associated with a codeword generate error bits, the codeword (e.g., the user data in the codeword) can become erroneous or invalid beyond the error recovery capability of the memory system or subsystem. Thus, replacing the error bits in a codeword with spare bits can improve the reliability of the system by providing reliable data to the host. In addition, the concepts disclosed herein can support spare replacement without introducing a large amount of latency and can contribute to the low-latency operation of a computing system.

[0021] The memory array of a memory die can be configured to include a set of minimum substitution regions (MSRs). An MSR can be configured as a reasonable fault containment region to effectively manage (e.g., replace, substitute) error bits in the memory array. In some cases, an MSR can include a group of memory cells configured as data units associated with error control operations. In addition, at least some (if not all) of the set can be associated with a counter configured to count the number of error bits in each MSR in the set. A group of MSRs across a set of channels of a memory medium (e.g., a group of MSRs operating in parallel) can hold a certain number of codewords. In some cases, a group of MSRs configured to generate the certain number of codewords can be referred to as an MSR stripe or an MSR region.

[0022] In some cases, as part of a background operation, a controller (e.g., a port manager associated with a memory medium) may read codewords from a memory medium that contains a set of MSRs. The codewords may include multiple bits each corresponding to a respective MSR in the set. The controller may use error control operations to identify the number of error bits in a codeword and set the value of a counter associated with the MSRs in the set, the value corresponding to the number of error bits. Additionally, the controller may determine the value of the counter relative to a threshold, where the counter is associated with an MSR that contains at least one of the number of error bits, and the controller may assign spare bits of the codeword to replace the error bits (e.g., the MSR corresponding to the error bits). The controller may write an indication of the spare bit assignment for the error bits, which may include saving the indication in a separate memory array (e.g., static random access memory (SRAM) cells) that may be configured to save such indications. In some cases, the controller may transfer information (e.g., one or more indications of spare bit assignments) to non-volatile memory prior to a power change or loss event.

[0023] During a read operation, the controller may identify spare bits in a first portion of the codeword based on accessing a memory array (e.g., SRAM cells) that contains an indication of the spare bit assignment to determine the error bits to be replaced. In some cases, the controller may replace the error bits with the spare bits concurrently with receiving a second portion of the codeword. The codeword may be configured according to a codeword format that supports low-latency operation to produce reliable user data sent to a host with the spare bits ready. For example, the first portion of the codeword may correspond to a first data burst (e.g., an initial data burst) that includes one or more spare bits, and the second portion of the codeword may correspond to one or more additional data bursts that are temporally after the initial data burst. In this way, the spare bits (e.g., the spare bits that replace error bits during a read operation) may be multiplexed into the bit stream of the codeword in a series of data bursts, which adds little or substantially no additional latency (other than the latency of the multiplexing components).

[0024] The following further describes the features of the present disclosure introduced herein in the context of Figure 1 a exemplary system level. The specific instances of the configuration of the system and the memory medium of the system are then described in the context of Figures 2 to 4 . These and other features of the present disclosure are further illustrated and described with reference to the following: a device diagram of Figure 5 various components related to the controller and a flowchart of Figures 6 to 8 operations related to spare replacement in a memory system.

[0025] Figure 1Illustrate an example of a computing system 100 that supports spare replacement in a memory system according to aspects disclosed herein. The computing system 100 may include a host device 105 coupled to a device 140 via a host interface 115 (which may also be referred to as a host link). The host device 105 may be or include a server, a system-on-chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU), among other examples. In some instances, the host device 105 may access one or more memory media 130 located in the device 140 (e.g., read from one or more memory media 130, write to one or more memory media 130) via the host interface 115.

[0026] The host interface 115 (e.g., host link) may be compatible with or employ a protocol (e.g., Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX) protocol) to facilitate access operations between the host device 105 and one or more memory media 130. The host interface 115 may be configured to transfer data at a first data transfer rate (e.g., 25 gigabytes per second (GBps)) in at least one direction (e.g., send direction or receive direction). In some instances, when the transaction size is 64 bytes, the 25 GBps data transfer rate may support approximately 586 million transactions per second. In other instances, when the transaction size is 128 bytes, the 25 GBps data transfer rate may support approximately 312.5 million transactions per second.

[0027] In some cases, the device 140 may be referred to as a memory system or subsystem or a memory device. In some cases, the device 140 may include a power management component. The power management component may monitor a power level, which may indicate a power change or loss related to the device 140 or the computing system 100. In some cases, the power level may fluctuate outside of a normal range to indicate such a power change or loss event. The device 140 may include a controller 120 coupled to one or more memory media 130 via a channel 125. In some cases, the channel 125 may be referred to as an aggregate channel 125, which includes a plurality of other channels (e.g., channels with a smaller bandwidth compared to the aggregate channel 125) as described in reference Figure 2 The device 140 may include a non-volatile memory 131 coupled to the controller 120 via a channel 126. In some instances, the controller 120, one or more memory media 130, or the non-volatile memory 131 or any combination thereof may be integrated with, in contact with, or placed on a board (e.g., a Peripheral Component Interconnect Express (PCIe) board). In some cases, the non-volatile memory 131 may be integrated as part of the controller 120.

[0028] The controller 120 may include various functional blocks that facilitate the operation of the device 140 and one or more memory media 130. In some cases, a power management component may be integrated as part of the controller 120. In some cases, the controller 120 may include aspects of an interface controller to accommodate different specifications, constraints, or characteristics associated with the host interface 115, the channel 125, the channel 126, or any combination thereof. In some instances, the controller 120 may be an ASIC, a general-purpose processor, other programmable logic device, discrete hardware components (e.g., chiplets), or may be a combination of components.

[0029] In some cases, the controller 120 may read data from or write data to the memory media 130 (e.g., memory media 130-a) in conjunction with a local controller (e.g., a controller local to the memory media 130-a), and the local controller may perform various operations (e.g., write data to a memory cell, read data from a memory cell, arrange codewords according to the codeword format described in the reference Figure 3 or the forwarded codeword format). In some instances, the local controller may send the requested data to the controller 120 via one of the channels 125, and the channel 125 may be an instance of an aggregated channel.

[0030] Each memory media (e.g., memory media 130-a) may include a plurality of memory dies (e.g., forty-four (44) memory dies) to obtain a specified or desired memory capacity of the memory media. In some instances, the memory dies may include a three-dimensional cross-point array of memory cells, which may include structures or components formed of chalcogenides (e.g., including 3D XPoint TM memory dies of 3DXP memory cells). In other instances, the memory dies may include other types of memory devices (e.g., FeRAM dies, MRAM dies, PCM dies). In some instances, codewords (e.g., codewords containing 128 bytes of user data) may be divided across multiple memory dies within the memory media (e.g., memory media 130-a).

[0031] In some cases, each memory die (e.g., each 3DXP memory die) among multiple memory dies may generate a certain amount of data (e.g., 128 - bit data) as units from the memory die associated with an access operation (e.g., a read operation). The amount of data (e.g., 128 - bit data) may include a sequence of bursts (e.g., sixteen (16) bursts), where each burst includes a certain amount of data (e.g., eight (8) - bit data) transmitted from the memory die via a bus (e.g., an 8 - bit wide bus). As an example, when the memory medium includes eleven (11) memory dies operating in parallel, and when each of the eleven (11) memory dies generates eight (8) - bit data at a given burst, the memory medium may generate 88 - bit data for the given burst. Since the eleven (11) memory dies may generate data over a total of sixteen (16) bursts, and each burst includes 88 - bit data from the eleven (11) memory dies, the data units (e.g., data units transmitted via a channel (e.g., an aggregation channel)) associated with the memory medium during an access operation may include 1,408 bits.

[0032] Thus, in this example, the codeword (e.g., the data unit during a transaction of an access operation) associated with the memory medium may include 1,408 bits. In some cases, a burst may be referred to as a channel burst or a data burst. In some cases, the channel between the controller 120 and the memory medium (e.g., memory medium 130 - a) may include multiple channels, where each channel may be associated with one or more memory dies of the memory medium (e.g., memory medium 130 - a) described with reference to Figure 3 and 4 the memory medium (e.g., memory medium 130 - a).

[0033] The memory medium (e.g., memory medium 130 - a) may include a set of memory dies each including a memory array. Each memory die (e.g., each memory array) in the set may be configured to include an MSR set as described with reference to Figure 4 The MSR may be configured as a reasonable fault - containment region to effectively manage (e.g., replace, substitute) error bits in the memory array. Additionally, at least some (if not all) of the set may be associated with a counter configured to count the number of error bits in each MSR in the set.

[0034] Channel 125 may be configured to transfer data (e.g., codewords) between controller 120 and one or more memory media 130. Each of channels 125 (e.g., channel 125-a, which may be an instance of an aggregated channel) may include a plurality of other channels (e.g., channels with a smaller bandwidth compared to channel 125-a) for transferring data (e.g., codewords) in parallel. In some cases, a codeword may include user data (e.g., 128 bytes of user data in a codeword) and other data sets (e.g., the remaining data in the codeword for generating reliable data with low latency). Each of channels 125 (e.g., channel 125-a, which may be an instance of an aggregated channel) may include other channels to carry information (e.g., metadata) related to various auxiliary functions. In some cases, the codeword format (which may also be referred to as the codeword layout) or the forwarded codeword layout (e.g., the forwarded codeword layout) may define the manner in which each of channels 125 (e.g., channel 125-a) may transfer data (e.g., codewords) between controller 120 and one or more memory media 130.

[0035] Non-volatile memory 131 may include an array of non-volatile memory cells that can maintain their logical states for a long period of time even without an external power source. For example, the non-volatile memory cells may be or include 3D XPoint TM memory cells, PCM cells, FeRAM cells, or flash (e.g., NAND flash, NOR flash) memory cells, and other examples. Additionally, non-volatile memory 131 may be configured to exchange information with controller 120 via channel 126. For example, non-volatile memory 131 may receive information from controller 120 via channel 126 and save the information when a power change or loss related to computing system 100 is detected.

[0036] In some cases, a memory subsystem or system that may include device 140 may include a power management component for managing power change or loss events. The power management component may be operable to detect a power change or loss signature (e.g., a power level indicating that a power change or loss may occur) and transmit an indication of the power change or loss signature to controller 120. Controller 120 may, upon receiving the indication, transmit information (e.g., an indication of an error state associated with a codeword, one or more indications of spare bit assignments for error bits) stored in a memory array (e.g., an SRAM memory array) in controller 120 to non-volatile memory 131. Non-volatile memory 131 may store the information such that the information may be retained in the absence of power to the memory subsystem or memory system that may include device 140. When power to computing system 100 is restored or otherwise adjusted, controller 120 may retrieve the information from non-volatile memory 131 to resume an operation that has been interrupted by a power change or loss event based on the information retained in non-volatile memory 131.

[0037] In some cases, as part of one or more background operations, controller 120 may read codewords from a memory medium (e.g., memory medium 130) that includes a set of MSRs. The codewords may include a plurality of bits that may each correspond to a respective MSR in the set. Controller 120 may use error control operations to identify the number of error bits in a codeword and set (e.g., initially set, update) the value of a counter associated with an MSR (e.g., the MSR in the set that includes the number of error bits) in the set based on identifying the number of error bits in the codeword. Additionally, controller 120 may determine the value of the counter relative to a threshold and assign spare bits of the codeword to the number of error bits based on the value of the counter relative to the threshold. In some cases, the threshold may be referred to as a bit-level replacement threshold.

[0038] In some cases, controller 120 may write an indication of the spare bit assignment for the number of error bits to the memory array in controller 120 based on assigning spare bits of the codeword. The memory array may be configured to store multiple such indications associated with spare bits and may include SRAM cells. In some cases, controller 120 may configure (e.g., program, adjust) a threshold for an error rate (e.g., raw bit error rate (RBER)) associated with the memory medium based on identifying the number of error bits in a codeword. In other cases, controller 120 may configure a threshold for the size of an MSR in the set based on identifying the number of error bits in a codeword.

[0039] Figure 2An example of a computing system 200 that supports spare replacement in a memory system according to aspects disclosed herein is described. The computing system 200 can be an example of the computing system 100 referenced Figure 1 as described. The computing system 200 can include a host device 205 coupled to a memory subsystem or system 220 using at least one host interface (e.g., host interface 215-a). In some cases, the host interface 215 can be referred to as one or more host links. The host device 205 can be an example of the host device 105 referenced Figure 1 as described. The host interface 215 can be an example of the host interface 115 referenced Figure 1 as described. In some instances, the host interface 215 can be configured to transfer data at a first data transfer rate (e.g., 50 GBps, 25 GBps in each direction).

[0040] The computing system 200 can include a memory subsystem or system 220. The memory subsystem or system 220 can be an example of the device 140 referenced Figure 1 as described. The memory subsystem or system 220 can be referred to as a memory device. The memory subsystem or system 220 can include a controller 230. In some cases, the memory subsystem or system 220 can include a power management component. The power management component can monitor a power level, which can indicate a power change or loss related to the memory subsystem or system 220 or the computing system 200. In some cases, the power level can fluctuate outside of a normal range to indicate such power change or loss events. The controller 230 can be an example of the controller 120 referenced Figure 1 as described. The controller 230 can include an interface component 210 and a plurality of port managers 260. In some cases, the power management component can be integrated as part of the controller 230.

[0041] The interface component 210 can be configured to facilitate data exchange between the host device 205 and the memory subsystem or system 220 via the host interface 215. The interface component 210 can be configured to exchange data with the plurality of port managers 260 (e.g., using signal paths 250). Each signal path in the signal paths 250 can be configured to exchange data at a rate different from the first data transfer rate of the host interface 215 (e.g., 12.8 GBps). In some cases, the interface component 210 can be configured to provide routing network functionality to allow more than one host interface (e.g., host interface 215-a and host interface 215-b) to be associated with the plurality of port managers 260.

[0042] The memory subsystem or system 220 may include a non-volatile memory 296. The non-volatile memory 296 may be configured to communicate information with the controller 230 via a channel 292. The non-volatile memory 296 may be an example of the non-volatile memory 131 described in Figure 1 reference. And the channel 292 may be an example of the channel 126 described in Figure 1 reference or may include aspects of the channel 126. Additionally, the non-volatile memory 296 may be configured to communicate information with a port manager 260 in the controller 230. For example, when the port manager 260 receives an indication of a power change or loss related to the computing system 200 or the memory subsystem or system 220, the port manager 260 may transmit various information (e.g., one or more indications of spare bit assignments for error bits) to the non-volatile memory 296 via the channel 292 and store the information in the non-volatile memory 296. In some cases, the non-volatile memory 296 may be integrated as part of the controller 230.

[0043] Each port manager among a plurality of port managers 260 (e.g., port manager 260-b) may be coupled to a memory medium (e.g., memory medium 295-b) via an aggregated channel (e.g., aggregated channel 290-b). In some cases, each port manager among the plurality of port managers may be coupled to different one or more memory media 295. In some instances, individual port managers among the plurality of port managers 260 (e.g., port manager 260-a) may operate independently of each other (e.g., independently of port managers 260-b, 260-c, and 260-c) and may support access operations or background operations associated with one or more memory media 295. The one or more memory media 295 may be an example of the one or more memory media 130 described in Figure 1 reference. In some cases, each of the one or more memory media 295 may be referred to as a media port.

[0044] Each aggregated channel in the aggregated channel 290 may include one or more channels 291. In some cases, the channel 291 may be referred to as a logical channel 291. In some instances, each channel 291 may be associated with one or more memory dies in a memory medium (e.g., memory medium 295-a), and may have a bandwidth smaller than that of the aggregated channel (e.g., aggregated channel 290-b). In some instances, the aggregated channel (e.g., aggregated channel 290-a) may include eleven (11) channels 291 (e.g., channels 291-a to 291-k). For clarity, a plurality of channels 291 (e.g., channels 291-a to channel 291-k) for the port manager 260-a are depicted, which represent one of the aggregated channels 290 (e.g., aggregated channel 290-a), while other aggregated channels 290 (e.g., aggregated channels 290-b, 290-c, and 290-d) for the port managers 260-b, 260-c, and 260-d are depicted, and the plurality of channels 291 associated with each aggregated channel are not shown.

[0045] An individual memory medium (e.g., memory medium 295-a) in the one or more memory media 295 may include one or more memory devices (e.g., 3DXP memory dies). In some cases, the memory devices in the individual memory medium may be configured to operate in parallel to obtain a desired (or specified) aggregated bandwidth via one of the aggregated channels 290. As an example, the 3DXP memory die may be configured to have an 8-bit wide data bus and may be associated with each of the channels 291 (e.g., channel 291-a), such that each channel 291 is 8-bit wide. Additionally, the 3DXP memory die may be configured to generate 128-bit data during a sequence of sixteen (16) bursts, where each burst may generate 8-bit wide data via the channel 291. Thus, 128-bit data may be considered a single data unit generated by each 3DXP memory die based on an access command (or during background operations) to read memory cells within the 3DXP memory die.

[0046] In some cases, a codeword (or a forwarded codeword) may be configured to include a set of bit fields indicating multiple data bursts (e.g., a sequence of sixteen (16) bursts) across multiple channels (e.g., eleven (11) channels 291-a to 291-k that generate 88 bits of data per data burst). Thus, in some cases, a codeword may contain 1,408 bits of information. The description herein may be understood in terms of a logical view of a memory medium. There may be a greater number of physical 3DXP memory dies than the number of logical 3DXP memory dies in the memory medium to account for the overhead associated with various access operations (e.g., read operations, write operations) or background operations associated with the memory medium. Within the memory medium, a codeword may be divided into portions and written to or read from more than one die (e.g., 128 bytes of user data held across ten (10) 3DXP memory dies), as referenced Figure 3 as described.

[0047] The various examples described herein use 3DXP memory dies (e.g., containing 3D XPoint TM memory cells) to illustrate the manner in which a memory medium 295 may be configured and operate in conjunction with a port manager 260 in accordance with methods, apparatus, and systems for supporting spare replacement in a memory system as disclosed herein. In some cases, the memory medium 295 may include other types of memory devices that employ a memory technology different from 3DXP memory technology, such as FeRAM technology, PCM technology, MRAM technology, and other technologies. Thus, the concepts disclosed herein are not limited to a particular memory technology (e.g., 3DXPoint TM memory technology).

[0048] A memory medium (e.g., memory medium 295-a) may include a set of memory dies each containing a memory array. Each memory die (e.g., each memory array) in the set may be configured to include as referenced Figure 4The described MSR set. The MSR can be configured as a reasonable fault containment region to effectively manage (e.g., replace, substitute) error bits in the memory array. In some cases, each bit in a codeword (e.g., each of the 1,408 bits in the codeword) can be associated with a corresponding MSR in the set (e.g., 1,408 MSRs). A group of MSRs across a set of channels of the memory media (e.g., channels 291-a to 291-k of memory media 295-a) can be configured to operate in parallel to maintain or generate a certain number of codewords. In some cases, the group of MSRs configured to generate the number of codewords can be referred to as an MSR stripe or an MSR region. Additionally, at least some (if not all) of the set can be associated with a counter configured to count the number of error bits in each MSR in the set.

[0049] In some cases, as part of a read operation, a port manager (e.g., port manager 260-a) receives a first portion of a codeword from a memory media (e.g., memory media 295-a). The codeword can include a set of bit fields indicating multiple data bursts across multiple channels (e.g., channels 291-a to 291-k). The port manager can identify spare bits in the first portion of the codeword to replace a bit field of the set. The port manager can determine the bit field of the set to be replaced by the spare bits based on the identified spare bits. The port manager can also receive a second portion of the codeword (e.g., one or more other data bursts), the second portion including the bit field of the set to be replaced by the spare bits. In some cases, the port manager can replace the bit field of the set in the second portion of the codeword with the spare bits (e.g., concurrently with receiving the second portion of the codeword). Thus, the spare bits can be multiplexed into the bit stream of the codeword in a series of data bursts, which adds very little additional latency or essentially no additional latency (except for the latency of the multiplexing component).

[0050] In some cases, a port manager may access a memory array of the port manager to determine a set of bit fields in a second portion of a codeword that are to be replaced by spare bits. The memory array may be configured to hold an indication of spare bit assignments for a set of bit fields of codewords and may include SRAM cells. In some cases, the port manager may perform error control operations for a codeword based on replacing the set of bit fields in the second portion with spare bits. In some cases, the size of the memory array (e.g., SRAM cells) for holding an indication of spare bit assignments may be based on the identification of a channel in a plurality of channels, the number of spare bits in a codeword, the identification of one or more MSRs of the number of MSRs associated with the codeword, the number of bits associated with a forwarded codeword in a memory medium, the error correction capability of the indication of spare bit assignments, the number of memory dies corresponding to a channel in the plurality of channels, the number of MSRs in the number of memory dies, or a bit indicating a change in spare bit assignments, or any combination thereof, and other examples.

[0051] Figure 3 An example of a codeword format 300 (which may also be referred to as a codeword layout 300) that supports spare substitution in a memory system in accordance with aspects disclosed herein is illustrated. The codeword format 300 may be an example of a codeword format for an entire codeword. The codeword may include a set of bit fields indicating a plurality of data bursts across a plurality of channels (e.g., channels 291-a through 291-k as described with reference to Figure 2 ). Figure 3 Also included are formats 301 through 305 (also referred to as layouts) that illustrate respective configurations for individual channels (e.g., channel 291-a as described with reference to Figure 2 ). Figure 3 Format 306 is also illustrated, which may correspond to a portion of a codeword (e.g., a subset of bit fields during one or more first data bursts across a plurality of channels).

[0052] As an example of a codeword format and structure, the codeword format 300 may include a number of data fields (e.g., bit fields) (e.g., 1,408 data bits) that may be generated by a memory medium (e.g., memory medium 130-a or memory medium 295-a as described with reference to Figure 1 and 2 ), in response to an access command or during a background operation or both. The codeword may include 128 bytes (e.g., 1,024 bits) of user data. The remaining bit fields (e.g., 384 bits of data) within the codeword may carry various information that may assist in transferring accurate user data during an access operation or during a background operation or both. Additionally, the remaining bits carrying various information may be configured to facilitate low-latency operations (e.g., spare substitution) associated with the codeword during an access operation.

[0053] Codeword format 300 can span multiple channels (e.g., channels 310-a to 310-k). One of these channels (e.g., channels 310-a to 310-k) can be an example of or include aspects of the channel 291 described as Figure 2 the channel 291-a. In some cases, each of the multiple channels 310 (e.g., channel 310-a) can be associated with one or more 3DXP dies, which can include an 8-bit wide data bus. For example, each channel can produce a total of 128 bits of data as a single object of a transaction (e.g., communication, operation) associated with an access command (e.g., read command) or a background operation or both. Additionally, 128 bits of data can be produced as a sequence of sixteen (16) data bursts, each data burst configured to produce eight (8) bits of data on an 8-bit wide data bus. Thus, each of the channels (e.g., channels 310-a to 310-k) within the codeword format can correspond to 128 bits of data that includes sixteen (16) groups of 8-bit data, such as G7…G0 for channel 310-g, where G7…G0 can represent a series of eight (8) 0s and 1s, where G7 can be the most significant bit (e.g., the eighth bit of the series of eight (8) 0s and 1s) and G0 can be the least significant bit (e.g., the first bit of the series of eight (8) 0s and 1s)), and where each of the sixteen (16) groups of 8-bit data can be associated with one of the sixteen (16) data bursts.

[0054] In one example, codeword format 300 can span eleven (11) channels and each of the eleven (11) channels can produce 8 bits of data at each data burst, and a total of 88 bits of data (e.g., first data burst 320-1 of 88 bits) can be produced across the eleven (11) channels at each data burst. Thus, codeword format 300 can include 1,408 bits of data (e.g., first data burst 320-1 to sixteenth data burst 320-16, each data burst producing 88 bits of data) as a single object of a transaction for a memory medium (e.g., memory medium 130-a or memory medium 295-a). Codeword format 300 can support reliable transactions (e.g., conveying accurate user data content) with low latency (e.g., a low number of clock edges to produce user data).

[0055] Each field (e.g., each bit field) or set of fields (e.g., set of bit fields) within a codeword may contain information that facilitates reliable transactions of user data with low latency. In some cases, one or more fields (e.g., bit fields) within a codeword format may be configured to indicate a codeword condition (e.g., using one or more CwCon bits). A codeword may be configured in one of a plurality of possible states (e.g., four states) indicated by the CwCon bits. In some cases, one or more fields within a codeword format may be configured to indicate the number of access operations (e.g., read operation, write operation) associated with the codeword (e.g., WrCnt bit). In some cases, one or more fields within a codeword format may be configured to indicate that a portion of the codeword may be invalid (e.g., using a poison bit).

[0056] In some cases, one or more fields within a codeword format may be configured as cyclic redundancy check (CRC) bits that can identify error bits related to error control operations. In some cases, one or more fields within a codeword format may be configured as codeword error control code bits (e.g., CwECC bits) that support error control operations. In some cases, one or more fields within a codeword format may be configured as XOR bits. Each of the XOR bits may contain the digital or Boolean logical exclusive OR (XOR) product of the corresponding bits of other channels of the respective data burst. Thus, the XOR bits may support repairing the corresponding bits of other channels and may be referred to as repair bits. In some cases, each XOR bit (e.g., XOR / sub-bit or XORSub bit) may replace a field within the codeword rather than repair the field.

[0057] In some cases, one or more fields within a codeword format may be configured as spare bits (e.g., CRC / spare bits, XORSub / spare bits). Bits configured as spare bits may be configured as CRC bits or XOR bits (or XORSub bits) and other alternatives. As an example, Figure 3 the codeword format 300 depicted in may include up to twenty-two (22) spare bits, such as twenty (20) CRC / spare bits and two (2) XORSub / spare bits. That is, some CRC bits may be configured as spare bits. Similarly, some repair bits (e.g., XORSub bits) may be configured as spare bits. Thus, the number of spare bits within a codeword may be configurable because the number of spare bits may be replaceable for the number of CRC bits or XORSub bits. In some cases, the number of spare bits in a codeword may be determined based on mature memory technologies (e.g., 3D XPoint TM , FeRAM, MRAM technology) used to construct a memory medium (e.g., memory medium 130, memory medium 295).

[0058] In some cases, spare bits may be configured to operate as a replacement for bits (e.g., error bits) designated as failed in a replacement codeword. In some cases, bits designated as failed may be associated with an MSR of a memory die (e.g., an MSR that includes a number of memory cells that may become faulty or unreliable). Spare bits (e.g., the MSR corresponding to the spare bits) may be routed (e.g., multiplexed using a multiplexing component) to replace (e.g., supersede) bits designated as failed (e.g., the MSR corresponding to the error bits) to support reliable transactions of user data within a codeword.

[0059] Still referring Figure 3 , each field (e.g., bit field) within the codeword format may be configured (e.g., arranged) to support low-latency operations during access operations associated with a memory medium. Figure 3 Includes formats 301 through 305, which illustrate various configurations for an 8-bit group for an individual channel (e.g., each of channels 310-a through 310-k). For example, each of formats 301 through 305 includes an eight (8)-bit group that a memory device (e.g., a 3DXP die) within a memory medium (e.g., memory medium 295-a) may generate at a given data burst. Example formats are described below, though the disclosure herein is not limited to these examples.

[0060] Format 301 may include CwCon bits in one or more (e.g., three) fields, CRC / spare bits in one or more (e.g., two) fields (which may be configured as CRC bits or spare bits), and CRC bits in one or more (e.g., three) fields. Format 302 may include CwCon bits in one or more (e.g., three) fields, CRC / spare bits in one or more (e.g., two) fields (which may be configured as CRC bits or spare bits), CRC bits in one or more (e.g., two) fields, and one or more WrCnt bits (e.g., counter bits).

[0061] Format 303 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / alternate bits (which may be configured as CRC bits or alternate bits), and one or more (e.g., three) fields of WrCnt bits (e.g., counter bits). Format 304 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / alternate bits (which may be configured as CRC bits or alternate bits), one or more fields of WrCnt bits (e.g., counter bits), and one or more (e.g., two) fields of suppression bits (e.g., bits indicating the invalidity of a portion of a codeword). Format 305 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of XORSub / alternate bits (which may be configured as XORSub bits or alternate bits), and one or more (e.g., three) fields of XORSub bits.

[0062] The codeword format 300 may also describe a 1,024-bit user data field (e.g., channels 310-a to 310-h on the second data burst 320-2 to the 16th data burst 320-16, and channels 310-i and 310-j on the second data burst 320-2 to the fifth data burst 320-5), a CwECC field (e.g., channels 310- and 310-j on the 6th data burst 320-6 to the 16th data burst 320-16), and an XOR / sub field (e.g., channel 310-k on the second data burst 320-2 to the 16th data burst 320-16).

[0063] As an example of a codeword format that supports low-latency operation, a subset of the bit fields corresponding to the first data burst (e.g., the first data burst 320-1) may be configured as described in format 306. In format 306, each group of 8-bit channels 310-a (e.g., A7…A0) and channels 310-b (e.g., B7…B0) may be configured to have format 301. Also, a group of 8-bit channels 310-c (e.g., C7…C0) may be configured to have format 302. At least some (if not all) groups of 8-bit channels 310-d (e.g., D7…D0) to channels 310-i (e.g., I7…I0) may be configured to have format 303. A group of 8-bit channels 310-j (e.g., J7…J0) may be configured to have format 304. Additionally, a group of 8-bit channels 310-k (e.g., K7…K0) may be configured to have format 305.

[0064] Due to configuring a subset of bit fields corresponding to a first data burst of codeword format 300 (e.g., first data burst 320-1) (e.g., a total of 88 bits, including eight (8) bits from each of eleven (11) channels), the first data burst of 88 bits (e.g., the 88 bits of format 306) can contain information that facilitates a low-latency reliable transaction (e.g., reading 1,024-bit user data) associated with the access operation of the codeword. In some cases, a port manager (e.g., port manager 260-a) can receive a first portion of a codeword associated with a memory medium (e.g., the bits corresponding to the first data burst 320-1 of format 306). The port manager can parse (e.g., interpret) the first portion of the codeword (e.g., identify spare bits) simultaneously with receiving additional portions of the received codeword (e.g., the bits corresponding to the second data burst 320-2 of codeword format 300, etc.) during subsequent data bursts. Thus, the port manager can parallelize various operations associated with the codeword to provide reliable low-latency communication or information exchange with the host.

[0065] As an example, within the first data burst (e.g., first data burst 320-1) depicted in format 306, there can be up to twenty-two (22) spare bit fields across eleven (11) channels (e.g., channels 310-a to 310-k), two fields per channel. In some cases, as part of a read operation, a controller (e.g., controller 120 or port manager 260-a as referenced Figure 1 and 2 described) can receive a first portion of a codeword from a memory medium (e.g., memory medium 130-a or memory medium 295-a as referenced Figure 1 and 2 described). The codeword can contain a set of bit fields indicating multiple data bursts across multiple channels (e.g., channels 310-a to 310-k).

[0066] The controller can identify a spare bit in the first part of the codeword (e.g., one of the twenty-two (22) spare bits in the first data burst 320-1) to replace a set of bit fields. The controller can determine the set of bit fields to be replaced by the spare bit (e.g., the D1 bit of channel 310-d within the third data burst 320-3) based on the identified spare bit. Additionally, the controller can receive the second part of the codeword (e.g., the second data bursts 320-2 to 320-16 or any part thereof, one or more additional data bursts). In some cases, the port manager 260-a can replace the set of bit fields in the second part of the codeword with the spare bit simultaneously with receiving the second part of the codeword (e.g., the fourth data bursts 320-4 to 320-16 or any part thereof). That is, in some cases, the port manager 260-a can replace the set of bit fields in the second part of the codeword with the spare bit without increasing the number of clock edges used to process a sequence of data bursts (e.g., 16 data bursts). For example, the port manager 260-a can receive a data burst and replace the bit fields over a first number of clock cycles while outputting the data burst with the replaced bit fields over the same number of clock cycles (e.g., the first number of clock cycles). In some cases, this may also be referred to as in-line, concurrent, parallel, or simultaneous error correction. Thus, the spare bits can be multiplexed into the bit stream of a codeword over a series of data bursts with very little additional latency or essentially no additional latency (other than the latency of the multiplexing components).

[0067] In some cases, the controller can access the memory array of the controller to determine the set of bit fields in the second part of the codeword to be replaced by the spare bit in the first part (e.g., the D1 bit of channel 310-d within the third data burst 320-3). The memory array can be configured to hold an indication of the spare bit assignment for the set of bit fields of the codeword and can include SRAM cells. In some cases, the controller can perform error control operations for the codeword based on replacing the set of bit fields in the second part of the codeword with the spare bit.

[0068] In some cases, replacing the set of bit fields in the second part of a codeword with spare bits may involve using different methods to replace the set of bit fields with spare bits, which may include using a combination of hierarchical logic gates configured based on multiple channels (e.g., eleven (11) channels, i.e., channels 310-a to 310-k), and so on. In some cases, the combination of hierarchical logic gates may be configured based on the number of bit fields in a set corresponding to a data burst among multiple data bursts (e.g., sixteen (16) data bursts) (e.g., eight (8) bits). Additionally, in some cases, the first part of the codeword may correspond to an initial data burst among multiple data bursts (e.g., the first data burst 320-1) and the second part of the codeword may correspond to one or more additional data bursts that are temporally after the initial data burst among multiple data bursts (e.g., the second data burst 320-2 to 320-16 or any part thereof).

[0069] In this way, the controller may receive spare bits in the first data burst of the codeword (e.g., up to 22 spare bits in the first data burst 320-1) and determine the error bits to be replaced based on accessing a memory array (e.g., SRAM cells that hold indications of spare bit assignments). The controller may replace (e.g., substitute) the error bits with spare bits either simultaneously with receiving additional data bursts (e.g., the second data burst to the sixteenth data burst or any part thereof) or simultaneously with the output of the corrected data burst. For example, when the controller determines that the D1 bit of channel 310-d within the third data burst 320-3 is the first error bit based on accessing the memory array, the controller may replace the D1 bit of channel 310-d within the third data burst 320-3 with a first spare bit (e.g., the spare bit A4 of channel 310-a in the first data burst 320-1) simultaneously with receiving additional data bursts (e.g., the fourth data burst 320-4, etc.). Thus, the controller may replace the error bits with spare bits before performing error control operations using the information in the CwECC field.

[0070] Figure 4 An example of a configuration 401 of a memory array and a configuration 402 of a memory medium that support spare replacement in a memory system according to aspects disclosed herein is illustrated. The memory array depicted in configuration 401 may be an example of a memory die of a memory medium (e.g., memory medium 130 or memory medium 295) as described in reference Figure 1 and 2 One. The memory medium depicted in configuration 402 may be a reference Figure 1 and 2Examples of the described memory media (e.g., memory media 130 or memory media 295). The memory media depicted in configuration 402 may include a number of memory arrays (e.g., forty-four (44) memory arrays) that may each be configured according to configuration 401.

[0071] Configuration 401 may include memory array 410. In some cases, memory array 410 may include a set of memory cells (e.g., 512 gigabits of memory cells, i.e., 2 39 memory cells). Memory array 410 may be organized with an array width 415 and an array depth 425. In some cases, array width 415 may be referred to as die width 415 and array depth 425 may be referred to as die depth 425. Additionally, each of array width 415 and array depth 425 may be divided into a number of partitions. In some cases, array width 415 may be divided into 128 segments. Thus, segment 420 depicted in configuration 401 may represent one of the 128 segments in array width 415. Additionally, each segment (e.g., segment 420) may be divided into 128 slices such that array depth 425 may be divided into 128 bars. A bar may be referred to as a segment, sub-segment, portion, element, etc. Thus, bar 430 depicted in configuration 401 may represent one of the 128 bars in array depth 425.

[0072] Thus, memory array 410 (e.g., 512 gigabit memory cells) may be divided into a number of segments 435 (e.g., segment 435-a, 435-b, or 435-c), which are depicted as squares inside memory array 410 as an example. In this example, memory array 410 may include 16,384 segments resulting from dividing array width 415 into 128 segments and further dividing each of those segments in array depth 425 into 128 bars (e.g., segments, sub-segments, portions, elements). Each segment 435 of memory array 410 may be referred to as an MSR 435. In some cases, an MSR 435 may include a group of memory cells (e.g., 2 25 memory cells) that may be configured as data units associated with error control operations. An MSR may be configured as a reasonable fault containment region to effectively manage (e.g., replace, substitute) error bits in the memory array.

[0073] The number of segments in the array width 415 (e.g., 128 segments) can be determined based on how the memory array in the memory die is constructed. For example, the memory array can have a certain number of tiles (e.g., 128 tiles), and the number of segments in the array width 415 can be based on the number of tiles of the memory array 410. Similarly, the number of bars in the array depth 425 (e.g., 128 bars) can be determined based on a common characteristic associated with each functional component (e.g., row decoder, column decoder, etc.). Since the memory array 410 is partitioned as depicted in configuration 401, each segment 435 (e.g., an MSR containing 2 25 memory cells out of 16,384 MSRs in a memory array containing 512 gigabits) can provide a group of memory cells (e.g., data units) to efficiently manage (e.g., replace, substitute) error bits in the memory array 410 without significant overhead. In some cases, the cell size of the memory cells (e.g., 2 25 memory cells of an MSR) can be referred to as the data granularity that supports efficient error control operations associated with the memory medium.

[0074] Still referring to configuration 401, the bars 430 across a certain number of segments (e.g., 128 segments) can represent a first number of bits (e.g., 128 bits) that are part of a codeword generated by the memory array 410. The first number of bits (e.g., 128 bits) of the bars 430 can be further demultiplexed down to a second number of bits (e.g., eight (8) bits), where each set of the second number of bits (e.g., eight (8) bits) can be generated at a given data burst (e.g., one of sixteen (16) data bursts that produce a total of 128 bits). Thus, the bars 430 can generate a part of the codeword, where each segment 435 (e.g., MSR 435) contributes one of the first number of bits (e.g., 128 bits) of the codeword. Additionally, the bars 430 (e.g., 128 bits generated over 16 data bursts) can correspond to a channel (e.g., channel 291-a as described in Figure 2 reference). When a certain number of memory arrays 410 (e.g., eleven (11) memory arrays 410) operate in parallel such that each memory array can generate a part of the bits that make up a complete codeword (e.g., each memory array 410 generates 128 bits over eleven (11) channels in sixteen (16) data bursts, equivalent to a 1,408-bit codeword in total), a complete codeword (e.g., a 1,408-bit codeword) can be generated.

[0075] Configuration 402 can include a set of memory arrays 410 (e.g., forty-four (44) memory arrays 410) to achieve a memory medium (e.g., as described in reference Figure 1and 2 the desired or specified capacity of the memory media 130 (a memory media 295) described. A collection of memory arrays in the memory media may be arranged to form multiple channels for the memory media. In some cases, the memory media may include eleven (11) channels (e.g., channels 440-a to 440-k) as illustrated in configuration 402. Each channel 440 may be an instance of or include aspects of the channel 291 (e.g., channels 291-a to 291-k) described with reference to Figure 2 the channel 291 described. Additionally, each channel 440 may be configured to include a subset of memory arrays. In some cases, a channel (e.g., channel 440-a) may include four (4) memory arrays 410-a to 410-d. Thus, in some cases, each channel in the multiple channels may include the total number of bars 430 (e.g., 512 bars), which corresponds to the number of bars of the memory arrays 410 (e.g., 128 bars) multiplied by the number of memory arrays 410 within the channel (e.g., four (4) memory arrays).

[0076] In some cases, a group of MSRs that generate codewords across multiple channels (e.g., eleven (11) channels, i.e., channels 440-a to 440-k) may be referred to as an MSR stripe (e.g., the MSR stripe 445 depicted in configuration 402). The MSR stripe may also be referred to as an MSR region. For example, the memory media of configuration 402 includes 512 MSR stripes (e.g., 512 MSR regions). Moreover, an MSR stripe (e.g., MSR stripe 445) may correspond to the collective array depth of the memory media (e.g., the collective die depth), e.g., the MSR stripe 445 depicted in configuration 402 may correspond to the 130th array depth of the memory media (e.g., the 130th MSR stripe out of the total array depth of 512 MSR stripes), where each memory array 410 includes 128 MSR stripes. In some cases, a flag may be associated with the MSR stripe (or MSR region) to indicate a change in the spare bit assignment associated with the codewords held in the MSR stripe (e.g., MSR stripe 345 or MSR region 345). The flag may be a part of a memory array (e.g., SRAM memory cells) in a controller (e.g., the controller 120 or port manager 260-a described with reference to Figure 1 and 2 described).

[0077] At least some (if not all) of the MSRs (e.g., MSR 435-a, MSR 435-b, MSR 435-c) of a memory array (e.g., memory array 410) may be associated with a counter configured to count the number of error bits therein. For example, as part of a background operation, a port manager (e.g., with reference toFigure 2 The described port manager 260 - a) can read codewords from an MSR strip (e.g., MSR strip 445) and perform error control operations for the codewords. The port manager can identify the number of error bits and correct the number of error bits in the codeword using a set of bits in the codeword (e.g., bits that support an error correction function). Each of the number of error bits (e.g., an error or unreliable memory cell) can correspond to a respective MSR of the MSR strip. The port manager can update a first counter associated with the first MSR of the MSR strip to count the number of error bits (e.g., error bit count) in the first MSR of the MSR strip.

[0078] The port manager can sort the values (e.g., error bit count) saved in counters for the codewords (e.g., 1,408 counters each corresponding to 1,408 MSRs) to identify a subset of values that are greater than the remaining values. For example, the port manager can sort the values (e.g., error bit count) in descending order to identify a subset of values (e.g., 160 highest error bit counts out of 1,408 error bit counts associated with the codeword). In this way, the port manager can identify a subset of MSRs that each contain a higher number of error bits compared to other MSRs. The port manager can identify a subset of MSRs (e.g., 160 MSRs out of 1,408 MSRs) as candidates for replacement (e.g., replacing such MSRs with reliable MSRs (e.g., spare MSRs)). In some cases, the port manager can configure the number of values in the subset (e.g., 200 highest error bit counts instead of 160 highest error bit counts) based on the number of error bits identified in the codeword. In some cases, such a number of values for the subset (e.g., the subset of MSRs identified as candidates for replacement) can be based on various factors (e.g., the memory technology of the memory devices used to manufacture the memory media, the maturity of such memory technology, the memory media usage pattern).

[0079] In addition, the port manager can replace one or more MSRs with a higher error bit count (e.g., the subset of MSRs identified as candidates for replacement) with a set of spare MSRs until the set of spare MSRs is exhausted. The port manager can determine which MSRs to replace based on the number of error bits (e.g., error bit count) in the MSRs relative to a threshold (e.g., a bit - level replacement threshold). In some cases, the port manager can determine to replace an MSR with an error bit count that is equal to or greater than the threshold with a spare MSR. The threshold can be based on the raw bit error rate (RBER) associated with the memory media. In some cases, the threshold can be based on the MSR size (e.g., 2 in the MSR) 25In some cases, the threshold may be configurable (e.g., programmable) to account for, for example, the maturity of the technology used to fabricate the memory cells of the memory medium and process variations that may affect the electrical characteristics of the memory cells of the memory medium.

[0080] The port manager may refer to any one of the MSRs equipped with spare bits (e.g., spare bits in the codeword) to replace the candidates identified for replacement (e.g., error bits in the codeword). In some cases, spare bits (e.g., spare MSRs) may be assigned on a first identified, first assigned basis. For example, during one or more background operations (e.g., media cleaner operations), the port manager may determine that a bit (e.g., A7 in channel 310-a of the sixth data burst 320-6 described with reference to Figure 3 is the first bit in the codeword that meets the threshold (e.g., the first MSR containing an equal to or greater than the bit-level replacement threshold number of error bits). Then, an available spare bit (e.g., an MSR corresponding to the first spare bit, e.g., spare bit A4 in channel 310-a of the first data burst 320-1) may be assigned to replace the first bit (e.g., A7 in channel 310-a of the sixth data burst 320-6).

[0081] Later (e.g., during a later media cleaner operation), the port manager may determine that another bit (e.g., B0 in channel 310-b of the third data burst 320-3 described with reference to Figure 3 is the second bit in the codeword that meets the threshold (e.g., the second MSR containing an equal to or greater than the bit-level replacement threshold number of error bits). Then, a second available spare bit (e.g., another MSR corresponding to the second spare bit, e.g., spare bit A3 in channel 310-a of the first data burst 320-1) may be assigned to replace the second bit (e.g., B0 in channel 310-b of the third data burst 320-3).

[0082] The port manager may repeat assigning spare bits for error bits in the codeword until all spare bits have been assigned (e.g., with reference to Figure 3Up to twenty-two (22) spare bits as described. In some cases, spare bits (e.g., spare MSRs) can be reassigned to different error bits (e.g., different MSRs containing an error bit count equal to or greater than a bit-level threshold). In other cases, once each spare bit has been assigned to a corresponding error bit, the spare bit can remain assigned to the corresponding error bit in the codeword. When the set of replacement error bits (e.g., the set of MSRs corresponding to the set of error bits) is larger than the available spare bits (e.g., the MSRs corresponding to the available spare bits), the port manager can assign the available spare bits to a subset of the error bits, where the subset of MSRs corresponding to the subset of error bits each contain a larger error bit count therein compared to other MSRs. Thus, the port manager can replace the most problematic MSRs (e.g., based on the error bit count in the MSR) with the available spare bits.

[0083] The port manager can save information indicating the spare assignment of the codeword (e.g., the spare bit assignment to the corresponding error bits) in a separate memory array. In some cases, the memory array can be integrated as part of the port manager. In some cases, the memory array can include static random access memory (SRAM) cells. The size of the memory array allocated for saving information can be based on the identification of channels in a plurality of channels (e.g., eleven (11) channels), the number of spare bits in the codeword (e.g., up to twenty-two (22) spare bits), the identification of one or more MSRs among the number of MSRs associated with the codeword (e.g., 1,408 MSRs), the number of bits associated with the forwarded codeword in the memory medium, the error correction capability of the indication for spare bit assignment, the number of memory dies corresponding to the channels in the plurality of channels (e.g., four (4) memory dies per channel), the number of MSR groups in the number of memory dies (e.g., 128 MSR bars), or a bit indicating a change in the spare bit assignment (e.g., a flag indicating a change in the spare assignment), or any combination thereof.

[0084] In some cases, the port manager can receive an indication of the power level from a power management component coupled to the port manager and transfer the information (e.g., the indication of the spare bit assignment) saved in the memory array (e.g., SRAM cells) for reference Figure 1 and 2 to the non-volatile memory (e.g., permanent memory) as described.

[0085] In some cases, the port manager may set a flag associated with the port manager based on spare bits of an assigned codeword to replace an error bit in the codeword. The flag may indicate a change in the spare bit assignment (e.g., spare bits assigned to new error bits in a codeword during media scrubber operations) associated with a codeword held in an MSR group (e.g., MSR region 345 or MSR stripe 345) that includes the corresponding MSR holding the codeword. The flag may be part of a memory array (e.g., SRAM memory cells) in the port manager.

[0086] In some cases, a codeword may be configured to support channel replacement. Channel replacement may refer to replacing one bar (e.g., bar 430-a or bar 430-b) with another bar (e.g., bar 430-k) within a codeword. A bar may be referred to as a section, sub-section, portion, element, etc. Thus, channel replacement may refer to a replacement in the die width 415, rather than in the die depth 425. Additionally, when one of the channels in a codeword contains a number of error bits (e.g., MSRs corresponding to the number of error bits) each meeting a first threshold (e.g., a bit-level replacement threshold), one of the channels 440-a to 440-j in the codeword may be replaced by channel 440-k in the codeword. If there is more than one such channel in the codeword, the port manager may determine to replace the worst channel (e.g., the channel containing the largest number of error bits meeting the bit-level replacement threshold).

[0087] In some cases, a controller (e.g., the controller 120 or port manager 260-a described with reference to Figure 1 and 2 may read a codeword from a memory medium (e.g., memory medium 130-a or memory medium 295-a) that includes a plurality of MSRs. The codeword may include a set of bit fields indicating a plurality of channels (e.g., channels 291-a to 291-k, channels 310-a to 310-k, or channels 440-a to 440-k described with reference to Figures 2 to 4 associated with the memory medium.

[0088] At least some (if not all) of the bit fields in the set may correspond to respective MSRs among the plurality of MSRs that may be associated with a counter. The controller may, based on reading the codeword, identify a channel among the plurality of channels (e.g., with reference to Figure 3 and 4a first quantity of counters associated with one of the described channels 310-a to 310-j or one of the channels 440-a to 440-j, where each of the first quantity of counters may have a value equal to or greater than a first threshold (e.g., a bit-level replacement threshold). The controller may determine that the first quantity is equal to or greater than a second threshold (e.g., a channel-level replacement threshold). In some cases, based on determining that the first quantity (e.g., the number of bit fields meeting the bit-level replacement threshold) is equal to or greater than the second threshold (e.g., the channel-level replacement threshold), the controller may assign a spare channel for the channel in the plurality of channels to the codeword (e.g., refer to Figure 3 and 4 the described channel 310-k or channel 440-k).

[0089] In some cases, the controller may use error control operations based on the size of one or more of the plurality of MSRs to identify the number of error bits and set (e.g., initially set, update) the value of the counter associated with the respective MSR corresponding to the number of error bits, such that based on setting (e.g., initially setting, updating) the value of the counter, the first quantity of counters associated with the channels in the plurality can be identified. In some cases, based on the assigned spare channel for the codeword, the controller may write an indication of the assigned spare channel for the channel in the plurality of channels to the memory array (e.g., SRAM cells) of the controller. In some cases, based on the assigned spare channel for the codeword, the controller may set a flag associated with the controller. The flag may indicate a change in the assigned spare channel associated with the codeword held in the memory medium. In some cases, the first threshold (e.g., the bit-level replacement threshold) may correspond to a configurable (e.g., programmable) value associated with assigning spare bits of the codeword to a set of bit fields. In some cases, the second threshold (e.g., the channel-level replacement threshold) may correspond to a second quantity of bit fields within the channel in the plurality of channels, where each of the second quantity of bit fields is associated with a respective counter having a value equal to or greater than the first threshold (e.g., the bit-level replacement threshold).

[0090] In some cases, the controller may perform one or more background operations for a set of codewords held in the memory medium in a manner independent of access operations from the host, such as reading the codewords, identifying the number of error bits in the codewords, updating the counters associated with the respective MSRs corresponding to the number of error bits in the codewords, determining the value of the counters relative to a threshold (e.g., the bit-level replacement threshold), assigning spare bits of the codeword to the error bits, writing an indication of the assigned spare bits to the memory array (e.g., SRAM cells), or setting a flag to indicate a change in the spare assignment in the MSR stripe after assigning new spare bits within the assigned MSR stripe, or any combination thereof.

[0091] The set of codewords may include at least some (if not all) of the codewords maintained in a memory medium, and the controller may perform background operations on all of the codewords one codeword at a time (e.g., sequentially). In some cases, the set of codewords may include all of the codewords maintained in an MSR group (e.g., MSR stripe 345 or MSR region 345) that includes a respective MSR of the codewords. Additionally, the controller may repeat the background operation for all of the codewords maintained in the memory medium (or MSR group), which may include periodically performing the background operation on one or more of the codewords in the memory medium (or MSR group). In some cases, the background operation may be referred to as a media scrubber operation (which may also be referred to as a media scrubbing function).

[0092] Figure 5 FIG. 500 is a block diagram showing a controller 515 that supports spare replacement in a memory system in accordance with aspects disclosed herein. The controller 515 may be an example of aspects of the controller 120 or controller 230 described with reference Figures 1 to 2 above. The controller 515 may include a biasing component 520, a timing component 525, an access manager 530, a codeword manager 535, and an error control manager 540. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0093] The access manager 530 may receive a first portion of a codeword from a memory medium, the codeword including a set of bit fields indicating a plurality of data bursts across a plurality of channels. In some cases, the access manager 530 may receive a second portion of the codeword based on determining a set of bit fields to be replaced by spare bits.

[0094] In some cases, the access manager 530 may read a codeword from a memory medium that includes a set of minimum substitution regions (MSRs), the codeword including a plurality of bits each corresponding to a respective MSR of the set. In some cases, as part of a background operation independent of an access command from a host, the access manager 530 may retrieve a codeword, where the number of error bits identified may be based on the retrieved codeword. In some cases, the access manager 530 may retrieve a plurality of codewords from an MSR subset that includes respective MSRs by sequentially retrieving each codeword, where the number of error bits identified is based on sequentially retrieving each codeword.

[0095] In some cases, the access manager 530 may read a codeword from a memory medium that includes a plurality of minimum substitution regions (MSRs), the codeword including a set of bit fields indicating a plurality of channels associated with the memory medium, where each bit field of the set may correspond to a respective MSR of a plurality of MSRs associated with a counter.

[0096] The codeword manager 535 can identify spare bits in the first part of the received codeword to replace a set of bit fields based on the first part of the received codeword. In some cases, the first part of the codeword can correspond to an initial data burst among a plurality of data bursts, and the second part of the codeword can correspond to one or more additional data bursts that are temporally after the initial data burst among the plurality of data bursts.

[0097] The error control manager 540 can determine a set of bit fields to be replaced by the spare bits based on identifying the spare bits. In some cases, the error control manager 540 can replace the set of bit fields in the second part of the codeword with the spare bits simultaneously with receiving the second part of the codeword. In some cases, the error control manager 540 can perform error control operations for the codeword based on replacing the set of bit fields in the second part of the codeword with the spare bits. In some cases, the error control manager 540 can access a memory array of the port manager, and the memory array is configured to hold an indication of the spare bit assignment for the set of bit fields of the codeword, wherein determining the set of bit fields in the second part of the codeword to be replaced by the spare bits can be based on accessing the memory array.

[0098] In some cases, the size of the memory array for holding the indication of the spare bit assignment can be based on the identification of the channels among a plurality of channels, the number of spare bits in the codeword, the identification of the minimum substitution region (MSR) of the number of MSRs associated with the codeword, the number of bits associated with the forwarded codeword in the memory medium, the error correction capability of the indication for the spare bit assignment, the number of memory dies corresponding to the channels among the plurality of channels, the number of MSRs in the number of memory dies, or a bit indicating a change in the spare bit assignment, or any combination thereof.

[0099] In some cases, replacing the set of bit fields in the second part of the codeword with the spare bits can additionally include replacing the set of bit fields with the spare bits using a combination of hierarchical logic gates configured based on a plurality of channels based on receiving the second part of the codeword. In some cases, replacing the set of bit fields in the second part of the codeword with the spare bits can additionally include replacing the set of bit fields with the spare bits using a combination of hierarchical logic gates configured based on the number of bit fields of the set corresponding to the data bursts among a plurality of data bursts based on receiving the second part of the codeword.

[0100] In some cases, the error control manager 540 may identify the number of error bits in a codeword using error control operations that may be based on the size of one or more MSRs of a set. In some cases, the error control manager 540 may set the value of a counter associated with the set of MSRs based on identifying the number of error bits in the codeword, where the set of MSRs corresponds to the number of error bits. In some cases, the error control manager 540 may determine the value of the counter relative to a threshold based on the value of the counter. In some cases, the error control manager 540 may assign spare bits of the codeword to the number of error bits based on the value of the counter relative to the threshold.

[0101] In some cases, the error control manager 540 may replace the number of error bits with spare bits of the codeword based on assigning the spare bits of the codeword. In some cases, the error control manager 540 may write an indication of the assignment of spare bits for the number of error bits to a memory array of the port manager based on assigning the spare bits of the codeword, where the memory array is configured to store a plurality of such indications associated with a plurality of spare bits in the codeword. In some cases, the error control manager 540 may configure the threshold to the raw bit error rate (RBER) associated with the memory medium based on identifying the number of error bits in the codeword. In some cases, the error control manager 540 may configure the threshold to the size of the set of MSRs based on identifying the number of error bits in the codeword. In some cases, the error control manager 540 may set a flag associated with the port manager based on assigning the spare bits of the codeword, where the flag indicates a change in the assignment of spare bits associated with a codeword held in a subset of MSRs that includes the corresponding MSR. In some cases, the subset of MSRs may include a plurality of codewords.

[0102] In some cases, the error control manager 540 may identify a first number of counters associated with a channel among a plurality of channels based on reading the codeword, where each of the first number of counters has a value equal to or greater than a first threshold. In some cases, the error control manager 540 may determine that the first number is equal to or greater than a second threshold based on identifying the first number of counters. In some cases, the error control manager 540 may assign a spare channel of the codeword to the channel among the plurality of channels based on determining that the first number is equal to or greater than the second threshold.

[0103] In some cases, the error control manager 540 may use an error control operation that may be based on the size of one or more of the multiple MSRs to identify the number of error bits. In some cases, the error control manager 540 may, based on identifying the number of error bits, set the value of a counter associated with a respective MSR corresponding to the number of error bits, wherein a counter identifying a first number associated with a channel among multiple channels may be based on setting the value of the counter. In some cases, the error control manager 540 may write an indication of an alternate channel assignment for a channel among multiple channels to a memory array of the port manager, based on an alternate channel of an assigned codeword. In some cases, the error control manager 540 may set a flag associated with the port manager based on an alternate channel of an assigned codeword, the flag indicating a change in an alternate channel assignment associated with a codeword held in a memory medium.

[0104] In some cases, a first threshold may correspond to a configurable value associated with assigning alternate bits of a codeword to a set of bit fields. In some cases, a second threshold may correspond to a second number of bit fields within a channel among multiple channels, each of the second number of bit fields being associated with a respective counter having a value equal to or greater than the first threshold.

[0105] Figure 6 A flowchart illustrating a method 600 for supporting alternate replacement in a memory system in accordance with aspects disclosed herein is shown. Operations of method 600 may be implemented by a controller or its components as described with reference to Figures 1 to 2 For example, operations of method 600 may be performed by a controller 120 or a controller 230 as described with reference to Figures 1 to 2 In some instances, controller 230 may execute a set of codes to control functional elements of a device to perform the functions described below. Additionally or alternatively, controller 230 may use dedicated hardware to perform aspects of the functions described below.

[0106] At 605, controller 230 may receive a first portion of a codeword from a memory medium, the codeword including a set of bit fields indicating multiple data bursts across multiple channels. Operation 605 may be performed according to a method as described with reference to Figures 1 - 5 In certain instances, aspects of operation 605 may be performed by an access manager as described with reference to Figure 5 For example, operations of method 600 may be performed by a controller 120 or a controller 230 as described with reference to

[0107] At 610, controller 230 may identify alternate bits in the first portion of the codeword to replace a set of bit fields, based on receiving the first portion of the codeword. Operation 610 may be performed according to a method as described with reference to Figures 1 - 5 In certain instances, aspects of operation 610 may be performed by a codeword manager as described with reference to Figure 5 For example, operations of method 600 may be performed by a controller 120 or a controller 230 as described with reference to

[0108] At 615, the controller 230 can determine a bit field of a set to be replaced by the spare bits based on identifying the spare bits. The operation at 615 can be performed according to the method described in the reference Figures 1 - 5 The operation at 615 can be performed according to the method described in the reference Figure 5 Aspects of the operation at 615 can be performed by the error control manager described in the reference

[0109] At 620, the controller 230 can receive a second part of the codeword based on determining the bit field of the set to be replaced by the spare bits. The operation at 620 can be performed according to the method described in the reference Figures 1 - 5 The operation at 620 can be performed according to the method described in the reference Figure 5 Aspects of the operation at 620 can be performed by the access manager described in the reference

[0110] At 625, the controller 230 can replace the bit field of the set in the second part of the codeword with the spare bits simultaneously with receiving the second part of the codeword. The operation at 625 can be performed according to the method described in the reference Figures 1 - 5 The operation at 625 can be performed according to the method described in the reference Figure 5 Aspects of the operation at 625 can be performed by the error control manager described in the reference

[0111] Describes an apparatus for performing one or more methods such as method 600. The apparatus can include means for receiving a first part of a codeword from a memory medium, the codeword including a set of bit fields indicating multiple data bursts across multiple channels; means for identifying spare bits in the first part of the codeword based on receiving the first part of the codeword to replace the set of bit fields; means for determining a bit field of the set to be replaced by the spare bits based on identifying the spare bits; means for receiving a second part of the codeword based on determining the bit field of the set to be replaced by the spare bits; and means for replacing the bit field of the set in the second part of the codeword with the spare bits simultaneously with receiving the second part of the codeword.

[0112] Describes another apparatus for performing one or more methods such as method 600. The apparatus can include a memory medium and a controller in electronic communication with the memory medium, wherein the controller can be operable to receive a first part of a codeword from the memory medium, the codeword including a set of bit fields indicating multiple data bursts across multiple channels; identify spare bits in the first part of the codeword based on receiving the first part of the codeword to replace the set of bit fields; determine a bit field of the set to be replaced by the spare bits based on identifying the spare bits; receive a second part of the codeword based on determining the bit field of the set to be replaced by the spare bits; and replace the bit field of the set in the second part of the codeword with the spare bits simultaneously with receiving the second part of the codeword.

[0113] Some examples of the method 600 and apparatus described herein may additionally include a process, feature, apparatus, or instruction for performing error control operations for a codeword based on replacing a set of bit fields in a second portion with spare bits. Some examples of the method 600 and apparatus described herein may additionally include a process, feature, apparatus, or instruction for accessing a memory array of a port manager, the memory array being configured to hold an indication of spare bit assignments for a set of bit fields of a codeword, wherein determining the set of bit fields in the second portion of the codeword to be replaced with spare bits may be based on accessing the memory array.

[0114] In some examples of the method 600 and apparatus described herein, the size of the memory array for holding an indication of spare bit assignments may be based on the identification of a channel among a plurality of channels, the number of spare bits in a codeword, the identification of a minimum substitution region (MSR) of the number of MSRs associated with the codeword, the number of bits associated with a forwarded codeword in a memory medium, the error correction capability for an indication of spare bit assignments, the number of memory dies corresponding to a channel among a plurality of channels, the number of MSR groups in the number of memory dies, or a bit indicating a change in spare bit assignments, or any combination thereof.

[0115] In some examples of the method 600 and apparatus described herein, replacing a set of bit fields in a second portion of a codeword with spare bits may additionally include replacing the set of bit fields with spare bits using a combination of hierarchical logic gates configured based on the number of bit fields corresponding to a set of data bursts among a plurality of data bursts, based on receiving the second portion of the codeword. In some examples of the method 600 and apparatus described herein, a first portion of a codeword may correspond to an initial data burst among a plurality of data bursts, and a second portion of the codeword may correspond to one or more additional data bursts among a plurality of data bursts that are temporally after the initial data burst among the plurality of data bursts.

[0116] Figure 7 A flowchart illustrating a method 700 for supporting spare substitution in a memory system in accordance with aspects disclosed herein is shown. Operations of method 700 may be implemented by a controller or components thereof described with reference to Figures 1 to 2 For example, operations of method 700 may be performed by a controller 120 or a controller 230 described with reference to Figures 1 to 2 In some examples, controller 230 may execute a set of codes to control functional elements of a device to perform the functions described below. Additionally or alternatively, controller 230 may use dedicated hardware to perform aspects of the functions described below.

[0117] At 705, the controller 230 may read codewords from a memory medium that includes a set of minimum substitution regions (MSRs), the codewords including a plurality of bits each corresponding to a respective MSR of the set. The operation of 705 may be performed according to the method described in reference Figures 1 - 5 In some instances, aspects of the operation of 705 may be performed by an access manager described in reference Figure 5

[0118] At 710, the controller 230 may identify the number of error bits in the codewords using an error control operation that may be based on the size of one or more MSRs of the set. The operation of 710 may be performed according to the method described in reference Figures 1 - 5 In some instances, aspects of the operation of 710 may be performed by an error control manager described in reference Figure 5

[0119] At 715, the controller 230 may set the value of a counter associated with the MSRs of the set that corresponds to the number of error bits, based on identifying the number of error bits in the codewords. The operation of 715 may be performed according to the method described in reference Figures 1 - 5 In some instances, aspects of the operation of 715 may be performed by an error control manager described in reference Figure 5

[0120] At 720, the controller 230 may determine the value of the counter relative to a threshold, based on the value of the counter. The operation of 720 may be performed according to the method described in reference Figures 1 - 5 In some instances, aspects of the operation of 720 may be performed by an error control manager described in reference Figure 5

[0121] At 725, the controller 230 may assign spare bits of the codewords to the number of error bits, based on the value of the counter relative to the threshold. The operation of 725 may be performed according to the method described in reference Figures 1 - 5 In some instances, aspects of the operation of 725 may be performed by an error control manager described in reference Figure 5

[0122] ​​​​​Describe an apparatus for performing one or more methods such as method 700. The apparatus may include means for reading a codeword from a memory medium comprising a set of minimum substitution regions (MSRs), the codeword comprising a plurality of bits each corresponding to a respective MSR of the set; means for identifying the number of error bits in the codeword using an error control operation that may be based on the size of one or more MSRs of the set; means for setting the value of a counter associated with the MSRs of the set, the MSRs of the set corresponding to the number of error bits, based on identifying the number of error bits in the codeword; means for determining the value of the counter relative to a threshold based on the value of the counter; and means for assigning spare bits of the codeword to the number of error bits based on the value of the counter relative to the threshold.

[0123] Describe another apparatus for performing one or more methods such as method 700. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, wherein the controller may be operable to read a codeword from a memory medium comprising a set of minimum substitution regions (MSRs), the codeword comprising a plurality of bits each corresponding to a respective MSR of the set; identify the number of error bits in the codeword using an error control operation that may be based on the size of one or more MSRs of the set; set the value of a counter associated with the MSRs of the set, the MSRs of the set corresponding to the number of error bits, based on identifying the number of error bits in the codeword; determine the value of the counter relative to a threshold based on the value of the counter; and assign spare bits of the codeword to the number of error bits based on the value of the counter relative to the threshold.

[0124] Some examples of method 700 and the apparatus described herein may further include a process, feature, means, or instruction for: replacing the number of error bits with spare bits of the codeword based on assigning the spare bits of the codeword. Some examples of method 700 and the apparatus described herein may further include a process, feature, means, or instruction for: writing an indication of the assignment of the spare bits for the number of error bits to a memory array of a port manager, the memory array being configured to store a plurality of such indications associated with a plurality of spare bits in the codeword, based on assigning the spare bits of the codeword. Some examples of method 700 and the apparatus described herein may further include a process, feature, means, or instruction for: configuring a threshold to an original bit error rate (RBER) associated with the memory medium based on identifying the number of error bits in the codeword.

[0125] Some examples of the method 700 and apparatus described herein may additionally include processes, features, devices, or instructions for: configuring a threshold to a size of a set of MSRs based on identifying a number of error bits in a codeword. Some examples of the method 700 and apparatus described herein may additionally include processes, features, devices, or instructions for: setting a flag associated with a port manager based on spare bits of an assigned codeword, the flag indicating a change in spare bit assignment associated with a codeword held in a subset of MSRs that includes a corresponding MSR. In some examples of the method 700 and apparatus described herein, the subset of MSRs may include multiple codewords.

[0126] In some examples of the method 700 and apparatus described herein, reading a codeword from the memory medium may additionally include retrieving the codeword as part of a background operation independent of an access command from a host, wherein identifying the number of error bits may be based on retrieving the codeword. In some examples of the method 700 and apparatus described herein, reading a codeword from the memory medium may additionally include retrieving multiple codewords from a subset of MSRs that includes a corresponding MSR by sequentially retrieving each codeword, wherein identifying the number of error bits may be based on sequentially retrieving each codeword.

[0127] Figure 8 A flowchart illustrating a method 800 that supports spare substitution in a memory system in accordance with aspects disclosed herein. Operations of method 800 may be implemented by a controller or components thereof as described with reference to Figures 1 to 2 described. For example, operations of method 800 may be performed by controller 120 or controller 230 as described with reference to Figures 1 to 2 described. In some examples, controller 230 may execute a set of codes to control functional elements of a device to perform the functions described below. Additionally or alternatively, controller 230 may use dedicated hardware to perform aspects of the functions described below.

[0128] At 805, controller 230 may read a codeword from a memory medium that includes a plurality of minimum substitution regions (MSRs), the codeword including a set of bit fields that indicate a plurality of channels associated with the memory medium, wherein each bit field of the set may correspond to a respective MSR of the plurality of MSRs associated with a counter. Operation 805 may be performed in accordance with a method as described with reference to Figures 1 - 5 described. In certain examples, aspects of operation 805 may be performed by an access manager as described with reference to Figure 5 described.

[0129] At 810, controller 230 may identify a first number of counters associated with a channel among the plurality of channels, the first number of counters each having a value equal to or greater than a first threshold, based on reading the codeword. Operation 810 may be performed in accordance with a method as described with reference to Figures 1 - 5The method described performs an operation of 810. In some instances, aspects of the operation of 810 may be performed by an error control manager referenced Figure 5 as described.

[0130] At 815, the controller 230 may determine that the first quantity is equal to or greater than a second threshold based on identifying a first quantity of counters. The operation of 815 may be performed according to a method referenced Figures 1 - 5 as described. In some instances, aspects of the operation of 815 may be performed by an error control manager referenced Figure 5 as described.

[0131] At 820, the controller 230 may assign a spare channel of a codeword to a channel among a plurality of channels based on determining that the first quantity is equal to or greater than the second threshold. The operation of 820 may be performed according to a method referenced Figures 1 - 5 as described. In some instances, aspects of the operation of 820 may be performed by an error control manager referenced Figure 5 as described.

[0132] Describes an apparatus for performing one or more methods such as method 800. The apparatus may include means for reading a codeword from a memory medium of a plurality of minimum substitution regions (MSRs), the codeword including a set of bit fields indicating a plurality of channels associated with the memory medium, wherein each bit field of the set may correspond to a respective MSR among the plurality of MSRs associated with a counter; means for identifying, based on reading the codeword, a first quantity of counters associated with a channel among the plurality of channels, each of the first quantity of counters having a value equal to or greater than a first threshold; means for determining that the first quantity is equal to or greater than a second threshold based on identifying the first quantity of counters; and means for assigning a spare channel of the codeword to a channel among the plurality of channels based on determining that the first quantity is equal to or greater than the second threshold.

[0133] Describes another apparatus for performing one or more methods such as method 800. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, wherein the controller may be operable to read a codeword from a memory medium including a plurality of minimum substitution regions (MSRs), the codeword including a set of bit fields indicating a plurality of channels associated with the memory medium, wherein each bit field of the set may correspond to a respective MSR among the plurality of MSRs associated with a counter; identify, based on reading the codeword, a first quantity of counters associated with a channel among the plurality of channels, each of the first quantity of counters having a value equal to or greater than a first threshold; determine that the first quantity is equal to or greater than a second threshold based on identifying the first quantity of counters; and assign a spare channel of the codeword to a channel among the plurality of channels based on determining that the first quantity is equal to or greater than the second threshold.

[0134] Some examples of the method 800 and apparatus described herein may additionally include a process, feature, apparatus, or instruction for: identifying the number of error bits using an error control operation that may be based on the size of one or more of the multiple MSRs. Some examples of the method 800 and apparatus described herein may additionally include a process, feature, apparatus, or instruction for: based on identifying the number of error bits, setting the value of a counter associated with a respective MSR corresponding to the number of error bits, wherein identifying a first number of counters associated with a channel among multiple channels may be based on setting the value of the counter.

[0135] Some examples of the method 800 and apparatus described herein may additionally include a process, feature, apparatus, or instruction for: writing an indication of the alternate channel assignment for a channel among multiple channels to a memory array of a port manager based on the alternate channel of the assigned codeword. Some examples of the method 800 and apparatus described herein may additionally include a process, feature, apparatus, or instruction for: setting a flag associated with the port manager based on the alternate channel of the assigned codeword, the flag indicating a change in the alternate channel assignment associated with a codeword held in a memory medium.

[0136] In some examples of the method 800 and apparatus described herein, a first threshold may correspond to a configurable value associated with assigning alternate bits of a codeword to a set of bit fields. In some examples of the method 800 and apparatus described herein, a second threshold may correspond to a second number of bit fields within a channel among multiple channels, each of the second number of bit fields being associated with a respective counter having a value equal to or greater than the first threshold.

[0137] Note that the method descriptions herein depict possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, two or more instances from the methods may be combined.

[0138] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, those of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0139] The terms "electronically communicate" and "coupled" refer to a relationship between components that supports an electronic flow between the components. This can include a direct connection between the components or can include intermediate components. Components that electronically communicate or are coupled to each other may actively exchange electrons or signals (e.g., in a powered circuit) or may not actively exchange electrons or signals (e.g., in a non-powered circuit), but may be configured and operable to exchange electrons or signals immediately after the circuit is powered. By way of example, two components physically connected via a switch (e.g., a transistor) electronically communicate or may be coupled regardless of the state of the switch (i.e., open or closed).

[0140] A chalcogenide material can be a material or alloy that includes at least one of the elements S, Se, and Te. The phase change materials discussed herein can be chalcogenide materials. Chalcogenide materials can include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Exemplary chalcogenide materials and alloys can include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, or Ge-Te-Sn-Pt. As used herein, a hyphenated chemical composition symbol indicates the elements included in a particular compound or alloy and is intended to represent all stoichiometric amounts involving the indicated elements. For example, Ge-Te can include Ge x Te y , where x and y can be any positive integers. Other examples of variable resistance materials can include binary metal oxide materials or mixed valence oxides, including two or more metals, such as transition metals, alkaline earth metals, and / or rare earth metals. The examples are not limited to one or more specific variable resistance materials associated with the memory elements of a memory cell. For example, other examples of variable resistance materials can be used to form memory elements and can include chalcogenide materials, colossal magnetoresistance materials, or polymer-based materials, among others.

[0141] The apparatus discussed herein includes a memory medium 130, which may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemical species including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

[0142] The description set forth herein with reference to the drawings describes exemplary configurations and does not represent all examples that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and does not mean "preferred" or "better than" other examples. For the purpose of providing an understanding of the described technology, the detailed description includes specific details. However, the technology may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0143] In the figures, similar components or features may have the same reference label. Additionally, various components of the same type can be distinguished by following the dashed lines and the reference labels of the second label, which are distinguished among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0144] Any of a variety of different technologies and techniques can be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description herein can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0145] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed by a general-purpose processor, a DSP, an ASIC, a field-programmable gate array (FPGA), or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0146] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination of these. The features implementing the functions can also be physically located in various places, including being distributed such that different parts of the functions are implemented at different physical locations. Further, as used herein (including in the claims), the "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list that includes the endpoints, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope disclosed herein. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0147] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with a laser. Combinations of the above are also included within the scope of computer-readable media.

[0148] The description herein is provided to enable a person having ordinary skill in the art to make or use the present disclosure. Those skilled in the art will readily appreciate various modifications to the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Accordingly, the present disclosure is not limited to the examples and designs described herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system, comprising: One or more processors; And One or more memories, coupled to the one or more processors and including instructions that, when executed by the one or more processors, cause the memory system to: Identify an access command for a memory device; Generate a codeword for the access command, the codeword including a plurality of fields; Group the bits of the codeword into a plurality of groups, wherein the bits of a first field among the plurality of fields are included in at least two of the plurality of groups, and wherein each bit group corresponds to one of a plurality of field arrangements, the plurality of field arrangements including a first field arrangement and a second field arrangement, and wherein the first field arrangement includes a first subset of bits of the first field and at least one subset of bits of a second field, and the second field arrangement includes a second subset of bits of the first field and at least one subset of bits of a third field; And Transmit the plurality of groups to the memory device in a plurality of bursts via a plurality of channels for the access command according to the plurality of field arrangements, wherein a corresponding set of the plurality of groups is transmitted via each of the plurality of channels, and wherein each group in the corresponding set of groups for a channel is transmitted in a corresponding burst among the plurality of bursts.

2. The memory system according to claim 1, wherein the first field arrangement includes one or more control fields and one or more spare fields.

3. The memory system according to claim 1, wherein at least two of the plurality of groups have the same field arrangement among the plurality of field arrangements.

4. The memory system according to claim 1, wherein the plurality of fields includes a plurality of control fields and one or more data fields.

5. The memory system according to claim 4, wherein the instructions for transmitting the plurality of groups include instructions that, when executed by the one or more processors, cause the memory system to transmit the plurality of control fields in a first burst among the plurality of bursts.

6. The memory system according to claim 1, wherein each of the plurality of groups includes 8 bits.

7. The memory system according to claim 1, wherein each of the plurality of groups includes a determined number of the bits.

8. A memory system, comprising: One or more processors; And One or more memories, coupled to the one or more processors and including instructions that, when executed by the one or more processors, cause the memory system to: Identify an access command for a memory device; Generate a codeword for the access command, the codeword including a plurality of fields; Group the bits of the codeword into a plurality of groups, wherein the bits of a first field among the plurality of fields are included in at least two of the plurality of groups and the bits of one or more second fields among the plurality of fields are included in at least one of the plurality of groups, wherein each bit group corresponds to one of a plurality of field arrangements, the plurality of field arrangements including a first field arrangement associated with the at least one group, and including an error control bit set associated with an error control operation for the bits of the first field; And Arrange the plurality of groups to be transmitted to the memory device via a plurality of channels in a plurality of bursts for the access command, wherein each respective set of the plurality of groups is transmitted via a respective one of the plurality of channels, and wherein each group in the respective set of groups for a channel is transmitted in a respective one of the plurality of bursts, wherein at least one group is distributed over more than one of the corresponding sets of groups.

9. The memory system of claim 8, wherein the error control operation includes identifying one or more error bits of the bits of the first field, correcting the one or more error bits, or both.

10. The memory system of claim 9, wherein the set of error control bits includes a set of cyclic redundancy check (CRC) bits for identifying the one or more error bits of the bits of the first field.

11. The memory system of claim 9, wherein the set of error control bits includes a set of bits for performing an exclusive OR (XOR) operation using the one or more error bits of the bits of the first field.

12. The memory system of claim 8, wherein a second field arrangement in the plurality of field arrangements includes one or more control fields and one or more spare fields.

13. The memory system of claim 8, wherein at least two of the plurality of groups have the same field arrangement in the plurality of field arrangements.

14. The memory system of claim 8, wherein the plurality of fields includes a plurality of control fields and one or more data fields.

15. The memory system of claim 14, wherein the instructions for transmitting the plurality of groups include instructions that, when executed by the one or more processors, cause the memory system to transmit the plurality of control fields in a first burst of the plurality of bursts.

16. The memory system of claim 8, wherein each of the plurality of groups includes 8 bits.

17. The memory system of claim 8, wherein each of the plurality of groups includes a determined number of the bits.

18. A method for operating a memory system, comprising: Receiving, via a plurality of channels in a plurality of bursts, a codeword from a memory device based at least in part on an access command, the codeword including a plurality of fields, wherein the bits of the codeword are grouped into a plurality of groups, and bits of a first field of the plurality of fields are included in at least two of the plurality of groups, wherein each of the plurality of groups corresponds to a respective field arrangement in a plurality of field arrangements, the plurality of field arrangements including a first field arrangement and a second field arrangement, wherein the first field arrangement includes a first subset of bits of the first field and at least one subset of bits of a second field, and the second field arrangement includes a second subset of bits of the first field and at least one subset of bits of a third field, wherein the codeword is received via the plurality of channels in the plurality of bursts according to the plurality of field arrangements, and wherein a respective set of the plurality of groups is received via each of the plurality of channels, and wherein each group in the corresponding set of groups for a channel is received in a respective one of the plurality of bursts; and parsing the codewords received in the plurality of bursts via the plurality of channels into the plurality of fields.

19. The method of claim 18, further comprising: reconstructing the codewords comprising the plurality of fields, wherein: receiving the codewords comprises: receiving a first portion of the codewords during a first one of the plurality of bursts; and receiving a second portion of the codewords during a second one of the plurality of bursts; and reconstructing the codewords comprises: replacing a second subset of bits of the second field with a first subset of bits of the first field while receiving the second portion of the codewords.

20. The method of claim 18, wherein: receiving the codewords comprises: receiving a first portion of the codewords during a first one of the plurality of bursts; and receiving a second portion of the codewords during a second one of the plurality of bursts; and parsing the codewords comprises: parsing the first portion of the codewords while receiving the second portion of the codewords.

Images