Detection module applied to processor, processor, equipment and method

Abstract

The invention discloses a detection module applied to a processor, the processor, equipment and a method, and relates to the technical field of chips. The detection module comprises a first detection unit and a register, the register is used for storing a lock table; the first detection unit is used for comparing whether a second storage address carried in a first detection request is overlapped with each first storage address or not according to the received first detection request sent by other processors; the first detection unit is further used for carrying out back pressure on the first detection request when the second storage address and at least one first storage address are overlapped, and when the first detection request is subjected to back pressure, other processors do not have the authority of executing the first atomic instruction pointing to the second storage address. By arranging the detection module in the processor, the mutual exclusion relation between the memory access requests sent by different processors can be judged in the processor, so that a global detector does not need to be arranged, and the chip area is reduced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular, to a detection module, a processor, a device, and a method applied to a processor. Background Art

[0002] In a multi-core CPU (Central Processing Unit) system, there are multi-core synchronization scenarios. For example, multiple CPU cores jointly maintain a storage space, that is, multiple processors access the same storage space. In such a scenario, it is desired that the memory access instructions sent by the processor to the storage space are atomic instructions, so that other processors cannot change the data at the memory access address corresponding to the memory access instruction, thereby ensuring the accuracy of the memory access result.

[0003] In the related art, detectors need to be arranged both inside and outside the processor. Among them, the detector inside the processor (also called the local detector) is used to judge the consistency of the memory access addresses corresponding to the memory access requests inside the processor, so as to maintain the mutual exclusion relationship between different memory access requests inside the processor. The detector outside the processor (also called the global detector) is used to judge the consistency of the memory access addresses corresponding to the memory access requests sent by different processors respectively, so as to maintain the mutual exclusion relationship between the memory access requests corresponding to different processors respectively.

[0004] In the above related art, not only a local detector is required, but also a global detector. When the number of processors in a multi-core CPU system is large, the capacity of the detector also needs to be increased, resulting in a relatively high chip area occupied by the detector. Summary of the Invention

[0005] Embodiments of this application provide a detection module, a processor, a device, and a method applied to a processor. The technical solutions are as follows:

[0006] According to one aspect of the embodiments of this application, a detection module applied to a processor is provided. The detection module includes: a first detection unit and a register;

[0007] The register is used to store a lock table, and the lock table is used to record at least one first storage address locked by the processor;

[0008] The first detection unit is used to compare whether there is an overlap between the second storage address carried in the first detection request and each of the first storage addresses according to the first detection request sent by another processor;

[0009] The first detection unit is further configured to backpressure the first detection request when there is an overlap between the second storage address and at least one of the first storage addresses, wherein when the first detection request is backpressured, the other processors do not have the permission to execute the first atomic instruction pointing to the second storage address.

[0010] According to one aspect of the embodiments of the present application, a processor is provided, and the processor includes the detection module as described above.

[0011] According to one aspect of the embodiments of the present application, a computer device is provided, and the computer device includes a processor, and the processor includes the detection module as described above.

[0012] According to one aspect of the embodiments of the present application, an instruction wake-up method applied to a detection module is provided. The detection module includes: a first detection unit and a register; the method includes:

[0013] The register stores a lock table, and the lock table is used to record at least one first storage address locked by the processor;

[0014] The first detection unit compares whether there is an overlap between the second storage address carried in the first detection request sent by another processor and each of the first storage addresses according to the received first detection request;

[0015] The first detection unit backpressures the first detection request when there is an overlap between the second storage address and at least one of the first storage addresses, wherein when the first detection request is backpressured, the other processors do not have the permission to execute the first atomic instruction pointing to the second storage address.

[0016] The technical solution provided by the embodiments of the present application can bring the following beneficial effects:

[0017] By setting the detection module inside the processor, the detection module includes a first detection unit and a register. The register is used to store a lock table, and the lock table is used to record at least one first storage address locked by the processor. That is, the addresses currently locked by the processor are recorded in the form of a lock table. The first detection unit is used to compare whether the second storage address carried in the detection request sent by other processors overlaps with each first storage address. When the second storage address overlaps with at least one first storage address, backpressure is applied to the first detection request. If the first detection request is backpressured, it indicates that the second storage address is currently locked by the processor, so other processors cannot execute atomic instructions pointing to the second storage address. In the embodiments of the present application, by setting the detection module in the processor, the mutual exclusion relationship between memory access requests sent by different processors can be determined inside the processor, thus eliminating the need to layout a global detector and reducing the chip area. Description of the Drawings

[0018] Figure 1 is a schematic diagram of non-atomic access to a public variable provided by the related art;

[0019] Figure 2 is a schematic diagram of the multi-core CPU system structure provided by the related art;

[0020] Figure 3 is a schematic diagram of the structure of a detection module applied to a processor provided by an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of the structure of a detection module applied to a processor provided by another embodiment of the present application;

[0022] Figure 5 is a schematic diagram of multi-core synchronization provided by an embodiment of the present application;

[0023] Figure 6 is a schematic diagram of SC (Store Conditional) failure provided by an embodiment of the present application;

[0024] Figure 7 is a schematic diagram of SC success provided by an embodiment of the present application;

[0025] Figure 8 is a flowchart of a detection method applied to a detection module provided by an embodiment of the present application. Detailed Embodiments

[0026] To make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the drawings.

[0027] Before introducing the technical solution of this application, some background technical knowledge related to this application will be introduced and explained. The following related technologies can be arbitrarily combined with the technical solution of the embodiments of this application as optional solutions, and they all fall within the protection scope of the embodiments of this application. The embodiments of this application include at least some of the following contents.

[0028] Artificial intelligence is to use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, a theory, method, technology, and application system that can perceive the environment, acquire knowledge, and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science. It attempts to understand the essence of intelligence and produce a new intelligent machine that can react in a way similar to human intelligence. Artificial intelligence also studies the design principles and implementation methods of various intelligent machines, enabling the machines to have the functions of perception, reasoning, and decision-making.

[0029] Artificial intelligence technology is an interdisciplinary subject, involving a wide range of fields, including both hardware-level technologies and software-level technologies. The basic technologies of artificial intelligence generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-trained model technology, operation / interaction systems, mechatronics, etc. Among them, the pre-trained model, also known as the large model or the foundation model, can be widely applied to downstream tasks in various major directions of artificial intelligence after fine-tuning. The software technologies of artificial intelligence mainly include several major directions such as computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0030] With the research and progress of artificial intelligence technology, artificial intelligence technology has been studied and applied in multiple fields. For example, common ones include smart home, smart wearable devices, virtual assistants, smart speakers, smart marketing, driverless, autonomous driving, drones, digital twins, virtual humans, robots, artificial intelligence generated content (AIGC), conversational interaction, intelligent healthcare, intelligent customer service, game AI (artificial intelligence), virtual reality (VR), augmented reality (AR), etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0031] The technical solution of this application mainly relates to the development and design of AI processors in the field of artificial intelligence technology, and mainly relates to a detection module applied to a processor. The computer device where the detection module is located includes but is not limited to mobile phones, computers, intelligent voice interaction devices, smart home appliances, vehicle terminal devices, aircraft, etc. The embodiments of this application can be applied to various scenarios, including but not limited to cloud technology, artificial intelligence, intelligent transportation, assisted driving, etc.

[0032] First, an exemplary description of the background technology related to atomic instructions will be given below.

[0033] In a multi-core CPU system, there are multi-core synchronization scenarios. For example, multiple CPU cores jointly maintain a storage space. Exemplarily, assume that there is a variable X in the common storage space, which represents the quantity of a certain resource. Multiple CPUs need to read this variable and subtract 1 from X after completing a certain task.

[0034] If ordinary load store (load and store) instructions are used to access the X variable, there will be synchronization problems, such as Figure 1 The 100 in is a non-atomic access to a common variable. Assume that the initial value of X is 5. Core0 accesses X through the load instruction and reads the value 5. After subtracting 1, it writes back to the original address, and X becomes 4. Before core0 writes X back, core1 reads X through the load instruction. At this time, the value read is still 5. After subtracting 1 and writing X, the final value of X is 4. Here, a problem occurs: after two subtraction operations, the value of X is 4, which obviously does not conform to the semantics of the program.

[0035] The reason for this problem is that the operations between the load (load) and store (store) instructions are not atomic. If an instruction is designed such that all operations between reading and writing are atomic operations, that is, other processors or threads are not allowed to change the value of this address, this problem can be solved. The LRSC instruction is introduced in RISC-V to implement atomic operations.

[0036] The LR (Load Reserved) instruction is a load reserved. After core0 executes LR, the system will record the address accessed by LR as the locked state of core0. The SC instruction is a conditional store. When core0 executes SC, the system will detect whether the current address is locked by core0. If so, the data is successfully written to this address; otherwise, the SC instruction fails and returns a failure flag. If other cores perform write operations on this address during the period when core0 locks this address, the lock information of core0 will be cleared, and the subsequent SC instruction of core0 will fail.

[0037] Therefore, it can be seen that the LRSC instruction requires the storage system to add a monitor to mark the access to the LRSC instruction.

[0038] In the related art, such as Figure 2 200 is a multi-core CPU system architecture. There is a local monitor inside each CPU for detecting the mutual exclusion relationship between instructions inside the CPU, and a global monitor is between multiple CPUs for detecting the mutual exclusion relationship between multiple CPUs. The CPUs are connected through the AXI (Advanced eXtensible Interface) bus.

[0039] In the related art, the detection of the mutual exclusion relationship inside and between CPUs can be completed, but monitors need to be placed at multiple positions. As the number of CPU cores increases, the capacity of the monitors also needs to increase, and the chip area occupied by them will increase accordingly.

[0040] Based on this, the embodiments of the present application maintain the mutual exclusion relationship inside and between CPUs in the form of a lock table inside the CPU. For the execution of instructions inside the CPU, the lock table needs to be queried and the status of the lock table needs to be updated. For the probe operation (detection request) between CPUs, the lock table also needs to be queried. If it is found through the query that there is an address lock, the probe (detection) request is back-pressured. In this way, the detection of the mutual exclusion relationship between multiple cores can be achieved only inside the CPU without introducing a global monitor, and the chip area consumed is greatly reduced.

[0041] Please refer to Figure 3 , which shows a schematic structural diagram of a detection module applied to a processor provided by an embodiment of the present application. The detection module can be a unit with a pure hardware structure, and it can be set on the chip of the processor. The detection module 300 includes: a first detection unit 310 and a register 320.

[0042] Before introducing the detection module proposed by the embodiments of the present application, an exemplary description is first made of the application environment of the detection module. The application environment of the detection module is a multi-core CPU system, that is, there are multiple processors jointly maintaining a storage space. The multi-core CPU system includes at least two processors and a common storage space. A detection module is arranged on the chip of each processor.

[0043] In some embodiments, the register 320 is used to store a lock table, and the lock table is used to record at least one first storage address locked by the processor.

[0044] Exemplarily, the lock table includes at least one entry. Each entry stores a first storage address. Exemplarily, if the processor is currently accessing memory at address A and wishes to lock address A, then address A is used as the first storage address and stored in the lock table. Exemplarily, if the processor is not accessing an address that needs to be locked, the content in the lock table is empty or the content in the lock table is invalid.

[0045] Exemplarily, if the current processor is executing a reserved load instruction for address B, then address B is saved in the lock table, and address B is considered the address locked by the current processor.

[0046] In some embodiments, the first detection unit 310 is configured to compare whether the second storage address carried in the first detection request received from another processor overlaps with each first storage address.

[0047] Exemplarily, the second storage address carried in the first detection request is compared with each first storage address respectively. When at least one first storage address overlaps with the second storage address, it is considered that the second storage address carried in the first detection request overlaps with each first storage address.

[0048] Exemplarily, the second storage address carried in the first detection request is compared with each first storage address respectively. When each first storage address does not overlap with the second storage address, it is considered that the second storage address carried in the first detection request does not overlap with the first storage addresses in the lock table.

[0049] Exemplarily, the first detection unit is configured to stop comparing as long as it detects that one first storage address overlaps with the second storage address. Exemplarily, the comparison method applied to the first detection unit can reduce the comparison overhead and improve the comparison efficiency.

[0050] Exemplarily, the first storage address locked in the lock table can be considered as the address that the current processor is currently accessing, or the address pointed to by the atomic instruction that the current processor is currently executing. Exemplarily, the first detection unit is configured to detect the mutual exclusion relationship between the memory access requests corresponding to different processors. Exemplarily, the first detection unit is configured to detect the mutual exclusion relationship between the atomic instructions corresponding to different processors. The mutual exclusion relationship here can be understood as whether they point to the same storage address.

[0051] Exemplarily, there are multiple processors in the multi-core CPU system, such as processor 1, processor 2, processor 3... processor N, where N is a positive integer greater than or equal to 2.

[0052] In some embodiments, when processor n (where n is a positive integer not greater than N) wants to execute an atomic instruction pointing to a second storage address, processor n first sends a first detection request to each of the other processors except processor n, and the second storage address is carried in the first detection request. If processor 1 receives the first detection request sent by processor n, the first detection unit in processor 1 is used to compare whether there is an overlap between the second storage address carried in the first detection request and the first storage address locked by the lock table in processor 1. If there is an overlap, the first detection request is back-pressured. If there is no overlap, the first detection request is not back-pressured. When none of the first detection requests sent by processor n to other processors are back-pressured, it means that none of the other processors have locked the second storage address, that is, when the second storage address is currently not accessed by any processor, then processor n has the permission to execute the atomic instruction pointing to the second storage address and can execute the atomic instruction pointing to the second storage address. When at least one of the first detection requests sent by processor n to other processors is back-pressured, it means that at least one of the other processors has locked the second storage address, that is, when the second storage address is currently accessed by some processor, then processor n does not have the permission to execute the atomic instruction pointing to the second storage address, and processor n cannot execute the atomic instruction pointing to the second storage address. Of course, when processor n is not allowed to execute the atomic instruction pointing to the second storage address, it can continuously send first detection requests to other processors until none of the first detection requests are back-pressured.

[0053] In some other embodiments, in addition to multiple processors, the multi-core CPU system further includes a buffer, which is respectively connected to each processor. When processor n (where n is a positive integer not greater than N) wants to execute an atomic instruction pointing to a second storage address, processor n first sends an inquiry instruction to the buffer. The inquiry instruction is used to loop through the buffer to check whether processor n has the permission to execute the atomic instruction pointing to the second storage address. The second storage address is carried in the inquiry instruction. In the case of receiving the inquiry instruction sent by processor n, the buffer is used to send a first detection request to each of the other processors except processor n. The second storage address is carried in the first detection request. If processor 1 receives the first detection request sent by the buffer, the first detection unit in processor 1 is used to compare whether the second storage address carried in the first detection request overlaps with the first storage address locked by the lock table in processor 1. If there is an overlap, the first detection request is back-pressured. If there is no overlap, the first detection request is not back-pressured. When none of the first detection requests sent by the buffer to other processors are back-pressured, it means that none of the other processors lock the second storage address. That is, when the second storage address is currently not accessed by any processor, processor n has the permission to execute the atomic instruction pointing to the second storage address. At this time, the buffer is further used to send a permission instruction to processor n. The permission instruction is used to inform processor n that it has the permission to execute the atomic instruction pointing to the second storage address. After receiving the permission instruction, processor n can execute the atomic instruction pointing to the second storage address. When at least one of the first detection requests sent by the buffer to other processors is back-pressured, it means that at least one of the other processors locks the second storage address. That is, when the second storage address is currently accessed by a processor, processor n does not have the permission to execute the atomic instruction pointing to the second storage address. At this time, the buffer is further used to send a prohibition instruction to processor n. The prohibition instruction is used to inform processor n that it does not have the permission to execute the atomic instruction pointing to the second storage address. After receiving the prohibition instruction, processor n cannot execute the atomic instruction pointing to the second storage address. Of course, when processor n is not allowed to execute the atomic instruction pointing to the second storage address, it can continuously send inquiry instructions to the buffer until it receives the permission instruction returned by the buffer. Exemplarily, the buffer is a secondary buffer (L2 buffer).

[0054] In some embodiments, the first detection unit 310 is further used to back-pressure the first detection request when the second storage address overlaps with at least one first storage address. When the first detection request is back-pressured, other processors do not have the permission to execute the first atomic instruction pointing to the second storage address.

[0055] Exemplarily, when there is an overlap between the second storage address and at least one first storage address, it is considered that the memory access requests of other processors and the memory access requests of the current processor are mutually exclusive, and then the detection requests of other processors are back-pressured. The embodiments of the present application do not limit the duration for which the first detection unit back-pressures the first detection request. Exemplarily, when there is an overlap between the second storage address and at least one first storage address, it is considered that the memory access requests of other processors and the memory access requests of the current processor are mutually exclusive, and then the detection requests of other processors are back-pressured for 5 seconds.

[0056] In some embodiments, the first detection unit 310 is further configured to not back-pressure the first detection request when there is no overlap between the second storage address and each first storage address. When the first detection request is not back-pressured, other processors have the permission to execute the first atomic instruction pointing to the second storage address.

[0057] Exemplarily, when the second storage address does not overlap with each first storage address, it is considered that the memory access requests of other processors and the memory access requests of the current processor are not mutually exclusive, and then the detection requests of other processors are not back-pressured. In some embodiments, not back-pressuring the detection requests of other processors may also be considered as confirming the reception of the first detection request and returning an instruction indicating successful reception.

[0058] Exemplarily, an atomic instruction is also called an atomic operation, which means one or a series of instructions or operations that cannot be interrupted. For example, when the atomic instruction is a store operation for address a, when executing this atomic instruction, other instructions cannot interrupt this atomic instruction or perform a memory access operation on address a. Generally speaking, in the related art, to implement such an atomic instruction, usually not only a local detector but also a global detector are required. However, in the present application, such an atomic instruction is implemented by introducing a detection module in the processor.

[0059] Exemplarily, when the first detection request is not back-pressured, other processors have the permission to execute the memory access request pointing to the second storage address. Exemplarily, when the first detection request is back-pressured, other processors do not have the permission to execute the memory access request pointing to the second storage address. Exemplarily, this memory access request may be an atomic request or may not be an atomic request.

[0060] The technical solution provided by the embodiment of this application sets the detection module inside the processor. The detection module includes a first detection unit and a register. The register is used to store a lock table, and the lock table is used to record at least one first storage address locked by the processor. That is, the addresses currently locked by the processor are recorded in the form of a lock table. The first detection unit is used to compare whether the second storage address carried in the detection request sent by other processors overlaps with each first storage address. When the second storage address overlaps with at least one first storage address, backpressure is applied to the first detection request. If the first detection request is backpressured, it means that the second storage address is currently locked by the processor, so other processors cannot execute atomic instructions pointing to the second storage address. In the embodiment of this application, by setting the detection module in the processor, the mutual exclusion relationship between memory access requests sent by different processors can be determined inside the processor, thus eliminating the need to layout a global detector and reducing the chip area.

[0061] The following gives an exemplary description of the first detection unit (check unit).

[0062] In some embodiments, the first detection unit 310 includes at least one comparator and a result determination gate circuit. The local table includes at least one entry, and each entry includes a first storage address.

[0063] In some embodiments, the i-th comparator in at least one comparator (abbreviated as cmp) is used to compare the second storage address with the first storage address in the i-th entry of the lock table to obtain the comparison result corresponding to the i-th comparator, where i is a positive integer.

[0064] This application does not limit the number of comparators. Exemplarily, the number of comparators is determined by the number of entries in the lock table. Exemplarily, the number of comparators is the same as the number of entries. Exemplarily, when there are K entries in the lock table or at most K entries are allowed to exist simultaneously in the lock table, the number of comparators is also K, where K is a positive integer.

[0065] Exemplarily, the first storage address includes a storage address information (abbreviated as addr) and a data type information. The storage address information is used to represent the storage location, and the data type information is used to represent the storage length. In some embodiments, the first storage address in an entry refers to the storage address information and the data type information, and the storage address information and the data type information are used to comprehensively represent the storage address represented by the entry. Exemplarily, the data type information includes at least one of byte, half word, word, and double word.

[0066] Exemplarily, the comparison result includes a first value and a second value. The first value is used to characterize that the addresses overlap, and the second value is used to characterize that the addresses do not overlap. Exemplarily, the first value is 0 and the second value is 1.

[0067] Exemplarily, the i-th comparator is used to determine the storage address represented by the i-th entry in the lock table according to the storage address information and data type information in the i-th entry.

[0068] Exemplarily, the second storage address includes storage address information (address) and data type information (datatype). The storage address information is used to characterize the storage location, and the data type information is used to characterize the storage length. In some embodiments, the second storage address refers to the storage address information and data type information.

[0069] Exemplarily, the i-th comparator is further used to compare the second storage address with the storage address represented by the i-th entry. When the second storage address and the storage address represented by the i-th entry overlap, it is determined that the comparison result corresponding to the i-th comparator is the first value; when the second storage address and the storage address represented by the i-th entry do not overlap, it is determined that the comparison result corresponding to the i-th comparator is the second value.

[0070] Exemplarily, according to the storage address information and data type information in the i-th entry, it is determined that the storage address represented by the i-th entry (referring to the actual storage situation corresponding to the storage space) is that the access length to the A address is a bytes. The second storage address is that the access length to the B address is b bytes. The i-th comparator is further used to compare whether the access length to the A address of a bytes and the access length to the B address of b bytes overlap. When there is an overlap, it is determined that the comparison result corresponding to the i-th comparator is the first value; when there is no overlap, it is determined that the comparison result corresponding to the i-th comparator is the second value.

[0071] In some embodiments, the result determination gate circuit is used to determine whether the second storage address and each first storage address overlap according to the comparison results respectively corresponding to at least one comparator.

[0072] Exemplarily, the result determination gate circuit is used to perform an or-not operation, that is, first perform an or operation with multiple inputs and then take the inverse. Exemplarily, the result determination gate circuit is a nor gate.

[0073] Exemplarily, a result determination gate circuit is configured to determine that a second storage address overlaps with at least one first storage address when at least one of the comparison results respectively corresponding to at least one comparator is a first numerical value. Exemplarily, a result determination gate circuit is configured to determine that a second storage address overlaps with at least one first storage address when at least one of the comparison results respectively corresponding to at least one comparator is 0. Exemplarily, at this time, the output result of the result determination gate circuit is 0.

[0074] Exemplarily, a result determination gate circuit is configured to determine that a second storage address does not overlap with at least one first storage address when the comparison results respectively corresponding to at least one comparator are all second numerical values. Exemplarily, a result determination gate circuit is configured to determine that a second storage address overlaps with at least one first storage address when the comparison results respectively corresponding to at least one comparator are all 1. Exemplarily, at this time, the output result of the result determination gate circuit is 1.

[0075] In some embodiments, the detection module 300 further includes a detection interface (probe interface).

[0076] In some embodiments, the detection interface is configured to perform format conversion on a first detection request and send the first detection request after format conversion to the first detection unit. In some embodiments, the detection interface is configured to perform format conversion on a first detection request (L2 probe request) sent by a secondary buffer and send the first detection request (probe request) after format conversion to the first detection unit.

[0077] In some embodiments, the detection interface is further configured to send a first instruction to other processors when the first detection unit applies backpressure to the first detection request, and the first instruction is used to instruct the processor not to allow other processors to execute a first atomic instruction pointing to the second storage address.

[0078] In some embodiments, the detection interface is further configured to send a second instruction to other processors when the first detection unit does not apply backpressure to the first detection request, and the second instruction is used to instruct the processor to allow other processors to execute a first atomic instruction pointing to the second storage address.

[0079] Exemplarily, when all other processors in the multi-core CPU system except the target processor that wants to execute the atomic instruction pointing to the second storage address send the second instruction to the target processor, the target processor has the permission to execute the atomic instruction pointing to the second storage address. Exemplarily, when at least one of all other processors in the multi-core CPU system except the target processor that wants to execute the atomic instruction pointing to the second storage address sends the first instruction to the target processor, the target processor does not have the permission to execute the atomic instruction pointing to the second storage address.

[0080] In some other embodiments, the detection interface is further configured to send a first instruction to the buffer when the first detection unit backpresses the first detection request, where the first instruction is used to instruct the processor not to allow other processors to execute the first atomic instruction pointing to the second storage address.

[0081] In some other embodiments, the detection interface is further configured to send a second instruction to the buffer when the first detection unit does not backpress the first detection request, where the second instruction is used to instruct the processor to allow other processors to execute the first atomic instruction pointing to the second storage address.

[0082] Exemplarily, when all other processors in the multi-core CPU system except the target processor that wants to execute the atomic instruction pointing to the second storage address send the second instruction to the buffer, the buffer is configured to send an allow instruction to the target processor, where the allow instruction is used to inform the target processor that it has the permission to execute the atomic instruction pointing to the second storage address. Exemplarily, when at least one of all other processors in the multi-core CPU system except the target processor that wants to execute the atomic instruction pointing to the second storage address sends the first instruction to the buffer, the buffer is configured to send a prohibit instruction to the target processor, where the prohibit instruction is used to inform the target processor that it does not have the permission to execute the atomic instruction pointing to the second storage address.

[0083] The following gives an exemplary description of the second detection unit (check unit) further included in the detection module.

[0084] In some embodiments, the detection module further includes a second detection unit.

[0085] Exemplarily, the second detection unit is configured to detect the mutual exclusion relationship between different memory access requests within the same processor. Exemplarily, the second detection unit is configured to detect the mutual exclusion relationship between atomic instructions corresponding to the same processor. The mutual exclusion relationship here can be understood as whether it points to the same storage address. It should be noted that the structures of the second detection unit and the first detection unit can be considered the same or similar. Therefore, for the technical details not mentioned in the following processing flow of the second detection unit, reference can be made to the explanations in the above embodiments and will not be elaborated here.

[0086] In some embodiments, the second detection unit is configured to update the lock table according to the memory access request of the processor.

[0087] Exemplarily, the memory access request of the processor here refers to the memory access request within the processor, which is different from the first detection request sent by the above-mentioned other processors. For the specific update method, refer to the following embodiments.

[0088] In some embodiments, when the memory access request of the processor is a second atomic instruction and the second detection request sent by the processor to other processors is not backpressure, the processor has the permission to execute the second atomic instruction. Exemplarily, the second atomic instruction refers to an instruction constructed by a reserved load instruction and a conditional store instruction, and the third storage address pointed to by the second atomic instruction is carried in the second detection request.

[0089] Reference Figure 4 , which shows a schematic structural diagram of a detection module provided by another embodiment of the present application. As Figure 4 shown in 400 of, the detection module 400 includes a first detection unit, a second detection unit, a detection interface, and a register. Among them, the lock table is stored in the register. There are a total of 4 field segments in the lock table (lock table). valid indicates whether the current entry is valid; addr (address) is the storage address information; data type is the data type information. When judging whether there is an address overlap between two requests, the addr and data type information should be considered comprehensively; failed is the failure status (failure information). If an atomic operation is destroyed by other write operations, the failed field segment is set to 1, and a failed flag (failure mark) is returned when the SC instruction is executed subsequently.

[0090] The core request (abbreviated as core req) is a memory access request within the core, that is, the memory access request of the above-mentioned processor. The L2 probe request (abbreviated as L2 probe req, that is, the L2 detection request) is a coherence detection request sent by the L2 (secondary cache), that is, the above-mentioned first detection request. The two are respectively input to the check unit for lock table detection. The check unit is instantiated twice, divided into the first detection unit and the second detection unit, and is used for core req and probe req respectively. The comparator (cmp) compares the stored address information and data type information to determine whether there is an address overlap between the two requests. The probe req contains the stored address information and data type information of the probe request, and needs to be compared with all entries in the locktable. The comparison result is input to a nor gate to obtain the result of whether there is an address overlap with the lock table address. For the probe req, if there is no address overlap with the lock table, the output result is 1, that is, the current L2 probe req is received, otherwise the request is backpressure. The probe interface is mainly used to process the L2 probe req request and convert it into a format that can be recognized internally.

[0091] The core req sent by the Core (processor core) also needs to be detected by the check unit, and it needs to be divided into three cases: (1) If the core req is an LR (load reserved) instruction, the check unit is used to determine whether it has the same address as the existing entry. If the same, the LR instruction information is directly updated to this entry, otherwise a new entry is allocated to this LR instruction (that is, Figure 4 the setting logic in), corresponding to the first case below; (2) If the core req is an SC (store conditional) instruction, the check unit is used to determine whether it has the same address as the existing entry. If it exists, the failed field segment is checked, and the failure information is returned as the result of the SC instruction, and all field segments of this entry are cleared (corresponding to Figure 4 the reset logic in), if it does not exist, the failure flag is directly returned, corresponding to the second case below; (3) If the core req is an ordinary store (store) instruction, the check unit is used to determine whether it has the same address as the existing entry. If the same, this store instruction destroys the atomicity of LRSC, and the failed field segment of this entry is set to 1 (corresponding to Figure 4 the failure logic in), corresponding to the third case below.

[0092] The embodiments of the present application do not limit the type of memory access requests inside the processor. The memory access request can be an atomic instruction or not. Whether the memory access request is an atomic instruction or not, when the second detection request carried by the processor to other processors and pointing to the memory access address of the memory access request is not backpressure, the processor has the permission to execute the memory access request. Conversely, when the second detection request carried by the processor to other processors and pointing to the memory access address of the memory access request is backpressure, the processor does not have the permission to execute the memory access request.

[0093] The following is an exemplary description of the processing flow of the second detection unit for the following three types of instructions.

[0094] First, the memory access request of the processor is a reserved load instruction.

[0095] Exemplarily, a reserved load instruction pointing to address A means that when the processor executes the reserved load instruction, address A will be locked by the processor.

[0096] In some embodiments, the lock table includes at least one entry, and each entry includes a first storage address.

[0097] In some embodiments, the second detection unit is configured to, when the processor has the permission to execute the second atomic instruction, compare the third storage address pointed to by the reserved load instruction with the first storage addresses respectively corresponding to at least one entry, and when the third storage address pointed to by the reserved load instruction is different from the first storage addresses respectively corresponding to at least one entry, determine that the comparison result is different.

[0098] Exemplarily, the first storage address includes storage address information and data type information. The storage address information is used to represent the storage location, and the data type information is used to represent the storage length. Exemplarily, compare the storage address information and data type information included in the third storage address pointed to by the reserved load instruction with the storage address information and data type information included in the first storage addresses respectively corresponding to at least one entry.

[0099] Exemplarily, when the third storage address pointed to by the reserved load instruction is different from the first storage addresses respectively corresponding to each entry, determine that the comparison result is different.

[0100] In some embodiments, the second detection unit is further configured to, when the comparison result is different, add a new entry to the lock table, and the new entry is used to represent the third storage address pointed to by the reserved load instruction. That is, when the third storage address pointed to by the reserved load instruction does not exist in the lock table, add an entry to the lock table to represent the third storage address. That is, lock the third storage address with the lock table.

[0101] In some embodiments, the second detection unit is further configured to determine that the comparison result is the same when the third storage address pointed to by the reservation load instruction is the same as the first storage address corresponding to at least one entry.

[0102] Exemplarily, the second detection unit is configured to, when the comparison result is the same, update the information related to the reservation load instruction to the m-th entry when the first storage address corresponding to the m-th entry in at least one entry is the same as the third storage address pointed to by the reservation load instruction, where m is a positive integer. Exemplarily, the storage address information in the third storage address pointed to by the reservation load instruction is the same as the storage address information in the first storage address corresponding to the m-th entry. Exemplarily, the data type information in the third storage address pointed to by the reservation load instruction is the same as the data type information in the first storage address corresponding to the m-th entry.

[0103] In some embodiments, each entry in the lock table includes, in addition to the first storage address, at least one of the valid information (valid) of the first storage address and the failure information (failed) of the first storage address. Among them, the valid information (valid) of the first storage address indicates whether the entry where the first storage address is located is valid. The failure information of the first storage address is used to indicate whether the locked state of the first storage address is damaged. Exemplarily, when the first storage address corresponding to the m-th entry in at least one entry is the same as the third storage address pointed to by the reservation load instruction and the information related to the reservation load instruction is updated to the m-th entry, at least the valid information in the m-th entry is changed to valid (it could be valid or invalid originally). Exemplarily, when the first storage address corresponding to the m-th entry in at least one entry is the same as the third storage address pointed to by the reservation load instruction and the information related to the reservation load instruction is updated to the m-th entry, at least the failure information in the m-th entry is changed to 0 (0 represents not damaged, it could be 0 or 1 (damaged) originally).

[0104] In the embodiments of the present application, by comparing the storage address pointed to by the reservation load instruction with the first storage address in the lock table, it is determined whether the storage address pointed to by the reservation load instruction is locked by the lock table. If it is not locked, a new entry is added to the lock table to lock the storage address. Therefore, the detection module can lock the storage address pointed to by the reservation load instruction to facilitate the execution of subsequent conditional load instructions.

[0105] Second, the memory access request of the processor is a conditional store instruction.

[0106] Exemplarily, a reserved load instruction pointing to address A means that when the processor executes the reserved load instruction, address A will be locked by the processor. Executing a conditional store instruction at address A means that when address A is locked by the processor, a store operation is performed at address A.

[0107] In some embodiments, the lock table includes at least one entry, and each entry includes a first storage address and failure information of the first storage address, where the failure information of the first storage address is used to characterize whether the locked state of the first storage address is damaged.

[0108] Exemplarily, when the failure information of the first storage address is 0, it indicates that the locked state of the first storage address is not damaged, that is, the currently executed operation is an atomic operation. Exemplarily, when the failure information of the first storage address is 1, it indicates that the locked state of the first storage address is damaged, that is, the currently executed atomic operation is damaged by other write operations (or write instructions).

[0109] In some embodiments, a second detection unit is configured to, when the processor has the permission to execute a second atomic instruction, compare the third storage address pointed to by the conditional store instruction with the first storage addresses respectively corresponding to at least one entry, and determine a target entry from at least one entry, where the first storage address corresponding to the target entry is the same as the third storage address pointed to by the conditional store instruction.

[0110] Exemplarily, the second detection unit invokes at least one comparator to parallelly compare whether the third storage address pointed to by the conditional store instruction is the same as the first storage addresses respectively corresponding to at least one entry. When they are the same, a target entry is determined from at least one entry, and the first storage address corresponding to the target entry is the same as the third storage address pointed to by the conditional store instruction. Exemplarily, the storage address information and data type information included in the first storage address corresponding to the target entry are respectively the same as the storage address information and data type information included in the third storage address pointed to by the conditional store instruction.

[0111] In some embodiments, the second detection unit is further configured to obtain the failure information of the first storage address in the target entry and clear the target entry in the lock table.

[0112] Exemplarily, when clearing the target entry in the lock table, the target entry is empty, or the valid information in the target entry changes to invalid (such as 0), and other data in the target entry is cleared.

[0113] In some embodiments, the second detection unit is further configured to return a success flag when the failure information indicates that the locked state of the first storage address is not damaged. Exemplarily, when the processor receives the success flag returned by the second detection unit, it executes the conditional store instruction and performs a store operation at the third storage address corresponding to the conditional store instruction.

[0114] In some embodiments, the second detection unit is further configured to return a failure flag when the failure information indicates that the locked state of the first storage address is damaged. Exemplarily, when the processor receives the failure flag returned by the second detection unit, the conditional storage instruction is not executed.

[0115] In some embodiments, the second detection unit is further configured to return a failure flag when the target entry does not exist in at least one entry. Exemplarily, when the target entry does not exist in at least one entry, it indicates that the third storage address is not recorded in the entries of the lock table. At this time, the third storage address is surely not locked, so a failure flag is returned.

[0116] Exemplarily, when the second detection unit returns a success flag, the processor executes the conditional storage instruction. When the second detection unit returns a failure flag, the processor cannot execute the conditional storage instruction.

[0117] In the embodiments of the present application, the storage address pointed to by the conditional storage instruction is compared with the first storage address in the lock table to determine whether the storage address pointed to by the conditional storage instruction is recorded in the lock table. If the storage address pointed to by the conditional storage instruction is recorded in the lock table and is locked, a success flag is returned and the conditional storage instruction is executed. If the storage address pointed to by the conditional storage instruction is recorded in the lock table but the lock of the address is damaged, a failure flag is returned and the conditional storage instruction is not executed. If the storage address pointed to by the conditional storage instruction is not recorded in the lock table, a failure flag is returned and the conditional storage instruction is not executed. Therefore, the detection module can determine whether to execute the conditional storage address according to whether the address is locked, so as to ensure the accuracy of the storage operation and ensure that the load instruction and the conditional storage instruction are atomic instructions.

[0118] Thirdly, the memory access request of the processor is other storage instructions except the conditional storage instruction.

[0119] Exemplarily, other storage instructions are also called ordinary storage instructions. Here, only storage instructions are used as examples in the third case. It should be known that other write instructions (or write operations) except storage instructions can also be regarded as the memory access requests here.

[0120] In some embodiments, the lock table includes at least one entry, and each entry includes a first storage address and the failure information of the first storage address. The failure information of the first storage address is used to characterize whether the locked state of the first storage address is damaged.

[0121] In some embodiments, a second detection unit is configured to compare the storage addresses pointed to by other storage instructions with the first storage addresses respectively corresponding to at least one entry, and determine a target entry from the at least one entry, where the first storage address corresponding to the target entry is the same as the storage address pointed to by the other storage instructions.

[0122] In some embodiments, the second detection unit is further configured to change the failure information of the first storage address in the target entry, and the failure information of the first storage address in the changed target entry indicates that the locked state of the first storage address is damaged.

[0123] Exemplarily, the other storage instruction is a normal storage instruction for address A. The second detection unit is configured to compare whether the address A exists in the first storage addresses respectively corresponding to at least one entry. If the address A exists, the failure information table of the entry where the address A is located is changed to the locked state being damaged. Exemplarily, at this time, the failure information of the original entry where the address A is located is not considered whether the locked state is damaged or not damaged. The updated lock table indicates that the locked state of the address A is damaged. Then when the subsequent processor wants to execute a conditional storage instruction pointing to the address A, according to the lock table indicating that the address A is not locked, the conditional storage instruction pointing to the address A is not executed.

[0124] In some embodiments, the second detection unit is configured not to update the lock table when the target entry does not exist in the at least one entry.

[0125] In the embodiments of the present application, by comparing the storage address pointed to by the normal storage instruction with the first storage address in the lock table, it is determined whether the storage address pointed to by the normal storage instruction is recorded in the lock table. If it is recorded, the failure information corresponding to the storage address is changed to the locked state being damaged, so as to facilitate determining whether to execute the conditional load instruction.

[0126] Please refer to Figure 5 , which shows a schematic diagram of multi-core synchronization provided by an embodiment of the present application.

[0127] As Figure 5As shown in 500, assume that both core0 and core1 need to perform an LRSC operation on address A. Assume that core0 first executes LR A, loading the data at address A into core0 internally. Then core1 executes LR A. Since the lock table in core0 has already registered the LR A information at this time, that is, address A is locked, core1 needs to perform a probe operation on other cores through L2 when executing LR A to obtain permission. However, at this time, address A is locked in the lock table of core0, so the detection request sent by core1 through L2 is backpressure until the SC A in core0 is executed and the lock on address A in the lock table is released. At this time, the backpressure of the probereq in L2 is released, and core1 is granted permission to execute the LR A instruction. When core1 executes LR A, core0 has already completed the atomic operation on address A, and core1 can see the execution result of core0. Subsequently, the LRSC operation of core1 does not destroy the atomicity of core1.

[0128] Please refer to Figure 6 , which shows a schematic diagram of SC failure provided by an embodiment of the present application.

[0129] As Figure 6 As shown in 600, at the initial moment, the lock table is empty; the LR A instruction is executed, setting the valid of entry0 to 1, and updating the instruction information to the entry; the Store A instruction is executed. By comparing with the lock table, it is found that the address coincides with that of entry0, and the store instruction destroys the atomicity of LRSC, updating the failed field segment to 1; the SC A instruction is executed. By comparing with the lock table, it is found that the address coincides with that of entry0, and its failed field segment is 1, then a failure flag (failure marker) is returned, and the entry is cleared.

[0130] Please refer to Figure 7 , which shows a schematic diagram of SC success provided by an embodiment of the present application.

[0131] As Figure 7 As shown in 700, at the initial moment, the lock table is empty; the LR A instruction is executed, setting the valid of entry0 to 1, and updating the instruction information to the entry; the SC A instruction is executed. By comparing with the lock table, it is found that the address coincides with that of entry0, and its failed field segment is 0, then a success flag is returned, and the entry is cleared.

[0132] The following are method embodiments of the present application. For details not described in detail in the method embodiments of the present application, reference can be made to the explanation of the embodiments of the detection module above.

[0133] Please refer to Figure 8, which shows a flowchart of a memory access method applied to a detection module provided by an embodiment of the present application. This method is applied to the detection module applied to the processor introduced above. The detection module includes: a first detection unit and a register. This method may include at least one of the following steps 810 to 830.

[0134] Step 810, the register stores a lock table, and the lock table is used to record at least one first storage address locked by the processor.

[0135] Step 820, the first detection unit compares whether the second storage address carried in the first detection request overlaps with each first storage address according to the first detection request sent by another processor.

[0136] In some embodiments, the first detection unit includes at least one comparator and a result determination gate circuit. The lock table includes at least one entry, and each entry includes a first storage address.

[0137] In some embodiments, the i-th comparator in the at least one comparator compares the second storage address with the first storage address in the i-th entry of the lock table to obtain a comparison result corresponding to the i-th comparator, where i is a positive integer.

[0138] In some embodiments, the result determination gate circuit determines whether the second storage address overlaps with each first storage address according to the comparison results respectively corresponding to the at least one comparator.

[0139] In some embodiments, the first storage address includes storage address information and data type information. The storage address information is used to represent the storage location, and the data type information is used to represent the storage length. The comparison result includes a first value and a second value. The first value is used to represent that the addresses overlap, and the second value is used to represent that the addresses do not overlap.

[0140] In some embodiments, the i-th comparator determines the storage address represented by the i-th entry according to the storage address information and data type information in the i-th entry of the lock table.

[0141] In some embodiments, the i-th comparator compares the second storage address with the storage address represented by the i-th entry. When the second storage address overlaps with the storage address represented by the i-th entry, it is determined that the comparison result corresponding to the i-th comparator is the first value; when the second storage address does not overlap with the storage address represented by the i-th entry, it is determined that the comparison result corresponding to the i-th comparator is the second value.

[0142] In some embodiments, the result determination gate circuit determines that the second storage address overlaps with at least one first storage address when at least one of the comparison results respectively corresponding to the at least one comparator is the first value.

[0143] In some embodiments, when the result determination gate circuit is all the second values in the comparison results respectively corresponding to at least one comparator, it is determined that there is no overlap between the second storage address and each of the first storage addresses.

[0144] Step 830: When there is an overlap between the second storage address and at least one of the first storage addresses, the first detection unit backpresses the first detection request. When the first detection request is backpressed, other processors do not have the permission to execute the first atomic instruction pointing to the second storage address.

[0145] In some embodiments, when there is no overlap between the second storage address and each of the first storage addresses, the first detection unit does not backpress the first detection request. When the first detection request is not backpressed, other processors have the permission to execute the first atomic instruction pointing to the second storage address.

[0146] In some embodiments, the detection module further includes a detection interface.

[0147] In some embodiments, the detection interface performs format conversion on the first detection request and sends the first detection request after format conversion to the first detection unit.

[0148] In some embodiments, when the first detection unit backpresses the first detection request, the detection interface sends a first instruction to other processors, and the first instruction is used to instruct the processors not to allow other processors to execute the first atomic instruction pointing to the second storage address.

[0149] In some embodiments, when the first detection unit does not backpress the first detection request, the detection interface sends a second instruction to other processors, and the second instruction is used to instruct the processors to allow other processors to execute the first atomic instruction pointing to the second storage address.

[0150] In some embodiments, the detection module further includes a second detection unit.

[0151] In some embodiments, the second detection unit updates the lock table according to the memory access request of the processor.

[0152] In some embodiments, when the memory access request of the processor is a second atomic instruction and the second detection request sent by the processor to other processors is not backpressed, the processor has the permission to execute the second atomic instruction. The second atomic instruction refers to an instruction constructed by a reserved load instruction and a conditional store instruction, and the third storage address pointed to by the second atomic instruction is carried in the second detection request.

[0153] In some embodiments, the lock table includes at least one entry, and each entry includes a first storage address; when the memory access request of the processor is a reserved load instruction, the second detection unit, when the processor has the permission to execute the second atomic instruction, compares the third storage address pointed to by the reserved load instruction with the first storage addresses respectively corresponding to the at least one entry. When the third storage address pointed to by the reserved load instruction is different from the first storage addresses respectively corresponding to the at least one entry, it is determined that the comparison result is different; when the comparison result is different, the second detection unit adds a new entry to the lock table, and the newly added entry is used to represent the third storage address pointed to by the reserved load instruction.

[0154] In some embodiments, the lock table includes at least one entry, and each entry includes a first storage address and failure information of the first storage address, and the failure information of the first storage address is used to represent whether the locked state of the first storage address is damaged; when the memory access request of the processor is a conditional store instruction, the second detection unit, when the processor has the permission to execute the second atomic instruction, compares the third storage address pointed to by the conditional store instruction with the first storage addresses respectively corresponding to the at least one entry, and determines a target entry from the at least one entry, where the first storage address corresponding to the target entry is the same as the third storage address pointed to by the conditional store instruction; the second detection unit obtains the failure information of the first storage address in the target entry and clears the target entry in the lock table; when the failure information indicates that the locked state of the first storage address is not damaged, the second detection unit returns a success flag; when the failure information indicates that the locked state of the first storage address is damaged, the second detection unit returns a failure flag; wherein, when the second detection unit returns a success flag, the processor executes the conditional store instruction, and when the second detection unit returns a failure flag, the processor cannot execute the conditional store instruction. In some embodiments, when the target entry does not exist in the at least one entry, the second detection unit returns a failure flag.

[0155] In some embodiments, the lock table includes at least one entry, and each entry includes a first storage address and failure information of the first storage address, and the failure information of the first storage address is used to represent whether the locked state of the first storage address is damaged; when the memory access request of the processor is a storage instruction other than the conditional store instruction, the second detection unit compares the storage address pointed to by the other storage instruction with the first storage addresses respectively corresponding to the at least one entry, and determines a target entry from the at least one entry, where the first storage address corresponding to the target entry is the same as the storage address pointed to by the other storage instruction; the second detection unit changes the failure information of the first storage address in the target entry, and the changed failure information of the first storage address in the target entry indicates that the locked state of the first storage address is damaged.

[0156] The technical solution provided by the embodiment of the present application sets the detection module inside the processor. The detection module includes a first detection unit and a register. The register is used to store a lock table, and the lock table is used to record at least one first storage address locked by the processor. That is, the addresses currently locked by the processor are recorded in the form of a lock table. The first detection unit compares whether the second storage address carried in the detection request sent by another processor overlaps with each first storage address. When the second storage address overlaps with at least one first storage address, backpressure is applied to the first detection request. If the first detection request is backpressured, it means that the second storage address is currently locked by the processor, so other processors cannot execute atomic instructions pointing to the second storage address. In the embodiment of the present application, by setting the detection module in the processor, the mutual exclusion relationship between memory access requests sent by different processors can be determined inside the processor, thus eliminating the need to layout a global detector and reducing the chip area.

[0157] In some embodiments, the present application also provides a processor, and the processor includes the detection module introduced in the above embodiment.

[0158] In some embodiments, the present application also provides a computer device, and the computer device includes a processor, and the processor includes the detection module introduced in the above embodiment.

[0159] In some embodiments, the processor is an AI processor or other processors that require memory access operations, and the present application does not make any limitations in this regard.

[0160] In some embodiments, the computer device can be a server, or terminal devices such as mobile phones, tablet computers, intelligent voice interaction devices, vehicle-mounted terminals, wearable devices, vehicle-mounted terminal devices, aircraft, smart home devices, etc., or it can also be any device applying the processor such as robots, base stations, etc., and the present application does not make any limitations in this regard.

[0161] It should be noted that the collection and processing of relevant data in the present application should strictly comply with the requirements of relevant national laws and regulations during actual application, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing behaviors within the scope authorized by laws and regulations and the personal information subject.

[0162] It should be understood that the "plurality" mentioned herein refers to two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. In addition, the step numbers described herein only exemplarily show a possible execution sequence between steps. In some other embodiments, the above steps may not be executed in the numbered order. For example, two steps with different numbers can be executed simultaneously, or two steps with different numbers can be executed in the reverse order of the illustration. The embodiments of the present application do not limit this.

[0163] The above are only exemplary embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A detection module applied to a processor, characterized in that, The detection module includes: a first detection unit and a register; The register is used to store a lock table, and the lock table is used to record at least one first storage address locked by the processor; The first detection unit is used to compare whether there is an overlap between the second storage address carried in the first detection request sent by another processor and each of the first storage addresses according to the received first detection request; The first detection unit is further used to backpressure the first detection request when there is an overlap between the second storage address and at least one of the first storage addresses. When the first detection request is backpressured, the other processor does not have the permission to execute the first atomic instruction pointing to the second storage address.

2. The detection module according to claim 1, wherein The first detection unit includes at least one comparator and a result determination gate circuit, and the lock table includes at least one entry, and each entry includes a first storage address; The i-th comparator in the at least one comparator is used to compare the second storage address with the first storage address in the i-th entry in the lock table to obtain a comparison result corresponding to the i-th comparator, where i is a positive integer; The result determination gate circuit is used to determine whether there is an overlap between the second storage address and each of the first storage addresses according to the comparison results respectively corresponding to the at least one comparator.

3. The detection module according to claim 2, characterized in that, The first storage address includes storage address information and data type information. The storage address information is used to represent the storage location, and the data type information is used to represent the storage length. The comparison result includes a first value and a second value. The first value is used to represent that the addresses overlap, and the second value is used to represent that the addresses do not overlap; The i-th comparator is used to determine the storage address represented by the i-th entry according to the storage address information and data type information in the i-th entry in the lock table; The i-th comparator is further used to compare the second storage address with the storage address represented by the i-th entry. When there is an overlap between the second storage address and the storage address represented by the i-th entry, it is determined that the comparison result corresponding to the i-th comparator is the first value; When there is no overlap between the second storage address and the storage address represented by the i-th entry, it is determined that the comparison result corresponding to the i-th comparator is the second value; The result determination gate circuit is used to determine that there is an overlap between the second storage address and at least one of the first storage addresses when at least one of the comparison results respectively corresponding to the at least one comparator is the first value.

4. The detection module according to claim 1, wherein The detection module further includes a detection interface; The detection interface is used to perform format conversion on the first detection request and send the first detection request after format conversion to the first detection unit; The detection interface is further used to send a first instruction to the other processor when the first detection unit backpressures the first detection request. The first instruction is used to instruct the processor not to allow the other processor to execute the first atomic instruction pointing to the second storage address.

5. The detection module according to claim 1, wherein The detection module further includes a second detection unit; The second detection unit is configured to update the lock table according to the memory access request of the processor.

6. The detection module according to claim 5, wherein when the memory access request of the processor is a second atomic instruction and the second detection request sent by the processor to the other processor is not backpressure, the processor has the permission to execute the second atomic instruction, and the second atomic instruction refers to an instruction constructed by a reserved load instruction and a conditional store instruction, and the third storage address pointed to by the second atomic instruction is carried in the second detection request.

7. The detection module according to claim 6, wherein The lock table includes at least one entry, and each entry includes a first storage address; when the memory access request of the processor is a reserved load instruction, the second detection unit is configured to, when the processor has the permission to execute the second atomic instruction, compare the third storage address pointed to by the reserved load instruction with the first storage addresses respectively corresponding to the at least one entry, and when the third storage address pointed to by the reserved load instruction is not the same as any of the first storage addresses respectively corresponding to the at least one entry, determine that the comparison result is different; the second detection unit is further configured to, when the comparison result is different, add a new entry to the lock table, and the new entry is used to represent the third storage address pointed to by the reserved load instruction.

8. The detection module according to claim 6, wherein The lock table includes at least one entry, and each entry includes a first storage address and failure information of the first storage address, and the failure information of the first storage address is used to represent whether the lock state of the first storage address is damaged; when the memory access request of the processor is a conditional store instruction, the second detection unit is configured to, when the processor has the permission to execute the second atomic instruction, compare the third storage address pointed to by the conditional store instruction with the first storage addresses respectively corresponding to the at least one entry, and determine a target entry from the at least one entry, and the first storage address corresponding to the target entry is the same as the third storage address pointed to by the conditional store instruction; the second detection unit is further configured to obtain the failure information of the first storage address in the target entry and clear the target entry in the lock table; the second detection unit is further configured to, when the failure information indicates that the lock state of the first storage address is not damaged, return a success flag; the second detection unit is further configured to, when the failure information indicates that the lock state of the first storage address is damaged, return a failure flag; wherein, when the second detection unit returns a success flag, the processor executes the conditional store instruction, and when the second detection unit returns a failure flag, the processor cannot execute the conditional store instruction.

9. The detection module according to claim 8, wherein the second detection unit is further configured to, when the target entry does not exist in the at least one entry, return the failure flag.

10. The detection module according to claim 5, characterized in that, The lock table includes at least one entry, and each entry includes a first storage address and failure information of the first storage address, where the failure information of the first storage address is used to indicate whether the locked state of the first storage address is damaged; when the memory access request of the processor is other storage instructions except the conditional storage instruction, The second detection unit is configured to compare the storage address pointed to by the other storage instruction with the first storage addresses respectively corresponding to the at least one entry, and determine a target entry from the at least one entry, where the first storage address corresponding to the target entry is the same as the storage address pointed to by the other storage instruction; The second detection unit is further configured to change the failure information of the first storage address in the target entry, and the changed failure information of the first storage address in the target entry indicates that the locked state of the first storage address is damaged.

11. A processor, characterized in that, The processor includes the detection module according to any one of claims 1 to 10.

12. A computer device, characterized in that, The computer device includes a processor, and the processor includes the detection module according to any one of claims 1 to 10.

13. A detection method applied to a detection module, characterized in that, The detection module includes: a first detection unit and a register; the method includes: The register stores a lock table, and the lock table is used to record at least one first storage address locked by the processor; The first detection unit compares, according to a first detection request sent by another processor, whether the second storage address carried in the first detection request overlaps with each of the first storage addresses; When the second storage address overlaps with at least one of the first storage addresses, the first detection unit backpressures the first detection request, where when the first detection request is backpressured, the other processor does not have the permission to execute the first atomic instruction pointing to the second storage address.

14. The method according to claim 13, characterized in that, The first detection unit includes at least one comparator and a result determination gate circuit, the lock table includes at least one entry, and each entry includes a first storage address; The first detection unit compares, according to a first detection request sent by another processor, whether the second storage address carried in the first detection request overlaps with each of the first storage addresses, including: The i-th comparator in the at least one comparator compares the second storage address with the first storage address in the i-th entry in the lock table to obtain a comparison result corresponding to the i-th comparator, where i is a positive integer; The result determination gate circuit determines whether the second storage address overlaps with each of the first storage addresses according to the comparison results respectively corresponding to the at least one comparator.

15. The method according to claim 14, wherein The first storage address includes storage address information and data type information, the storage address information is used to indicate a storage location, the data type information is used to indicate a storage length, the comparison result includes a first value and a second value, the first value is used to indicate that the addresses overlap, and the second value is used to indicate that the addresses do not overlap; The i-th comparator among the at least one comparator compares the second storage address with the first storage address in the i-th entry of the lock table to obtain a comparison result corresponding to the i-th comparator, including: The i-th comparator determines the storage address represented by the i-th entry according to the storage address information and data type information in the i-th entry of the lock table; The i-th comparator compares the second storage address with the storage address represented by the i-th entry. When there is an overlap between the second storage address and the storage address represented by the i-th entry, it is determined that the comparison result corresponding to the i-th comparator is the first value; when there is no overlap between the second storage address and the storage address represented by the i-th entry, it is determined that the comparison result corresponding to the i-th comparator is the second value; The result determination gate circuit determines whether there is an overlap between the second storage address and each of the first storage addresses according to the comparison results respectively corresponding to the at least one comparator, including: The result determination gate circuit determines that there is an overlap between the second storage address and at least one of the first storage addresses when at least one of the comparison results respectively corresponding to the at least one comparator is the first value.

16. The method according to claim 13, wherein The detection module further includes a detection interface; the method further includes: The detection interface performs format conversion on the first detection request and sends the first detection request after format conversion to the first detection unit; When the first detection unit performs backpressure on the first detection request, the detection interface sends a first instruction to the other processor, and the first instruction is used to instruct the processor not to allow the other processor to execute the first atomic instruction pointing to the second storage address.

17. The method according to claim 13, wherein The detection module further includes a second detection unit; the method further includes: The second detection unit updates the lock table according to the memory access request of the processor.

18. The method according to claim 17, wherein When the memory access request of the processor is a second atomic instruction and the second detection request sent by the processor to the other processor is not backpressured, the processor has the permission to execute the second atomic instruction, and the second atomic instruction is an instruction constructed by a reserved load instruction and a conditional store instruction, and the third storage address pointed to by the second atomic instruction is carried in the second detection request.

19. The method according to claim 18, characterized in that, The lock table includes at least one entry, and each entry includes a first storage address; when the memory access request of the processor is a reserved load instruction The second detection unit updates the lock table according to the memory access request of the processor, including: The second detection unit, when the processor has the permission to execute the second atomic instruction, compares the third storage address pointed to by the reserved load instruction with the first storage addresses respectively corresponding to the at least one entry. When the third storage address pointed to by the reserved load instruction is not the same as each of the first storage addresses respectively corresponding to the at least one entry, it is determined that the comparison result is different; When the comparison result is different, the second detection unit adds a new entry to the lock table, and the added entry is used to represent the third storage address pointed to by the reserved load instruction.

20. The method according to claim 18, wherein The lock table includes at least one entry, and each entry includes a first storage address and failure information of the first storage address. The failure information of the first storage address is used to represent whether the locking state of the first storage address is damaged. When the memory access request of the processor is a conditional store instruction The second detection unit updates the lock table according to the memory access request of the processor, including: When the processor has the permission to execute the second atomic instruction, the second detection unit compares the third storage address pointed to by the conditional store instruction with the first storage addresses corresponding to the at least one entry respectively, and determines a target entry from the at least one entry. The first storage address corresponding to the target entry is the same as the third storage address pointed to by the conditional store instruction. The second detection unit obtains the failure information of the first storage address in the target entry and clears the target entry in the lock table. When the failure information indicates that the locking state of the first storage address is not damaged, the second detection unit returns a success flag. When the failure information indicates that the locking state of the first storage address is damaged, the second detection unit returns a failure flag. Wherein, when the second detection unit returns a success flag, the processor executes the conditional store instruction; when the second detection unit returns a failure flag, the processor cannot execute the conditional store instruction.

Images