Memory device bias control

Abstract

This application relates to bias control of a memory device. The memory system may store an indication of whether data is coherent. In some instances, the indication may be stored as metadata, wherein a first value indicates that the data is incoherent, and a second or third value indicates that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second or third value.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the invention patent application filed on December 27, 2021, with application number 202180095001.7 and title "Bias Control of Memory Device".

[0003] Cross-reference

[0004] This patent application is the national phase application of International Patent Application No. PCT / US2021 / 073118, entitled “Bias Control for a Memory Device,” filed December 27, 2021, by Walker et al., which claims priority to U.S. Patent Application No. 17 / 198,084, entitled “Bias Control for a Memory Device,” filed March 10, 2021, by Walker et al., each of which is assigned to the assignee and each of which is expressly incorporated herein by reference. Technical Field

[0005] The technical field relates to bias control of memory devices. Background Technology

[0006] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored in the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0007] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) may maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0008] Describe a system. The system may include: a memory; and a controller coupled to the memory, wherein the controller is configured to: cache a coherent state of a dataset stored in the memory relative to a host device; and access the memory based at least in part on a bias state of the dataset determined based at least in part on the stored coherent state of the dataset, based on a command that identifies an access operation of the dataset stored in the memory, wherein the bias state is associated with control of access to the dataset by the controller.

[0009] Describe a system. The system may include: a memory; and a controller coupled to the memory, wherein the controller is configured to: cache a coherent state of a dataset stored in the memory relative to a host device; and access the memory based at least in part on a bias state of the dataset determined based at least in part on the stored coherent state of the dataset, based on a command that identifies an access operation of the dataset stored in the memory, wherein the bias state is associated with control of access to the dataset by the host device.

[0010] Describe a method. The method may include: storing a coherent state of a dataset stored in memory relative to a cache of a host device; accessing the memory based at least in part on a bias state of the dataset determined based at least in part on the stored coherent state of the dataset, based on an identification of a command that performs an access operation of the dataset stored in the memory, wherein the bias state is associated with control of access to the dataset by a controller associated with the memory.

[0011] Describe a method. The method may include: storing a coherent state of a dataset stored in memory relative to a cache of a host device; and accessing the memory based at least in part on a bias state of the dataset determined based at least in part on the stored coherent state of the dataset, based on an identification of a command that performs an access operation of the dataset stored in the memory, wherein the bias state is associated with control of access to the dataset by the host device.

[0012] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium may contain instructions that, when executed by a processor of an electronic device, cause the electronic device to: store a coherent state of a dataset stored in memory relative to a cache of a host device; and access the memory, at least in part, based on a bias state of the dataset determined at least in part based on the stored coherent state of the dataset, according to a command identifying an access operation of the dataset stored in the memory, wherein the bias state is associated with control of access to the dataset by a controller associated with the memory. Attached Figure Description

[0013] Figure 1 Examples of systems supporting bias control of memory devices are shown, based on examples disclosed herein.

[0014] Figure 2 Examples of systems supporting bias control of memory devices are shown, based on examples disclosed herein.

[0015] Figure 3 Examples of systems supporting bias control of memory devices are shown, based on examples disclosed herein.

[0016] Figure 4 An example of a process flowchart supporting bias control of a memory device is shown, based on examples disclosed herein.

[0017] Figure 5 An example of a process flowchart supporting bias control of a memory device is shown, based on examples disclosed herein.

[0018] Figure 6 A block diagram of a memory controller that supports bias control of a memory device according to examples disclosed herein is shown.

[0019] Figure 7 and 8 Flowcharts illustrating one or more methods for supporting bias control of memory devices based on examples disclosed herein are shown. Detailed Implementation

[0020] Some interfaces (e.g., the Compute High-Speed ​​Link (CXL) interface) provide mechanisms for bias-based coherence models. Specifically, the CXL specification states that device-attached memory can track bias states to determine whether the device needs to send a request to a host device to resolve coherence when the device (e.g., a processing unit of the device) accesses the memory. The two bias states are host bias, where the device needs to send a request to resolve coherence to the host device; and device bias, where the memory device can access the memory independently of the host device.

[0021] The CXL specification indicates that the device will maintain bias tables for memory blocks (e.g., pages) and transition agents for managing bias transitions. Bias transitions are typically managed by software via commands between the memory device and the host device, and on a per-block basis. However, managing bias transitions on a per-block basis can lead to inefficiencies when portions of a block may have different coherent states.

[0022] This document describes methods and systems for managing bias transitions with relatively finer granularity. The CXL specification describes the metadata that can be maintained for each row of data. One of the metadata fields described is the Meta0-state, which can hold one of three values: Invalid, Any, or Shared. An invalid state indicates that the host does not have a cacheable copy of the row, any state indicates that the host can have a shared, exclusive, or modified copy of the row, and a shared state indicates that the host can have at most a shared copy of the row. The CXL specification therefore instructs that the bias state used to synchronize control for coherence is maintained separately from the Meta0-state indicating cache or coherence states. The Meta0-state for each row can be stored, and the Meta0-state can be stored along with the row data.

[0023] As described herein, the Meta0-state field can be used to track the current bias state. Specifically, depending on various aspects, the Meta0-state Invalid can be equivalent to the device bias, and both Any and Shared can be equivalent to the host bias. Tracking the device-attached media bias at a granularity corresponding to the cache line size of the host device allows the device to change the bias of the media on any component with access to the media. This allows for complete hardware control of the bias and eliminates the need for software to perform the complex task of changing the device-attached media bias for optimal device performance. In some instances, the Meta0-state may be stored in the memory medium along with the data line, or it may be stored only in the device cache (e.g., maintained in the cache only for lines). If it is stored only in the cache, the device will present the Any state when a cache miss occurs. In either case, using the Meta0-state of the CXL specification to track the bias state on a per-cache-line basis improves the overall performance of the memory device while maintaining a relatively simple programming model.

[0024] First, as referenced Figures 1 to 3 The features of this disclosure are described within the context of the system being described. (Referencing...) Figure 4 and 5 The features of this disclosure are described in the context of the process flowchart. (See references...) Figure 6-8 The device diagrams and flowcharts relating to bias control of memory devices are described in further detail, and these and other features of this disclosure are described with reference to the device diagrams and flowcharts.

[0025] Figure 1 An example of a system 100 supporting bias control of a memory device is shown, according to examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0026] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form-factor DIMM (SO-DIMM), or a Non-volatile DIMM (NVDIMM), and other possibilities.

[0027] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing means.

[0028] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a control component configured to cause host system 105 to perform various operations according to instances described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to and read data from memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0029] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 are configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise communicate control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include (but are not limited to) SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), Low Power Dual Data Rate (LPDDR) interfaces, and CXL interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported therebetween the host system controller 106 of host system 105 and the memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0030] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0031] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0032] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0033] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0034] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, in the case of reading from or writing to memory device 130, data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., in the case of reduced latency relative to memory device 130).

[0035] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135 within memory device 130 to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130 managed at least in part by memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device, but other types of managed memory devices are also supported. For example, a managed memory device may include any type or number of volatile or non-volatile memory devices.

[0036] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0037] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0038] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding block set 170, wherein each block 170 may include a corresponding page set 175, and each page 175 may include a set of memory cells.

[0039] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0040] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations can be performed within different planes 165. For example, parallel operations can be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0041] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0042] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0043] System 100 may include any number of non-transitory computer-readable media that support bias control of the memory device. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), these instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0044] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0045] In some instances, host system 105 may include a cache containing one or more pages (e.g., one or more pages for storing data). Each page may contain one or more rows associated with a certain amount of data. As described herein, memory system controller 115 may be configured to track the coherence of data shared between host system 105 and memory system 110. For example, memory system controller 115 may track the coherence of data shared between memory device 130-a or memory device 130-b and host system 105. Data coherence may involve indicating one of three states: whether a coherent copy of the data does not exist at host system 105 and memory system 110, or whether a shared, exclusive, or modified copy of the data exists.

[0046] Memory system 110 may be an example of a CXL device, and memory system controller 115 may be an example of a processing unit configured to access memory devices 130-a and 130-b. For example, memory system controller 115 may be configured to access memory devices 130-a and 130-b according to a host bias mode or a device bias mode. When operating according to device bias mode, memory system controller 115 may access memory devices 130-a or 130-b independently of host system 105 (e.g., after receiving an access request or access command). Conversely, when operating according to host bias mode, memory system controller 115 may access memory devices 130-a or 130-b via host system 105. Furthermore, when one or more pages are associated with a host bias mode, the host may modify the version of said one or more pages maintained by the host without notifying memory system controller 115.

[0047] In some instances, each row of data stored in memory device 130-a or memory device 130-b may be associated with an optional 2-bit Meta0 field. As described herein, the 2-bit Meta0 field can be used to indicate the bias state of the associated data based on the three coherent states. For example, when data is associated with a first coherent state (e.g., an "invalid" state; in which case no coherent copy of the data exists), the Meta0 field may indicate operation according to the device bias mode. Alternatively, when data is associated with a second coherent state (e.g., an "any" state; in which case a coherent copy of the data exists) or a third coherent state (e.g., a "shared" state; in which case a coherent copy of the data exists), the Meta0 field may indicate operation according to the host bias mode. Therefore, using the Meta0 state to track device bias allows for tracking bias states with greater granularity.

[0048] Figure 2 An example of a system 200 supporting bias control of a memory device is shown, according to examples disclosed herein. System 200 may be a reference. Figure 1 An example of system 100 as described in the references thereof. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may be implemented as described in the references. Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0049] As described herein, memory system 210 may include memory device 240 for storing data transferred between memory system 210 and host system 205, for example, in response to receiving an access command from host system 205. Memory device 240 may include references Figure 1 The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0050] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from memory device 240, for example, for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. The memory controller 230 may communicate directly with memory device 240 or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may implement a reference... Figure 1 Aspects of the local controller 135 described.

[0051] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data being transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used, for example, by translating data between the host system 205 and the memory device 240 as shown by the data path 250, and may be collectively referred to as the data path components.

[0052] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and once the burst stops, the buffered data can be stored or emitted (or both). Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM) or hardware accelerators or both to allow for fast storage and retrieval of data in and out of buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0053] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data from an additional access command). Furthermore, buffer 225 can be a non-cached buffer. That is, the host system 205 may not read data directly from buffer 225. For example, a read command can be added to a queue without requiring an address to be matched against an address already in buffer 225 (e.g., no cached address matching or lookup operation is needed).

[0054] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be as described in reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0055] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. For example, this may be advantageous if the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, if used, the queues may be located anywhere within the memory system 210.

[0056] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 through data path components instead of bus 235. Memory system controller 215 can control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0057] If host system 205 issues an access command to memory system 210, interface 220 can receive the command, for example, according to a protocol (e.g., UFS protocol, eMMC protocol, CXL protocol). Therefore, interface 220 can be considered as the front end of memory system 210. Upon receiving each access command, interface 220 can transmit the command to memory system controller 215, for example, via bus 235. In some cases, interface 220 can add each command to command queue 260 to transmit the command to memory system controller 215.

[0058] The memory system controller 215 may determine that an access command has been received based on communication from interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving a command from command queue 260. After, for example, the command has been retrieved from command queue 260 by memory system controller 215, the command may be removed from the command queue. In some cases, the memory system controller 215 may cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0059] Once an access command has been received, the memory system controller 215 can execute the access command. For a read command, this could mean obtaining data from the memory device 240 and transmitting the data to the host system 205. For a write command, this could mean receiving data from the host system 205 and moving the data to the memory device 240.

[0060] In either case, the memory system controller 215 may use the buffer 225 for (in particular) temporary storage of data received from or sent to the host system 205. The buffer 225 can be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0061] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available for storing the data associated with the write command, for example via firmware (e.g., controller firmware).

[0062] In some cases, buffer queue 265 can be used to control a stream of commands associated with data stored in buffer 225, the stream of commands including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating the location in buffer 225 that stores data associated with each command can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least some portions of the access commands can be processed in parallel.

[0063] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to deliver" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to deliver the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data delivery to buffer 225 has been completed.

[0064] Once written data has been stored in buffer 225 via interface 220, the data can be transferred out of buffer 225 and stored in memory device 240. This can be done using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the data transfer to memory device 240 has been completed.

[0065] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can (e.g., via bus 235) push write commands from buffer queue 265 to memory queue 270 for processing. Memory queue 270 can contain entries for each access command. In some instances, memory queue 270 can additionally contain: a buffer pointer (e.g., an address) indicating where in buffer 225 the data associated with the command is stored; and a memory pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, memory controller 230 can obtain the location within buffer 225 from which data is to be retrieved, either from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the location of data to be stored in memory device 240 (e.g., performing wear leveling, garbage collection, etc.). Entries can be added to memory queue 270, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 270, for example, via the storage controller 230 or the memory system controller 215.

[0066] In order to process a read command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0067] In some cases, buffer queue 265 can be used to assist in buffering data associated with read commands in a manner similar to that discussed above with respect to write commands. For example, if buffer 225 has sufficient space to store read data, memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235 whether data transfer to buffer 225 has been completed.

[0068] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of data to be retrieved from the memory device 240 from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location of data to be stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of data to be stored in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0069] Once data has been stored in buffer 225 by storage controller 230, it can be transferred out of buffer 225 and sent to host system 205. For example, storage system controller 215 can cause interface 220 to retrieve data from buffer 225 using data path 250 and transmit the data to host system 205, for example, according to a protocol (e.g., UFS protocol, eMMC protocol, CXL protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that data transmission to host system 205 has been completed.

[0070] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in, first-out order of the command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moving into and stored in buffer 225, the command can remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been passed from buffer 225), the command can be removed from buffer queue 265, for example, by the memory system controller 215. If the command is removed from buffer queue 265, the address where the data associated with the command was previously stored can be used to store the data associated with the new command.

[0071] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control operations (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more adjacent LBAs may correspond to non-adjacent physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0072] In some instances, host system 205 may include a cache containing one or more pages (e.g., one or more pages for storing data). Each page may contain one or more rows associated with a certain amount of data. As described herein, memory system controller 215 may be configured to track the coherence of data shared between host system 205 and memory system 210. For example, memory system controller 215 may track the coherence of data shared between device memory (not shown) and host system 205 (not shown). For example, one or more of the memory devices 240 may be CXL devices configured to access data stored in various device-accessible memories (e.g., device memory). Memory system controller 215 may track data coherence, which may involve indicating one of three states: whether a coherent copy of the data does not exist at host system 205 and memory system 210, or whether a shared, exclusive, or modified copy of the data exists.

[0073] Memory system 210 may be an example of a CXL device that can be configured to access device memory (memory device 240). For example, a CXL device may include processing means (not shown) configured to access device memory according to host bias mode or device bias mode. When operating according to device bias mode, memory system controller 215 may access device memory independently of host system 205 (e.g., after receiving an access request or access command). Conversely, when operating according to host bias mode, memory system controller 215 may access device memory via host system 205. Therefore, when operating according to host bias mode, host system 205 may be configured to access device memory for the corresponding CXL device.

[0074] In some instances, each line of data stored in the device memory can be associated with an optional 2-bit Meta0 field. As described herein, the 2-bit Meta0 field can be used to indicate the bias state of the associated data based on the three coherent states. For example, when data is associated with a first coherent state (e.g., an "invalid" state; in which case no coherent copy of the data exists), the Meta0 field can indicate operation according to the device bias mode. Alternatively, when data is associated with a second coherent state (e.g., an "any" state; in which case a coherent copy of the data exists) or a third coherent state (e.g., a "shared" state; in which case a coherent copy of the data exists), the Meta0 field can indicate operation according to the host bias mode. Therefore, using the Meta0 state to track device bias allows for tracking bias states with greater granularity.

[0075] Figure 3 An example of a system 300 supporting bias control of a memory device is shown, based on examples disclosed herein. System 300 may include a memory system 305 and a host device 310. Memory system 305 may be coupled to host device 310 via interface 315, which may be a CXL interface. Memory system 305 may include device memory 320, cache 325, controller 330, and processing unit 335, and host device 310 may include cache 340. In some instances, system 300 may be configured to use one or more metadata fields (e.g., Meta0-state) to track the coherent state of data. Furthermore, using Meta0-state to track bias state on a per-cache-line basis can improve the overall performance of memory system 305 while maintaining a relatively simple programming model.

[0076] The memory system 305 may be a CXL device. The device memory 320 may be accessed by one or more accelerators, which include or may be associated with a processing unit 335. Figure 3The processing unit 335 and controller 330 shown herein may be a single logic component formed on the same field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). However, in some instances, the controller 330 and processing unit 335 may be separate components. For example, processing unit 335 may be associated with a graphics processing unit (GPU) or general-purpose graphics processing unit (GPGPU) of memory system 305. Processing unit 335 may be configured to issue signaling and / or commands for accessing device memory 320 to controller 330. As described herein, controller 330 may access device memory 320 independently of host device 310 in device bias state, while controller 330 may access device memory 320 via host device 310 in host bias state.

[0077] In some instances, host device 310 may include cache 340. Cache 340 may contain a collection of pages, each of which may contain 4kB of data. Furthermore, each page may contain one or more blocks, which may be referred to as cache lines, and each cache line may contain 64B of data. Although the size of each page and cache line is intended for illustrative purposes only, and each page and cache line may be configured to store different amounts of data, memory system 305 may be configured to track bias states on a per-cache-line basis using a Meta0-state rather than a page-based bias table. That is, using a Meta0-state bias tracking device allows for tracking bias states with greater granularity.

[0078] Device memory 320 can be configured to store data accessible by processing unit 335 (e.g., via controller 330) and host device 310. Because the data is accessible by both processing unit 335 and host device 310 (e.g., the data is shared), tracking data coherence is necessary. That is, it is necessary for both processing unit 335 and host device 310 to know whether the data in cache 340 is coherent with the corresponding data (for the same address) in device memory 320. To track cache coherence, three states of cache coherence can be maintained and tracked using metadata. For example, a first state can be associated with an "invalid" state—for example, host device 310's cache 340 does not have a cacheable copy of the data. A second state can be associated with an "any" state—for example, host device 310's cache 340 may have a shared, exclusive, or modified copy of the data. A third state can be associated with a "shared" state—for example, host device 310's cache 340 may have at most a shared copy of the data. As the coherence state of the data changes, the updated metadata associated with the coherence state can be stored in the device memory 320.

[0079] In some instances, data stored in device memory 320 can be accessed according to either device bias mode or host bias mode. Host bias mode prioritizes coherent accesses from host device 310 to device memory 320. Host bias mode can be used during job submission (when data is being written from host device 310 to device memory 320) and during job completion (when data is being read from device memory 320 by host device 310). In host bias mode, device memory 320 may behave as a memory attached to host device 310 to the memory system (or to processing unit 335). If processing unit 335 needs to access device memory 320 while operating in host bias mode, the access operation is first processed by sending a request (e.g., command; signaling) to host device 310 via controller 330.

[0080] Conversely, in device bias mode, processing unit 335 can directly access device memory 320. That is, processing unit 335 can access device memory 320 without any interaction with host device 310. Therefore, if processing unit 335 needs to access device memory 320 while operating in device bias mode, the access operation can be handled by directly accessing device memory 320 through controller 330.

[0081] The CXL specification provides an optional 2-bit Meta0 field that can be associated with the device attachment medium. According to the various aspects described herein, the 2-bit Meta0 field can be used to deliver the coherence state of data (e.g., data associated with the size of a cache line of cache 340), and this coherence state can be used to determine the bias state of the associated data. In some instances, the Meta0 field can be configured to store a first value (e.g., a first bit value) associated with an “invalid” coherence state. When the Meta0 field contains the first value, the data associated with the Meta0 field can be accessed according to the device bias mode. Alternatively, the Meta0 field can be configured to store a second value (e.g., a second bit value) and a third value (e.g., a third bit value) associated with “shared” and “any” states. When the Meta0 field contains either the second or third value, the data associated with the Meta0 field can be accessed according to the host bias mode.

[0082] In some instances, the corresponding Meta0 field may be associated with each row of data stored in device memory 320, and thus can be determined when processing unit 335 needs to access device memory 320. For example, processing unit 335 may transmit an access request (e.g., a command; signaling) to controller 330, and controller may determine the Meta0 value of the associated data. Depending on the Meta0 value (e.g., coherence state), controller 330 may be able to directly access the data row (e.g., according to device bias mode), or may transmit a request (e.g., a command; signaling) to host device 310 for resolving the coherence associated with the data (e.g., according to host bias mode).

[0083] The host device 310 may periodically update the coherence state of the data and / or the Meta0 field associated with the data. For example, if the host device 310 performs any operation that affects the coherence of the data, the host device 310 may transmit the changes to the memory system 305. In some instances, the host device 310 may transmit the updated coherence state to the memory system 305 (e.g., explicitly or implicitly from an access command), and the controller 330 may use the updated coherence state to update the Meta0 field of the associated data stored in the device memory 320 or cache 325. In other instances, the host device 310 may transmit the updated Meta0 field to the memory system 305, and the controller 330 may update the Meta0 field of the associated data stored in the device memory 320 or cache 325.

[0084] Alternatively, cache 325 can be used to determine whether data is accessed based on device bias state or host bias state. For example, data and the associated Meta0 field may be stored in cache 325. That is, in some instances, the Meta0 field may be stored only with cached data rather than data stored in device memory 320. When processing unit 335 needs to access data (e.g., when processing unit 335 transmits a command for data to controller 330), controller 330 may determine whether the data is stored in cache 325. If the data is stored in cache (e.g., when a cache "hit" occurs), the data may be accessed based on the coherent state indicated by the Meta0 field (e.g., by associating the coherent state with the bias state). In other instances, if the data is not stored in cache (e.g., when a cache "hit" occurs), controller 330 may assume that the data is associated with the host bias state. Accordingly, when a cache miss occurs, the processing unit 335 can access the device memory 320 via the host device 310. Whether the Meta0 field is stored in the device memory 320 or in the cache 325, tracking the bias state on a per-cache-line basis using the Meta0 state can improve the overall performance of the memory system 305 while maintaining a relatively simple programming model.

[0085] Figure 4 An example of a process flowchart 400 supporting bias control of a memory device according to examples disclosed herein is shown. Process flowchart 400 may illustrate the operation of a processing unit 405, a controller 410, a device memory 415, and a cache 420. In some instances, the processing unit 405, the controller 410, the device memory 415, and the cache 420 may be respectively relative to… Figure 3 Examples of the processing unit 335, controller 330, device memory 320, and cache 325 of the described memory system 305 are shown. A process flowchart 400 illustrates the use of the Meta0 state to track bias states on a per-cache-line basis, which improves the overall performance of the memory system 305 while maintaining a relatively simple programming model.

[0086] At 425, the coherent state of a data row can be stored at device memory 415. In some instances, the coherent states of multiple data rows can be stored. For example, the coherent state of each data row can be stored in device memory 415. As described herein, the coherent state may correspond to an "invalid," "any," or "shared" state and may be stored in the Meta0 field associated with the corresponding data row. In other instances, the coherent state of the data can be updated at 425. That is, the coherent state of one or more data rows may have been previously stored in device memory 415, but the stored state can be updated due to a change in the coherent state. In any example, the coherent state stored at 425 can be used to determine the bias state associated with the data. Although shown as being stored at device memory 415, the coherent state may additionally or alternatively be stored at cache 420, as described below.

[0087] At 430, processing unit 405 may determine whether to access a data line. For example, processing unit 405 may determine whether to read a data line from device memory 415 or to write a data line to device memory 415. For illustrative purposes, the data line may be stored at device memory 415. However, in some instances, the data line may be stored in cache 420 (e.g., data may be cached), and processing unit 405 or controller 410 may determine whether the data is stored in cache 420 or device memory 415.

[0088] At 435, processing unit 405 may send signaling to controller 410. The signaling may be in response to determining access to a data line (e.g., at 425), and may contain a command (e.g., a read command, a write command), a request, or another type of communication. The signaling may indicate to controller 410 the type of access operation and the address (e.g., a memory address) of the device memory 415 for the data line.

[0089] At 440, controller 410 may send a signaling message to cache 420. The signaling message may indicate the type of access operation and the address of device memory 415 (e.g., at 435), and may contain a command (e.g., a read command), a request, or another type of communication. The signaling message may initiate a read on cache 420 to determine whether an associated data line is stored in cache 420.

[0090] At 445, controller 410 may receive signaling from cache 420. This signaling may be in response to a signaling transmitted at 440 and may indicate whether a data line is stored in the cache (e.g., cache “hit” or cache “miss”). For illustrative purposes only, the signaling may indicate a cache “miss”.

[0091] At 450, controller 410 may send signaling to device memory 415. The signaling may be in response to a cache miss indication, and may contain a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on device memory 415.

[0092] At 455, controller 410 may receive signaling from device memory 415. This signaling may be in response to signaling transmitted at 450 and may include a data line read from device memory 415. Furthermore, the signaling may include a Meta0 state associated with the data line. As described herein, the Meta0 state may indicate a first value corresponding to an "invalid" coherent state, a second value corresponding to a "shared" coherent state, or a third value corresponding to an "any" state. Alternatively, the Meta0 state may not be stored in device memory 415, and controller 410 may present the Meta0 state as "any" or "shared" after a cache miss.

[0093] At 460, controller 410 can determine the bias state of a data line read from device memory 415. Controller 410 can determine the bias state of the data line in response to signaling received by controller 410 (e.g., at 455). For example, the signaling may indicate that the Meta0 field contains a first value corresponding to an "invalid" coherent state. Therefore, controller 410 can determine the device bias state of the data line stored at the first memory address and can complete the access operation without any interaction from the host device.

[0094] In other instances, signaling (e.g., at 435) may indicate a write command at a second memory address of device memory 415. In these instances, controller 410 may determine the bias state for writing data to the second memory address based on the Meta0 field associated with the data row. For example, controller 410 may send signaling to device memory 415 to read a data row corresponding to the second memory address from device memory 415. In response, controller 410 may receive signaling indicating the Meta0 state of the data row. If the Meta0 state corresponds to an "invalid" coherent state, controller 410 may operate according to the device bias. In this example, controller 410 may write data to the second memory address of device memory 415 without any interaction from the host device.

[0095] In other instances, instead of sending signaling to cache 420 and / or device memory 415, controller 410 may maintain a table for tracking the Meta0 state of one or more data rows. For example, for both read and write operations, controller 410 may track Meta0 values ​​on a per-row basis, such that when a processing unit determines that data access is needed (e.g., at 430), the controller can determine the Meta0 state based on the table. Accordingly, based on the Meta0 state, controller 410 may operate in device bias mode or host bias mode.

[0096] At 465, data can be transmitted to processing unit 405. In some instances, data can be transmitted in response to determining the bias state of the data (e.g., at 450). In some instances, data can be transmitted directly to processing unit 405, while in others, data can be transmitted to controller 410, and controller 410 can transmit data to processing unit 405.

[0097] At 470, processing unit 405 may determine to access a data line (e.g., another data line). For example, processing unit 405 may determine to read a data line stored in cache 420 (e.g., a cached data line). For illustrative purposes, the data line may be stored in cache 420. However, in some instances, the data line may not be stored in cache 420 (e.g., the data may bypass the cache), resulting in a cache "miss". When a cache "miss" occurs, controller 410 may determine to access the data according to the host bias mode.

[0098] At 475, processing unit 405 may send signaling to controller 410. The signaling may be in response to determining access to a data line (e.g., at 465), and may contain a command (e.g., a read command, a write command), a request, or another type of communication. The signaling may indicate to controller 410 the type of access operation and the address of device memory 415 (e.g., a memory address).

[0099] At 480, controller 410 may send a signaling message to cache 420. The signaling message may indicate the type of access operation and the address of device memory 415 (e.g., at 475), and may contain a command (e.g., a read command), a request, or another type of communication. The signaling message may initiate a read on cache 420 to determine whether an associated data line is stored in cache 420.

[0100] At 485, controller 410 may receive signaling from cache 420. This signaling may be in response to signaling transmitted at 440 and may indicate whether a data line is stored in the cache (e.g., cache “hit” or cache “miss”). For illustrative purposes only, the signaling may indicate a cache “hit.” Accordingly, the signaling may include a data line and an associated Meta0 state, which may indicate a first value corresponding to an “invalid” coherent state, a second value corresponding to a “shared” coherent state, or a third value corresponding to an “any” state.

[0101] At 490, controller 410 can determine the bias state of a data line read from cache 420. Controller 410 can determine the bias state of the data line in response to signaling received by controller 410 (e.g., at 485). For example, the signaling may indicate that the Meta0 field contains a first value corresponding to an "invalid" coherent state. Therefore, controller 410 can determine the device bias state of the data line stored in the cache and can complete the access operation without any interaction from the host device.

[0102] At position 495, data can be transmitted to processing unit 405. In some instances, data can be transmitted in response to a signaling sent from controller 410 to the processing unit (e.g., at position 475). In some instances, data can be transmitted directly to processing unit 405, while in others, data can be transmitted to controller 410, which can then transmit the data to processing unit 405. Whether the Meta0 field is stored in device memory 415, cache 420, or tracked by controller 410, tracking the bias state on a per-cache-line basis using the Meta0 state improves the overall performance of the memory system while maintaining a relatively simple programming model.

[0103] Figure 5 An example of a process flowchart 500 supporting bias control of a memory device is shown, based on examples disclosed herein. Process flowchart 500 may show examples as described in the references. Figure 3 The operation of memory system 501 and host device 525, examples of memory system 305 and host device 310, is described. Memory system 501 may include processing unit 505, controller 510, device memory 515, and cache 520. Process flowchart 500 may illustrate tracking bias states on a per-cache-line basis using Meta0-states, which improves the overall performance of memory system 501 while maintaining a relatively simple programming model.

[0104] At 530, the coherent state of a data row can be stored in device memory 515. In some instances, the coherent states of multiple data rows can be stored. For example, the coherent state of each data row can be stored in device memory 515. As described herein, the coherent state can correspond to an "invalid," "any," or "shared" state and can be stored in the Meta0 field associated with the corresponding data row. In other instances, the coherent state of the data can be updated at 530. That is, the coherent state of one or more data rows may have been previously stored in device memory 415, but the stored state can be updated due to a change in the coherent state. In any example, the coherent state stored at 530 can be used to determine the bias state associated with the data.

[0105] At 535, processing unit 505 may determine whether to access a data line. For example, processing unit 505 may determine whether to read a data line from device memory 515 or to write a data line to device memory 515. For illustrative purposes, the data line may be stored in device memory 515. However, in some instances, the data line may be stored in cache 520 (e.g., data may be cached), and processing unit 505 or controller 510 may determine whether the data is stored in cache 520 or device memory 515.

[0106] At 540, processing unit 505 may send signaling to controller 510. The signaling may be in response to determining access to a data line (e.g., at 535), and may contain a command (e.g., a read command, a write command), a request, or another type of communication. The signaling may indicate to controller 510 the type of access operation and the address of device memory 515 (e.g., a memory address).

[0107] After 540, controller 510 can send signaling to cache 520, which is not in... Figure 5 The signaling may be in response to an indication of the type of access operation and the address of device memory 515 (e.g., at 540), and may contain a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on cache 520 to determine whether an associated data line is stored in cache 520.

[0108] After transmitting the signaling to cache 520, controller 510 can receive the signaling from cache 520, which it does not... Figure 5 The signaling can indicate whether a data line is stored in the cache (e.g., cache "hit" or cache "miss"). For illustrative purposes only, this signaling indicates a cache "miss". In some instances, after a cache "miss", the controller 510 may then operate in host bias mode.

[0109] After receiving the signaling, the controller 510 can transmit the signaling to the device memory 515, which is not in the memory. Figure 5 The signaling may be in response to a cache miss indication, and may contain a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on device memory 515.

[0110] After transmitting signaling to device memory 515, controller 510 can receive signaling from device memory 515, which is not in the memory. Figure 5 The signaling may include a data line read from device memory 515. Furthermore, the signaling may include a Meta0 state associated with the data line. As described herein, the Meta0 state may indicate a first value corresponding to an "invalid" coherent state, a second value corresponding to a "shared" coherent state, or a third value corresponding to an "any" state.

[0111] At 545, controller 510 may determine the bias state of a data line stored in device memory 515 in response to receiving a data line and an associated Meta0 state. Controller 510 may determine the bias state based on the Meta0 state. For example, the Meta0 field may indicate a first value corresponding to an "invalid" coherent state and generate a device bias for the data line. Alternatively, the Meta0 field may indicate a second value corresponding to a "shared" state or a third value corresponding to an "any" state, both of which generate a host bias for the data line. For illustrative purposes only, controller 510 may determine the host bias state of a data line stored in a first memory address.

[0112] At 550, controller 510 may send signaling to host device 525. This signaling may be in response to determining access to device memory 415 according to a host bias mode (e.g., at 545), and may include a command (e.g., a read command), a request, or another type of communication. For example, the signaling may include a request from host device 525 to resolve the coherence of a data line, or it may include a request from host device 525 to controller 510 to grant access to a data line.

[0113] At 555, host device 525 may transmit signaling to controller 510 (or to another component of memory system 501). The signaling may be in response to signaling transmitted to host device 525 (e.g., at 550), and may contain commands (e.g., a second command, a read command), requests, or other types of communication. For example, a second command may resolve data coherence by granting controller 510 direct access to data rows.

[0114] In other instances, signaling (e.g., at 540) may indicate a write command at a second memory address of device memory 515. In these instances, controller 510 may determine the bias state for writing data to the second memory address based on the Meta0 field associated with the data row. For example, controller 510 may send signaling to device memory 515 to read a data row corresponding to the second memory address from device memory 515. In response, controller 510 may receive signaling indicating the Meta0 state of the data row. If the Meta0 state corresponds to an "invalid" coherent state, controller 510 may operate according to the device bias. In this instance, controller 510 may write data to the second memory address of device memory 515 without any interaction from the host device.

[0115] In other instances, instead of sending signaling to cache 520 and / or device memory 515, controller 510 may maintain a table for tracking the Meta0 state of one or more data rows. For example, for both read and write operations, controller 510 may track Meta0 values ​​on a per-row basis, such that when a processing unit determines that data access is needed (e.g., at 530), the controller can determine the Meta0 state based on the table. Accordingly, based on the Meta0 state, controller 410 may operate in device bias mode or host bias mode.

[0116] At 560, data can be transmitted to processing unit 505. In some instances, data can be transmitted in response to a signaling transmitted from host device 525 to controller 510 (e.g., at 555). In some instances, data can be transmitted directly to processing unit 505, while in other instances, data can be transmitted to controller 510, and controller 510 can transmit data to processing unit 505.

[0117] At 565, processing unit 505 may determine to access a data line (e.g., another data line). For example, processing unit 505 may determine to read a data line that can be stored in cache 520 (e.g., a cached data line). For illustrative purposes, the data line may not be stored in cache 520. However, in some instances, the data line may be stored in cache 520 (e.g., data may be cached), resulting in a cache "hit". When a cache "hit" occurs, controller 510 may determine to access the data based on a coherent state associated with the data line (e.g., a Meta0 field).

[0118] At 570, processing unit 505 may send signaling to controller 510. The signaling may be in response to determining access to a data line (e.g., at 565), and may contain a command (e.g., a read command, a write command), a request, or another type of communication. The signaling may indicate to controller 510 the type of access operation and the address of device memory 515 (e.g., a memory address).

[0119] After 570, controller 510 can send signaling to cache 520, which is not in Figure 5 The signaling may be in response to an indication of the type of access operation and the address of device memory 515 (e.g., at 540), and may contain a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on cache 520 to determine whether an associated data line is stored in cache 520.

[0120] After transmitting the signaling to cache 520, controller 510 can receive the signaling from cache 520, which it does not... Figure 5 The signaling may indicate whether a data line is stored in the cache (e.g., cache "hit" or cache "miss"). For illustrative purposes only, this signaling indicates a cache "hit". Furthermore, the signaling may include a data line read from cache 520 and may include a Meta0 state associated with the data line. As described herein, the Meta0 state may indicate a first value corresponding to an "invalid" coherent state, a second value corresponding to a "shared" coherent state, or a third value corresponding to an "any" state.

[0121] At 575, controller 510 may determine the bias state of a data line stored in device memory 520 in response to receiving a data line and an associated Meta0 state. Controller 510 may determine the bias state based on the Meta0 state. For example, the Meta0 field may indicate a first value corresponding to an "invalid" coherent state and generate a device bias for the data line. Alternatively, the Meta0 field may indicate a second value corresponding to a "shared" state or a third value corresponding to an "any" state, both of which generate a host bias for the data line. For illustrative purposes only, controller 510 may determine the host bias state of a data line stored in cache 520.

[0122] At 580, controller 510 may send signaling to host device 525. This signaling may be in response to determining access to cache 520 based on a host bias mode (e.g., at 575), and may include a command (e.g., a read command), a request, or another type of communication. For example, the signaling may include a request from host device 525 to resolve the coherence of a data line, or it may include a request from host device 525 to controller 510 to grant access to a data line.

[0123] At 585, host device 525 may transmit signaling to controller 510 (or to another component of memory system 501). The signaling may be in response to signaling transmitted to host device 525 (e.g., at 580), and may contain commands (e.g., a second command, a read command), requests, or other types of communication. For example, a second command may resolve data coherence by granting controller 510 direct access to data rows.

[0124] At point 590, data can be transmitted to processing unit 505. In some instances, data can be transmitted directly to processing unit 505, while in others, data can be transmitted to controller 510, which can then transmit the data to processing unit 505. Whether the Meta0 field is stored in device memory 515, cache 520, or tracked by controller 510, tracking bias states on a per-cache-line basis using the Meta0 state improves the overall performance of the memory system while maintaining a relatively simple programming model.

[0125] Figure 6 A block diagram 600 illustrates a memory controller 620 that supports bias control of a memory device according to an example disclosed herein. The memory controller 620 may be as described in the reference... Figures 1 to 5 Examples of aspects of the described memory controller. Memory controller 620 or its various components may be examples of components used to perform various aspects of bias control of the memory device as described herein. For example, memory controller 620 may include coherence component 625, memory access component 630, transmit component 635, receive component 640, determine component 645, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0126] Coherence component 625 may be configured or otherwise support components for coherent state of a dataset stored in memory relative to a cache of a host device. In some instances, coherence component 625 may be configured or otherwise support components for coherent state of a dataset stored in memory relative to a cache of a host device.

[0127] The memory access component 630 may be configured or otherwise support a component for accessing the memory based on a bias state of the dataset determined at least in part based on a stored coherent state of the dataset, based on a command for performing an access operation on the dataset stored in the memory, wherein the bias state is associated with control of the access to the dataset by a controller associated with the memory.

[0128] In some instances, memory access component 630 may be configured or otherwise supported for accessing memory at least partially based on bias states independent of the host device. In some instances, the command includes a read command, and memory access component 630 may be configured or otherwise supported for accessing a dataset stored in a cache at least partially based on determining that the dataset is stored in a cache associated with the memory.

[0129] In some instances, memory access component 630 may be configured or otherwise support means for accessing memory based at least in part on a bias state of the dataset determined based at least in part on a stored coherent state of the dataset, based on a command that identifies an access operation performed on the dataset stored in memory, wherein the bias state is associated with control of access to the dataset by the host device. In some instances, the command includes a read command, and memory access component 630 may be configured or otherwise support means for accessing memory for the dataset based at least in part on receiving a second command from the host device.

[0130] In some instances, the coherent state of the dataset is stored independently of the command, and the transmitting component 635 may be configured or otherwise supported for means of transmitting an instruction to the host device, at least in part, for an access operation to be performed on the dataset, based on determining the bias state processing command. In some instances, the transmitting component 635 may be configured or otherwise supported for means of transmitting a dataset received from the host device to memory, at least in part, based on receiving the dataset from the host device.

[0131] In some instances, the coherent state of the dataset is stored independently of the command, and the receiving component 640 may be configured or otherwise supported to receive, at least in part, a second command from the host device indicating direct access to the dataset for the access operation, based on an instruction to transmit the access operation.

[0132] In some instances, the command includes a read command, and the determining component 645 may be configured or otherwise supported for determining whether a dataset is stored in a cache associated with memory.

[0133] In some instances, the memory is configured to store a first value associated with a first coherent state of the dataset, a second value associated with a second coherent state of the dataset, or a third value associated with a third coherent state of the dataset. In some instances, the first value indicates that the dataset is incoherent. In some instances, the second and third values ​​indicate that the dataset is coherent, wherein the controller is configured to process the command based at least in part on the first value of the dataset stored in the memory according to the bias state.

[0134] In some instances, the dataset is associated with a first quantity of data. In some instances, a cache line of a host device coupled to memory is configured to store the first quantity of data. In some instances, the bias state corresponds to a first bias state. In some instances, a second bias state is associated with control of access to the dataset by the host device. In some instances, memory is configured to store a first value associated with a first coherent state of the dataset, a second value associated with a second coherent state of the dataset, or a third value associated with a third coherent state of the dataset.

[0135] In some instances, the first value indicates that an invalid version of the dataset is stored in the host device's cache. In some instances, the second value indicates that a shared or exclusive version of the dataset is stored in the host device's cache. In some instances, the third value indicates that a shared version of the dataset is stored in the host device's cache. In some instances, the second and third values ​​indicate that the dataset is coherent. In some instances, the command is processed based on the bias state, at least in part, based on the second or third value of the dataset stored in memory.

[0136] In some instances, the dataset is associated with a first quantity of data. In some instances, a cache line of a host device coupled to memory is configured to store the first quantity of data. In some instances, a first bias state is associated with control of access to the dataset by a controller. In some instances, the bias state corresponds to a second bias state.

[0137] Figure 7 A flowchart illustrating a method 700 for supporting bias control of a memory device according to an example disclosed herein is provided. Operation of method 700 may be implemented by a memory controller or its components as described herein. For example, operation of method 700 may be implemented by, as referenced herein... Figures 1 to 5 The memory controller described in section 6 performs the functions described herein. In some instances, the memory controller may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory controller may use dedicated hardware to perform aspects of the described functions.

[0138] At 705, the method may include coherent states of a dataset stored in memory relative to a cache of the host device. The operation at 705 can be performed according to examples disclosed herein. In some instances, aspects of the operation at 705 may be derived from references... Figure 6 The described coherent component 625 is executed.

[0139] At 710, the method may include accessing the memory based at least in part on a bias state of the dataset determined based at least in part on a stored coherent state of the dataset, based on a command that identifies an access operation of the dataset stored in the memory, wherein the bias state is associated with control of access to the dataset by a controller associated with the memory. The operation of 710 may be performed according to examples disclosed herein. In some examples, aspects of the operation of 710 may be as described in references... Figure 6 The memory access component 630 described herein is executed.

[0140] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: storing a coherent state of a dataset stored in memory relative to a cache of a host device; and accessing memory based at least in part on a bias state of the dataset determined based at least in part on the stored coherent state of the dataset, based on an identification of a command to perform an access operation on the dataset stored in memory, wherein the bias state is associated with control of access to the dataset by a controller associated with the memory.

[0141] Some examples of the methods 700 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for accessing memory, at least in part, based on bias states independently of the host device.

[0142] In some instances of the method 700 and apparatus described herein, the command includes a read command, and the method, apparatus, and non-transitory computer-readable medium may include additional operations, features, circuitry, logic, components, or instructions for determining that a dataset can be stored in a cache associated with memory, and accessing the dataset stored in the cache, at least in part, based on the determination that the dataset can be stored in the cache associated with memory.

[0143] In some instances of the method 700 and apparatus described herein, the memory may be configured to store a first value that can be associated with a first coherent state of the dataset, a second value that can be associated with a second coherent state of the dataset, or a third value that can be associated with a third coherent state of the dataset.

[0144] In some instances of the method 700 and device described herein, a first value indicates that the dataset may be incoherent, and a second and third value indicate that the dataset may be coherent, wherein the controller may be configured to process the command based at least in part on the first value of the dataset stored in memory according to the bias state.

[0145] In some instances of the method 700 and device described herein, a dataset may be associated with a first quantity of data, and a cache line of a host device coupled to memory may be configured to store the first quantity of data.

[0146] In some instances of the method 700 and device described herein, the bias state corresponds to a first bias state, and the second bias state may be associated with control of access to the dataset by the host device.

[0147] Figure 8 A flowchart illustrating a method 800 for supporting bias control of a memory device according to an example disclosed herein is provided. Operation of method 800 may be implemented by a memory controller or its components as described herein. For example, operation of method 800 may be performed by, as referenced... Figures 1 to 5 The memory controller described in section 6 performs the functions described herein. In some instances, the memory controller may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory controller may use dedicated hardware to perform aspects of the described functions.

[0148] At 805, the method may include coherent states of a dataset stored in memory relative to a cache of the host device. The operation of 805 can be performed according to examples disclosed herein. In some instances, aspects of the operation of 805 may be referenced... Figure 6 The described coherent component 625 is executed.

[0149] At 810, the method may include accessing the memory based at least in part on a bias state of the dataset determined based at least in part on a stored coherent state of the dataset, based on a command that identifies an access operation of the dataset stored in memory, wherein the bias state is associated with control of access to the dataset by a host device. The operation of 810 may be performed according to examples disclosed herein. In some examples, aspects of the operation of 810 may be as described in references... Figure 6 The memory access component 630 described herein is executed.

[0150] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: storing a coherent state of a dataset stored in memory relative to a cache of a host device; and accessing the memory based at least in part on a bias state of the dataset determined based at least in part on the stored coherent state of the dataset, based on an identification of a command to perform an access operation on the dataset stored in memory, wherein the bias state is associated with control of access to the dataset by the host device.

[0151] In some instances of the method 800 and apparatus described herein, the coherent state of the dataset may be stored independently of commands, and the method, apparatus, and non-transitory computer-readable medium may include additional operations, features, circuitry, logic, components, or instructions for: transmitting an instruction to a host device, at least in part, based on determining a bias state processing command, of an access operation to be performed on the dataset; and receiving from the host device, at least in part, based on the instruction of transmitting the access operation, a second command indicating direct access to the dataset for the access operation.

[0152] In some instances of the method 800 and apparatus described herein, the command includes a read command, and the method, apparatus, and non-transitory computer-readable medium may include additional operations, features, circuitry, logic, components, or instructions for accessing memory for a dataset, at least in part based on receiving a second command from a host device.

[0153] Some instances of the method 800 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for transmitting a dataset received from a host device to a memory, at least in part based on receiving the dataset from the host device.

[0154] In some instances of the method 800 and apparatus described herein, the memory may be configured to store a first value that can be associated with a first coherent state of the dataset, a second value that can be associated with a second coherent state of the dataset, or a third value that can be associated with a third coherent state of the dataset.

[0155] In some instances of the method 800 and device described herein, a first value indicates that an invalid version of the dataset may be stored in the cache of the host device, a second value indicates that a shared or exclusive version of the dataset may be stored in the cache of the host device, and a third value indicates that a shared version of the dataset may be stored in the cache of the host device.

[0156] In some instances of the method 800 and device described herein, the second and third values ​​indicate that the dataset is coherent and that the command is processed based at least in part on the second or third value of the dataset stored in memory, according to the bias state.

[0157] In some instances of the method 800 and device described herein, a dataset may be associated with a first quantity of data, and a cache line of a host device coupled to memory may be configured to store the first quantity of data.

[0158] In some instances of the method 800 and device described herein, a first bias state may be associated with control of access to a dataset by a controller, and the bias state corresponds to a second bias state.

[0159] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0160] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0161] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be electronically connected (or electrically contacted, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacted, connected, or coupled) to each other can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0162] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via conductive paths, while in a closed-circuit relationship, signals can be transmitted between components via conductive paths. If a component, such as a controller, couples other components together, then that component begins to allow the change of signal flow between the other components via conductive paths that were previously not permitted.

[0163] The term "isolation" refers to a relationship between components in which signals are currently not allowed to flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, the controller performs the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0164] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0165] The term "in response to" can refer to a condition or action occurring at least partially (if not completely) as a result of a previous condition or action. For example, a first condition or action can be performed, and a second condition or action can occur at least partially as a result of the occurrence of the previous condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0166] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" that other condition or action.

[0167] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0168] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0169] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0170] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, components of the same type can be distinguished by a hyphen following the reference label and a second label distinguishing them from each other. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, but not to the second reference label.

[0171] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations.

[0172] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0173] As used herein, the word "or" in a list of items contained in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0174] Computer-readable media include both non-transitory computer storage media and communication media, with communication media including any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available medium accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor.

[0175] Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0176] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: a memory; and a controller coupled with the memory, wherein the controller is configured to: receive first signaling comprising an indication of a type of an access operation and an address of the memory associated with data; receive second signaling comprising an indication of a coherency state of the data, wherein the coherency state indicates whether a copy of the data is stored at a host device; and determine a bias state of the data based at least in part on the coherency state, wherein the bias state indicates whether to access the host device as part of the access operation.

2. The system of claim 1, wherein the controller is further configured to: access the data independent of the host device based at least in part on the bias state.

3. The system of claim 1, wherein the controller is further configured to: receive the data from the memory based at least in part on the bias state; and transfer the data to a processing unit based at least in part on receiving the data from the memory.

4. The system of claim 1, wherein the memory is configured to: transfer the data to a processing unit based at least in part on the bias state of the data.

5. The system of claim 1, wherein the memory is configured to: store a plurality of coherency states, each coherency state corresponding to respective data, wherein the plurality of coherency states comprises the coherency state of the data.

6. The system of claim 1, further comprising: a cache coupled with the controller, wherein the cache is configured to: store a plurality of coherency states, each coherency state corresponding to respective data, wherein the plurality of coherency states comprises the coherency state of the data.

7. The system of claim 1, further comprising: a processing unit coupled with the controller, wherein the processing unit is configured to: determine to access the data based at least in part on the type of the access operation indicated by the first signaling.

8. The system of claim 1, wherein the controller is further configured to: transfer third signaling to a cache coupled with the controller based at least in part on the indication of the type of the access operation, the third signaling comprising a first access command; and receive fourth signaling from the cache coupled with the controller based at least in part on transferring the third signaling to the cache coupled with the controller, the fourth signaling comprising an indication of whether the data is stored in the cache coupled with the controller.

9. The system of claim 8, wherein the controller is further configured to: transfer fifth signaling to the memory based at least in part on the indication of whether the data is stored in the cache coupled with the controller, the fifth signaling comprising a second access command to access the memory.

10. The system of claim 1, wherein the second signaling is received from the memory based at least in part on the data being stored in the memory.

11. The system of claim 1, wherein the second signaling is received from a cache coupled with the controller based at least in part on the data being stored in the cache coupled with the controller.

12. The system of claim 11, further comprising: a processing unit coupled with the cache, wherein the cache is further configured to: transfer the data to the processing unit based at least in part on the bias state of the data.

13. A system comprising: a memory; and a controller coupled with the memory, wherein the controller is configured to: receive first signaling comprising an indication of a type of an access operation and an address of the memory associated with data; receive second signaling comprising an indication of a coherence state of the data, wherein the coherence state indicates whether a copy of the data is stored at a host device; determine a bias state of the data based at least in part on the coherence state, wherein the bias state indicates whether to access the host device as part of the access operation by the controller; and transfer third signaling to the host device based at least in part on determining the bias state of the data.

14. The system of claim 13, wherein the controller is further configured to: receive fourth signaling from the host device based at least in part on transferring the third signaling to the host device, wherein the fourth signaling grants access rights to the data.

15. The system of claim 14, wherein the memory is configured to: transfer the data to a processing unit based at least in part on receiving the fourth signaling granting access rights to the data.

16. The system of claim 13, wherein the controller is further configured to: receive fifth signaling comprising a second indication of a second type of a second access operation and a second address of the memory associated with second data; transfer sixth signaling to a cache coupled with the controller to determine whether the second data is stored in the cache coupled with the controller; receive seventh signaling from the cache coupled with the controller comprising an indication of whether the second data is stored in the cache coupled with the controller and an indication of a coherence state of the second data; and determine a bias state of the second data based at least in part on the coherence state of the second data, wherein the bias state indicates whether to access the host device as part of the second access operation by the controller.

17. The system of claim 16, wherein the controller is further configured to: transfer eighth signaling to the host device based at least in part on determining the bias state of the second data; and ​ ​ receiving a ninth signaling from the host device based at least in part on transmitting the eighth signaling, wherein the ninth signaling grants access rights to the second data.

18. The system of claim 17, wherein the memory is configured to: transmit the second data to a processing unit based at least in part on receiving the ninth signaling that grants access rights to the second data.

19. The system of claim 13, wherein determining the bias state of the data further comprises determining that the bias state is a host bias state, transmitting the third signaling to the host device based at least in part on the bias state being the host bias state.

20. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive first signaling comprising a type of an access operation and an indication of a memory address associated with data; receive second signaling comprising an indication of a coherence state of the data, wherein the coherence state indicates whether a copy of the data is stored at a host device; and determine a bias state of the data based at least in part on the coherence state, wherein the bias state indicates whether a controller is to access the host device as part of the access operation.

21. The system of claim 20, wherein the type of the access operation comprises a read operation, a write operation, or a copy operation.

22. The system of claim 20, wherein the coherence state comprises a valid state, an invalid state, or a dirty state.

23. The system of claim 20, wherein the bias state comprises a host bias state or a controller bias state.

24. The system of claim 20, wherein the instructions, when executed by the processor, further cause the electronic device to: determine the bias state of the data based at least in part on the coherence state and a type of the access operation.

25. The system of claim 20, wherein the instructions, when executed by the processor, further cause the electronic device to: determine the bias state of the data based at least in part on the coherence state and a type of the access operation.

26. The system of claim 20, wherein the instructions, when executed by the processor, further cause the electronic device to: determine the bias state of the data based at least in part on the coherence state and a type of the access operation.

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