A pre-emphasis circuit

Abstract

The present application provides a pre-emphasis circuit, comprising: a pre-emphasis main circuit, configured to provide an additional drive current to a low-voltage differential drive circuit for a delay time, so as to increase the amplitude of the high-frequency component of the differential signal and obtain a target differential signal; a pre-emphasis control circuit, connected to the pre-emphasis main circuit, configured to control the states of the differential signal and the reverse delay signal, so as to control the pre-emphasis main circuit to provide an additional drive current for a delay time, wherein the delay time is less than the rise and fall time of the differential signal; the pre-emphasis main circuit is configured to control the pre-emphasis main circuit to provide an additional drive current for a delay time, and then control the pre-emphasis main circuit to be turned off. The present application simplifies the structure of the pre-emphasis main circuit, and combines it with the precise control of the control circuit to meet greater pre-emphasis requirements with a smaller area.

Description

Technical Field

[0001] The present application belongs to the technical field of integrated circuits, and in particular relates to a pre-emphasis circuit. Background Art

[0002] LVDS (Low-Voltage Differential Signaling) is a level standard used for signal transmission. It uses extremely low voltage swings for high-speed differential data transmission, enabling point-to-point or point-to-multipoint connections. It offers advantages such as low power consumption, low bit error rate, low crosstalk, and low radiation. It is widely used in serial high-speed data communication applications, such as high-speed backplanes, cables, and communication links within PCBs. Pre-emphasis is a signal processing method that compensates for high-frequency components in the input signal at the transmitter.

[0003] In LVDS driver circuit technologies, when faced with large load capacitance, current pre-emphasis circuits are typically used to provide a higher current during the initial charging phase to ensure sufficient drive capability even with large load capacitance. However, the large number of transistors connected in series in the pre-emphasis circuit is not suitable for low-voltage architectures (because each transistor generates a voltage drop). Furthermore, when handling large capacitive loads, larger transistors are required to increase drive capability.

[0004] Therefore, it is particularly necessary to develop a pre-emphasis circuit that is suitable for low-voltage environments and occupies a small area. Summary of the Invention

[0005] The present application discloses a pre-emphasis circuit, which achieves greater pre-emphasis capability with a smaller area by simplifying the structure of the pre-emphasis main circuit and accurately controlling the pre-emphasis main circuit.

[0006] Other purposes and advantages of this application can be further understood from the technical features disclosed in this application.

[0007] To achieve one, part, or all of the above objectives or other objectives, the present application provides a pre-emphasis circuit, which is applied to a low-voltage differential drive circuit. The pre-emphasis circuit includes:

[0008] a pre-emphasis main circuit, configured to provide an additional driving current for the low voltage differential driving circuit for a delay time, so as to increase the amplitude of the high frequency component of the differential signal and obtain a target differential signal;

[0009] A pre-emphasis control circuit is connected to the pre-emphasis main circuit and is used to control the states of the differential signal and the reverse delay signal to control the pre-emphasis main circuit to provide an additional drive current for a delay time, wherein the delay time is less than the rise and fall time of the differential signal; and the pre-emphasis main circuit is used to control the pre-emphasis main circuit to be turned off after the pre-emphasis main circuit provides the additional drive current for the delay time.

[0010] Furthermore, the low-voltage differential drive circuit includes a main driving circuit, which includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein the source of the first PMOS transistor is connected to a power supply terminal, the source of the first NMOS transistor is grounded, the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to form a first node, and the drain of the third PMOS transistor and the drain of the third NMOS transistor are connected to form a second node;

[0011] The pre-emphasis main circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are both connected to the first node, the drain of the fifth PMOS transistor and the drain of the fifth NMOS transistor are both connected to the second node, the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are both connected to the power supply, and the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are both grounded.

[0012] Furthermore, the differential signal includes a first differential signal and a second differential signal, the gate of the second PMOS transistor and the gate of the second NMOS transistor are used to input the first differential signal, and the pre-emphasis main circuit provides an additional drive current through the fourth PMOS transistor and the fifth NMOS transistor for a delay time to obtain a target differential signal; the gate of the third PMOS transistor and the gate of the third NMOS transistor are used to input the second differential signal, and the pre-emphasis main circuit provides an additional drive current through the fourth NMOS transistor and the fifth PMOS transistor for a delay time to obtain the target differential signal.

[0013] Furthermore, the pre-emphasis control circuit includes a first control circuit connected to the gate of the fourth PMOS transistor and a second control circuit connected to the gate of the fifth NMOS transistor;

[0014] The first control circuit includes a first control PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a first inverting chain for providing a delay time. The first inverting chain inputs a first differential signal and is connected to the gate of the seventh PMOS transistor and the gate of the sixth NMOS transistor. The drain of the seventh PMOS transistor and the drain of the sixth NMOS transistor are both connected to the source of the first control PMOS transistor. The gate of the sixth PMOS transistor inputs the first differential signal, the gate of the seventh NMOS transistor and the gate of the first control PMOS transistor input a second differential signal, and the source of the first control PMOS transistor is directly connected to a power supply.

[0015] The second control circuit includes a first control NMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a second inverting chain for providing a delay time. The second inverting chain inputs a second differential signal, and the second inverting chain is connected to the gate of the ninth PMOS transistor and the gate of the eighth NMOS transistor. The drain of the ninth PMOS transistor and the drain of the eighth NMOS transistor are both connected to the drain of the first control NMOS. The gate of the eighth PMOS transistor and the gate of the first control NMOS transistor input the first differential signal, the source of the first control NMOS transistor is grounded, and the gate of the ninth NMOS transistor inputs the second differential signal.

[0016] Further, when the first differential signal is high, the second differential signal is low, the sixth PMOS transistor and the seventh NMOS transistor are turned off, the first control PMOS transistor is turned on, and the first reverse delay signal is output as high, driving the fourth PMOS transistor to turn off; or, when the first differential signal is low, the second differential signal is high, the sixth PMOS transistor and the seventh NMOS transistor are turned on, the first control NMOS transistor is turned off, and the first reverse delay signal is output as high, driving the fourth PMOS transistor to turn off; or, when the first differential signal jumps from high to low, the sixth PMOS transistor and the seventh NMOS transistor are instantaneously turned on, and the first control PMOS transistor is instantaneously turned off; the first reverse delay signal is output as low, driving the fourth PMOS transistor to turn on and output additional drive current until the delay time lasts, and then the first reverse delay signal rises, driving the fourth PMOS transistor to turn off.

[0017] Further, when the first differential signal is high, the second differential signal is low, the eighth PMOS transistor and the ninth NMOS transistor are turned off, the first control NMOS transistor is turned on, and the second reverse delay signal is output as low, driving the fifth NMOS transistor to turn off; or, when the first differential signal is low, the second differential signal is high, the eighth PMOS transistor and the ninth NMOS transistor are turned on, the first control NMOS transistor is turned off, and the second reverse delay signal is output as low, controlling the fifth NMOS transistor to turn off; or, when the first differential signal jumps from high to low, the eighth PMOS transistor and the ninth NMOS transistor are instantaneously turned on, the first control NMOS transistor is turned on, the second reverse delay signal is output as high, driving the fifth NMOS transistor to turn on and output additional drive current. After the delay time, the second reverse delay signal is pulled low, and driving the fifth NMOS transistor to turn off.

[0018] Furthermore, the pre-emphasis control circuit includes a third control circuit connected to the gate of the fifth PMOS transistor and a fourth control circuit connected to the gate of the fourth NMOS transistor;

[0019] The third control circuit includes a second control PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a third inverting chain for providing a delay time, the third inverting chain inputting the second differential signal, the third inverting chain being connected to the gate of the eleventh PMOS transistor and the gate of the tenth NMOS transistor, the drain of the eleventh PMOS transistor and the drain of the tenth NMOS transistor being connected to the source of the second control PMOS transistor, the gate of the tenth PMOS transistor being inputting the second differential signal, the gate of the second control PMOS transistor and the gate of the eleventh NMOS transistor being inputting the first differential signal, and the source of the second control PMOS transistor being connected to a power supply;

[0020] The fourth control circuit includes a second control NMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a fourth inverting chain for providing a delay time. The fourth inverting chain inputs the first differential signal. The fourth inverting chain is connected to the gate of the thirteenth PMOS transistor and the gate of the twelfth NMOS transistor. The drain of the thirteenth PMOS transistor and the drain of the twelfth NMOS transistor are both connected to the drain of the first control NMOS. The gate of the second control NMOS transistor and the gate of the twelfth PMOS transistor input the second differential signal, the source of the second control NMOS transistor is grounded, and the gate of the thirteenth NMOS transistor inputs the first differential signal.

[0021] Further, when the second differential signal is high, the first differential signal is low, the tenth PMOS transistor and the eleventh NMOS transistor are turned off, the second control PMOS transistor is turned on, and the third reverse delay signal is output as high, driving the fifth PMOS transistor to turn off; or, when the second differential signal is low, the first differential signal is high, the tenth PMOS transistor and the eleventh NMOS transistor are turned on, the second control PMOS transistor is turned off, and the third reverse delay signal is output as high, driving the fifth PMOS transistor to turn off; or, when the second differential signal jumps from high to low, the tenth PMOS transistor and the eleventh NMOS transistor are instantaneously turned on, the second control PMOS transistor is instantaneously turned off, and the third reverse delay signal is output as low, driving the fifth PMOS transistor to turn on and output additional drive current until the delay time lasts, and then the third reverse delay signal rises, driving the fifth PMOS transistor to turn off.

[0022] Further, when the second differential signal is high, the first differential signal is low, the twelfth PMOS transistor and the thirteenth NMOS transistor are turned off, the second control NMOS transistor is turned on, and the fourth reverse delay signal is output as high, driving the fourth NMOS transistor to turn off; or, when the second differential signal is low, the first differential signal is high, the twelfth PMOS transistor and the thirteenth NMOS transistor are turned on, the second control NMOS transistor is turned off, and the fourth reverse delay signal is output as high, driving the fourth NMOS transistor to turn off; or, when the second differential signal jumps from high to low, the twelfth PMOS transistor and the thirteenth NMOS transistor are instantaneously turned on, the second control NMOS transistor is instantaneously turned off, and the fourth reverse delay signal is output as high, driving the fourth NMOS transistor to turn on and output additional drive current until the delay time lasts, and then the fourth reverse delay signal is pulled low, driving the fourth NMOS transistor to turn off.

[0023] Furthermore, the first inverting strand and the fourth inverting strand are the same; and / or the second inverting strand and the third inverting strand are the same.

[0024] The above-mentioned pre-emphasis circuit directly connects the transistors of the pre-emphasis main circuit to the power supply and the ground, omitting the transistors that control the current source and the current drain, thereby reducing the voltage drop and ensuring that the pre-emphasis main circuit provides a sufficiently large current to the driving main circuit, so that the output signal can have a faster rising edge and falling edge to ensure the integrity of the signal during high-speed transmission, and simplifies the area overhead of the pre-emphasis main circuit; the present application also realizes precise control of the pre-emphasis main circuit through the pre-emphasis control circuit, thereby reducing the area overhead and improving the pre-emphasis capability of the low-voltage driving circuit.

[0025] In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 This is a schematic diagram of a driving main circuit and load capacitor of the present application.

[0028] Figure 2 This is a schematic diagram of a pre-emphasis circuit of the present application.

[0029] Figure 3 This is a signal timing diagram of a pre-emphasis circuit of the present application. DETAILED DESCRIPTION

[0030] The aforementioned and other technical contents, features, and functions of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first," "second," and the like in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, and this is merely a way of distinguishing objects of the same attributes when describing them in the embodiments of the present application.

[0031] In LVDS driving circuits, when faced with large load capacitance, a current pre-emphasis circuit is usually used to provide a higher current in the initial stage of charging to ensure sufficient driving capability when the load capacitance is large. Figure 1The load capacitance of the main driving circuit is measured. The main driving circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3. The first PMOS transistor PM1 is a current source with its source connected to a power supply, while the first NMOS transistor NM1 is a current sink with its source connected to ground. Both transistors are used to provide a stable current for the main driving circuit. The drain of the first PMOS transistor PM1 is connected to the source of the second PMOS transistor PM2 and the source of the third PMOS transistor PM3. The drain of the first NMOS transistor NM1 is connected to the source of the second NMOS transistor NM2 and the source of the third NMOS transistor NM3. The drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2 to form a first node OUT_N, and the drain of the third PMOS transistor PM3 is connected to the drain of the third NMOS transistor NM3 to form a second node OUT_P. The first node OUT_N is connected to the capacitor C1 and the resistor R1 , and the second node OUT_P is connected to the capacitor C2 and the resistor R2 .

[0032] It should be noted that in the drawings of this application, the connections of multiple circuits are connected with the same names according to the annotations, and will not be repeated below.

[0033] The first differential signal out_pre_p and the second differential signal out_pre_n form a pair of differential signals. When the first differential signal out_pre_p is high, the second differential signal out_pre_n is low. When the first differential signal out_pre_p transitions from high to low, the second differential signal out_pre_n transitions from low to high. At this time, PM2 and NM3 are turned on, while PM3 and NM2 are turned off. Current flows from PM1 along PM2 to the first node OUT_N in the middle, then through resistors R1 and R2, back to the second node OUT_P, through NM3 and NM1, and to ground, forming a complete loop. Here, the current I1 is 3.5 mA, and the resistors R1 and R2 are equal, each with a resistance of 50 ohms. Therefore, the total voltage drop Vod across resistors R1 and R2 is 350 mV. However, when faced with large load capacitance, such as that caused by package pins or multiple interface multiplexing, the larger the capacitance, the slower the charging, and the slower the voltage rises or falls. As a result, the 3.5 mA current cannot guarantee the signal's rise and fall times, thereby affecting the signal transmission quality. Here, the signal's rise and fall time refers to the time required for the voltage drop to change from 20% to 80%. The rise time is the time it takes for the signal to change from 20% to 80%, and the fall time is the time it takes for the signal to change from 80% to 20%.

[0034] In order to optimize the above problem, the embodiment of the present application provides an additional driving current for a delay time to the driving main circuit by pre-emphasizing the main circuit in the initial stage of charging, thereby increasing the amplitude of the high-frequency component of the differential signal, obtaining the target differential signal and outputting it. Figure 2 The pre-emphasis main circuit includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5. The drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are both connected to the first node, the drain of the fifth PMOS transistor PM5 and the drain of the fifth NMOS transistor NM5 are both connected to the second node, the source of the fourth PMOS transistor PM5 and the source of the fifth PMOS transistor PM5 are both connected to the power supply, and the source of the fourth NMOS transistor NM4 and the source of the fifth NMOS transistor NM5 are both grounded.

[0035] The pre-emphasis circuit of an embodiment of the present application includes a pre-emphasis control circuit connected to a main pre-emphasis circuit. The circuit is configured to control the main pre-emphasis circuit to provide an additional drive current for a delay time, thereby controlling the rise of the reverse delay signal of the differential signal to obtain a target differential signal, wherein the delay time is less than the rise and fall time of the differential signal. Furthermore, the main pre-emphasis circuit is configured to control the main pre-emphasis circuit to stably shut down after the main pre-emphasis circuit provides the additional drive current for the delay time, thereby not affecting the normal operation of the LVDS driver circuit.

[0036] In summary, the present application reduces the voltage drop by directly connecting the transistors of the pre-emphasis main circuit to the power supply and the ground, omitting the transistors that control the current source and the current drain, thereby ensuring that the pre-emphasis main circuit provides a sufficiently large current to the driving main circuit, so that the output signal can have a faster rising edge and falling edge to ensure the integrity of the signal during high-speed transmission, and simplifies the area overhead of the pre-emphasis main circuit; the present application also realizes precise control of the pre-emphasis main circuit through the pre-emphasis control circuit, thereby reducing the area overhead and improving the pre-emphasis capability of the low-voltage driving circuit.

[0037] As an optional implementation, the gate of the second PMOS transistor and the gate of the second NMOS transistor are used to input the first differential signal, and the pre-emphasis main circuit provides an additional drive current through the fourth PMOS transistor and the fifth NMOS transistor for a delay time to increase the first differential signal to obtain a target differential signal; the gate of the third PMOS transistor and the gate of the third NMOS transistor are used to input the second differential signal, and the pre-emphasis main circuit provides an additional drive current through the fourth NMOS transistor and the fifth PMOS transistor for a delay time to increase the second differential signal to obtain a target differential signal.

[0038] As an optional implementation, the pre-emphasis control circuit includes a first control circuit connected to the gate of the fourth PMOS transistor and a second control circuit connected to the gate of the fifth NMOS transistor.

[0039] refer to Figure 2 The first control circuit includes a first control PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a first inverting chain for providing a delay time. The first inverting chain inputs a first differential signal and is connected to the gate of the seventh PMOS transistor and the gate of the sixth NMOS transistor. The drain of the seventh PMOS transistor and the drain of the sixth NMOS transistor are both connected to the source of the first control PMOS transistor. The gate of the sixth PMOS transistor inputs the first differential signal, the gate of the seventh NMOS transistor and the gate of the first control PMOS transistor input the second differential signal, and the source of the first control PMOS transistor is directly connected to a power supply. The second control circuit includes a first control NMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a second inverting chain for providing a delay time. The second inverting chain inputs the second differential signal and is connected to the gate of the ninth PMOS transistor and the gate of the eighth NMOS transistor. The drain of the ninth PMOS transistor and the drain of the eighth NMOS transistor are both connected to the drain of the first control NMOS transistor. The gate of the eighth PMOS transistor and the gate of the first control NMOS transistor input the first differential signal. The source of the first control NMOS transistor is grounded, and the gate of the ninth NMOS transistor inputs the second differential signal.

[0040] The following text Figure 3 Taking moment ① in the figure as an example, the control process of the control circuit of the present application is described in detail. Among them, the PMOS tube is turned on when the gate signal is low, and the PMOS tube is turned off when the gate signal is high; the NMOS tube is turned on when the gate signal is high, and the NMOS tube is turned off when the gate signal is low.

[0041] Combine Figure 1 、 Figure 2 and Figure 3 In the first control circuit, when the first differential signal out_pre_p is high, the second differential signal out_pre_n is low. At this time, the sixth PMOS transistor PM6 and the seventh NMOS transistor NM7 are turned off; the first control PMOS transistor PM01 directly connected to the power supply is turned on, so that the first inverse delay signal out_pre_p_delay_inv_p1 is output high, and the fourth PMOS transistor PM4 connected to the first inverse delay signal out_pre_p_delay_inv_p1 is turned off.

[0042] When the first differential signal out_pre_p is low, the second differential signal out_pre_n is high, the first control PMOS transistor PM01 is turned off, and the sixth PMOS transistor PM6 and the seventh NMOS transistor NM7 are turned on, so that the first inverse delay signal out_pre_p_delay_inv_p1 obtained by the first differential signal out_pre_p through the first inversion chain A1 is output high, and the fourth PMOS transistor PM4 is controlled to be turned off.

[0043] When the first differential signal out_pre_p transitions from high to low, the sixth PMOS transistor PM6 and the seventh NMOS transistor NM7 are instantaneously turned on, and the first control PMOS transistor PM01 is instantaneously turned off. Because the first differential signal out_pre_p was previously high, the first inverse delay signal out_pre_p_delay_inv_p1 is output low, driving the fourth PMOS transistor PM4 to turn on and output an additional drive current for a delay time Δt, thus performing pre-emphasis. Due to the delay of the inverting chain A1, the first inverse delay signal out_pre_p_delay_inv_p1 remains low until, after the delay time Δt, the first inverse delay signal out_pre_p_delay_inv_p1, obtained by the inverting chain A1 from the low first differential signal out_pre_p, goes high. This then drives the fourth PMOS transistor PM4 off, completing pre-emphasis.

[0044] Combine Figure 1 、 Figure 2 and Figure 3 In the second control circuit, when the first differential signal out_pre_p is high, the second differential signal out_pre_n is low. At this time, the eighth PMOS transistor PM8 and the ninth NMOS transistor NM9 are turned off, and the grounded first control NMOS transistor NM01 is turned on, so that the second inverse delay signal out_pre_n_delay_inv_n2 is output low, controlling the fifth NMOS transistor NM5 to turn off.

[0045] When the first differential signal out_pre_p is low, the second differential signal out_pre_n is high, the first control NMOS transistor NM01 is turned off, and the eighth PMOS transistor PM8 and the ninth NMOS transistor NM9 are turned on, so that the second inverse delay signal out_pre_n_delay_inv_n2 obtained after the second differential signal out_pre_n passes through the second inversion chain B1 is output as low, and the fifth NMOS transistor NM5 is controlled to be turned off.

[0046] When the first differential signal out_pre_p transitions from high to low, the eighth PMOS transistor PM8 and the ninth NMOS transistor NM9 are instantaneously turned on, and the first control NMOS transistor NM01 is turned off. The second inverse delay signal out_pre_n_delay_inv_n2 is output high, driving the fifth NMOS transistor NM5 to turn on, outputting an additional drive current for a delay time Δt. After the delay time Δt, the second inverse delay signal out_pre_n_delay_inv_n2 is pulled low, driving the fifth NMOS transistor NM5 to turn off, completing pre-emphasis.

[0047] As described above, this embodiment controls the pre-emphasis process by controlling the gate signal level in the pre-emphasis main circuit through the high and low levels of the differential signal, a PMOS transistor directly connected to the power supply, and an NMOS transistor connected to ground. This achieves precise and effective control of pre-emphasis through the first and second control circuits. Furthermore, after the delay time Δt, the pre-emphasis circuit is turned off when pre-emphasis is complete to avoid affecting the operation of the drive circuit, thereby improving the accuracy and stability of the pre-emphasis circuit control.

[0048] As an optional implementation, similar to the first control circuit and the second control circuit, the pre-emphasis control circuit includes a third control circuit connected to the gate of the fifth PMOS transistor PM5 and a fourth control circuit connected to the gate of the fourth NMOS transistor NM4.

[0049] refer to Figure 2The third control circuit includes a second control PMOS transistor PM02, a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, and a third inverting chain for providing a delay time. The third inverting chain is connected to the gate of the eleventh PMOS transistor PM11 and the gate of the tenth NMOS transistor NM10. The third inverting chain inputs the second differential signal. The drain of the eleventh PMOS transistor PM11 and the drain of the tenth NMOS transistor NM10 are both connected to the source of the second control PMOS transistor PM02. The gate of the tenth PMOS transistor inputs the second differential signal. The gate of the second control PMOS transistor and the gate of the eleventh NMOS transistor input the first differential signal. The source of the second control PMOS transistor is connected to the power supply. The fourth control circuit includes a second control NMOS transistor NM02, a twelfth PMOS transistor PM12, a thirteenth PMOS transistor PM13, a twelfth NMOS transistor NM12, a thirteenth NMOS transistor NM13, and a fourth inverting chain for providing a delay time. The fourth inverting chain is connected to the gate of the thirteenth PMOS transistor PM13 and the gate of the twelfth NMOS transistor NM12. The fourth inverting chain inputs the first differential signal. The drain of the thirteenth PMOS transistor PM13 and the drain of the twelfth NMOS transistor NM12 are both connected to the drain of the second control NMOS transistor NM02. The gate of the second control NMOS transistor and the gate of the twelfth PMOS transistor input the second differential signal. The source of the second control NMOS transistor is grounded, and the gate of the thirteenth NMOS transistor inputs the first differential signal.

[0050] Combine Figure 1 、 Figure 2 and Figure 3 In the third control circuit, when the second differential signal out_pre_n is high, the first differential signal out_pre_p is low. At this time, the tenth PMOS transistor PM10 and the eleventh NMOS transistor NM11 are turned off, and the second control PMOS transistor PM02 connected to the power supply is turned on, so that the third inverse delay signal out_pre_p_delay_inv_p2 is output high, controlling the fifth PMOS transistor PM5 to turn off.

[0051] When the second differential signal out_pre_n is low, the first differential signal out_pre_p is high, the second control PMOS transistor PM02 is turned off, and the tenth PMOS transistor PM10 and the eleventh NMOS transistor NM11 are turned on, so that the third inverse delay signal out_pre_p_delay_inv_p2 obtained by the second differential signal out_pre_n through the third inversion chain A2 is output high, controlling the fifth PMOS transistor PM5 to be turned off.

[0052] When the second differential signal out_pre_n transitions from high to low, the tenth PMOS transistor PM10 and the eleventh NMOS transistor NM11 are momentarily turned on, and the second control PMOS transistor PM02 is momentarily turned off. The third inverse delay signal out_pre_p_delay_inv_p2 is output low, driving the fifth PMOS transistor PM5 to turn on, outputting an additional drive current for a delay time Δt. After the delay time Δt, the third inverse delay signal out_pre_p_delay_inv_p2 goes high, driving the fifth PMOS transistor PM5 to turn off, completing pre-emphasis.

[0053] Combine Figure 1 、 Figure 2 and Figure 3 In the fourth control circuit, when the second differential signal out_pre_n is high, the first differential signal out_pre_p is low. At this time, the twelfth PMOS transistor PM12 and the thirteenth NMOS transistor NM13 are turned off, and the second control NMOS transistor NM02 is turned on, so that the fourth inverse delay signal out_pre_p_delay_inv_n1 is output high, controlling the fourth NMOS transistor NM4 to turn off.

[0054] When the second differential signal out_pre_n is low, the first differential signal out_pre_p is high, the second control NMOS transistor NM02 is turned off, the twelfth PMOS transistor PM12 and the thirteenth NMOS transistor NM13 are turned on, so that the fourth inverse delay signal out_pre_p_delay_inv_n1 is output high, controlling the fourth NMOS transistor NM4 to be turned off.

[0055] When the second differential signal out_pre_n transitions from high to low, the twelfth PMOS transistor PM12 and the thirteenth NMOS transistor NM13 are momentarily turned on, and the second control NMOS transistor NM02 is momentarily turned off. The fourth inverse delay signal out_pre_p_delay_inv_n1 is output high, driving the fourth NMOS transistor NM4 to turn on and output an additional drive current for a delay time Δt. After the delay time Δt, the fourth inverse delay signal out_pre_p_delay_inv_n1 is pulled low, driving the fourth NMOS transistor NM4 to turn off, thus completing pre-emphasis.

[0056] In this embodiment, by providing a third control circuit similar to the first control circuit and a fourth control circuit similar to the second control circuit, flexible control of the pre-emphasis main circuit is achieved, thereby improving the applicability of the pre-emphasis circuit.

[0057] As an optional implementation, the first inverting chain and the fourth inverting chain are the same; and / or the second inverting chain and the third inverting chain are the same. By setting up a shared inverting chain, circuit area overhead can be further saved.

[0058] In summary, the pre-emphasis circuit of the present application simplifies the main pre-emphasis circuit, achieving the goal of meeting greater pre-emphasis requirements with a smaller area, and further improves the precise control of pre-emphasis through the pre-emphasis control circuit, thereby not affecting the function of the LVDS driver circuit.

[0059] It should be noted that, for those skilled in the art, various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention. It should be understood that certain features of the present invention described in the context of separate embodiments for the sake of clarity may also be provided in combination in a single embodiment. Conversely, various features of the present invention described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present invention.

Claims

1. A pre-emphasis circuit, wherein the pre-emphasis circuit is applied to a low voltage differential drive circuit, characterized in that: The pre-emphasis circuit comprises: A pre-emphasis main circuit, comprising a fourth PMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, wherein the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are both connected to the first node of the low-voltage differential drive circuit, the drain of the fifth PMOS transistor and the drain of the fifth NMOS transistor are both connected to the second node of the low-voltage differential drive circuit, the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are both connected to a power supply, and the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are both grounded; and is configured to provide an additional drive current to the low-voltage differential drive circuit via the first node and the second node for a delay time, so as to increase the amplitude of the high-frequency component of the differential signal and obtain a target differential signal, wherein the differential signal includes a first differential signal and a second differential signal; The pre-emphasis control circuit includes: a first control circuit connected to the gate of the fourth PMOS transistor, for controlling the fourth PMOS transistor to be turned on and off according to a first differential signal and an inverse delayed signal thereof, so as to control the fourth PMOS transistor to supply an additional drive current for a delay time; and a second control circuit connected to the gate of the fifth NMOS transistor, for controlling the fifth NMOS transistor to be turned on and off according to a second differential signal and an inverse delayed signal thereof, so as to control the fifth NMOS transistor to supply an additional drive current for a delay time; wherein the delay time is less than a rise time and a fall time of the differential signal.

2. A pre-emphasis circuit according to claim 1, characterized in that: The low-voltage differential drive circuit includes a main driving circuit, which includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The source of the first PMOS transistor is connected to the power supply end, the source of the first NMOS transistor is grounded, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor to form a first node, and the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor to form a second node.

3. A pre-emphasis circuit according to claim 2, characterized in that: The gate of the second PMOS transistor and the gate of the second NMOS transistor are used to input a first differential signal, and the pre-emphasis main circuit provides an additional drive current through the fourth PMOS transistor and the fifth NMOS transistor for a delay time to obtain a target differential signal; the gate of the third PMOS transistor and the gate of the third NMOS transistor are used to input a second differential signal, and the pre-emphasis main circuit provides an additional drive current through the fourth NMOS transistor and the fifth PMOS transistor for a delay time to obtain a target differential signal.

4. A pre-emphasis circuit according to claim 3, characterized in that: The first control circuit includes a first control PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a first inverting chain for providing a delay time. The first inverting chain inputs a first differential signal and is connected to the gate of the seventh PMOS transistor and the gate of the sixth NMOS transistor. The drain of the seventh PMOS transistor and the drain of the sixth NMOS transistor are both connected to the source of the first control PMOS transistor. The gate of the sixth PMOS transistor inputs the first differential signal, the gate of the seventh NMOS transistor and the gate of the first control PMOS transistor input a second differential signal, and the source of the first control PMOS transistor is directly connected to a power supply. The second control circuit includes a first control NMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a second inverting chain for providing a delay time. The second inverting chain inputs a second differential signal, and the second inverting chain is connected to the gate of the ninth PMOS transistor and the gate of the eighth NMOS transistor. The drain of the ninth PMOS transistor and the drain of the eighth NMOS transistor are both connected to the drain of the first control NMOS. The gate of the eighth PMOS transistor and the gate of the first control NMOS transistor input the first differential signal, the source of the first control NMOS transistor is grounded, and the gate of the ninth NMOS transistor inputs the second differential signal.

5. A pre-emphasis circuit according to claim 4, characterized in that: When the first differential signal is high, the second differential signal is low, the sixth PMOS transistor and the seventh NMOS transistor are turned off, the first control PMOS transistor is turned on, the first reverse delay signal is output high, and the fourth PMOS transistor is driven to turn off; or, When the first differential signal is low, the second differential signal is high, the sixth PMOS transistor and the seventh NMOS transistor are turned on, the first control NMOS transistor is turned off, and the first reverse delay signal is output high, driving the fourth PMOS transistor to turn off; or, When the first differential signal jumps from high to low, the sixth PMOS transistor and the seventh NMOS transistor are instantaneously turned on, and the first control PMOS transistor is instantaneously turned off; the first reverse delay signal is output as low, driving the fourth PMOS transistor to turn on and output additional drive current until the first reverse delay signal rises after the delay time, driving the fourth PMOS transistor to turn off.

6. The pre-emphasis circuit according to claim 4, characterized in that: When the first differential signal is high, the second differential signal is low, the eighth PMOS transistor and the ninth NMOS transistor are turned off, the first control NMOS transistor is turned on, and the second reverse delay signal is output as low, driving the fifth NMOS transistor to turn off; or, When the first differential signal is low, the second differential signal is high, the eighth PMOS transistor and the ninth NMOS transistor are turned on, the first control NMOS transistor is turned off, the second reverse delay signal is output as low, and the fifth NMOS transistor is controlled to be turned off; or, When the first differential signal jumps from high to low, the eighth PMOS transistor and the ninth NMOS transistor are instantaneously turned on, the first control NMOS transistor is turned on, and the second reverse delay signal is output high, driving the fifth NMOS transistor to turn on and output additional drive current. After the delay time, the second reverse delay signal is pulled low and drives the fifth NMOS transistor to turn off.

7. The pre-emphasis circuit according to claim 4, characterized in that: The pre-emphasis control circuit includes a third control circuit connected to the gate of the fifth PMOS transistor and a fourth control circuit connected to the gate of the fourth NMOS transistor; The third control circuit includes a second control PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a third inverting chain for providing a delay time, the third inverting chain inputting the second differential signal, the third inverting chain being connected to the gate of the eleventh PMOS transistor and the gate of the tenth NMOS transistor, the drain of the eleventh PMOS transistor and the drain of the tenth NMOS transistor being connected to the source of the second control PMOS transistor, the gate of the tenth PMOS transistor being inputting the second differential signal, the gate of the second control PMOS transistor and the gate of the eleventh NMOS transistor being inputting the first differential signal, and the source of the second control PMOS transistor being connected to a power supply; The fourth control circuit includes a second control NMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a fourth inverting chain for providing a delay time. The fourth inverting chain inputs the first differential signal. The fourth inverting chain is connected to the gate of the thirteenth PMOS transistor and the gate of the twelfth NMOS transistor. The drain of the thirteenth PMOS transistor and the drain of the twelfth NMOS transistor are both connected to the drain of the first control NMOS. The gate of the second control NMOS transistor and the gate of the twelfth PMOS transistor input the second differential signal, the source of the second control NMOS transistor is grounded, and the gate of the thirteenth NMOS transistor inputs the first differential signal.

8. The pre-emphasis circuit according to claim 7, characterized in that: When the second differential signal is high, the first differential signal is low, the tenth PMOS transistor and the eleventh NMOS transistor are turned off, the second control PMOS transistor is turned on, and the third reverse delay signal is output high, driving the fifth PMOS transistor to turn off; or, When the second differential signal is low, the first differential signal is high, the tenth PMOS transistor and the eleventh NMOS transistor are turned on, the second control PMOS transistor is turned off, and the third reverse delay signal is output high, driving the fifth PMOS transistor to turn off; or, When the second differential signal jumps from high to low, the tenth PMOS transistor and the eleventh NMOS transistor are instantaneously turned on, the second control PMOS transistor is instantaneously turned off, and the third reverse delay signal is output as low, driving the fifth PMOS transistor to turn on and output additional drive current until the delay time lasts, at which time the third reverse delay signal rises and drives the fifth PMOS transistor to turn off.

9. The pre-emphasis circuit according to claim 7, characterized in that: When the second differential signal is high, the first differential signal is low, the twelfth PMOS transistor and the thirteenth NMOS transistor are turned off, the second control NMOS transistor is turned on, and the fourth reverse delay signal is output high, driving the fourth NMOS transistor to turn off; or, When the second differential signal is low, the first differential signal is high, the twelfth PMOS transistor and the thirteenth NMOS transistor are turned on, the second control NMOS transistor is turned off, and the fourth reverse delay signal is output high, driving the fourth NMOS transistor to turn off; or, When the second differential signal jumps from high to low, the twelfth PMOS transistor and the thirteenth NMOS transistor are instantaneously turned on, the second control NMOS transistor is instantaneously turned off, and the fourth reverse delay signal is output high, driving the fourth NMOS transistor to turn on and output additional drive current until the delay time lasts, and then the fourth reverse delay signal is pulled low and drives the fourth NMOS transistor to turn off.

10. The pre-emphasis circuit according to claim 7, characterized in that: The first inverting strand and the fourth inverting strand are the same; and / or the second inverting strand and the third inverting strand are the same.

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