Pre-emphasis circuit with bidirectional adjustment of time and current

Abstract

The invention provides a pre-emphasis circuit with two-way adjustment of time and current. The pre-emphasis circuit comprises a pre-emphasis main body circuit comprising a plurality of transistors; the bidirectional adjusting circuit comprises configurable transistors, a controllable switch circuit and an inverter chain, the configurable transistors comprise first configuration transistors and second configuration transistors, and the pre-emphasis time is adjusted by adjusting the number of the first configuration transistors and adjusting the delay time of differential signals passing through the inverter chain; the inverter chain is used for converting the differential signal into a reverse delay signal; the size of the pre-emphasis current is adjusted by adjusting the number of the second configuration transistors and combining the controllable switch circuit to control the output state of the reverse delay signal; and the common-mode level adjusting circuit is used for adjusting the number of the configurable transistors according to the current magnitude and the output voltage of the pre-emphasis main body circuit so as to balance the common-mode voltage. Therefore, bidirectional adjustment of the pre-emphasis current and the time is realized, and the problem of common-mode voltage offset is avoided.

Description

Technical Field

[0001] This application belongs to the technical field of integrated circuit design, and particularly relates to a pre-emphasis circuit with bidirectional regulation of time and current. Background Art

[0002] LVDS (Low-Voltage Differential Signaling) technology is a level standard for high-speed data transmission. This technology transmits data at high speed differentially with an extremely low voltage swing, supporting point-to-point or point-to-multipoint connection modes. It has significant advantages such as low power consumption, low bit error rate, low crosstalk, and low radiation, so it is widely used in the field of high-speed serial data communication, such as in high-speed backplanes, cables, and internal communication links of PCBs. The pre-emphasis technology is a signal processing method that compensates for the high-frequency components of the input signal at the signal transmitter.

[0003] In the related technologies of LVDS driver circuits, when the load capacitance is large, the current pre-emphasis circuit provides a large current at the initial stage of charging to ensure sufficient driving ability in the face of a large-capacitance load. However, the adjustment of the pre-emphasis ability needs to be achieved by adjusting the number of bias transistors and the bias voltage shared by the main bias circuit, which leads to some problems: due to the presence of intermediate PMOS and NMOS transistors in the pre-emphasis circuit, the VDS voltage left for the current source and current sink is small. To increase VDS, the sizes of the intermediate PMOS and NMOS transistors must be increased, which will result in a large area overhead. Therefore, it is not suitable for working in a low-voltage environment or for the case of a large load capacitance; adjusting the driving ability by changing the number of current sources requires reserving a large area for the current source and current sink to ensure sufficient driving current, resulting in an increase in the circuit area overhead.

[0004] Therefore, developing a pre-emphasis circuit suitable for a low-voltage environment, with a small area overhead and adjustable, has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application discloses a pre-emphasis circuit with bidirectional regulation of time and current, which can balance the common-mode voltage while realizing bidirectional regulation of pre-emphasis current and time, improving the accuracy and flexibility of pre-emphasis circuit control, achieving higher pre-emphasis requirements with a smaller circuit area, and enhancing the applicability of the pre-emphasis circuit.

[0006] Other objects and advantages of this application can be further understood from the technical features disclosed in this application.

[0007] For achieving one or part or all of the above purposes or other purposes, in a first aspect, the present application provides a pre-emphasis circuit with two-way regulation of time and current. The pre-emphasis circuit is applicable to a driving circuit and includes: A pre-emphasis main circuit, including a plurality of transistors, for providing a pre-emphasis current for the driving circuit to enhance the high-frequency component of the differential signal; A two-way regulation circuit, including configurable transistors, a controllable switch circuit, and an inverter chain. The configurable transistors include a first configurable transistor and a second configurable transistor. By adjusting the number of the first configurable transistors, the delay time of the differential signal passing through the inverter chain is adjusted to adjust the pre-emphasis time. The inverter chain is used to convert the differential signal into a reverse delay signal. By adjusting the number of the second configurable transistors and combining with the controllable switch circuit to control the output state of the reverse delay signal, the pre-emphasis current is adjusted; A common-mode level regulation circuit, for adjusting the number of the configurable transistors according to the current magnitude and output voltage of the pre-emphasis main circuit to balance the common-mode voltage.

[0008] In an embodiment, the controllable switch circuit is a CMOS transmission gate. The CMOS transmission gate includes an input end, an output end, and a control end. The input end of the CMOS transmission gate is connected to the first configurable transistor. One control end of the CMOS transmission gate is connected to the gate of the second configurable transistor. The output end of the CMOS transmission gate is connected to the drain of the same second configurable transistor. The two control ends of the CMOS transmission gate are used to receive control signals that are differential signals to adjust the number of the second configurable transistors.

[0009] In an embodiment, the common-mode level regulation circuit includes a comparator. The comparator includes a first input end, a second input end, and a comparison output end. The first input end is connected between two load resistors to obtain an output voltage. The second input end is connected to a reference circuit to obtain a reference voltage. The comparison output end is used to output the comparison result of the output voltage and the reference voltage. The common-mode level regulation circuit adjusts the number of the configurable transistors according to the comparison result until the output voltage is equal to half of the reference voltage.

[0010] In an embodiment, the first configurable transistor includes a first configurable PMOS transistor and a first configurable NMOS transistor. The pre-emphasis main circuit includes an adjustable PMOS transistor and an adjustable NMOS transistor controlled by the two-way regulation circuit; When the adjustable PMOS transistor is controlled by the two-way adjustment circuit, the second configuration transistor is a PMOS transistor with a configurable number. When the adjustable NMOS transistor is controlled by the two-way adjustment circuit, the second configuration transistor is an NMOS transistor with a configurable number.

[0011] In one embodiment, when the branch current of the adjustable PMOS transistor is greater than the branch current of the adjustable NMOS transistor, the number of the adjustable NMOS transistors connected is increased through the second configuration transistor; and / or, when the branch current of the adjustable PMOS transistor is greater than the branch current of the adjustable NMOS transistor, the number of the adjustable PMOS transistors connected is decreased through the second configuration transistor.

[0012] In one embodiment, when the output result of the comparison output terminal is high, the number of the second configuration transistors is controlled to decrease sequentially until the output result becomes low. The decreased number is recorded as the first reference number, and the number of the adjustable PMOS transistors is controlled to be at most lower than the number of the adjustable NMOS transistors by the first reference number; or, when the output result of the comparison output terminal is low, the number of the second configuration transistors is controlled to decrease sequentially until the output result becomes high. The decreased number is recorded as the second reference number, and the number of the adjustable NMOS transistors is controlled to be at most lower than the number of the adjustable PMOS transistors by the second reference number.

[0013] In one embodiment, the more the number of the first configuration transistors connected to the circuit, the smaller the delay time and the smaller the pre-emphasis ability; the fewer the number of the first configuration transistors connected to the circuit, the longer the delay time and the greater the pre-emphasis ability.

[0014] In one embodiment, the differential signal includes a first differential signal and a second differential signal. The drive circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The source of the first PMOS transistor is connected to a current source. The source of the first NMOS transistor is grounded. The drains of the second PMOS transistor and the second NMOS transistor are connected to a first node. The drains of the third PMOS transistor and the third NMOS transistor are connected to a second node; The pre-emphasis main circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to a current source, and the sources of the sixth NMOS transistor and the seventh NMOS transistor are grounded; the sixth PMOS transistor, the seventh PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are transistors with adjustable quantities. The drains of the sixth PMOS transistor and the fourth NMOS transistor are connected to the first node for pre-emphasizing the first differential signal; the drains of the seventh PMOS transistor and the fifth NMOS transistor are connected to the second node for pre-emphasizing the second differential signal. The bidirectional adjustment circuit includes a first adjustment circuit connected to the gate of the sixth PMOS transistor, a second adjustment circuit connected to the gate of the fourth NMOS transistor, a third adjustment circuit connected to the gate of the seventh PMOS transistor, and a fourth adjustment circuit connected to the gate of the fifth NMOS transistor. The first adjustment circuit and the third adjustment circuit are used to control the pre-emphasis current of the first differential signal; the second adjustment circuit and the fourth adjustment circuit are used to control the pre-emphasis current of the second differential signal.

[0015] In one embodiment, the first differential signal passes through the inverter chain. After the delay time and when the controllable switch circuit is turned on, a first reverse delay signal is obtained and output as high, controlling at least one transistor of the ninth PMOS transistor in the pre-emphasis main circuit to turn on and output a pre-emphasis current; and / or, the first differential signal passes through the inverter chain. After the delay time and when the controllable switch circuit is turned on, a first reverse delay signal is obtained and output as high, controlling at least one transistor of the tenth PMOS transistor in the pre-emphasis main circuit to output a pre-emphasis current.

[0016] In one embodiment, the second differential signal passes through the inverter chain. After the delay time and when the controllable switch circuit is turned on, a second reverse delay signal is obtained and output as low, controlling at least one transistor of the seventh NMOS transistor in the pre-emphasis main circuit to output a pre-emphasis current; and / or, the second differential signal passes through the inverter chain. After the delay time and when the controllable switch circuit is turned on, a second reverse delay signal is obtained and output as low, controlling at least one transistor of the eighth NMOS transistor in the pre-emphasis main circuit to output a pre-emphasis current.

[0017] The above-mentioned pre-emphasis circuit with bidirectional regulation of time and current adjusts the delay time by adjusting the number of configurable transistors, and adjusts the magnitude of the pre-emphasis current by adjusting the number of configurable transistors and the output state of the controllable switch circuit; moreover, while achieving bidirectional regulation, the common-mode voltage offset problem that may occur during the adjustment of the configurable transistors is processed by the common-mode level adjustment module, so as to meet higher pre-emphasis requirements with a smaller circuit area combined with fine circuit control logic, realizing precise and flexible control of the pre-emphasis circuit, improving the applicability to low-voltage circuits, and enhancing the driving ability of the LVDS driving circuit under large-capacitance loads.

[0018] To make the above and other objects, features, and advantages of the present application more obvious and understandable, the following specifically presents preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the technical solutions in the specific embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following-described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a schematic diagram of a low-voltage differential driving circuit provided by the present application.

[0021] Figure 2 It is a schematic diagram of a current pre-emphasis circuit in the related art provided by the present application.

[0022] Figure 3 It is a schematic diagram of a pre-emphasis circuit with bidirectional regulation of time and current provided by the present application.

[0023] Figure 4 It is a schematic diagram of the timing of differential signals provided by the present application.

[0024] Figure 5 It is a schematic diagram of the circuit control logic of a pre-emphasis circuit provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The foregoing and other technical contents, features, and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the accompanying drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0026] Reference Figure 1 , which is a schematic diagram of the structure of the LVDS driving circuit. The first differential signal out_pre_p and the second differential signal out_pre_n are a pair of differential signals, that is, when one is at a high level, the other is at a low level. Specifically, the first PMOS transistor PM1 is a current source, and the first NMOS transistor NM1 is a current drain, responsible for providing a stable current. When the first differential signal out_pre_p changes from high to low, the second differential signal out_pre_n changes from low to high. At this time, the second PMOS transistor PM2 and the third NMOS transistor NM3 are turned on, and the third PMOS transistor PM3 and the second NMOS transistor NM2 are turned off. The current flows from PM1 along PM2 to the middle first node OUT_N, passes through the first resistor R1 and the second resistor R2, and then returns to the second node OUT_P, and then flows to the ground through PM3 and NM1 to form a complete loop. The typical magnitude of the current I1 is 3.5 mA, and R1 = R2 = 50 ohms. Therefore, the total voltage drop Vod across the first resistor R1 and the second resistor R2 is 350 mV. When the load capacitance is large (usually due to large capacitance loads caused by package pins or multiplexing of many interfaces), the 3.5 mA current cannot ensure the signal's tr / tf (rise / fall time, the time for Vod to change from 20% (80%) of the final voltage to 80% (20%) of the final voltage). Because the larger the capacitance, the slower the charging, and the slower the voltage rises (falls).

[0027] It should be noted that for the convenience of display, in the drawings of the present application, each part of the circuit diagram is connected by the same name connection method, that is, signal terminals with the same name have a connection relationship. The xth PMOS transistor in the present application is simply referred to as PMx, and the xth NMOS transistor is simply referred to as NMx.

[0028] To optimize the signal rise / fall time, many designs use a current pre-emphasis circuit to provide a large current at the initial stage of charging and optimize the signal rise / fall time. Reference Figure 2, which is a current pre - emphasis circuit in the related art. Among them, transistors PM5’, PM6’, NM5’, and NM6’ are respectively connected to PM2, PM3, NM2, and NM3 in the driving circuit. The first differential signal out_pre_p and the second differential signal out_pre_n are delayed by a delay time Δt to obtain the first reverse - delayed signal out_pre_p_delay_inv and the second reverse - delayed signal out_pre_n_delay_inv respectively. When the first differential signal out_pre_p changes from high to low, out_pre_p_delay_inv, which was low before, becomes high after a delay of Δt. In this way, PM5’ and PM7’ will conduct together with PM2 (the delay time is Δt, which is equivalent to the pre - emphasis circuit on the right charging current for an additional Δt time to increase the charging speed and improve tr). Similarly, at this time, NM6’, NM8’ and NM3 conduct simultaneously (NM6’ and NM8’ also last for Δt). Through current pre - emphasis, sufficient driving ability can be ensured when there is a large capacitive load, and both tr and tf meet the requirements.

[0029] In the research, the inventors of the present application found that in the current pre - emphasis circuit in the related art, to adjust the pre - emphasis ability, the number of bias transistors and the same bias voltages vb1 and vbias used in the main bias circuit need to be adjusted, resulting in the following defects: For the current source PM4’ and current drain NM4’ on the pre - emphasis circuit, because the transistors from PM5’ to NM8’ in the middle consume a lot of voltage, the VDS voltage left for the current source PM4’ and current drain NM4’ is very small. To increase VDS, only the size of the transistors from PM5’ to NM8’ can be increased. (If VDS is very small, the current source PM4’ and current drain NM4’ cannot operate in the saturation region), and the area overhead is relatively large. Therefore, it is not suitable for working under low - voltage conditions; This structure requires a very large - sized current source PM4’ and current drain NM4’ as well as the transistors from PM5’ to NM8’ in the middle, and is not suitable for the case of a large load capacitance; To adjust the driving ability by changing the number of the current source PM4’ and current drain NM4’, a large area needs to be reserved for the current source PM4’ and current drain NM4’ in order to ensure sufficient driving current.

[0030] To solve the above - mentioned technical problems, the embodiments of the present application provide a pre - emphasis circuit with bidirectional adjustment of time and current. Refer to Figure 3, the pre-emphasis circuit includes a pre-emphasis main circuit, a bidirectional adjustment circuit, and a common-mode level adjustment circuit. Among them, the pre-emphasis circuit is applied to a driving circuit, especially suitable for a low-voltage differential driving circuit. The pre-emphasis main circuit is used to provide a pre-emphasis current for the driving circuit to enhance the high-frequency components of the differential signal, thereby compensating for the high-frequency loss during transmission and improving the signal quality. The bidirectional adjustment circuit includes configurable transistors, a controllable switch circuit, and an inverter chain. The configurable transistors include a first configurable transistor and a second configurable transistor. By adjusting the number of the first configurable transistors, the delay time of the differential signal passing through the inverter chain is adjusted to adjust the magnitude of the pre-emphasis time; the inverter chain is used to convert the differential signal into a reverse delay signal; by adjusting the number of the second configurable transistors and combining the controllable switch circuit to control the output state of the reverse delay signal, the magnitude of the pre-emphasis current is adjusted. The common-mode level adjustment circuit is used to adjust the number of configurable transistors according to the current magnitude and output voltage of the pre-emphasis main circuit to balance the common-mode voltage.

[0031] The pre-emphasis circuit of this embodiment adjusts the delay time by adjusting the number of configurable transistors, and adjusts the magnitude of the pre-emphasis current by adjusting the number of configurable transistors and the output state of the controllable switch circuit; moreover, while realizing bidirectional adjustment, the common-mode voltage offset problem that may occur during the adjustment of the configurable transistors is processed by the common-mode level adjustment module, so as to meet higher pre-emphasis requirements with a smaller circuit area combined with a fine circuit control logic, realizing precise and flexible control of the pre-emphasis circuit, improving the applicability to low-voltage circuits, and enhancing the driving ability of the LVDS driving circuit under large-capacitance loads.

[0032] In one implementation, the controllable switch circuit is a CMOS transmission gate. The CMOS transmission gate includes an input terminal, an output terminal, and a control terminal. The input terminal of the CMOS transmission gate is connected to the first configurable transistor. One control terminal of the CMOS transmission gate is connected to the gate of the second configurable transistor. The output terminal of the CMOS transmission gate is connected to the drain of the same second configurable transistor. The two control terminals of the CMOS transmission gate are used to receive control signals that are differential signals to adjust the number of the second configurable transistors. By designing the circuit connection of the COMS transmission gate and the configurable transistors combined with the circuit control logic, precise control and flexible adjustment of the pre-emphasis current are realized to adapt to changes in different working conditions and data rates, better compensate for the high-frequency loss of the differential signal during transmission, make the rising edge and falling edge of the signal steeper, thereby reducing the bit error rate and improving the accuracy and reliability of data transmission.

[0033] In one implementation, refer to Figure 3, the common-mode level adjustment circuit includes a comparator, and the comparator includes a first input terminal, a second input terminal, and a comparison output terminal; the first input terminal is connected between two load resistors to obtain an output voltage, the second input terminal is connected to a reference circuit to obtain a reference voltage, and the comparison output terminal is used to output the comparison result of the output voltage and the reference voltage; the common-mode level adjustment circuit adjusts the number of configurable transistors according to the comparison result until the output voltage is equal to half of the reference voltage. Among them, the reference voltage here is the power supply voltage. In this way, the adaptive adjustment ability of the circuit is improved, so that the circuit can automatically adjust the number of configurable transistors according to the actual pre-emphasis voltage change, avoid the adverse effect on signal transmission caused by the offset between the pull-up current of the PMOS transistor and the pull-down current of the NMOS transistor, maintain the stability of the common-mode level, and further improve the stability and reliability of signal transmission.

[0034] In one embodiment, the first configuration transistor includes a first configuration PMOS transistor and a first configuration NMOS transistor, and the pre-emphasis main circuit includes an adjustable PMOS transistor and an adjustable NMOS transistor controlled by a bidirectional adjustment circuit; when the bidirectional adjustment circuit controls the adjustable PMOS transistor, the second configuration transistor is a PMOS transistor with a configurable number, and when the bidirectional adjustment circuit controls the adjustable NMOS transistor, the second configuration transistor is an NMOS transistor with a configurable number.

[0035] When the branch current of the adjustable PMOS transistor is greater than the branch current of the adjustable NMOS transistor, the number of accesses of the adjustable NMOS transistor is increased through the second configuration transistor; and / or, when the branch current of the adjustable PMOS transistor is greater than the branch current of the adjustable NMOS transistor, the number of accesses of the adjustable PMOS transistor is reduced through the second configuration transistor.

[0036] Similarly, when the branch current of the adjustable PMOS transistor is less than the branch current of the adjustable NMOS transistor, the number of accesses of the adjustable NMOS transistor is reduced through the second configuration transistor, and / or, when the branch current of the adjustable PMOS transistor is less than the branch current of the adjustable NMOS transistor, the number of accesses of the adjustable PMOS transistor is increased through the second configuration transistor.

[0037] Further, when the output result at the comparison output terminal is high, control the number of the second configuration transistors to decrease sequentially until the output result becomes low, record the decreasing number as the first reference number, and control the number of the adjustable PMOS transistors to be at most lower than the first reference number by the number of the adjustable NMOS transistors; or, when the output result at the comparison output terminal is low, control the number of the second configuration transistors to decrease sequentially until the output result becomes high, record the decreasing number as the second reference number, and control the number of the adjustable NMOS transistors to be at most lower than the second reference number by the number of the adjustable PMOS transistors.

[0038] In this embodiment, through the precise adjustment of the pre-emphasis main circuit by the bidirectional adjustment circuit, that is, when the pre-emphasis time is fixed, by increasing the transistors, the pre-emphasis current can be increased, and the stronger the pre-emphasis ability; similarly, when the transistors are reduced, the pre-emphasis current will be reduced, and the weaker the pre-emphasis ability. Thus, through the detection and comparison of the common-mode level adjustment circuit and the adjustment of the bidirectional adjustment circuit, the common-mode voltage can be better balanced, the problem of common-mode point offset can be improved, and the stability of the pre-emphasis circuit can be enhanced.

[0039] In one implementation, the more the number of first configuration transistors connected to the circuit, the smaller the delay time and the smaller the pre-emphasis ability; the fewer the number of first configuration transistors connected to the circuit, the higher the delay time and the greater the pre-emphasis ability. By adjusting the number of first configuration transistors, it is possible to achieve precise adjustment of the pre-emphasis time when the pre-emphasis current is fixed, thereby achieving flexible and precise control of the pre-emphasis circuit.

[0040] Reference Figure 3 , in one implementation, the differential signal includes a first differential signal and a second differential signal, and the LVDS driving circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The source of the first PMOS transistor is connected to the current source, the source of the first NMOS transistor is grounded, the drains of the second PMOS transistor and the second NMOS transistor are connected to the first node, and the drains of the third PMOS transistor and the third NMOS transistor are connected to the second node.

[0041] The pre-emphasis main circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to the current source, and the sources of the sixth NMOS transistor and the seventh NMOS transistor are grounded; the sixth PMOS transistor, the seventh PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are transistors with adjustable numbers. The drains of the sixth PMOS transistor and the fourth NMOS transistor are connected to the first node for pre-emphasizing the first differential signal; the drains of the seventh PMOS transistor and the fifth NMOS transistor are connected to the second node for pre-emphasizing the second differential signal. Thus, by directly connecting the pre-emphasis main circuit to the power supply, the transistors of the current source and the current drain are omitted, simplifying the pre-emphasis main circuit to be applicable to the pre-emphasis of the low-voltage driving circuit, and achieving higher pre-emphasis requirements with a smaller area.

[0042] The bidirectional adjustment circuit includes a first adjustment circuit connected to the gate of the sixth PMOS transistor, a second adjustment circuit connected to the gate of the fourth NMOS transistor, a third adjustment circuit connected to the gate of the seventh PMOS transistor, and a fourth adjustment circuit connected to the gate of the fifth NMOS transistor. The first adjustment circuit and the third adjustment circuit are used to control the pre-emphasis current of the first differential signal; the second adjustment circuit and the fourth adjustment circuit are used to control the pre-emphasis current of the second differential signal.

[0043] Further, the first adjustment circuit includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor. The eighth PMOS transistor and the ninth NMOS transistor are first configuration transistors, and the tenth PMOS transistor is a second configuration transistor.

[0044] The second adjustment circuit includes an eleventh PMOS transistor, a twelfth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor. The eleventh PMOS transistor and the twelfth NMOS transistor are first configuration transistors, and the tenth NMOS transistor is a second configuration transistor.

[0045] The third adjustment circuit includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor. The thirteenth PMOS transistor and the fourteenth NMOS transistor are first configuration transistors, and the fifteenth PMOS transistor is a second configuration transistor.

[0046] The fourth adjustment circuit includes a sixteenth PMOS transistor, a seventeenth PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a seventeenth NMOS transistor. The sixteenth PMOS transistor and the seventeenth NMOS transistor are first configuration transistors, and the fifteenth NMOS transistor is a second configuration transistor.

[0047] The first adjustment circuit and the second adjustment circuit share the same inverter chain; the third adjustment circuit and the fourth adjustment circuit share the same inverter chain to save circuit area.

[0048] Further, after the first differential signal passes through the inverter chain, when the delay time has elapsed and the controllable switch circuit is turned on, a first reverse delay signal is output as high, controlling at least one transistor of the ninth PMOS transistor in the pre-emphasis main circuit to turn on and output a pre-emphasis current; and / or, after the first differential signal passes through the inverter chain, when the delay time has elapsed and the controllable switch circuit is turned on, a first reverse delay signal is output as high, controlling at least one transistor of the tenth PMOS transistor in the pre-emphasis main circuit to output a pre-emphasis current.

[0049] Further, the second differential signal passes through an inverter chain, and after a delay time and when the controllable switch circuit is turned on, a second inverted delay signal is obtained with an output of low, controlling at least one transistor of the seventh NMOS transistor of the pre-emphasis main circuit to output a pre-emphasis current; and / or, the second differential signal passes through an inverter chain, and after a delay time and when the controllable switch circuit is turned on, a second inverted delay signal is obtained with an output of low, controlling at least one transistor of the eighth NMOS transistor of the pre-emphasis main circuit to output a pre-emphasis current.

[0050] Reference Figure 4 , is a signal timing diagram of the pre-emphasis circuit based on the present application. Below, taking the moment ① of Figure 4 as an example, in combination with Figure 3 the upper left circuit diagram and the lower right circuit diagram of

[0051] the adjustment and control process of the pre-emphasis circuit of the present application will be described in detail. Among them, <1:0> behind the transistor represents two transistors, and <3:0> behind the transistor represents four transistors, indicating that these are configurable or adjustable transistors. For example, only selecting <0> means that <1> does not need to participate, so the transistor corresponding to <1> is turned off. The gate of the PMOS transistor is set high to be turned off and low to be turned on; the gate of the NMOS transistor is set low to be turned off and high to be turned on.

[0052] Specifically, out_pre_p_delay_invp1<3:0> is an inverted and delayed signal of out_pre_p with a delay of △t. Therefore, when out_pre_p changes from high to low, after a time of △t, out_pre_p_delay_invp1<3:0> becomes high. During the △t time, PM4 and PM6<3:0> are turned on, and the current flows from the power supply through PM4 and PM6<3:0>, reaches the OUT_N point to participate in pre-emphasis, and flows back to the ground through NM5<3:0> and NM7, forming a complete loop.

[0053] Taking the first adjustment circuit as an example, illustrate how the delay time Δt is achieved and how to control the pre-emphasis current: out_pre_p passes through several levels of delay to reach A1. A1 passes through an inverter (formed by PM8, PM9, NM8, and NM9), and then reaches the output out_pre_p_delay_invp1<3:0> through the input terminal TG1 of the CMOS transmission gate. When selecting <0> and closing <3> for out_pre_p_delay_invp1<3:0>, for example, emp_ItrimN<3:0> = 0001, and emp_ItrimP<3:0> is the opposite = 1110. At this time, TG<3>, TG<2>, and TG<1> are all closed, TG<0> is open, PM10<3>, PM10<2>, and PM10<1> are open, the outputs of out_pre_p_delay_invp1<3>, out_pre_p_delay_invp1<2>, and out_pre_p_delay_invp1<1> are high, controlling PM6<3>, PM6<2>, and PM6<1> to close; PM10<0> is closed, and the output of out_pre_p_delay_invp1<0> is controlled by the previous stage and is low, controlling PM6<0> to open and normally participate in pre-emphasis. The same principle applies to the other adjustment circuits. The difference is that the NMOS transistors are controlled by outputting a constant low to turn them off.

[0054] Taking the first adjustment circuit as an example, illustrate the scheme of adjusting the pre-emphasis delay magnitude to adjust the pre-emphasis ability: By controlling the switches of PM8<3:0> and NM9<3:0> (controlled by emp_TtrimP<3:0> and emn_TtrimN<3:0> respectively), the magnitudes of the pull-up and pull-down currents are controlled. Moreover, the more transistors connected in the circuit, the greater the pull-up and pull-down capabilities, the lower the delay Δt, and the weaker the pre-emphasis ability; similarly, the fewer transistors connected in the circuit, the smaller the pull-up and pull-down capabilities, the greater the delay Δt, and the stronger the pre-emphasis ability.

[0055] It should be noted that for the specific working processes of the other adjustment circuits, refer to the above description of the first adjustment circuit and will not be elaborated here.

[0056] Taking the calibration of the currents of the PMOS and NMOS transistors from the upper left to the lower right as an example: Atrim1 and Atrim1_n are a pair of control signals and are differential signals. When it is necessary to calibrate whether the currents of the PMOS branch and the NMOS branch (upper left and lower right) match, Atrim1 is pulled high, out_pre_p is pulled low, the branch is opened, and the current flows from the power supply through PM4 and PM6, through the resistor to NM5 and NM7, and then to the ground. Ideally, the Vcom voltage should be equal to half of the power supply voltage, that is, the vref voltage. According to the result of the comparator, it is possible to judge and adjust the matching degree of the PMOS current and the NMOS current and optimize the common-mode point of the pre-emphasis circuit.

[0057] Specifically, referring to Figure 5 , the adjustment process includes the following steps: Step 1: Initially, turn off the drive circuit, pull out_pre_p low, pull Atrim1 high, and turn on the PMOS in the upper left and the NMOS in the lower right corners of the pre-emphasis circuit.

[0058] Step 2: Obtain and judge the level of the output result comp_out.

[0059] Step 3: If the comp_out output is high, the signal of emp_ItrimN1<3:0> starts to decrease by 1 in sequence from all 1s (i.e., 1111) until the output result comp_out is low; record the reduced quantity at this time as the reference quantity n1.

[0060] Step 4: When adjusting the pre-emphasis ability, set the gear of the PMOS to be n1 gears lower than that of the NMOS, and re-run the above process according to the actual gear setting of the NMOS to obtain the most accurate n1* at the current gear.

[0061] Step 5: If the comp_out output is low, emp_ItrimN4<3:0> starts to decrease by 1 in sequence from all 1s until the output is low; record the reduced quantity at this time as the reference quantity n4.

[0062] Step 6: When adjusting the pre-emphasis ability, set the gear of the NMOS to be n4 gears lower than that of the PMOS, and re-run the above process according to the actual gear setting of the PMOS to obtain the most accurate n4* at the current gear.

[0063] In this embodiment, through the common-mode level adjustment circuit, initially, the reference quantity for transistor adjustment is obtained, so that when adjusting the pre-emphasis ability, the adjustment gear is set according to the reference quantity, solving the problem of the common-mode voltage offset caused by the mismatch between the pull-up current of the pmos transistor and the pull-down current of the nmos transistor due to processes and other reasons, and improving the stability of the adjustment process of the pre-emphasis circuit.

[0064] In summary, the pre-emphasis circuit with two-way regulation of time and current according to the embodiments of the present application simplifies the pre-emphasis main circuit, making it also applicable to low-voltage pre-emphasis, and a larger pre-emphasis capability can be achieved with a smaller area; the pre-emphasis capability can also be adjusted from two dimensions of pre-emphasis time and pre-emphasis current magnitude, which is more flexible and has stronger adaptability; the common-mode voltage of the currents in the PMOS branch and the NMOS branch of the pre-emphasis circuit can also be improved, avoiding the problem of LVDS common-mode point offset caused by the mismatch of the currents in the two branches, and further improving the stability and applicability of the pre-emphasis circuit.

[0065] It should be noted that for those of ordinary skill in the art of the present technology, without departing from the principle of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of separate embodiments for clarity can also be provided in a single embodiment by combination. Conversely, the various features of the present disclosure described in the context of a single embodiment for clarity can also be provided separately or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A pre-emphasis circuit with bidirectional regulation of time and current, characterized in that, The pre-emphasis circuit is applicable to a driving circuit, and the pre-emphasis circuit includes: A pre-emphasis main circuit, including a plurality of transistors, for providing a pre-emphasis current for the driving circuit to enhance the high-frequency component of the differential signal; A bidirectional adjustment circuit, including configurable transistors, a controllable switch circuit, and an inverter chain. The configurable transistors include a first configurable transistor and a second configurable transistor. By adjusting the number of the first configurable transistors, the delay time of the differential signal passing through the inverter chain is adjusted to adjust the pre-emphasis time. The inverter chain is used to convert the differential signal into a reverse delay signal. By adjusting the number of the second configurable transistors and combining the controllable switch circuit to control the output state of the reverse delay signal, the magnitude of the pre-emphasis current is adjusted; A common-mode level adjustment circuit, for adjusting the number of the configurable transistors according to the current magnitude and output voltage of the pre-emphasis main circuit to balance the common-mode voltage.

2. The pre-emphasis circuit with two-way adjustment of time and current according to claim 1, wherein The controllable switch circuit is a CMOS transmission gate. The CMOS transmission gate includes an input end, an output end, and a control end. The input end of the CMOS transmission gate is connected to the first configurable transistor. One control end of the CMOS transmission gate is connected to the gate of the second configurable transistor. The output end of the CMOS transmission gate is connected to the drain of the same second configurable transistor. The two control ends of the CMOS transmission gate are used to receive control signals that are differential signals to adjust the number of the second configurable transistors.

3. The pre-emphasis circuit with two-way regulation of time and current according to claim 2, characterized in that, The common-mode level adjustment circuit includes a comparator. The comparator includes a first input end, a second input end, and a comparison output end. The first input end is connected between two load resistors to obtain an output voltage. The second input end is connected to a reference circuit to obtain a reference voltage. The comparison output end is used to output the comparison result of the output voltage and the reference voltage; The common-mode level adjustment circuit adjusts the number of the configurable transistors according to the comparison result until the output voltage is equal to half of the reference voltage.

4. A pre-emphasis circuit with bidirectional regulation of time and current according to claim 3, characterized in that, The first configurable transistor includes a first configurable PMOS transistor and a first configurable NMOS transistor. The pre-emphasis main circuit includes an adjustable PMOS transistor and an adjustable NMOS transistor controlled by the bidirectional adjustment circuit; When the adjustable PMOS transistor is controlled by the bidirectional adjustment circuit, the second configurable transistor is a PMOS transistor with a configurable number. When the adjustable NMOS transistor is controlled by the bidirectional adjustment circuit, the second configurable transistor is an NMOS transistor with a configurable number.

5. A pre-emphasis circuit with two-way adjustment of time and current according to claim 4, characterized in that, When the branch current of the adjustable PMOS transistor is greater than the branch current of the adjustable NMOS transistor, the number of the adjustable NMOS transistors connected in is increased through the second configurable transistor; and / or, when the branch current of the adjustable PMOS transistor is greater than the branch current of the adjustable NMOS transistor, the number of the adjustable PMOS transistors connected in is reduced through the second configurable transistor.

6. The pre-emphasis circuit with two-way adjustment of time and current according to claim 5, characterized in that When the output result at the comparison output terminal is high, control the number of the second configuration transistors to decrease sequentially until the output result becomes low. Record the decreased number as the first reference number, and control the number of the adjustable PMOS transistors to be at most lower than the number of the adjustable NMOS transistors by the first reference number; or, when the output result at the comparison output terminal is low, control the number of the second configuration transistors to decrease sequentially until the output result becomes high. Record the decreased number as the second reference number, and control the number of the adjustable NMOS transistors to be at most lower than the number of the adjustable PMOS transistors by the second reference number.

7. A pre-emphasis circuit with bidirectional regulation of time and current according to claim 1, characterized in that, The more the number of the first configuration transistors connected to the circuit, the smaller the delay time and the smaller the pre-emphasis ability; the fewer the number of the first configuration transistors connected to the circuit, the longer the delay time and the greater the pre-emphasis ability.

8. A pre-emphasis circuit with bidirectional adjustment of time and current according to claim 1, characterized in that The differential signal includes a first differential signal and a second differential signal. The driving circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The source of the first PMOS transistor is connected to a current source, the source of the first NMOS transistor is grounded, the drains of the second PMOS transistor and the second NMOS transistor are connected to a first node, and the drains of the third PMOS transistor and the third NMOS transistor are connected to a second node. The pre-emphasis main circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to a current source, and the sources of the sixth NMOS transistor and the seventh NMOS transistor are grounded; the sixth PMOS transistor, the seventh PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are transistors with adjustable numbers. The drains of the sixth PMOS transistor and the fourth NMOS transistor are connected to the first node for pre-emphasizing the first differential signal; the drains of the seventh PMOS transistor and the fifth NMOS transistor are connected to the second node for pre-emphasizing the second differential signal. The bidirectional adjustment circuit includes a first adjustment circuit connected to the gate of the sixth PMOS transistor, a second adjustment circuit connected to the gate of the fourth NMOS transistor, a third adjustment circuit connected to the gate of the seventh PMOS transistor, and a fourth adjustment circuit connected to the gate of the fifth NMOS transistor. The first adjustment circuit and the third adjustment circuit are used to control the pre-emphasis current of the first differential signal; the second adjustment circuit and the fourth adjustment circuit are used to control the pre-emphasis current of the second differential signal.

9. A pre-emphasis circuit with bidirectional adjustment of time and current according to claim 8, characterized in that, The first differential signal passes through the inverter chain. After the delay time and when the controllable switch circuit is turned on, a first inverted delay signal is obtained with a high output, controlling at least one transistor of the ninth PMOS transistor in the pre-emphasis main circuit to turn on and output a pre-emphasis current; and / or, the first differential signal passes through the inverter chain. After the delay time and when the controllable switch circuit is turned on, a first inverted delay signal is obtained with a high output, controlling at least one transistor of the tenth PMOS transistor in the pre-emphasis main circuit to output a pre-emphasis current.

10. A pre-emphasis circuit with bidirectional adjustment of time and current according to claim 8, characterized in that, The second differential signal passes through the inverter chain. After the delay time and when the controllable switch circuit is turned on, a second inverted delay signal is obtained with a low output, controlling at least one transistor of the seventh NMOS transistor in the pre-emphasis main circuit to output a pre-emphasis current; and / or, the second differential signal passes through the inverter chain. After the delay time and when the controllable switch circuit is turned on, a second inverted delay signal is obtained with a low output, controlling at least one transistor of the eighth NMOS transistor in the pre-emphasis main circuit to output a pre-emphasis current.

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