Multi-core synchronization method, device and system and storage medium

Abstract

The invention provides a multi-core synchronization method, device and system and a storage medium, and belongs to the technical field of data processing.The method comprises the steps that a first synchronization request is received from a first processing unit, and the first synchronization request indicates that a synchronization task of the first processing unit is completed, the first synchronization request carries a target synchronization domain identifier of a synchronization task executed by the first processing unit; adding 1 to a first numerical value of a target counter corresponding to the target synchronization domain identifier according to the first synchronization request to obtain a second numerical value; if the second value is smaller than the preset value of the processing unit for processing the synchronization task corresponding to the target synchronization domain identifier, not responding; if the second value is equal to the preset value, sending first response information; wherein the first response information is used for indicating a second processing unit corresponding to the target synchronization domain identifier in the plurality of processing units to execute a subsequent task. According to the scheme, whether synchronization is completed or not is determined through the multi-core synchronization device, frequent polling of public resources is not needed, and the synchronization efficiency is improved.

Description

Technical Field

[0001] This application belongs to the technical field of data processing, and particularly relates to a multi-core synchronization method, device, system, and storage medium. Background Art

[0002] With the development of data processing technology, in data processing, in order to improve the efficiency of data processing, multi-core processors are often used for data processing. A multi-core processor includes multiple processing units, and the multiple processing units can access the same data cache area to perform synchronization tasks.

[0003] In related technologies, semaphores are used to achieve synchronization between processing units. Among them, a semaphore is a non-negative counter. By setting a semaphore in the data cache area, access to the data cache area by the processing unit is restricted. That is, it is judged whether the processing unit has the permission to access the data cache area through the value of the semaphore. For example, when the value of the semaphore is greater than 0, the processing unit can access the data cache area, otherwise access to the cache area is not allowed.

[0004] In the above related technologies, when accessing the data cache area, it is necessary to frequently read and write and poll the semaphore in the data cache area, which affects the access efficiency of the data cache area and further affects the multi-core synchronization efficiency. Summary of the Invention

[0005] The purpose of this application is to provide a multi-core synchronization method, device, system, and storage medium, aiming to solve the problem of low synchronization efficiency in the traditional synchronization process.

[0006] The first aspect of the embodiment of this application provides a multi-core synchronization method, which is applied to a system including multiple processing units, and the multiple processing units include a first processing unit. The method includes:

[0007] Receiving a first synchronization request from the first processing unit, where the first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed, and the first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit;

[0008] Adjusting the value of the target counter from a first value to a second value according to the first synchronization request, where the second value is greater than the first value, and the difference between the second value and the first value is 1, and the target counter is the counter corresponding to the target synchronization domain identifier;

[0009] If the second value is less than the preset value corresponding to the target synchronization domain identifier, determining not to send the first response information; or,

[0010] If the second value is equal to the preset value corresponding to the target synchronization domain identifier, send a first response message;

[0011] Wherein, the first response message is used to instruct the processing unit corresponding to the target synchronization domain identifier among the multiple processing units to perform subsequent tasks, and the preset value is the number of processing units for processing the synchronization task.

[0012] In the embodiments of the present application, by setting a multi-core synchronization device for multiple processing units, the multi-core synchronization device records the processing units that need to be synchronized. When a processing unit completes the current synchronization task, it sends a synchronization request to the multi-core synchronization device. The multi-core synchronization device adjusts the count value of the target counter corresponding to the synchronization domain according to the synchronization domain identifier carried in the synchronization request. When the count value of the target counter is equal to the preset data corresponding to the synchronization domain identifier, it indicates that all the processing units executing the current synchronization task have completed synchronization. In this way, the multi-core synchronization device sends a first response message to the multiple processing units corresponding to the synchronization domain, so that the processing units can continue to execute the next task. In this way, the multi-core synchronization device is used to determine whether the synchronization is completed, without frequently polling the common resources, improving the synchronization efficiency.

[0013] In some embodiments, the step of if the second value is equal to the preset value corresponding to the target synchronization domain identifier, send a first response message, includes:

[0014] If the second value is equal to the preset value corresponding to the target synchronization domain identifier, according to the target synchronization domain identifier, determine the unit identifiers of at least one of the second processing units from multiple processing unit information tables, where the second processing unit is a processing unit among the multiple processing units that has sent a synchronization request carrying the target synchronization domain identifier;

[0015] Send the first response message to the second processing unit according to the unit identifier of the second processing unit.

[0016] Recording the unit identifiers of the processing units that have completed synchronization through the processing unit information table facilitates finding all the processing units corresponding to the same synchronization domain identifier, saving the time for finding the processing units, and further improving the synchronization efficiency.

[0017] In some embodiments, the method further includes:

[0018] Switch the status of the processing unit information table of the second processing unit from the running state to the waiting state;

[0019] The step of sending the first response message to the second processing unit according to the unit identifier of the second processing unit includes:

[0020] Determine the status of the multiple processing unit information tables at preset time intervals;

[0021] If the status of the multiple processing unit information tables includes the waiting status, send the first response information to the processing unit corresponding to the processing unit information table in the waiting status among the multiple processing unit information tables.

[0022] Since the multi-core synchronization device can be connected to multiple processing units, in order to avoid the blocking problem caused by simultaneously sending the first response information to multiple processing units, in the embodiments of the present application, the status of the processing unit information table is first switched from the running status to the waiting status, and the first response information is sent to the processing unit in the processing unit information table in the waiting status at preset time intervals, which ensures timely notification of the completion of synchronization for the processing unit while preventing blocking caused by excessive information content.

[0023] In some embodiments, the first synchronization request further carries the unit identifier of the first processing unit;

[0024] After receiving the first synchronization request from the first processing unit, the method further includes:

[0025] Correspondingly store the unit identifier of the first processing unit and the target synchronization domain identifier into the first processing unit information table;

[0026] Switch the status of the first processing unit information table from the idle status to the running status.

[0027] The multi-core synchronization device correspondingly stores the unit identifier of the first processing unit and the synchronization domain identifier into the processing unit information table, and switches the status of the processing unit information table from the idle status to the running status, so as to record the unit identifiers of the processing units corresponding to the same synchronization domain identifier through the processing unit information table, so that when synchronization is completed, the first response information can be sent to all the processing units corresponding to the target synchronization domain identifier.

[0028] In some embodiments, the first synchronization request includes a status field,

[0029] The correspondingly storing the unit identifier of the first processing unit and the target synchronization domain identifier into the first processing unit information table includes:

[0030] If the status field indicates that the first synchronization request is a record request, correspondingly store the unit identifier of the first processing unit and the target synchronization domain identifier into the first processing unit information table;

[0031] The method further includes:

[0032] If the status field indicates that the first synchronization request is a cache request, cache the synchronization request;

[0033] Send second response information to the first processing unit, where the second response information is used to indicate that the first synchronization request has been cached.

[0034] By adding a status field to the synchronization request, different types of synchronization requests can be sent to different bypasses, so that it is not necessary to wait for all processing units corresponding to the synchronization domain identifier to complete synchronization, and the processing unit can continue to execute subsequent tasks, improving the synchronization efficiency and the efficiency of the processing unit itself.

[0035] A second aspect of the embodiments of the present application provides a multi-core synchronization device, where the multi-core synchronization device includes: a synchronization domain status recording module and a processing unit information recording module;

[0036] The synchronization domain status recording module stores target counters corresponding to multiple synchronization domain identifiers, and is used to receive a first synchronization request from the first processing unit. The first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed. The first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit; adjust the value of the target counter from a first value to a second value according to the first synchronization request, where the second value is greater than the first value, and the difference between the second value and the first value is 1. The target counter is the counter corresponding to the target synchronization domain identifier; if the second value is less than the preset value corresponding to the target synchronization domain identifier, determine not to send the first response information; or, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, send a release information to the processing unit information recording module, where the release information carries the target synchronization domain identifier;

[0037] The processing unit information recording module stores multiple processing unit information tables, and is used to, in response to receiving the release information sent by the synchronization domain status recording module, determine the unit identifiers of multiple processing units corresponding to the target synchronization domain identifier from the multiple processing unit information tables according to the target synchronization domain identifier carried in the release information, and send a first response information to the processing unit corresponding to the target synchronization domain identifier according to the unit identifier.

[0038] In some embodiments, the processing unit information recording module is used to, in response to receiving a first synchronization request sent by a first processing unit, store the unit identifier of the first processing unit and the target synchronization domain identifier in a first processing unit information table in a corresponding manner; switch the status of the first processing unit information table from an idle state to a running state.

[0039] In some embodiments, the first synchronization request includes a status field, and the multi-core synchronization device further includes a cache module;

[0040] The multi-core synchronization device is further configured to parse the first synchronization request to obtain a status field; if the status field indicates that the first synchronization request is a cache request, send the first synchronization request to the multi-core synchronization device; if the status field indicates that the first synchronization request is a record request, send the first synchronization request to the processing unit information recording module;

[0041] The cache module is configured to, in response to receiving the first synchronization request, cache the first synchronization request, and send second response information to a first processing unit corresponding to the first synchronization request, where the second response information is used to indicate that the synchronization request of the first processing unit has been cached.

[0042] In some embodiments, the processing unit information recording module is further configured to, in response to receiving a first synchronization request sent by a first processing unit, store the unit identifier of the first processing unit and the target synchronization domain identifier in a processing unit information table in a corresponding manner; and switch the status of the processing unit information table from an idle state to an operating state;

[0043] The processing unit information recording module is further configured to, after receiving the release information, switch the status of the processing unit information tables of the first processing unit and the second processing unit from an operating state to a waiting state; determine the status of the multiple processing unit information tables at preset time intervals; if the status of the multiple processing unit information tables includes the waiting state, send the first response information to a processing unit corresponding to the processing unit information table in the waiting state among the multiple processing unit information tables; and switch the status of the processing unit information table corresponding to the processing unit that has sent the first response information from the waiting state to the idle state.

[0044] A third aspect of the embodiments of the present application provides a multi-core synchronization system, where the multi-core synchronization system includes multiple processing units and the multi-core synchronization device according to any one of the second aspects of the embodiments of the present application;

[0045] For any processing unit, the processing unit is configured to, in response to the processing unit completing a synchronization task to be performed, send a synchronization request to the multi-core synchronization device, where the synchronization request is used to indicate that the synchronization task of the processing unit has been completed, the first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit;

[0046] The multi-core synchronization device is configured to execute the multi-core synchronization method according to any one of the first aspects of the present application.

[0047] The fourth aspect of the embodiments of the present application provides a multi-core synchronization device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the above-mentioned multi-core synchronization method is implemented.

[0048] The fifth aspect of the embodiments of the present application provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned multi-core synchronization method is implemented.

[0049] The beneficial effects of the embodiments of the present invention compared with the prior art are: BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 The schematic diagram of a multi-core synchronization system provided by an exemplary embodiment is shown;

[0051] Figure 2 The functional schematic diagram of a multi-core synchronization device provided by an exemplary embodiment is shown;

[0052] Figure 3 The functional schematic diagram of a multi-core synchronization device provided by an exemplary embodiment is shown;

[0053] Figure 4 The flowchart of a multi-core synchronization method provided by an exemplary embodiment is shown;

[0054] Figure 5 The flowchart of a multi-core synchronization method provided by an exemplary embodiment is shown;

[0055] Figure 6 The flowchart of a multi-core synchronization method provided by an exemplary embodiment is shown;

[0056] Figure 7 The flowchart of a multi-core synchronization method provided by an exemplary embodiment is shown;

[0057] Figure 8 The schematic diagram of a synchronization model to which the multi-core synchronization method provided by an exemplary embodiment is applied is shown;

[0058] Figure 9 The schematic diagram of a synchronization model to which the multi-core synchronization method provided by an exemplary embodiment is applied is shown;

[0059] Figure 10 The structural schematic diagram of a multi-core synchronization device provided by an exemplary embodiment is shown. DETAILED DESCRIPTION

[0060] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application clearer and more understandable, the following further details this application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0061] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality" means two or more, unless otherwise specifically defined.

[0062] To improve the efficiency of data processing, multi-core processors are often used for data processing. Among them, multi-core refers to multiple processing units. A number of processing units need to coordinate with each other to achieve synchronization in order to complete the same task, that is, before a certain processing unit starts to execute an operation, it is required that another processing unit has completed a certain operation, otherwise this processing unit needs to wait. Therefore, communication is required between each processing unit to understand the situation of the relevant processing unit executing operations. For example, for two processing units that need to use the same data cache area, one processing unit writes the processed data to the data cache area, and the other processing unit reads the data from the data cache area and further processes the read data; after the previous processing unit finishes writing data to the data cache area, the other processing unit can read the data from this data cache area for processing. In this way, after the previous processing unit finishes writing data to the data cache area, it needs to notify the other processing unit that the data writing has been completed. In the related art, there are various synchronization schemes between processing units, but each scheme has deficiencies. Several common multi-core synchronization methods are introduced below.

[0063] In some implementation manners, semaphores are used to achieve synchronization between processing units. Among them, a semaphore is a non-negative counter. By setting a semaphore in the data cache area, the access of the processing unit to the data cache area is restricted. That is, it is judged whether the processing unit has the permission to access the data cache area through the value of the semaphore. For example, when the value of the semaphore is greater than 0, the processing unit can access the data cache area, otherwise it is not allowed to access the cache area. In this technical solution, when accessing the data cache area, it is necessary to frequently read and write and poll the semaphore in the data cache area, which affects the access efficiency of the data cache area and further affects the multi-core synchronization efficiency.

[0064] In some other implementation manners, asynchronous communication between processing units is achieved by setting up a Mailbox. That is, a processing unit can write a message corresponding to the execution status of a task into the Mailbox and then continue to execute other tasks. When another processing unit needs to know the execution status of the previous processing unit, it can read the execution status of other processing units from this Mailbox. In this implementation manner, a shared buffer needs to be set up to store messages. When multiple processing units synchronize with the same processing unit, a large number of messages are sent by multiple processing units to the buffer corresponding to the same processing unit, resulting in buffer overflow or performance degradation. Moreover, Mailbox communication requires the processing units to abide by the same communication protocol. Therefore, the requirements for processing units are relatively high.

[0065] In summary, there are many deficiencies in the multi-core synchronization methods in the related technologies, which affect the efficiency of multi-core synchronization. Therefore, there is an urgent need for a new multi-core synchronization solution to solve the deficiencies in the related technologies and improve the synchronization efficiency between processing units.

[0066] In the embodiments of the present application, to solve the above process synchronization problem, a multi-core synchronization method, apparatus, and system are provided. By setting up a synchronization device between multiple processing units, the synchronization device coordinates each processing unit to achieve synchronization between processing units. Please refer to Figure 1 , which shows a multi-core synchronization system provided by an exemplary embodiment. The multi-core synchronization system includes: a multi-core synchronization device 10 and multiple processing units 20.

[0067] The multi-core synchronization device 10 is communicatively connected to the multiple processing units 20 respectively. The multiple processing units 20 are all used to process operations in a process to implement the tasks corresponding to the process. The multiple processing units 20 can be divided into different synchronization domains as needed, where the processing units corresponding to the same synchronization domain need to execute synchronization tasks. The multiple processing units 20 are connected to a storage system outside the multi-core synchronization system, and the storage system is used to store the data written by each processing unit 20 and provide readable data for each processing unit 20.

[0068] For any processing unit 20, the processing unit 20 is used to send a synchronization request to the multi-core synchronization device 10 in response to the completion of the synchronization task that needs to be synchronized. The synchronization request is used to indicate that the synchronization task of the processing unit has been completed. The synchronization request includes the synchronization domain identifier corresponding to the synchronization task and the unit identifier of the processing unit 20, and the synchronization domain identifier is the identifier corresponding to the synchronization task executed by the processing unit 20.

[0069] When the processing unit 20 executes a task, it loads the instructions corresponding to the task. In the embodiments of the present application, the last instruction of the synchronization task is set as a synchronization request instruction. When the synchronization task loads the synchronization request instruction at the instruction level, the processing unit 20 sends a synchronization request to the multi-core synchronization device 10. The synchronization request instruction carries a variety of information. For example, the synchronization request carries information such as a synchronization domain identifier, a unit identifier of the processing unit 20, a status field of the synchronization request, and a preset value corresponding to the synchronization domain identifier. The synchronization request can be any type of instruction. For example, the synchronization request can be a bar instruction or the like.

[0070] The multi-core synchronization device 10 is configured to, in response to receiving a synchronization request sent by any processing unit 20, according to the synchronization domain identifier in the synchronization request, adjust the value of the target counter from a first value to a second value according to the synchronization request, where the second value is greater than the first value, and the difference between the second value and the first value is 1, and the target counter is the counter corresponding to the target synchronization domain identifier. Accordingly, after receiving a synchronization request sent by any processing unit 20, the multi-core synchronization device 10 parses the synchronization request to obtain the synchronization domain identifier carried in the synchronization request and the preset value corresponding to the synchronization domain identifier, and the preset value represents the number of processing units 20 for processing the synchronization task. The multi-core synchronization device 10 queries the synchronization domain identifiers corresponding to the existing counters according to the synchronization domain identifier. If among the existing counters, there is a target counter with a synchronization domain identifier identical to the target synchronization domain identifier, the count value of the target counter is adjusted. If among the existing counters, there is no counter with a synchronization domain identifier identical to the target synchronization domain identifier, a target counter corresponding to the synchronization domain identifier is created, and the count value of the target counter is adjusted.

[0071] It should be noted that the multi-core synchronization device can adjust the count value of the target counter according to any preset adjustment method. In the embodiments of the present application, the counting method of the target counter is not specifically limited. For example, the adjustment method can be to increment the count value of the target counter by one, and accordingly, the initial value of the target counter can be set to 0. For another example, the adjustment method can also be to decrement the count value of the target counter by one. Correspondingly, the initial value of the target counter can be set to the preset value. Correspondingly, when the count value of the target counter is 0, the multi-core synchronization device 10 determines that the synchronization is completed and performs subsequent operations.

[0072] After the multi-core synchronization device 10 adjusts the count value of the target counter corresponding to the synchronization domain identifier, it determines whether the adjusted second value is less than the preset value corresponding to the target synchronization domain identifier. If the second value is less than the preset value corresponding to the synchronization domain identifier, the multi-core synchronization device 10 determines not to send the first response message and does not perform other responses. If the second value is equal to the preset value corresponding to the target synchronization domain identifier, the multi-core synchronization device 10 sends the first response message. Accordingly, multiple processing units 20 that execute the synchronization task receive the first response message, where the first response message is used to instruct the processing unit corresponding to the target synchronization domain identifier among the multiple processing units to execute the subsequent task, and the preset value is the number of processing units that process the synchronization task. The first response message is used to indicate that the current synchronization task of the processing unit 20 has been completed. When any synchronization unit determines that the current synchronization is completed, it continues to execute the next task.

[0073] Taking the processing unit that currently sends the synchronization request as the first processing unit and the processing unit corresponding to the target synchronization area as the second unit as an example, the multi-core synchronization device is used to receive a first synchronization request from the first processing unit. The first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed. The first synchronization request carries the target synchronization domain identifier, and the target synchronization domain identifier is the identifier of the synchronization task executed by the first processing unit; adjust the value of the target counter from the first value to the second value according to the first synchronization request, where the second value is greater than the first value, and the difference between the second value and the first value is 1. The target counter is the counter corresponding to the target synchronization domain identifier; if the second value is less than the preset value corresponding to the target synchronization domain identifier, determine not to send the first response message; or, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, send the first response message; where the first response message is used to instruct the second processing unit corresponding to the target synchronization domain identifier among the multiple processing units to execute the subsequent task, and the preset value is the number of processing units that process the synchronization task.

[0074] Among them, the number of second processing units is at least one, and the second processing units include the first processing unit.

[0075] It should be noted that when the multi-core synchronization device 10 receives a synchronization request, it can also store the synchronization domain identifier carried in the synchronization request and the unit identifier of the processing unit 20 in a corresponding manner, so that when receiving the first response information from multiple processing units 20 that execute the synchronization task, it can determine, according to the synchronization domain identifier, the multiple unit identifiers corresponding to the synchronization domain identifier carried in the currently received synchronization request from the stored corresponding relationship between the synchronization domain identifier and the unit identifier, and thus send the first response information to the multiple processing units 20 corresponding to the synchronization domain identifier according to the multiple unit identifiers. Correspondingly, the first synchronization request also carries the unit identifier of the first processing unit; after receiving the first synchronization request from the first processing unit, the multi-core synchronization device stores the unit identifier of the first processing unit and the target synchronization domain identifier in a corresponding manner in the first processing unit information table; and changes the state of the first processing unit information table from the idle state to the running state.

[0076] In this implementation manner, by recording the unit identifier and the target synchronization domain identifier in the synchronization request, the multi-core synchronization device can quickly find the unit identifiers corresponding to the target synchronization domain identifier, thereby improving the efficiency of determining the unit identifiers and further improving the synchronization efficiency.

[0077] It should be noted that another point is that the multi-core synchronization system provided by the embodiments of the present application also supports parallel synchronization of multiple synchronization domains. For different synchronization domains, different synchronization domain identifiers are set. Correspondingly, the multiple processing units 20 connected to the multi-core synchronization device 10 are divided into different synchronization domains, and each synchronization domain can operate independently without interference. Moreover, the number of processing units 20 in the multi-core synchronization system can be set according to needs. Therefore, it can be flexibly adapted to changes in the chip specifications, making the application scenarios of the multi-core synchronization system more extensive.

[0078] The multi-core synchronization device 10 will be described below to further illustrate the principle of how the multi-core synchronization device 10 implements the above functions.

[0079] In some embodiments, referring to Figure 2 , the multi-core synchronization device 10 includes a synchronization domain status recording module 11 and a processing unit information recording module 12.

[0080] The synchronization domain status recording module 11 stores counters corresponding to multiple synchronization domain identifiers. In some embodiments, the multiple counters and the synchronization domain identifiers corresponding to the counters are stored in a processing unit information table. Among them, the processing unit information table can be set to an information table corresponding to each processing unit, or can be set to an information table corresponding to multiple processing units. In the embodiments of the present application, no specific limitation is made thereto. In response to receiving a synchronization request sent by any processing unit 20, the synchronization domain status recording module 11 determines, from the processing unit information table, the target counter corresponding to the target synchronization domain identifier according to the synchronization domain identifier carried in the synchronization request, and adjusts the value of the target counter from a first value to a second value according to the first synchronization request, where the second value is greater than the first value, and the difference between the second value and the first value is 1, and the target counter is the counter corresponding to the target synchronization domain identifier; if the second value is less than the preset value corresponding to the target synchronization domain identifier, it is determined not to send the first response information; or, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, a release information is sent to the processing unit information recording module, and the release information carries the target synchronization domain identifier.

[0081] If the adjusted count value is less than the preset value corresponding to the synchronization domain identifier, the synchronization domain status recording module 11 will not make other responses. If the adjusted count value is equal to the preset value corresponding to the synchronization domain identifier, the synchronization domain status recording module 11 sends a release information to the processing unit information recording module 12.

[0082] The processing unit information recording module 12 stores multiple processing unit information tables, and the synchronization domain identifier, unit identifier, and the status of the processing unit information table are correspondingly stored in the processing unit information table. The processing unit information recording module 12 is configured to receive the release information sent by the synchronization domain status recording module 11, determine, from the multiple processing unit information tables, the multiple processing unit 20 information tables corresponding to the synchronization domain identifier according to the synchronization domain identifier carried in the release information, and send a first response information to the processing units corresponding to the multiple unit identifiers according to the unit identifiers recorded in the multiple processing unit information tables corresponding to the synchronization domain identifier.

[0083] For example, it is described by taking that the synchronization domain status recording module receives the first synchronization request of the first processing unit as an example. In the synchronization domain status recording module, target counters corresponding to multiple synchronization domain identifiers are stored, and are used to receive the first synchronization request from the first processing unit. The first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed. The first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit; according to the first synchronization request, the value of the target counter is adjusted from a first value to a second value, the second value is greater than the first value, and the difference between the second value and the first value is 1. The target counter is the counter corresponding to the target synchronization domain identifier; if the second value is less than the preset value corresponding to the target synchronization domain identifier, it is determined not to send the first response message; or, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, a release message is sent to the processing unit information recording module, and the target synchronization domain identifier is carried in the release message;

[0084] The processing unit information recording module stores multiple processing unit information tables, and is used to, in response to receiving the release message sent by the synchronization domain status recording module, determine the unit identifier of the second processing unit corresponding to the target synchronization domain identifier from the multiple processing unit information tables according to the target synchronization domain identifier carried in the release message, and send a first response message to the second processing unit according to the unit identifier.

[0085] It should be noted that, before the first processing unit sends the first synchronization request, or, after the first processing unit sends the first synchronization request, but when the second count value is less than the preset value, the multi-core synchronization device 10 also receives a second synchronization request sent by another processing unit for processing the synchronization task of the target synchronization domain identifier, and records the relevant information of the second synchronization request according to the above process. In the embodiments of the present application, this is not elaborated herein.

[0086] The status in the processing unit 20 information table is adjusted along with the synchronization process. In some embodiments, when the processing unit information recording module 12 receives the release message, the status of the processing unit 20 information tables corresponding to the multiple processing units 20 corresponding to the synchronization domain identifier carried in the release message is switched from the running state (RUN) to the waiting state (WAIT); after the processing unit information recording module 12 sends the first response message to the multiple processing units 20, the processing unit information recording module 12 switches the status of the multiple processing unit 20 tables from the waiting state to the idle state (IDLE).

[0087] In some embodiments, the processing unit information recording module 12 is further configured to, in response to receiving a first synchronization request sent by a first processing unit, store the unit identifier of the first processing unit and the target synchronization domain identifier in the processing unit information table in a corresponding manner; switch the state of the processing unit information table from the idle state to the running state; the processing unit information recording module 12 is further configured to, after receiving the release information, switch the states of the processing unit information tables of the first processing unit and the second processing unit from the running state to the waiting state; determine the states of the multiple processing unit information tables at preset time intervals; if the states of the multiple processing unit information tables include the waiting state, send the first response information to the processing unit corresponding to the processing unit information table in the waiting state among the multiple processing unit information tables; and switch the state of the processing unit information table corresponding to the processing unit that has sent the first response information from the waiting state to the idle state.

[0088] Since the multi-core synchronization device 10 can be connected to multiple processing units 20, to avoid the blocking problem caused by simultaneously sending the first response information to multiple processing units 20, in the embodiments of the present application, first, the state of the processing unit 20 information table is switched from the running state to the waiting state, and the first response information is sent to the processing unit 20 in the processing unit 20 information table in the waiting state at preset time intervals. This ensures that the processing unit 20 is timely notified of the synchronization completion while preventing blocking caused by excessive information content.

[0089] Among them, the preset time interval can be set as needed. In the embodiments of the present application, no specific limitation is imposed on the preset time interval. For example, the preset time interval can be 1 clock cycle.

[0090] Prior to this, the multi-core synchronization device 10 needs to record the processing units 20 that have completed synchronization in the processing unit information recording module 12. Correspondingly, in response to the multi-core synchronization device 10 receiving a synchronization request, the synchronization request is sent to the processing unit information recording module 12, and the processing unit information recording module 12 associates and stores the synchronization domain identifier carried in the multi-core synchronization request and the unit identifier of the processing unit 20 in the processing unit information table, and switches the state of the synchronization unit information table from the idle state to the running state.

[0091] In some embodiments, refer to Figure 3, the multi-core synchronization device 10 further includes a cache module 13. The multi-core synchronization device 10 is further configured to parse the first synchronization request to obtain a status field; if the status field indicates that the first synchronization request is a cache request, send the first synchronization request to the cache module 13; if the status field indicates that the first synchronization request is a record request, send the first synchronization request to the processing unit information recording module 12. The cache module 13 is configured to, in response to receiving the first synchronization request, cache the first synchronization request and send second response information to the first processing unit corresponding to the first synchronization request, where the second response information is used to indicate that the synchronization request of the first processing unit has been cached. The processing unit 20 receives the second response information and does not further respond to the second response information.

[0092] It should be noted that the cache module 13 can send the second response information to the corresponding processing unit 20 in real time after receiving the synchronization request. The cache module 13 can also send the second response information to the corresponding processing unit 20 every preset time period. In the embodiments of the present application, no specific limitation is made thereto.

[0093] After the processing unit 20 sends a synchronization request of the cache request type to the multi-core synchronization device 10, since there is no need to respond to the second response information returned by the cache module 13, the processing unit 20 does not need to wait for the cache module 13 to return the second response information. After sending the synchronization request of the cache request type, the processing unit 20 can continue to execute subsequent tasks. It can be seen that the identifier of the processing unit 20 at this time does not need to be recorded in the processing unit information recording module 12. Because in the embodiments of the present application, the synchronization requests can be classified so that different modules in the multi-core synchronization device 10 process different types of synchronization requests respectively. In some embodiments, a status field indicating the status is added to the synchronization request, and the type of the synchronization request is indicated by the status field. Wherein, the types of the synchronization requests include cache requests and record requests. For example, the status field is the sync field, indicating that the type of the synchronization request is a record request. The status field is the pass field, indicating that the type of the synchronization request is a cache type.

[0094] Correspondingly, the multi-core synchronization device 10 is further configured to parse the received synchronization request to obtain a status field; if the status field indicates that the synchronization request is a cache request, send the synchronization request to the multi-core synchronization device 10; if the status field indicates that the synchronization request is a record request, send the synchronization request to the processing unit information recording module 12.

[0095] In this implementation, by adding a status field to the synchronization request, different types of synchronization requests can be sent to different bypasses, so that it is not necessary to wait until all the processing units 20 corresponding to the synchronization domain identifier complete synchronization, and the processing unit 20 can continue to execute subsequent tasks, improving the synchronization efficiency and the data processing efficiency of the processing unit 20 itself.

[0096] In the embodiment of the present application, a multi-core synchronization device 10 is set for multiple processing units 20. The multi-core synchronization device 10 records the processing units 20 that need to perform synchronization. When the processing unit 20 completes the current synchronization task, it sends a synchronization request to the multi-core synchronization device 10. The multi-core synchronization device 10 adjusts the count value of the target counter corresponding to the synchronization domain according to the synchronization domain identifier carried in the synchronization request. When the count value of the synchronization domain counter is equal to the preset data corresponding to the synchronization domain identifier, it indicates that all the processing units 20 executing the current synchronization task have completed synchronization. In this way, the multi-core synchronization device 10 sends a first response message to the multiple processing units 20 corresponding to the synchronization domain, so that the processing unit 20 can continue to execute the next task. In this way, the multi-core synchronization device 10 is used to determine whether the synchronization is completed, without frequently polling the common resources, improving the synchronization efficiency.

[0097] Furthermore, by communicating between the multi-core synchronization device 10 and multiple processing units 20 respectively, there is no need for cooperative communication between the multiple processing units 20. Therefore, there is no need to limit the communication protocol between the multiple processing units 20, reducing the synchronization difficulty.

[0098] Moreover, only by designing the synchronization domain identifier in the synchronization request at the processing level, the processing units 20 for synchronization can be divided, so that the multi-core processing unit 20 realizes any one-to-many, many-to-one, and many-to-many synchronization processing.

[0099] Among the multiple processing units corresponding to the same synchronization domain identifier, only the last processing unit that completes synchronization sends a synchronization request to the multi-core synchronization unit, and the processing method of the multi-core processing unit is different. After the other processing units except the last processing unit that completes synchronization complete synchronization and send a synchronization request to the multi-core synchronization device, the processing method of the multi-core synchronization device is the same. In the embodiment of the present application, the current received synchronization request is taken as an example of the synchronization request sent by the first processing unit for description. Among them, the first synchronization request can be any processing unit in the above multi-core synchronization system. Refer to Figure 4 , which shows a flowchart of the multi-core synchronization method provided by the present application. By way of example and not limitation, this method is applied in the above multi-core synchronization device.

[0100] S401. The multi-core synchronization device receives a first synchronization request from the first processing unit. The first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed. The first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is the identifier of the synchronization task executed by the first processing unit.

[0101] After the first processing unit finishes processing the current synchronization task, it generates a first synchronization request according to information such as the target synchronization domain identifier corresponding to the synchronization task, the pre-designed value corresponding to the target synchronization domain identifier, and the unit identifier of the first processing unit, and sends the first synchronization request to the multi-core synchronization device.

[0102] In some embodiments, after receiving the first synchronization request, the multi-core synchronization device also stores the synchronization domain identifier in the first synchronization request and the unit identifier of the processing unit in a corresponding manner. Accordingly, the multi-core synchronization device stores the unit identifier of the first processing unit and the target synchronization domain identifier in the first processing unit information table correspondingly; and changes the state of the first processing unit information table from the idle state to the running state.

[0103] In this implementation, the multi-core synchronization device stores the unit identifier of the first processing unit and the synchronization domain identifier in the processing unit information table correspondingly, and changes the state of the processing unit information table from the idle state to the running state, so as to record the unit identifiers of the processing units corresponding to the same synchronization domain identifier through the processing unit information table, so that when the synchronization is completed, the first response information can be sent to all the processing units corresponding to the target synchronization domain identifier.

[0104] S402. The multi-core synchronization device adjusts the value of the target counter from a first value to a second value according to the first synchronization request. The second value is greater than the first value, and the difference between the second value and the first value is 1. The target counter is the counter corresponding to the target synchronization domain identifier.

[0105] In response to receiving the first synchronization request sent by the first processing unit, the multi-core synchronization device adjusts the count value of the target counter corresponding to the target synchronization domain identifier according to the target synchronization domain identifier in the first synchronization request.

[0106] In some embodiments, after receiving the first synchronization request, the multi-core synchronization device parses the first synchronization request to obtain the target synchronization domain identifier carried in the first synchronization request and the preset value corresponding to the target synchronization domain identifier. The preset value is the number of processing units for processing the synchronization task. The multi-core synchronization device queries the synchronization domain identifiers corresponding to the existing counters according to the target synchronization domain identifier. If there is a target counter in the existing counters whose synchronization domain identifier is the same as the target synchronization domain identifier, the count value of the target counter is adjusted. If there is no counter in the existing counters whose synchronization domain identifier is the same as the target synchronization domain identifier, a target counter corresponding to the target synchronization domain identifier is created, and the count value of the target counter is adjusted.

[0107] In the embodiments of the present application, the count value of the target counter can be adjusted according to any preset adjustment method. In the embodiments of the present application, the counting method of the target counter is not specifically limited. For example, the adjustment method can be to increment the count value of the target counter by one, and then the initial value of the target counter can be set to 0. For another example, the adjustment method can also be to decrement the count value of the target counter by one. Correspondingly, the initial value of the target counter can be set to the preset value. Correspondingly, when the count value of the target counter is 0, the multi-core synchronization device determines that the synchronization is completed and performs subsequent operations.

[0108] After the multi-core synchronization device adjusts the count value of the target counter corresponding to the synchronization domain identifier, it determines whether the adjusted count value (the second value) is less than the preset value corresponding to the synchronization domain identifier. If the adjusted count value (the second value) is less than the preset value corresponding to the synchronization domain identifier, the multi-core synchronization device executes step S403, does not make other responses, and then continues to execute steps S401 - S402. If the adjusted count value (the second value) is equal to the preset value corresponding to the synchronization domain identifier, the multi-core synchronization device executes step S404.

[0109] S403, if the second value is less than the preset value corresponding to the target synchronization domain identifier, the multi-core synchronization device determines not to send the first response message.

[0110] If the second value is less than the preset value corresponding to the target synchronization domain identifier, the multi-core synchronization device continues to receive the second synchronization request sent by the third processing unit among the multiple processing units, parses the second synchronization request to obtain the synchronization domain identifier carried in the second synchronization request. If the synchronization domain identifier carried in the second synchronization request is the same as the target synchronization domain identifier, continue to adjust the count value of the target counter; until the adjusted count value of the target counter is equal to the preset value, execute step S404.

[0111] S404, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, the multi-core synchronization device sends a first response message.

[0112] Among them, the first response message is used to instruct the second processing unit corresponding to the target synchronization domain identifier among the multiple processing units to perform subsequent tasks, and the preset value is the number of processing units for processing the synchronization task. The first response message includes information such as the unit identifier of the second processing unit, and is used to indicate that the current synchronization of the second processing unit has been completed and other tasks can be continued. Among them, the second processing unit is the processing unit for processing the synchronization task corresponding to the target synchronization domain identifier, the number of the second processing units is at least one, and the second processing unit includes the first processing unit.

[0113] It should be noted that when receiving the synchronization request, the multi-core synchronization device can also store the synchronization domain identifier carried in the synchronization request and the unit identifier of the processing unit in a corresponding manner, so that when receiving the first response message from the multiple processing units performing the synchronization task, it can be based on the synchronization domain identifier. Determine the multiple unit identifiers corresponding to the synchronization domain identifier carried in the received synchronization request from the stored corresponding relationship between the synchronization domain identifier and the unit identifier, and thus send the first response message to the multiple processing units corresponding to the synchronization domain identifier.

[0114] In some embodiments, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, the multi-core synchronization device determines the unit identifier of the at least one second processing unit from multiple processing unit information tables according to the target synchronization domain identifier. The second processing unit is the processing unit that has sent a synchronization request carrying the target synchronization domain identifier among the multiple processing units; and sends the first response message to the second processing unit according to the unit identifier of the second processing unit.

[0115] The multi-core synchronization device determines the multiple unit identifiers corresponding to the target synchronization domain identifier according to the corresponding relationship between the synchronization domain identifier and the unit identifier stored in the multiple processing unit information tables, and thus sends the first response message to the processing units corresponding to the multi-core unit identifiers. In this way, by recording the unit identifiers of the processing units that have completed synchronization in the processing unit information table, it is convenient to find all the processing units corresponding to the same synchronization domain identifier, saving the time for finding the processing units and further improving the synchronization efficiency.

[0116] In some embodiments, after the multi-core synchronization device determines that the synchronization is completed, it first adjusts the status of the processing unit information table, and then sends the first response information to the processing units in the waiting state. The process is as follows: the multi-core synchronization device switches the status of the processing unit information table of the second processing unit from the running state to the waiting state; at every preset time interval, it determines the status of the multiple processing unit information tables; if the status of the multiple processing unit information tables includes the waiting state, it sends the first response information to the processing unit corresponding to the processing unit information table in the waiting state among the multiple processing unit information tables.

[0117] Since the multi-core synchronization device can be connected to multiple processing units, in order to avoid the blocking problem caused by sending the first response information to multiple processing units simultaneously, in the embodiments of the present application, the status of the processing unit information table is first switched from the running state to the waiting state, and the first response information is sent to the processing units in the waiting state of the processing unit information table at every preset time interval. This ensures that the processing units are timely notified of the completion of synchronization while preventing blocking caused by excessive information content.

[0118] Among them, the preset time interval can be set as needed, and in the embodiments of the present application, no specific limitation is made on the preset time interval. For example, the preset time interval can be 1 clock cycle.

[0119] In the embodiments of the present application, by setting a multi-core synchronization device for multiple processing units, the multi-core synchronization device records the processing units that need to be synchronized. When a processing unit completes the current synchronization task, it sends a synchronization request to the multi-core synchronization device. The multi-core synchronization device adjusts the count value of the target counter corresponding to the synchronization domain according to the synchronization domain identifier carried in the synchronization request. When the count value of the target counter is equal to the preset data corresponding to the synchronization domain identifier, it indicates that all the processing units executing the current synchronization task have completed synchronization. In this way, the multi-core synchronization device sends the first response information to the multiple processing units corresponding to the synchronization domain, so that the processing units can continue to execute the next task. In this way, the multi-core synchronization device is used to determine whether the synchronization is completed, without frequently polling the common resources, improving the synchronization efficiency.

[0120] Furthermore, by the multi-core synchronization device communicating with multiple processing units respectively, there is no need for cooperation communication between the multiple processing units. Therefore, there is no need to limit the communication protocol between the multiple processing units, reducing the synchronization difficulty.

[0121] Moreover, by only designing the synchronization domain identifier in the synchronization request at the processing level, the synchronized processing units can be divided, enabling the multi-core processing units to achieve any one-to-many, many-to-one, and many-to-many synchronization processing.

[0122] In practical applications, some processing units can continue to execute without waiting for the multi-core synchronization device to return a response message. To implement such a synchronization process, in the embodiments of the present application, the synchronization requests are classified. Taking the receipt of the first synchronization request as an example, the classification processing method will be described below. In fact, the classification processing method for the second synchronization request is the same, and will not be elaborated in the embodiments of the present application. Refer to Figure 5 , which shows a flowchart of the multi-core synchronization method provided by the present application. By way of example and not limitation, this method is applied in the above multi-core synchronization device.

[0123] S501, in response to receiving a first synchronization request sent by a first processing unit, the multi-core synchronization device parses the first synchronization request to obtain a status field.

[0124] The types of the synchronization request include a cache request and a record request. For example, if the status field is the sync field, it indicates that the type of the synchronization request is a record request. If the status field is the pass field, it indicates that the type of the synchronization request is a cache type.

[0125] If the status field indicates that the first synchronization request is a cache request, step S502 is executed; if the status field indicates that the first synchronization request is a record request, step S504 is executed.

[0126] S502, if the status field indicates that the first synchronization request is a cache request, the multi-core synchronization device caches the synchronization request.

[0127] S503, the multi-core synchronization device sends a second response message to the first processing unit, and the second response message is used to indicate that the first synchronization request has been cached.

[0128] Refer to Figure 6 , if the status field carried by the first synchronization request sent by the first processing unit indicates that the first synchronization request is a cache request, the multi-core synchronization device caches the first synchronization request through bypass, and sends a second response message to the first processing unit. After sending the first synchronization request, the first processing unit continues to execute subsequent tasks and does not perform other processing after receiving the second response message.

[0129] S504, if the status field indicates that the first synchronization request is a record request, the multi-core synchronization device stores the unit identifier of the first processing unit and the target synchronization domain identifier in the first processing unit information table correspondingly.

[0130] Refer to Figure 7, if the status field carried in the first synchronization request sent by the first processing unit indicates that the first synchronization request is a cache request, after sending the first synchronization request, the first processing unit suspends and waits for a response from the multi-core synchronization device. The multi-core synchronization device receives the first synchronization request and stores the synchronization domain identifier and unit identifier carried in the first synchronization request in the processing unit information table. Then, it adjusts the count value of the target counter according to the first synchronization request. If the count value is less than the preset value, it continues to receive other synchronization requests. If the count value is equal to the preset value, the multi-core synchronization device sends the first response message to the first processing unit and the second processing unit corresponding to the target synchronization domain identifier according to the synchronization domain identifier and unit identifier of the processing unit recorded in the processing unit information table. Correspondingly, after receiving the first response message, the processing unit and the second processing unit resume and continue to run.

[0131] In the embodiment of the present application, by adding a status field to the synchronization request, different types of synchronization requests can be sent to different bypasses, so that it is not necessary to wait for all processing units corresponding to the synchronization domain identifier to complete synchronization, and the processing unit can continue to execute subsequent tasks, improving the synchronization efficiency and the efficiency of the processing unit itself.

[0132] In the embodiment of the present application, by setting a multi-core synchronization device for multiple processing units, the multi-core synchronization device records the processing units that need to perform synchronization. When a processing unit completes the current synchronization task, it sends a synchronization request to the multi-core synchronization device. The multi-core synchronization device adjusts the count value of the target counter corresponding to the synchronization domain according to the synchronization domain identifier carried in the synchronization request. When the count value of the target counter is equal to the preset data corresponding to the synchronization domain identifier, it indicates that all processing units executing the current synchronization task have completed synchronization. In this way, the multi-core synchronization device sends the first response message to multiple processing units corresponding to the synchronization domain, so that the processing unit can continue to execute the next task. In this way, the multi-core synchronization device is used to determine whether synchronization is completed, without frequently polling public resources, improving the synchronization efficiency.

[0133] The multi-core synchronization method, device, and system provided by the embodiments of the present application can be applied to various multi-core synchronization models. For example, it can be applied to the producer-consumer model or the barrier model. Below, taking these two models as examples respectively, the usage method of this solution in practical applications is introduced.

[0134] In one implementation, it is applied to the producer-consumer model.

[0135] See Figure 8, initially, the producer includes processing unit 0 and processing unit 1, and the consumer includes processing unit 2 and processing unit 3. For any processing unit in the producer, after the processing unit produces the first batch of data, it writes the data to address A. Since there is no need to wait for the consumer, the type of synchronous request adopted is a cache request (carrying a pass field). After the producer sends a synchronous request for completing the first batch of data, it can prepare the next batch of data. At this time, the consumer has completed the previous batch of data. Therefore, it sends a synchronous request and then suspends waiting.

[0136] In this relational model, both the producer and the consumer can be any processing unit connected to the multi-core synchronization device, and the synchronous requests sent by the producer and the consumer carry the same synchronous domain identifier. Among them, the identities of the processing units corresponding to the producer and the consumer can change flexibly. For example, when it is necessary to produce data to the same physical address, to avoid data overwrite, it is necessary to wait for the consumer to completely consume the previous batch of data. At this time, the relationship between the producer and the consumer is interchanged. The original producer needs to send a synchronous request of the record request type (carrying a sync field), while the original consumer only needs to send a synchronous request of the cache request type (carrying a pass field) to cooperate with the synchronization device to complete the second synchronization.

[0137] For example, in Figure 8 In the shown synchronization process, during the first synchronization, the synchronous requests all carry the synchronous domain identifier ID = 1. Processing unit 0 and processing unit 1, as the producer, first produce data and write it to data A. At this time, processing unit 2 and processing unit 3, as the consumer, send synchronous requests of the record request type (carrying a sync field) and suspend waiting. After processing unit 0 and processing unit 1 send synchronous requests of the cache request type (carrying a pass field), they continue to produce data until processing unit 0 and processing unit 1 complete the data production in this synchronization process. Since both the producer and the consumer have sent synchronous requests at this time, it means that the synchronization is completed at this time, and the consumer starts to consume the data, that is, reads the data from address A for processing. After each group of data is processed, it can send a synchronous request of the cache request type (carrying a pass field) and continue to consume the data. The corresponding producer in this process sends a synchronous request of the record request type (carrying a sync field) and suspends waiting. Since the data production process and the data consumption process are two different synchronization processes, although the same processing units are used, different synchronous domain identifiers are adopted.

[0138] In one implementation, it is applied to the barrier model.

[0139] See Figure 9, when multiple processing units need to be executed to the same position, the processing units participating in synchronization can send a synchronization request of the record request type (carrying the sync field), and then enter the suspended state until the multi-core synchronization device returns a response message to release the suspension.

[0140] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0141] Figure 10 is a schematic diagram of a multi-core synchronization device provided by an exemplary embodiment of the present application. As Figure 10 shown, the vehicle controller 10 of this embodiment includes: a processor 100, a memory 101, and a computer program 102 stored in the memory 101 and executable on the processor 100, such as a multi-core synchronization program. When the processor 100 executes the computer program 102, it implements the steps in the above-mentioned various multi-core synchronization method embodiments, such as Figure 4 the steps S401 to S405 shown. Alternatively, when the processor 100 executes the computer program 102, it implements the functions of each unit in the above-mentioned device embodiments, such as Figure 3 the functions of the synchronization domain status recording module and the processing unit information recording module shown.

[0142] Exemplarily, the computer program 102 can be divided into one or more units. The one or more units are stored in the memory 101 and executed by the processor 100 to complete the present application. The one or more units can be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program 102 in the multi-core synchronization device 10. For example, the computer program 102 can be divided into a synchronization domain status recording module and a processing unit information recording module, and the specific functions of each module are as described in the above embodiments.

[0143] The multi-core synchronization device 10 can be any synchronization controller with a synchronization function. The multi-core synchronization device 10 can include, but is not limited to, a processor 100 and a memory 101. Those skilled in the art can understand that Figure 10 merely examples of the multi-core synchronization device 10 do not constitute a limitation on the multi-core synchronization device 10, and may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, the multi-core synchronization device 10 may further include input / output devices, network access devices, buses, etc.

[0144] The so-called processor 100 may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0145] The memory 101 may be an internal storage unit of the multi-core synchronization device 10, such as the hard disk or memory of the multi-core synchronization device 10. The memory 101 may also be an external storage device of the multi-core synchronization device 10, such as a plug-in hard disk equipped on the multi-core synchronization device 10, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. Further, the memory 101 may also include both the internal storage unit and the external storage device of the multi-core synchronization device 10. The memory 101 is used to store the computer program and other programs and data required by the terminal device. The memory 101 may also be used to temporarily store the data that has been output or will be output.

[0146] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is used as an example. In actual applications, the above-mentioned functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0147] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0148] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0149] In the embodiments provided in this application, it should be understood that the disclosed device / terminal device and method can be implemented in other ways. For example, the device / terminal device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical or other form.

[0150] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0151] In addition, the functional units in each embodiment of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0152] When the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-described embodiment methods of this application, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice within the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0153] An embodiment of this application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-described method embodiments are implemented.

[0154] An embodiment of this application also provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in the above-described method embodiments when executed.

[0155] The above-described embodiments are only used to illustrate the technical solutions of this application, rather than to limit them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A multi-core synchronization method, characterized in that, Applied to a multi-core synchronization device, which is a device in a multi-core synchronization system. The multi-core synchronization system further includes a plurality of processing units, and the plurality of processing units include a first processing unit. The method includes: Receiving a first synchronization request from the first processing unit. The first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed. The first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit; Adjusting the value of a target counter from a first value to a second value according to the first synchronization request. The second value is greater than the first value, and the difference between the second value and the first value is 1. The target counter is the counter corresponding to the target synchronization domain identifier; If the second value is less than a preset value corresponding to the target synchronization domain identifier, determining not to send a first response message; or, If the second value is equal to the preset value corresponding to the target synchronization domain identifier, sending a first response message; Wherein, the first response message is used to instruct a second processing unit corresponding to the target synchronization domain identifier among the plurality of processing units to execute a subsequent task, and the preset value is the number of processing units for processing the synchronization task.

2. The method according to claim 1, wherein The step of "if the second value is equal to the preset value corresponding to the target synchronization domain identifier, sending a first response message" includes: If the second value is equal to the preset value corresponding to the target synchronization domain identifier, determining, according to the target synchronization domain identifier, the unit identifier of at least one second processing unit from a plurality of processing unit information tables. The second processing unit is a processing unit among the plurality of processing units that has sent a synchronization request carrying the target synchronization domain identifier; Sending the first response message to the second processing unit according to the unit identifier of the second processing unit.

3. The method according to claim 2, wherein The method further includes: Switching the state of the processing unit information table of the second processing unit from a running state to a waiting state; The step of "sending the first response message to the second processing unit according to the unit identifier of the second processing unit" includes: Determining the state of the plurality of processing unit information tables every preset time period; If the state of the plurality of processing unit information tables includes the waiting state, sending the first response message to the processing unit corresponding to the processing unit information table in the waiting state among the plurality of processing unit information tables.

4. The method according to any one of claims 1 to 3, characterized in that, The first synchronization request further carries the unit identifier of the first processing unit; After receiving the first synchronization request from the first processing unit, the method further includes: Correspondingly storing the unit identifier of the first processing unit and the target synchronization domain identifier into a first processing unit information table; Switching the state of the first processing unit information table from an idle state to a running state.

5. The method according to claim 4, characterized in that The first synchronization request includes a status field, The step of "correspondingly storing the unit identifier of the first processing unit and the target synchronization domain identifier into a first processing unit information table" includes: If the status field indicates that the first synchronization request is a record request, store the unit identifier of the first processing unit and the target synchronization domain identifier correspondingly in the first processing unit information table; The method further includes: If the status field indicates that the first synchronization request is a cache request, cache the synchronization request; Send second response information to the first processing unit, where the second response information is used to indicate that the first synchronization request has been cached.

6. A multi-core synchronization device, characterized in that, The multi-core synchronization device includes: a synchronization domain status recording module and a processing unit information recording module; The synchronization domain status recording module stores target counters corresponding to multiple synchronization domain identifiers, and is used to receive a first synchronization request from the first processing unit. The first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed. The first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is the identifier of the synchronization task executed by the first processing unit; adjust the value of the target counter from a first value to a second value according to the first synchronization request, where the second value is greater than the first value, and the difference between the second value and the first value is 1. The target counter is the counter corresponding to the target synchronization domain identifier; if the second value is less than the preset value corresponding to the target synchronization domain identifier, determine not to send the first response information; or, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, send a release information to the processing unit information recording module, and the release information carries the target synchronization domain identifier; The processing unit information recording module stores multiple processing unit information tables, and is used to, in response to receiving the release information sent by the synchronization domain status recording module, determine the unit identifier of the second processing unit corresponding to the target synchronization domain identifier from the multiple processing unit information tables according to the target synchronization domain identifier carried in the release information, and send the first response information to the second processing unit according to the unit identifier.

7. The multi-core synchronization device according to claim 6, wherein The first synchronization request includes a status field, and the multi-core synchronization device further includes a cache module; The multi-core synchronization device is further used to parse the first synchronization request to obtain the status field; if the status field indicates that the first synchronization request is a cache request, send the first synchronization request to the cache module; If the status field indicates that the first synchronization request is a record request, send the first synchronization request to the processing unit information recording module; The cache module is used to, in response to receiving the first synchronization request, cache the first synchronization request, and send second response information to the first processing unit corresponding to the first synchronization request, where the second response information is used to indicate that the first processing unit synchronization request has been cached.

8. The multi-core synchronization device according to claim 6, characterized in that The processing unit information recording module is further used to, in response to receiving the first synchronization request sent by the first processing unit, store the unit identifier of the first processing unit and the target synchronization domain identifier correspondingly in the processing unit information table; switch the status of the processing unit information table from the idle state to the running state; The processing unit information recording module is further configured to, after receiving the release information, switch the status of the processing unit information tables of the first processing unit and the second processing unit from the running state to the waiting state; determine the status of the multiple processing unit information tables every preset time period; if the status of the multiple processing unit information tables includes the waiting state, send the first response information to the processing unit corresponding to the processing unit information table in the waiting state among the multiple processing unit information tables; and switch the status of the processing unit information table corresponding to the processing unit that has sent the first response information from the waiting state to the idle state.

9. A multi-core synchronization system, characterized in that, The multi-core synchronization system includes multiple processing units and the multi-core synchronization device according to any one of claims 6-8; For any processing unit, the processing unit is configured to, in response to the completion of the synchronization task by the processing unit, send a synchronization request to the multi-core synchronization device, where the synchronization request is used to indicate that the synchronization task of the processing unit has been completed, and the first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit; The multi-core synchronization device is configured to execute the multi-core synchronization method according to any one of claims 1-5.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the multi-core synchronization method according to any one of claims 1 to 5.

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