Fast Fourier transform hardware circuit structure based on random calculation and design method thereof

Abstract

The invention provides a fast Fourier transform hardware circuit structure based on random calculation and a design method of the fast Fourier transform hardware circuit structure. A binary data conversion circuit, a four-point FFT calculation circuit and a complex multiplication circuit. The design method comprises the following steps of: 1, comparing a binary complex number needing to be subjected to FFT (Fast Fourier Transform) operation with a random number generated by a random number generator to obtain N paths of random bit data streams; 2, dividing every four random bit data streams into one group according to a butterfly computation rule of FFT (Fast Fourier Transform), totally dividing the random bit data streams into N / 4 groups, and executing Fourier transform of four points; 3, a binary data conversion circuit is adopted to convert twiddle factors in the FFT calculation process into random bit data streams, and complex multiplication operation is carried out on the random bit data streams and the four-point Fourier transform result obtained in the step 2; 4, the step 2 and the step 3 are repeated until log4N times of calculation are completed, and an FFT result of N points is obtained; and 5, converting the random bit data stream into binary data.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and relates to a hardware circuit structure of fast Fourier transform based on stochastic computing and a design method thereof. Background Art

[0002] By converting a signal from the time domain to the frequency domain, the Fourier transform can decompose a complex signal into a superposition of a series of simple sine and cosine functions, and effectively analyze the amplitude-frequency characteristics and phase-frequency characteristics of each frequency component in the signal. The Fourier transform has a wide range of applications in modern communication systems, and plays an important role in different applications such as digital signal processing, modulation and demodulation, channel equalization, and noise interference analysis.

[0003] As an efficient Fourier transform calculation algorithm, the Fast Fourier Transform (FFT) effectively reduces the computational complexity of the Fourier transform from O(N 2 ) to O(N*log N) by recursively decomposing the traditional calculation scheme. As an extended scheme for FFT calculation, the radix-4 FFT further reduces the calculation time of the Fourier transform by increasing the number of calculation tasks in each recursive decomposition.

[0004] However, although the FFT significantly reduces the computational complexity of the Fourier transform, a large number of complex multiplication operations are involved in its calculation process, and the resource overhead of complex multiplication calculation based on binary is relatively large on hardware platforms. When performing FFT operations using traditional binary calculation schemes on hardware platforms such as Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs), a large amount of computing resources are consumed, which is not conducive to the hardware deployment and optimization of the FFT.

[0005] As a new type of calculation scheme, Stochastic Computing (SC) represents numerical values using random bitstreams and realizes mathematical calculations by operating on the random bitstreams. Compared with traditional binary calculation schemes, since the calculation data of SC is converted from multi-bit binary data to single-bit random data streams, the system's computational resource overhead is significantly reduced, and the hardware calculation efficiency is improved.

[0006] In view of the problem that traditional binary computing has a large hardware resource overhead when performing FFT operations, the present invention proposes an SC-based FFT hardware circuit structure and its design method, which can effectively solve the problem of large hardware circuit resource overhead in the FFT calculation process and reduce the hardware complexity of FFT. Summary of the Invention

[0007] The object of the present invention is to provide a fast Fourier transform hardware circuit structure based on stochastic computing and its design method to solve the problem of excessive resource overhead of traditional binary computing technology when performing FFT operations and reduce the hardware complexity of FFT.

[0008] To achieve the above object, a fast Fourier transform hardware circuit structure based on stochastic computing proposed by the present invention includes:

[0009] A complete computing circuit structure includes several parts such as a binary data conversion circuit, a 4-point FFT computing circuit, and a complex multiplication circuit. More specifically, the binary data conversion circuit consists of a random number generator and a comparator. The 4-point FFT computing circuit includes an inverter based on a NOT gate and a four-input scaled adder based on a multiplexer. The complex multiplication circuit includes a multiplier based on an XNOR gate and a two-input unscaled adder. The two-input unscaled adder includes a multiplexer, an adder, a subtractor, and a comparator. The specific structure of the above circuits can be seen in Appendix Figure 1 ~Appendix Figure 6 。

[0010] Based on the proposed circuit structure, the binary input data is converted into a single-bit random data stream through the binary data conversion circuit. The single-bit data stream first passes through a random inverter circuit to obtain a new single-bit data stream, and then through a four-input scaled random adder circuit for scaled summation calculation. The rotation factor in stochastic computing is also generated into a single-bit random data stream through the binary data conversion circuit. After passing it through the random multiplier circuit with the data stream after the four-input scaled adder, and then through a random inverter and a two-input unscaled random adder circuit, a corrected random data stream is obtained. Repeat the above computing circuit until all calculation steps of the FFT operation have realized the corresponding hardware circuit structure.

[0011] Based on the above circuit structure, the present invention also proposes a design method for this circuit structure, and the specific steps are as follows:

[0012] Step 1: Compare the binary complex numbers that need to perform FFT operations with the random numbers generated by the random number generator to obtain N random bit data streams. In SC, a single random bit data stream cannot represent the real and imaginary parts of a complex number at the same time. Therefore, each data stream contains two data streams, namely the real part and the imaginary part of the signal.

[0013] The random number generator generates a series of random numbers. The random numbers are compared with the input data. If the input data is greater than the random number, the result is the logical value 1; otherwise, it is the logical value 0. The specific calculation formula can be expressed as:

[0014]

[0015] where X is the input binary data, r(t) is a series of random numbers generated by the random number generator, and x(t) is the converted random bit data stream.

[0016] Considering that the input data is signed binary, and the output of the binary data conversion circuit is a single-bit unsigned data stream, a signal mapping process is performed when converting binary data to a random bit data stream. The signal mapping formula can be expressed as:

[0017]

[0018] where P x is the probability value of the logical value 1 in the random bit data stream.

[0019] Step 2: According to the butterfly calculation rule of FFT, every 4 random bit data streams are grouped into one group, with a total of N / 4 groups, and a 4-point Fourier transform is performed. The calculation formula can be expressed as:

[0020]

[0021] where a1 - a4 are the input data of the 4-point Fourier transform, A1 - A4 are the input data of the 4-point Fourier transform, and j is the imaginary unit.

[0022] The whole calculation process is divided into two steps. The first step is to calculate the results of j*a2, -j*a2, -a3, j*a4, and -j*a4 according to the random bit streams of a2, a3, and a4. The second step is to perform a summation operation on the random bit data streams of the 4 signals.

[0023] In complex number calculations, multiplying a data by -1, j, and -j means that in addition to reversing the real and imaginary parts of some data, the opposite number of the data also needs to be calculated. Since the opposite number of the binary data corresponding to the random bit stream is calculated in this step, the mathematical formula can be expressed as:

[0024]

[0025] where, is the probability value of the random bit stream corresponding to the opposite number of x corresponding to the opposite number of x.

[0026] According to the calculation formula, the truth table corresponding to the inverter is:

[0027]

[0028] Therefore, the computing circuit of the inverter is a NOT gate, as Figure 2 shown.

[0029] Next, it is necessary to sum the random bit streams of 4 signals. At this time, what needs to be calculated is still the sum result of the binary data corresponding to the random bit stream, rather than the sum result of the random bit stream itself. Since only data in the range of 0-1 can be represented in SC, when performing the summation of 4-channel data, in order to prevent data overflow, the sum result needs to be scaled down by 1 / 4. The mathematical formula of the four-input scaled random adder in this step can be expressed as:

[0030]

[0031] The four-input scaled random adder circuit can be equivalent to a 4-way selector, as Figure 3 shown, and its truth table is:

[0032] <![CDATA[P x1 > <![CDATA[P x2 > <![CDATA[P x3 > <![CDATA[P x4 > Sel <![CDATA[P y > 0 x x x 0 0 1 x x x 0 1 x 0 x x 1 0 x 1 x x 1 1 x x 0 x 2 0 x x 1 x 2 1 x x x 0 3 0 x x x 1 3 1

[0033] Among them, P x1 -P x4 are the probability values of the random bit streams converted from 4 binary data, and P y is the probability value of the random bit stream represented by the sum result of 4 binary data.

[0034] Step 3: Use the binary data conversion circuit to convert the rotation factor in the FFT calculation process into a random bit data stream, and perform a complex multiplication operation with the 4-point Fourier transform result obtained in Step 2.

[0035] In the complex multiplication calculation, the product of two complex numbers a + jb and c + jd is (ac - bd) + j(ad + bc). In the calculation process, an inverter, a multiplier, and a two-input adder are required. The design scheme of the inverter is as Figure 2 shown, and will not be elaborated here.

[0036] For the multiplier, it needs to calculate the product of the binary data corresponding to two random bit streams, and its mathematical formula is:

[0037]

[0038] Among them, P x1 and P x2 are the probability values of the random bit streams converted from 2 binary data to be multiplied, and P y is the probability value of the random bit stream represented by the product result of 2 binary data.

[0039] Its truth table is as follows:

[0040] <![CDATA[P x1 > <![CDATA[P x2 > <![CDATA[P y > 0 0 1 0 1 0 1 0 0 1 1 1

[0041] Therefore, the calculation circuit of the multiplier is an exclusive-NOR gate, as Figure 4 shown.

[0042] After calculating the real product, in order to obtain the required complex product result, a two-input adder is used to sum it. Since the modulus value of the rotation factor is 1, in this step, even if the two-input adder does not perform scaling, the sum result will not exceed the maximum range of SC. Therefore, a binary non-scaled random adder circuit is used in this step, and its mathematical formula can be expressed as:

[0043]

[0044] During the calculation process, in addition to summing the results of the two-way data, a constant term needs to be subtracted to correct the sum result. To achieve this process, a State variable is introduced in the calculation circuit of the present invention to represent the state transformation during the calculation process and realize the real-time correction of the calculation result. Therefore, its truth table can be expressed as:

[0045] <![CDATA[P 1 / 2 > <![CDATA[P x1 > <![CDATA[P x2 > <![CDATA[State n > <![CDATA[P y > <![CDATA[State n+1 > 0 0 0 n n>0？1:0 <![CDATA[n-P y > 0 0 1 n n+1>0？1:0 <![CDATA[n+1-P y > 0 1 0 n n+1>0？1:0 <![CDATA[n+1-P y > 0 1 1 n n+2>0？1:0 <![CDATA[n+2-P y > 1 0 0 n n-1>0？1:0 <![CDATA[n-1-P y > 1 0 1 n n>0？1:0 <![CDATA[n-P y > 1 1 0 n n>0？1:0 <![CDATA[n-P y > 1 1 1 n n+1>0？1:0 <![CDATA[n+1-P y >

[0046] The calculation circuit of the two-input non-scaled random adder is as Figure 5 shown. In the circuit, through P 1 / 2 , P x1 and P x2 as the selection signals of the multiplexer, the adjustment amount of the register State n in the circuit under the current input state is determined, and according to whether the updated State n value is greater than 0, the output of the two-input non-scaled random adder is determined, and the update of State n+1 is determined.

[0047] Step 4: Repeat the above Step 2 and Step 3 until log4N calculations are completed to obtain the FFT result of N points.

[0048] Step 5: Convert the random bit data stream into binary data.

[0049] In order to convert the random bit data stream into binary data, it is necessary to count the number of logical 1s in the random bit stream and perform the inverse mapping of the number domain conversion on the statistical result, and its mathematical formula can be expressed as:

[0050]

[0051] Among them, N is the length of the random bit data stream.

[0052] In a specific circuit design, the random bit data stream passes through a counter. Every time a logical value 1 appears in the data stream, the counter result is incremented by one. After completing the statistics of the entire data stream, multiply the statistical result by 2, subtract the data stream length N, and finally divide by the data stream length N to convert the random bit data stream back into a binary calculation result.

[0053] In the present invention, a circuit design method for implementing FFT calculation through a random bit stream is constructed by basic random calculation circuit units such as a random inverter circuit, a four-input scaled random adder circuit, a random multiplier circuit, and a two-input unscaled random adder circuit. In the circuit design, implementation schemes for converting binary data into a random bit stream and converting a random bit stream into binary data are also considered to ensure the compatibility and scalability of the FFT calculation circuit based on SC.

[0054] The advantages and beneficial effects of the present invention are as follows: In the FFT calculation process of the present invention, a random inverter, a random multiplier, and two random adders are used to implement an FFT calculation circuit based on SC. The calculation circuit structure is simple, which can effectively reduce the hardware resource overhead of FFT calculation and improve the calculation efficiency of the hardware system. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a schematic diagram of the binary data conversion circuit adopted by the present invention.

[0056] Figure 2 It is a schematic diagram of the random inverter circuit adopted by the present invention.

[0057] Figure 3 It is a schematic diagram of the four-input scaled random adder circuit adopted by the present invention.

[0058] Figure 4 It is a schematic diagram of the random multiplier circuit adopted by the present invention.

[0059] Figure 5 It is a schematic diagram of the two-input unscaled random adder circuit proposed by the present invention.

[0060] Figure 6 It is a schematic diagram of the 16-point FFT calculation circuit based on random calculation proposed by the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0061] The present invention will be further described in detail below with reference to the drawings and embodiments.

[0062] Taking a 16-length input sequence as an example, the 16-point FFT calculation circuit based on random calculation includes 16 binary data conversion circuits, 8 4-point FFT calculation circuits, and 16 complex multiplication circuits.

[0063] Taking a 16-length input sequence as an example, the specific implementation scheme proposed by the present invention will be introduced in detail.

[0064] Step 1: Use 32 random number generators. Each random number generator generates 100 random numbers respectively. Compare the real and imaginary parts of the 16-channel binary input with the results of the 32 random number generators, and then obtain 16 random sequences. The data stream lengths of the real and imaginary parts of each sequence are both 100 bits.

[0065] Step 2: Divide the 1st, 5th, 9th, and 13th of the 16-channel data into one group, the 2nd, 6th, 10th, and 14th into one group, the 3rd, 7th, 11th, and 15th into one group, and the 4th, 8th, 12th, and 16th into one group. Calculate the Fourier transform results of 4 points for each group respectively.

[0066] Assume that the 4-channel data of each group are x1, x2, x3, and x4 respectively. The Fourier transform results can be expressed as:

[0067]

[0068] During the calculation process, use Figure 2 and Figure 3 's inverters and scaling adders to calculate and obtain 16 calculation results.

[0069] Step 3: Use binary data conversion circuits to convert into 100-bit random data streams respectively, where

[0070] The 16 calculation results in Step 2 are respectively multiplied by the corresponding random bit data streams.

[0071] During the calculation process, use Figure 2 , Figure 4 and Figure 5 's inverters, multipliers, and non-scaling adders to calculate and obtain 16 calculation results.

[0072] Step 4: Divide the 1st - 4th of the 16 random bit data streams into one group, the 5th - 8th into one group, the 9th - 12th into one group, and the 13th - 16th into one group. Use Figure 2 and Figure 3 's inverters and scaling adders again to obtain the Fourier transform results of 4 points. Thus, the 16-point FFT calculation is completed.

[0073] Step 5: Use a counter to separately count the number of logic 1s in each of the 16 - way random bit data streams, denoted as k i , and then calculate k for each path i corresponding value, and the FFT calculation result in binary form can be obtained.

[0074] In summary, a fast Fourier transform hardware circuit structure and its design method based on stochastic computing proposed by the present invention utilize the characteristics of simple stochastic computing hardware circuits, realize the complex calculation process of FFT through simple circuit design, have less hardware resource overhead in the whole calculation process, and have higher calculation efficiency compared with binary calculation.

Claims

1. A design method for a fast Fourier transform hardware circuit structure based on stochastic computing, characterized in that: The steps include: Step 1, the binary complex number that needs to perform FFT operation is compared with the random number generated by the random number generator to obtain N random bit data streams; Step 2: According to the butterfly calculation rule of FFT, the random bit data stream is divided into groups of 4, and a total of N / 4 groups are divided, and Fourier transform of 4 points is performed; Step 3: using a binary data conversion circuit to convert the rotation factors in the FFT calculation process into a random bit data stream, and perform a complex multiplication operation with the 4-point Fourier transform result obtained in step 2; Step 4: Repeat steps 2 and 3 above until log4N calculations are completed to obtain the FFT results of N points. Step 5: Convert the random bit data stream into binary data.

2. The method for designing a fast Fourier transform hardware circuit structure based on stochastic calculation according to claim 1, characterized in that: In step 1, a random bit data stream in the random calculation SC cannot represent the real and imaginary parts of a complex number at the same time, so each data stream contains two data streams, the real and imaginary parts of the signal; The random number generator will generate a series of random numbers and compare the random numbers with the input data. If the input data is greater than the random number, the result is a logical value of 1, otherwise it is a logical value of 0. The specific calculation formula is expressed as: Where X is the input binary data, r(t) is a series of random numbers generated by the random number generator, and x(t) is the converted random bit data stream.

3. The method for designing a fast Fourier transform hardware circuit structure based on stochastic calculation according to claim 1 or 2, characterized in that: When binary data is converted into a random bit data stream, it goes through a signal mapping process. The signal mapping formula is expressed as: Among them, P x It is the probability value of logic value 1 in a random bit data stream.

4. The method for designing a fast Fourier transform hardware circuit structure based on stochastic calculation according to claim 1, characterized in that: In step 2, the calculation formula for performing the Fourier transform of 4 points is expressed as: Among them, a1-a4 is the input data of 4-point Fourier transform, A1-A4 is the input data of 4-point Fourier transform, and j is the imaginary unit; the whole calculation process is divided into two steps. The first step is to calculate the results of j*a2, -j*a2, -a3, j*a4 and -j*a4 according to the random bit streams of a2, a3 and a4; the second step is to sum the random bit data streams of the four signals.

5. The method for designing a fast Fourier transform hardware circuit structure based on stochastic calculation according to claim 4, characterized in that: The opposite number of the binary data corresponding to the random bit stream is expressed as: Among them, P x is the opposite of x The probability value of the corresponding random bit stream.

6. The method for designing a fast Fourier transform hardware circuit structure based on stochastic calculation according to claim 4 or 5, characterized in that: To sum the random bit streams of four signals, the summation result needs to be reduced by 1 / 4; the formula for a four-input scaled random adder is: Among them, P x1 -P x4 is the probability value of the random bit stream converted from 4 binary data, P y The probability value of the random bit stream represented by the sum of 4 binary data.

7. The method for designing a fast Fourier transform hardware circuit structure based on stochastic calculation according to claim 1, characterized in that: In step 3, for the multiplier, it is necessary to calculate the product of the binary data corresponding to the two random bit streams, and the formula is: Among them, P x1 and P x2 is the probability value of converting two binary data to be multiplied into a random bit stream, P y It is the probability value of the random bit stream represented by the product of two binary data; After the real product is calculated, a two-input adder is used to sum the complex product result; it is expressed as: In the calculation process, in addition to summing the results of the two data channels, a constant term needs to be subtracted to correct the summation result. Therefore, a State variable is introduced to represent the state change in the calculation process to achieve real-time correction of the calculation results. In the circuit, through P 1 / 2 , P x1 and P x2 As the selection signal of the multiplexer, it determines the register State in the circuit at the current input state. n The adjustment amount, and according to the updated State n Whether the value is greater than 0 determines the output of the two-input non-scaling random adder and determines the State n+1 Updates.

8. The method for designing a fast Fourier transform hardware circuit structure based on stochastic calculation according to claim 1, characterized in that: In step five, the formula for the inverse mapping is expressed as: Where N is the length of the random bit data stream; In the specific circuit design, the random bit data stream passes through a counter. Every time a logical value 1 appears in the data stream, the counter result is increased by one. After completing the statistics of the entire data stream, the statistical result is multiplied by 2 and the data stream length N is subtracted. Finally, it is divided by the data stream length N to convert the random bit data stream back into a binary calculation result.

9. A fast Fourier transform hardware circuit structure based on random computing, characterized in that: include: Binary data conversion circuit, 4-point FFT calculation circuit, complex multiplication circuit; wherein the binary data conversion circuit includes a random number generator and a comparator; The 4-point FFT calculation circuit includes an inverter based on a NOT gate and a four-input scaling adder based on a multiplexer; the complex multiplication circuit includes a multiplier based on an XNOR gate and a two-input non-scaling adder, and the two-input non-scaling adder includes a multiplexer, an adder, a subtractor and a comparator.

10. The fast Fourier transform hardware circuit structure based on stochastic calculation according to claim 9, characterized in that: Binary input data is converted into a single-bit random data stream through a binary data conversion circuit. The single-bit data stream first passes through a random inverter circuit to obtain a new single-bit data stream, and then performs scaling and summation calculations through a four-input scaling random adder circuit. The rotation factors in the random calculation are also converted into a single-bit random data stream through a binary data conversion circuit. After the single-bit random data stream and the data stream after the four-input scaling adder are passed through a random multiplier circuit, the modified random data stream is obtained through a random inverter and a two-input non-scaling random adder circuit.

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