Method, device, equipment and program product for determining matrix multiplication result

Abstract

The invention is applicable to the technical field of data processing, and provides a method, a device, equipment and a program product for determining a matrix multiplication result. The method comprises the steps that one or more sub-matrix combinations are determined according to a first matrix and a second matrix, and each sub-matrix combination comprises a first sub-matrix corresponding to the first matrix and a second sub-matrix corresponding to the second matrix; the plurality of first sub-matrixes are obtained by partitioning a first matrix according to the number of storable elements of a first vector register, and the plurality of second sub-matrixes are obtained by partitioning a second matrix according to the number of storable elements of a second vector register; determining a matrix operation result corresponding to each sub-matrix combination by using the first vector register and the second vector register; and determining a matrix multiplication result of the first matrix and the second matrix according to the matrix operation result corresponding to each sub-matrix combination. Through the method, the space utilization rate of the vector register can be improved, so that the efficiency of determining the matrix multiplication operation result is improved.

Description

Technical Field

[0001] This application belongs to the technical field of data processing, and particularly relates to a method, apparatus, device, and program product for determining the result of matrix multiplication operation. Background Art

[0002] When it is necessary to determine the result of the multiplication operation of a first matrix and a second matrix, the existing method usually reads all the elements in a single row of the first matrix into a first vector register each time, and reads all the elements in a single column of the second matrix into a second vector register each time. After the first vector register and the second vector register read the corresponding elements each time, the first vector register and the second vector register can obtain the operation result corresponding to the elements in this row of the first matrix and the elements in this column of the second vector register. Repeating the above steps can determine the result of the multiplication operation of the first matrix and the second matrix.

[0003] However, the above method will cause a large amount of unused space in the vector register in the scenario of calculating the multiplication between small matrices by a long vector register. Exemplarily, the number of elements in a single row of the first matrix is 25, the number of elements in a single column of the second matrix is 25, and the number of elements that can be stored in the first vector register and the second vector register is 128. By the above method, there will be 103 spaces for storing elements unused in the first vector register and the second vector register each time during the operation, ultimately resulting in low efficiency in determining the result of the multiplication operation of the first matrix and the second matrix. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a method, apparatus, device, and program product for determining the result of matrix multiplication operation to solve the technical problem of low efficiency in the existing method for determining the result of matrix multiplication operation.

[0005] In a first aspect, an embodiment of the present application provides a method for determining the result of matrix multiplication operation, including:

[0006] Obtain a first matrix and a second matrix;

[0007] According to the first matrix and the second matrix, determine one or more sub-matrix combinations, where a sub-matrix combination includes a first sub-matrix corresponding to the first matrix and a second sub-matrix corresponding to the second matrix; the multiple first sub-matrices are obtained by partitioning the first matrix according to the number of elements that can be stored in the first vector register, and the multiple second sub-matrices are obtained by partitioning the second matrix according to the number of elements that can be stored in the second vector register;

[0008] Determine the matrix operation result corresponding to each of the sub - matrix combinations by using the first vector register and the second vector register. Determine the matrix multiplication result of the first matrix and the second matrix according to the matrix operation result corresponding to each of the sub - matrix combinations.

[0009] Optionally, before determining one or more sub - matrix combinations according to the first matrix and the second matrix, the method further includes:

[0010] Determine the first quantity of elements included in the first matrix in the first direction, and / or determine the second quantity of elements included in the second matrix in the second direction;

[0011] According to the first quantity and / or the second quantity, and the number of elements that can be stored in the first vector register and / or the number of elements that can be stored in the second vector register, determine whether the first matrix and the second matrix meet the preset operation conditions;

[0012] If it is determined that the first matrix and the second matrix meet the preset operation conditions, then perform the steps of determining one or more sub - matrix combinations according to the first matrix and the second matrix and subsequent steps.

[0013] Optionally, the method provided by the embodiments of the present application may further include: perform matrix block processing on the first matrix according to the number of elements that can be stored in the first vector register to obtain a number of first sub - matrices, and perform matrix block processing on the second matrix according to the number of elements that can be stored in the second vector register to obtain a number of second sub - matrices.

[0014] As an example, performing matrix block processing on the first matrix according to the number of elements that can be stored in the first vector register to obtain a number of first sub - matrices, and performing matrix block processing on the second matrix according to the number of elements that can be stored in the second vector register to obtain a number of second sub - matrices includes:

[0015] Determine the third quantity of the first sub - matrices according to the number of elements that can be stored in the first vector register and the first quantity, and perform block processing on the first matrix according to the third quantity to obtain the third quantity of the first sub - matrices;

[0016] Determine the fourth quantity of the second sub - matrices according to the number of elements that can be stored in the second vector register and the second quantity, and perform block processing on the second matrix according to the fourth quantity to obtain the fourth quantity of the second sub - matrices.

[0017] Optionally, the step of reading all elements of the first sub - matrix in the sub - matrix combination through the first vector register includes:

[0018] Arrange the first sub-matrix in the sub-matrix combination in the first direction as the main order to obtain the third sub-matrix of the sub-matrix combination;

[0019] Set a fourth sub-matrix that is exactly the same as the third sub-matrix at the end position in the first direction of the third sub-matrix to obtain a fifth sub-matrix;

[0020] Obtain a sliding window with the same number of storable elements as the number of elements in the first matrix;

[0021] Determine each target element combination corresponding to the first sub-matrix in the sub-matrix combination according to the sliding window and the fifth sub-matrix;

[0022] Read in each of the target element combinations sequentially through the first vector register.

[0023] Optionally, using the first vector register and the second vector register to determine the matrix operation result corresponding to each sub-matrix combination includes:

[0024] For any sub-matrix combination, read in all elements of the first sub-matrix in any sub-matrix combination through the first vector register and read in all elements of the second sub-matrix in the sub-matrix combination through the second vector register;

[0025] Determine the matrix operation result corresponding to any sub-matrix combination according to the elements in the first vector register and the elements in the second vector register.

[0026] Optionally, the step of reading in all elements of the second sub-matrix in the sub-matrix combination through the second vector register includes:

[0027] Arrange the second sub-matrix in the sub-matrix combination in the second direction as the main order to obtain the sixth sub-matrix of the sub-matrix combination;

[0028] Read in all elements of the sixth sub-matrix in the sub-matrix combination sequentially through the second vector register.

[0029] Optionally, the step of determining the matrix operation result corresponding to the sub-matrix combination according to the elements in the first vector register and the elements in the second vector register includes:

[0030] For each target element combination, determine the matrix operation sub-result corresponding to the target element combination according to the target element combination and all elements of the sixth sub-matrix;

[0031] Determine the matrix operation result corresponding to any sub-matrix combination according to each matrix operation sub-result.

[0032] Optionally, determining the matrix multiplication result of the first matrix and the second matrix according to the matrix operation results corresponding to each of the sub-matrix combinations includes:

[0033] For any one of the sub-matrix combinations, determine the target position corresponding to the sub-matrix combination according to the position of the first sub-matrix included in the sub-matrix combination in the first matrix and the position of the second sub-matrix included in the sub-matrix combination in the second matrix;

[0034] Determine the matrix multiplication result according to the matrix operation results corresponding to each of the sub-matrix combinations and the target positions corresponding to each of the sub-matrix combinations.

[0035] In a second aspect, an embodiment of the present application provides an apparatus for determining a matrix multiplication result, including:

[0036] A matrix acquisition unit, configured to acquire a first matrix and a second matrix;

[0037] A matrix determination unit, configured to determine one or more sub-matrix combinations according to the first matrix and the second matrix, where one sub-matrix combination includes a first sub-matrix corresponding to the first matrix and a second sub-matrix corresponding to the second matrix; the multiple first sub-matrices are obtained by partitioning the first matrix according to the number of storable elements of a first vector register, and the multiple second sub-matrices are obtained by partitioning the second matrix according to the number of storable elements of a second vector register;

[0038] A first determination unit, configured to use the first vector register and the second vector register to determine the matrix operation result corresponding to each of the sub-matrix combinations;

[0039] A second determination unit, configured to determine the matrix multiplication result of the first matrix and the second matrix according to the matrix operation results corresponding to each of the sub-matrix combinations.

[0040] In a third aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where when the processor executes the computer program, the steps of the method for determining a matrix multiplication result as described in the first aspect are implemented.

[0041] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for determining a matrix multiplication result as described in the first aspect are implemented.

[0042] Fifth aspect, an embodiment of the present application provides a computer program, which, when running on an electronic device, causes the electronic device to execute the steps of the method for determining the result of matrix multiplication operation as described in the first aspect above.

[0043] The method, apparatus, device, and program product for determining the result of matrix multiplication operation provided by the embodiments of the present application have the following beneficial effects:

[0044] In the method for determining the result of matrix multiplication operation provided by the embodiments of the present application, first, a first matrix and a second matrix are obtained, and then, based on the first matrix and the second matrix, one or more sub-matrix combinations are determined. Among them, the first matrix can be processed by matrix block division according to the number of storable elements of the first vector register to obtain several first sub-matrices, and the second matrix can be processed by matrix block division according to the number of storable elements of the second vector register to obtain several second sub-matrices. Then, for each sub-matrix combination, the matrix operation result corresponding to the sub-matrix combination is determined through the first vector register and the second vector register. Finally, based on the matrix operation results corresponding to each sub-matrix combination, the matrix multiplication operation result of the first matrix and the second matrix is determined. In the method for determining the result of matrix multiplication operation of the present application, since the matrix operation result corresponding to each sub-matrix combination is determined by using the first vector register and the second vector register, and the first sub-matrix and the second sub-matrix in the sub-matrix combination are determined by the number of storable elements of the first vector register and the number of storable elements of the second vector register respectively, the first vector register can read in all elements of the first sub-matrix, and the second vector register can read in all elements of the second sub-matrix. Compared with the prior art, the space utilization rate of the vector register of this method is relatively high, thereby improving the efficiency of determining the result of matrix multiplication operation. Description of the Drawings

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0046] Figure 1 It is a flowchart of the implementation of a method for determining the result of matrix multiplication operation provided by an embodiment of the present application;

[0047] Figure 2 It is a schematic diagram of the block division of the first matrix provided by an embodiment of the present application;

[0048] Figure 3 It is a schematic diagram of the block division of the second matrix provided by an embodiment of the present application;

[0049] Figure 4 Schematic diagram of obtaining a third sub - matrix provided by an embodiment of the present application;

[0050] Figure 5 Schematic diagram of obtaining a fifth sub - matrix provided by an embodiment of the present application;

[0051] Figure 6 Schematic diagram of determining various target element combinations corresponding to a first sub - matrix provided by an embodiment of the present application;

[0052] Figure 7 Schematic diagram of obtaining a sixth sub - matrix provided by an embodiment of the present application;

[0053] Figure 8 Schematic diagram of matrix operation results corresponding to a sub - matrix combination provided by an embodiment of the present application;

[0054] Figure 9 Schematic diagram of matrix multiplication operation results of a first matrix and a second matrix provided by an embodiment of the present application;

[0055] Figure 10 Schematic diagram of the structure of a device for determining matrix multiplication operation results provided by an embodiment of the present application;

[0056] Figure 11 Schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0057] It should be noted that the terms used in the embodiments of the present application are only for explaining the specific embodiments of the present application, rather than aiming to limit the present application. In the description of the embodiments of the present application, unless otherwise specified, "a plurality of" means two or more than two, "at least one", "one or more" means one, two or more than two. The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0058] References to "one embodiment" or "some embodiments" etc. described in this specification mean that specific features, structures, or characteristics described in connection with that embodiment are included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear at different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized.

[0059] The execution subject of the method for determining the result of matrix multiplication provided by the embodiments of the present application can be an electronic device, where the electronic device can include a first vector register and a second vector register. Exemplarily, the electronic device can include, but is not limited to, devices such as mobile phones, tablet computers, laptop computers, desktop computers, in-vehicle control devices, etc.

[0060] The method for determining the result of matrix multiplication provided by the embodiments of the present application can be applied to the scenario of determining the result of the multiplication operation of any two matrices. When a user needs to determine the result of the multiplication operation of any two matrices, the electronic device can execute each step of the method for determining the result of matrix multiplication provided by the embodiments of the present application, so as to efficiently determine the result of the multiplication of these two matrices.

[0061] Please refer to Figure 1 , Figure 1 is a flowchart of the implementation of a method for determining the result of matrix multiplication provided by the embodiments of the present application. The method for determining the result of matrix multiplication can include S101 to S104, which are described in detail as follows:

[0062] In S101, obtain a first matrix and a second matrix.

[0063] In the embodiments of the present application, the electronic device can first obtain a first matrix and a second matrix to be subjected to matrix multiplication.

[0064] Among them, when a matrix multiplication operation of A×B needs to be performed, the first matrix in the present application is matrix A, and the second matrix in the present application is matrix B.

[0065] In a possible implementation manner, after obtaining the first matrix and the second matrix and before executing S102, the electronic device can first determine whether the first matrix and the second matrix meet a preset operation condition. Specifically, the electronic device can determine whether the first matrix and the second matrix meet the preset operation condition through steps a to c. The details are as follows:

[0066] In step a, determine the first quantity of elements included in the first matrix in the first direction, and / or determine the second quantity of elements included in the second matrix in the second direction.

[0067] In this implementation, when the electronic device determines whether the first matrix and the second matrix meet the preset operation conditions, it can first determine the first quantity of elements included in the first matrix in the first direction, and / or determine the second quantity of elements included in the second matrix in the second direction.

[0068] Among them, the first quantity of elements included in the first matrix in the first direction can be the first quantity of elements included in each row of the first matrix, and the second quantity of elements included in the second matrix in the second direction can be the first quantity of elements included in each column of the second matrix.

[0069] In practical applications, according to the knowledge of matrix multiplication operations, it can be known that the first quantity of elements included in the first matrix in the first direction is equal to the second quantity of elements included in the second matrix in the second direction. Therefore, the electronic device can only determine the first quantity of elements included in the first matrix in the first direction, or only determine the second quantity of elements included in the second matrix in the second direction. Of course, it can also determine both the first quantity of elements included in the first matrix in the first direction and the second quantity of elements included in the second matrix in the second direction.

[0070] Exemplarily, if the electronic device needs to perform matrix multiplication operation of A×B, the size of matrix A is M×K, and the size of matrix B is K×N, then both the first quantity and the second quantity can be K.

[0071] In step b, according to the first quantity and / or the second quantity, and the number of storable elements in the first vector register and / or the number of storable elements in the second vector register, determine whether the first matrix and the second matrix meet the preset operation conditions.

[0072] In this implementation, in addition to determining the first quantity of elements included in the first matrix in the first direction, and / or determining the second quantity of elements included in the second matrix in the second direction, the electronic device also needs to determine the number of storable elements in the first vector register and / or the number of storable elements in the second vector register.

[0073] Since the first quantity of elements included in the first matrix in the first direction is the same as the second quantity of elements included in the second matrix in the second direction, in practical applications, the number of storable elements in the first vector register in the electronic device is usually the same as that in the second vector register. Therefore, the electronic device can determine only the number of storable elements in the first vector register, or only the number of storable elements in the second vector register. Of course, it can also determine the number of storable elements in the first vector register and the number of storable elements in the second vector register simultaneously.

[0074] After determining the first quantity and / or the second quantity, and the number of storable elements in the first vector register and / or the number of storable elements in the second vector register, the electronic device can determine whether the first matrix and the second matrix meet the preset operation conditions according to the following method: If it is determined that the first quantity or the second quantity is less than or equal to half of the number of storable elements in the first vector register or the second vector register, it is determined that the first matrix and the second matrix meet the preset operation conditions; if it is determined that the first quantity or the second quantity is greater than half of the number of storable elements in the first vector register or the second vector register, it is determined that the first matrix and the second matrix do not meet the preset operation conditions.

[0075] Exemplarily, if the first quantity and the second quantity are 25, and the number of storable elements in the first vector register and the second vector register are both 128, it can be determined that the first quantity or the second quantity is less than or equal to half of the number of storable elements in the first vector register or the second vector register, and then it is determined that the first matrix and the second matrix meet the preset operation conditions.

[0076] It should be noted that setting this preset operation condition is to judge whether the method of calculating the matrix multiplication result of the present application can improve the efficiency of calculating the first matrix and the second matrix. If it is judged that the first matrix and the second matrix meet the preset operation conditions, it can be considered that the method of calculating the matrix multiplication result of the present application can improve the efficiency of calculating the first matrix and the second matrix. If it is judged that the first matrix and the second matrix do not meet the preset operation conditions, it can be considered that the efficiency of calculating the first matrix and the second matrix by the method of calculating the matrix multiplication result of the present application is the same as that of the prior art method, so the efficiency of calculating the first matrix and the second matrix cannot be improved.

[0077] In step c, if it is determined that the first matrix and the second matrix meet the preset operation conditions, then determine one or more sub-matrix combinations according to the first matrix and the second matrix.

[0078] In this implementation manner, after determining whether the first matrix and the second matrix meet the preset operation conditions, if it is determined that the first matrix and the second matrix meet the preset operation conditions, the electronic device may execute each step from S102 to S104.

[0079] It should be noted that if it is determined that the first matrix and the second matrix do not meet the preset operation conditions, it can be considered that the efficiency of calculating the first matrix and the second matrix by the method for the matrix multiplication result of the present application is the same as that of the method in the prior art for calculating the first matrix and the second matrix. Therefore, if it is determined that the first matrix and the second matrix do not meet the preset operation conditions, the electronic device may choose the method in the prior art to determine the multiplication result of the first matrix and the second matrix, or may also choose the method for the matrix multiplication result of the present application to determine the multiplication result of the first matrix and the second matrix.

[0080] In S102, one or more sub-matrix combinations are determined according to the first matrix and the second matrix.

[0081] Wherein, one sub-matrix combination includes a first sub-matrix corresponding to the first matrix and a second sub-matrix corresponding to the second matrix; the multiple first sub-matrices are obtained by partitioning the first matrix according to the number of elements that can be stored in the first vector register, and the multiple second sub-matrices are obtained by partitioning the second matrix according to the number of elements that can be stored in the second vector register.

[0082] In the embodiment of the present application, after obtaining the first matrix and the second matrix, the electronic device may perform matrix partitioning processing on the first matrix according to the number of elements that can be stored in the first vector register to obtain a plurality of first sub-matrices, and perform matrix partitioning processing on the second matrix according to the number of elements that can be stored in the second vector register to obtain a plurality of second sub-matrices.

[0083] It should be noted that since the first number of elements included in the first matrix in the first direction is the same as the second number of elements included in the second matrix in the second direction, in practical applications, the number of elements that can be stored in the first vector register in the electronic device is usually the same as the number of elements that can be stored in the second vector register. Therefore, optionally, the electronic device may perform matrix partitioning processing on the first matrix according to the number of elements that can be stored in the first vector register and / or the number of elements that can be stored in the second vector register to obtain a plurality of first sub-matrices, and perform matrix partitioning processing on the second matrix according to the number of elements that can be stored in the first vector register and / or the number of elements that can be stored in the second vector register to obtain a plurality of second sub-matrices.

[0084] In a possible implementation, the electronic device can perform matrix block processing on the first matrix according to the number of storable elements of the first vector register to obtain a number of first sub-matrices, and perform matrix block processing on the second matrix according to the number of storable elements of the second vector register to obtain a number of second sub-matrices. The details are as follows:

[0085] In step d, according to the number of storable elements of the first vector register and the first quantity, determine the third quantity of the first sub-matrix, and perform block processing on the first matrix according to the third quantity to obtain the third quantity of the first sub-matrices.

[0086] In this implementation, the electronic device can first determine all the elements of x rows that the first vector register can accommodate each time according to the number of storable elements of the first vector register and the first quantity, and determine the third quantity of the first sub-matrix according to x.

[0087] Exemplarily, if the number of storable elements of the first vector register is 128, the size of the first matrix is 10×25, that is, the first quantity is 25. Therefore, it can be determined that the first vector register can accommodate all the elements of 5 rows each time, that is, x is 5. After that, since the first matrix has 10 rows, the third quantity of the first sub-matrix can be determined to be 2.

[0088] After determining the third quantity, the electronic device can perform block processing on the first matrix to obtain the third quantity of the first sub-matrices. Among them, the number of elements included in each first sub-matrix in the first direction is the same as the first quantity of elements included in the first matrix in the first direction.

[0089] Please refer to Figure 2 , Figure 2 which is a schematic diagram of block processing of the first matrix provided by an embodiment of the present application. Figure 2 The schematic diagram of block processing of the first matrix shown corresponds to the data in the above example.

[0090] As Figure 2 shown, the size of matrix A is 10×25, and the third quantity of the first sub-matrix is 2. Therefore, the first matrix A can be block processed to obtain the first sub-matrix a1 and the first sub-matrix a2. Among them, the elements included in any row of the first sub-matrix a1 are the same as the elements included in the corresponding row of the first matrix A. For example, the elements included in the first row of the first sub-matrix a1 are the same as the elements included in the first row of the first matrix A. Similarly, the elements included in any row of the first sub-matrix a2 are the same as the elements included in the corresponding row of the first matrix A. For example, the elements included in the sixth row of the first sub-matrix a2 are the same as the elements included in the sixth row of the first matrix A.

[0091] In step e, according to the number of storable elements of the second vector register and the second quantity, determine the fourth quantity of the second sub-matrix, and perform a block processing on the second matrix according to the fourth quantity to obtain the second sub-matrix with the fourth quantity.

[0092] In this implementation, the electronic device may first determine all the elements that the second vector register can hold for y columns each time according to the number of storable elements of the second vector register and the second quantity, and determine the fourth quantity of the second sub-matrix according to y.

[0093] Exemplarily, if the number of storable elements of the second vector register is 128 and the size of the second matrix is 25×10, that is, the second quantity is 25, it can be determined that the second vector register can hold all the elements of 5 columns each time, that is, y is 5. Then, since the second matrix has 10 columns, it can be determined that the fourth quantity of the second sub-matrix is 2.

[0094] After determining the fourth quantity, the electronic device may perform a block processing on the second matrix to obtain the second sub-matrix with the fourth quantity. Among them, the number of elements included in each second sub-matrix in the second direction is the same as the second quantity of the elements included in the second matrix in the second direction.

[0095] Please refer to Figure 3 , Figure 3 which is a schematic diagram of a block processing on the second matrix provided by an embodiment of the present application. Figure 3 The schematic diagram of the block processing on the second matrix shown corresponds to the data of the above example.

[0096] As Figure 3 shown, the size of matrix B is 25×10 and the fourth quantity of the second sub-matrix is 2. Therefore, the second matrix B can be block processed to obtain the second sub-matrix b1 and the first sub-matrix b2. Among them, the elements included in any column of the second sub-matrix b1 are the same as the elements included in the corresponding column of the second matrix B. For example, the elements included in the first column of the second sub-matrix b1 are the same as the elements included in the first column of the second matrix B. Similarly, the elements included in any column of the second sub-matrix b2 are the same as the elements included in the corresponding column of the second matrix B. For example, the elements included in the sixth column of the second sub-matrix b2 are the same as the elements included in the sixth column of the second matrix B.

[0097] After the electronic device obtains a number of first sub-matrices and a number of second sub-matrices, it can combine each first sub-matrix and each second sub-matrix to obtain a plurality of sub-matrix combinations. Among them, each sub-matrix combination includes a first sub-matrix and a second sub-matrix.

[0098] Exemplarily, as Figure 2 and Figure 3As shown, the first sub-matrix includes the first sub-matrix a1 and the first sub-matrix a2, and the second sub-matrix includes the second sub-matrix b1 and the second sub-matrix b2. Therefore, the first sub-matrix a1 and the first sub-matrix a2, as well as the second sub-matrix b1 and the second sub-matrix b2, can be combined to obtain four sub-matrix combinations: 1. The sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b1; 2. The sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b2; 3. The sub-matrix combination composed of the first sub-matrix a2 and the second sub-matrix b1; 4. The sub-matrix combination composed of the first sub-matrix a2 and the second sub-matrix b2.

[0099] In S103, the matrix operation result corresponding to each sub-matrix combination is determined by using the first vector register and the second vector register.

[0100] In the embodiment of the present application, after obtaining multiple sub-matrix combinations, the electronic device can, for any sub-matrix combination, read all elements of the first sub-matrix in any sub-matrix combination through the first vector register, and read all elements of the second sub-matrix in any sub-matrix combination through the second vector register.

[0101] In a possible implementation manner, the electronic device can implement reading all elements of the first sub-matrix in any sub-matrix combination through steps f to j. Details are as follows:

[0102] It should be noted that the examples in the following steps f to j are all based on the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b1.

[0103] In step f, the first sub-matrix in any sub-matrix combination is arranged in the first direction as the main order to obtain the third sub-matrix of any sub-matrix combination.

[0104] In this implementation manner, the electronic device can arrange the first sub-matrix a1 in the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b1 in row-major order, so as to obtain the third sub-matrix a3 of the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b1.

[0105] Please refer to Figure 4 , Figure 4 which is a schematic diagram of obtaining the third sub-matrix provided by the embodiment of the present application. In Figure 4 , the elements included in each row of the first sub-matrix a1 are the same as the elements included in the corresponding column of the third sub-matrix a3. For example, the elements included in the first row of the first sub-matrix a1 are the same as the elements included in the first column of the third sub-matrix a3, the elements included in the second row of the first sub-matrix a1 are the same as the elements included in the second column of the third sub-matrix a3, and so on.

[0106] In step g, a fourth sub-matrix that is exactly the same as the third sub-matrix is set at the end position in the first direction of the third sub-matrix to obtain a fifth sub-matrix.

[0107] In this implementation, the electronic device can set a fourth sub-matrix a4 that is exactly the same as the third sub-matrix a3 at the end position in the first direction of the third sub-matrix a3 to obtain a fifth sub-matrix a5.

[0108] Please refer to Figure 5 , Figure 5 which is a schematic diagram of obtaining a fifth sub-matrix provided by an embodiment of this application.

[0109] In step h, a sliding window with the same number of storable elements as the number of elements in the first matrix is obtained.

[0110] In this implementation, since the size of the first matrix is 10×25, that is, the number of elements in the first matrix is 125, a sliding window with 125 storable elements can be obtained.

[0111] In step i, according to the sliding window and the fifth sub-matrix, the respective target element combinations corresponding to the first sub-matrix in any sub-matrix combination are determined.

[0112] In this implementation, after obtaining a sliding window with 125 storable elements and the fifth sub-matrix as shown in Figure 5 , the electronic device can determine the respective target element combinations corresponding to the first sub-matrix in any sub-matrix combination according to the sliding window and the fifth sub-matrix in the following manner:

[0113] As shown in Figure 6 , Figure 6 which is a schematic diagram of determining the respective target element combinations corresponding to the first sub-matrix provided by an embodiment of this application.

[0114] As shown in Figure 6 , the electronic device first sets the starting position of the sliding window in the first direction at the starting position of the fifth sub-matrix a5 in the first direction, so as to obtain a first target element combination, where the first target element combination is an element combination formed by arranging the elements in columns ①, ②, ③, ④, and ⑤ of the fifth sub-matrix a5 in sequence.

[0115] After that, the electronic device can move the sliding window to the end position in the first direction, and the moving distance is the distance corresponding to the elements included in each column of the fifth sub-matrix a5. That is, the starting position of the sliding window in the first direction is set at the starting position of the second column of the fifth sub-matrix a5, so that a second target element combination can be obtained. The second target element combination is an element combination formed by arranging the elements of the second, third, fourth, fifth, and first columns of the fifth sub-matrix a5 in sequence.

[0116] By analogy, the electronic device can obtain a third target element combination, a fourth target element combination, and a fifth target element combination. Among them, the third target element combination is an element combination formed by arranging the elements of the third, fourth, fifth, first, and second columns of the fifth sub-matrix a5 in sequence; the fourth target element combination is an element combination formed by arranging the elements of the fourth, fifth, first, second, and third columns of the fifth sub-matrix a5 in sequence; the fifth target element combination is an element combination formed by arranging the elements of the fifth, first, second, third, and fourth columns of the fifth sub-matrix a5 in sequence.

[0117] In step j, each target element combination is read in sequentially through the first vector register.

[0118] In this implementation manner, after determining each target element combination, the electronic device can read in each target element combination sequentially through the first vector register.

[0119] Specifically, the electronic device can first read in the first target element combination through the first vector register, then read in the second target element combination through the first vector register, then read in the third target element combination through the first vector register, then read in the fourth target element combination through the first vector register, and finally read in the fifth target element combination through the first vector register.

[0120] In a possible implementation manner, the electronic device can implement reading in all the elements of the second sub-matrix in the sub-matrix combination through step k to step l. The details are as follows:

[0121] It should be noted that the examples in the following steps k to l take the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b1 as an example.

[0122] In step k, the second sub-matrix in the sub-matrix combination is arranged in column-major order in the second direction to obtain a sixth sub-matrix of the sub-matrix combination.

[0123] In this implementation manner, the electronic device can arrange the second sub-matrix b1 in the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b1 in column-major order, so as to obtain a sixth sub-matrix b3 of the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b1.

[0124] Please refer to Figure 7 , Figure 7 , which is a schematic diagram of obtaining a sixth sub-matrix provided by an embodiment of the present application. In Figure 7 , the elements included in each column of the second sub-matrix b1 are the same as the elements included in the corresponding column of the sixth sub-matrix b3. For example, the elements included in the first column of the second sub-matrix b1 are the same as the elements included in the first column of the sixth sub-matrix b3, the elements included in the second column of the second sub-matrix b1 are the same as the elements included in the second column of the sixth sub-matrix b3, and so on.

[0125] In step l, all elements of the sixth sub-matrix in the sub-matrix combination are read in sequentially through the second vector register.

[0126] In this implementation manner, after obtaining the sixth sub-matrix in the sub-matrix combination, the electronic device can read in all elements of the sixth sub-matrix b3 sequentially by column through the second vector register.

[0127] Taking Figure 7 as an example, the second vector register can first read in the elements included in the first column of the sixth sub-matrix b3, then read in the elements included in the second column of the sixth sub-matrix b3, then read in the elements included in the third column of the sixth sub-matrix b3, then read in the elements included in the fourth column of the sixth sub-matrix b3, and then read in the elements included in the fifth column of the sixth sub-matrix b3.

[0128] Based on this, the elements read in by the second vector register are the elements formed by arranging the elements of the first, second, third, fourth, and fifth columns of the sixth sub-matrix b3 in sequence.

[0129] In an embodiment of the present application, after all elements of the first sub-matrix in the sub-matrix combination are read in through the first vector register and all elements of the second sub-matrix in the sub-matrix combination are read in through the second vector register, the electronic device can determine the matrix operation result corresponding to the sub-matrix combination according to the elements of the first vector register and the elements of the second vector register.

[0130] It should be noted that, as can be seen from steps i and j, the elements read in by the first vector register will change. Specifically, the elements read in by the first vector register are the elements of the first target element combination, the elements of the second target element combination, the elements of the third target element combination, the elements of the fourth target element combination, and the elements of the fifth target element combination in sequence. And as can be seen from step l, the elements read in by the second vector register are unchanged. Specifically, the elements read in by the second vector register are the elements formed by arranging the elements of the first, second, third, fourth, and fifth columns of the sixth sub-matrix b3 in sequence.

[0131] Based on this, the electronic device can determine the matrix operation result corresponding to any sub-matrix combination through step m to step n. The details are as follows:

[0132] In step m, for each target element combination, according to the target element combination and all elements of the sixth sub-matrix, determine the matrix operation sub-result corresponding to the target element combination.

[0133] In this implementation, for the first target element combination (the element combination composed of the elements of the 1st, 2nd, 3rd, 4th, and 5th columns of the fifth sub-matrix a5 arranged in sequence), the electronic device can perform multiplication operations on each column element in the first target element combination with the corresponding column element in the sixth sub-matrix b3 (having the 1st, 2nd, 3rd, 4th, and 5th column elements) respectively, so as to obtain the matrix operation sub-result corresponding to the first target element combination.

[0134] For the second target element combination (the element combination composed of the elements of the 2nd, 3rd, 4th, 5th, and 1st columns of the fifth sub-matrix a5 arranged in sequence), the electronic device can perform multiplication operations on each column element in the second target element combination with the corresponding column element in the sixth sub-matrix b3 (having the 1st, 2nd, 3rd, 4th, and 5th column elements) respectively, so as to obtain the matrix operation sub-result corresponding to the second target element combination.

[0135] For the third target element combination (the element combination composed of the elements of the 3rd, 4th, 5th, 1st, and 2nd columns of the fifth sub-matrix a5 arranged in sequence), the electronic device can perform multiplication operations on each column element in the third target element combination with the corresponding column element in the sixth sub-matrix b3 (having the 1st, 2nd, 3rd, 4th, and 5th column elements) respectively, so as to obtain the matrix operation sub-result corresponding to the third target element combination.

[0136] For the fourth target element combination (the element combination composed of the elements of the 4th, 5th, 1st, 2nd, and 3rd columns of the fifth sub-matrix a5 arranged in sequence), the electronic device can perform multiplication operations on each column element in the fourth target element combination with the corresponding column element in the sixth sub-matrix b3 (having the 1st, 2nd, 3rd, 4th, and 5th column elements) respectively, so as to obtain the matrix operation sub-result corresponding to the fourth target element combination.

[0137] For the fifth target element combination (the element combination composed of the elements of the 5th, 1st, 2nd, 3rd, and 4th columns of the fifth sub-matrix a5 arranged in sequence), the electronic device can perform multiplication operations on each column element in the fifth target element combination with the corresponding column element in the sixth sub-matrix b3 (having the 1st, 2nd, 3rd, 4th, and 5th column elements) respectively, so as to obtain the matrix operation sub-result corresponding to the fifth target element combination.

[0138] In step n, according to the results of each matrix operator, determine the matrix operation result corresponding to any sub-matrix combination.

[0139] In this implementation manner, after determining the results of each matrix operator, the electronic device can determine the matrix operation result corresponding to any sub-matrix combination according to the results of each matrix operator.

[0140] Please refer to Figure 8 , Figure 8 which is a schematic diagram of the matrix operation result corresponding to a sub-matrix combination provided by an embodiment of the present application.

[0141] Among them, in the matrix operation result of the first target element combination, the result obtained by multiplying the elements in the first column of the fifth sub-matrix a5 by the elements in the first column of the sixth sub-matrix b3 can be output to the first row and first column in the matrix operation result; the result obtained by multiplying the elements in the second column of the fifth sub-matrix a5 by the elements in the second column of the sixth sub-matrix b3 can be output to the first row and first column in the matrix operation result, and so on, so as to obtain the matrix operation results of (1,1), (2, 2), (3, 3), (4, 4), (5, 5) respectively according to the matrix operation result of the first target element combination.

[0142] In the matrix operation result of the second target element combination, the result obtained by multiplying the elements in the second column of the fifth sub-matrix a5 by the elements in the first column of the sixth sub-matrix b3 can be output to the second row and first column in the matrix operation result; the result obtained by multiplying the elements in the third column of the fifth sub-matrix a5 by the elements in the second column of the sixth sub-matrix b3 can be output to the third row and second column in the matrix operation result, and so on, so as to obtain the matrix operation results of (2,1), (3, 2), (4, 3), (5, 4), (1, 5) respectively according to the matrix operation result of the first target element combination.

[0143] Similarly, the matrix operation results of (3,1), (4, 2), (5, 3), (1, 4), (2,5) can be obtained according to the matrix operation result of the third target element combination; the matrix operation results of (4,1), (5, 2), (1, 3), (2, 4), (3, 5) can be obtained according to the matrix operation result of the fourth target element combination; the matrix operation results of (5,1), (1, 2), (2, 3), (3, 4), (4, 5) can be obtained according to the matrix operation result of the fifth target element combination.

[0144] It should be noted that the above provides a method for obtaining the matrix operation result corresponding to the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b1, and the matrix operation results corresponding to other sub-matrix combinations can be obtained through this method.

[0145] In S104, according to the matrix operation result corresponding to each sub-matrix combination, determine the matrix multiplication result of the first matrix and the second matrix.

[0146] In the embodiment of the present application, after determining the matrix operation result corresponding to each sub-matrix combination, the electronic device can determine the matrix multiplication result of the first matrix and the second matrix through step o to step p. Details are as follows:

[0147] In step o, for any sub-matrix combination, determine the target position corresponding to the sub-matrix combination according to the position of the first sub-matrix included in the sub-matrix combination in the first matrix and the position of the second sub-matrix included in the sub-matrix combination in the second matrix.

[0148] Taking the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b1 as an example, since the position of the first sub-matrix a1 in the first matrix in this sub-matrix combination is the first to fifth rows, and the position of the second sub-matrix b1 in the second matrix in this sub-matrix combination is the first to fifth columns, the target position corresponding to this sub-matrix combination is the two-dimensional space formed by the first to fifth rows and the first to fifth columns.

[0149] By analogy, the target position corresponding to the sub-matrix combination composed of the second sub-matrix a2 and the second sub-matrix b1 is the two-dimensional space formed by the sixth to tenth rows and the first to fifth columns; the target position corresponding to the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b2 is the two-dimensional space formed by the first to fifth rows and the sixth to tenth columns; the target position corresponding to the sub-matrix combination composed of the second sub-matrix a2 and the second sub-matrix b2 is the two-dimensional space formed by the sixth to tenth rows and the sixth to tenth columns.

[0150] In step p, determine the matrix multiplication result according to the matrix operation result corresponding to each sub-matrix combination and the target position corresponding to each sub-matrix combination.

[0151] In this implementation manner, the electronic device can, for each sub-matrix combination, according to the target position corresponding to the sub-matrix combination, set the matrix operation result corresponding to the sub-matrix combination at the corresponding position in the matrix multiplication result, so as to obtain the matrix multiplication result of the first matrix and the second matrix.

[0152] Please refer to Figure 9 , Figure 9 which is a schematic diagram of the matrix multiplication result of a first matrix and a second matrix provided by the embodiment of the present application. InFigure 9 In it, the two-dimensional space formed by the 1st to 5th rows and the 1st to 5th columns is the corresponding position of the matrix operation result corresponding to the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b1. The two-dimensional space formed by the 6th to 10th rows and the 1st to 5th columns is the corresponding position of the matrix operation result corresponding to the sub-matrix combination composed of the first sub-matrix a2 and the second sub-matrix b1. The two-dimensional space formed by the 1st to 5th rows and the 6th to 10th columns is the corresponding position of the matrix operation result corresponding to the sub-matrix combination composed of the first sub-matrix a1 and the second sub-matrix b2. The two-dimensional space formed by the 6th to 10th rows and the 6th to 10th columns is the corresponding position of the matrix operation result corresponding to the sub-matrix combination composed of the first sub-matrix a2 and the second sub-matrix b2.

[0153] As can be seen from the above, in the method for determining the matrix multiplication operation result provided in the embodiments of the present application, first, a first matrix and a second matrix are obtained, and then one or more sub-matrix combinations are determined according to the first matrix and the second matrix. Among them, the first matrix can be processed by matrix block division according to the number of storable elements of the first vector register to obtain a number of first sub-matrices, and the second matrix can be processed by matrix block division according to the number of storable elements of the second vector register to obtain a number of second sub-matrices. Then, for each sub-matrix combination, the matrix operation result corresponding to the sub-matrix combination is determined through the first vector register and the second vector register. Finally, according to the matrix operation results corresponding to each sub-matrix combination, the matrix multiplication operation result of the first matrix and the second matrix is determined. In the method for determining the matrix multiplication operation result in the present application, since the matrix operation result corresponding to each sub-matrix combination is determined by using the first vector register and the second vector register, and the first sub-matrix and the second sub-matrix in the sub-matrix combination are respectively determined by the number of storable elements of the first vector register and the number of storable elements of the second vector register, the first vector register can read in all elements of the first sub-matrix, and the second vector register can read in all elements of the second sub-matrix. Compared with the prior art, the space utilization rate of the vector register in this method is relatively high, thereby improving the efficiency of determining the matrix multiplication operation result.

[0154] Based on the method for determining the matrix multiplication operation result provided in the above embodiments, the embodiments of the present application further provide a device for determining the matrix multiplication operation result for implementing the above method embodiments. Please refer to Figure 10 , Figure 10 which is a schematic structural diagram of a device for determining the matrix multiplication operation result provided in the embodiments of the present application. As Figure 10 shown, the device 100 for determining the matrix multiplication operation result may include: a matrix acquisition unit 101, a matrix determination unit 102, a first determination unit 103, and a second determination unit 104. Among them:

[0155] The matrix acquisition unit 101 is used to acquire a first matrix and a second matrix.

[0156] The matrix determination unit 102 is used to determine one or more sub-matrix combinations according to the first matrix and the second matrix. A sub-matrix combination includes a first sub-matrix corresponding to the first matrix and a second sub-matrix corresponding to the second matrix. The multiple first sub-matrices are obtained by partitioning the first matrix according to the number of storable elements in the first vector register, and the multiple second sub-matrices are obtained by partitioning the second matrix according to the number of storable elements in the second vector register.

[0157] The first determination unit 103 is used to determine the matrix operation result corresponding to each sub-matrix combination by using the first vector register and the second vector register.

[0158] The second determination unit 104 is used to determine the matrix multiplication operation result of the first matrix and the second matrix according to the matrix operation result corresponding to each sub-matrix combination.

[0159] Optionally, the device 100 for determining the matrix multiplication operation result may further include a third determination unit. Wherein:

[0160] The third determination unit is specifically used for:

[0161] Determine the first quantity of elements included in the first matrix in the first direction, and / or determine the second quantity of elements included in the second matrix in the second direction;

[0162] According to the first quantity and / or the second quantity, and the number of storable elements in the first vector register and / or the number of storable elements in the second vector register, determine whether the first matrix and the second matrix meet the preset operation conditions;

[0163] If it is determined that the first matrix and the second matrix meet the preset operation conditions, then execute determining one or more sub-matrix combinations according to the first matrix and the second matrix.

[0164] Optionally, the device 100 for determining the matrix multiplication operation result may further include: a matrix partitioning unit.

[0165] The matrix partitioning unit is specifically used for:

[0166] Determine the third quantity of the first sub-matrix according to the number of storable elements in the first vector register and the first quantity;

[0167] Partition the first matrix according to the third quantity to obtain the third quantity of first sub-matrices;

[0168] Determine the fourth quantity of the second sub-matrix according to the number of storable elements in the second vector register and the second quantity;

[0169] Partition the second matrix according to the fourth quantity to obtain second sub-matrices of the fourth quantity.

[0170] Optionally, the apparatus 100 for determining the result of matrix multiplication operation may further include: a matrix element reading unit.

[0171] The matrix element reading unit is configured to:

[0172] For any sub-matrix combination, read all elements of the first sub-matrix in the sub-matrix combination through the first vector register and read all elements of the second sub-matrix in the sub-matrix combination through the second vector register;

[0173] Determine the matrix operation result corresponding to any sub-matrix combination according to the elements of the first vector register and the elements of the second vector register.

[0174] Optionally, the matrix element reading unit is specifically configured to:

[0175] Arrange the first sub-matrix in any sub-matrix combination in the first direction as the major order to obtain the third sub-matrix of any sub-matrix combination;

[0176] Set a fourth sub-matrix identical to the third sub-matrix at the end position in the first direction of the third sub-matrix to obtain a fifth sub-matrix;

[0177] Obtain a sliding window with the same number of storable elements as the number of elements of the first matrix;

[0178] Determine each target element combination corresponding to the first sub-matrix in any sub-matrix combination according to the sliding window and the fifth sub-matrix;

[0179] Read in each target element combination sequentially through the first vector register.

[0180] Optionally, the matrix element reading unit is further specifically configured to:

[0181] Arrange the second sub-matrix in any sub-matrix combination in the second direction as the major order to obtain the sixth sub-matrix of the sub-matrix combination;

[0182] Read in all elements of the sixth sub-matrix in any sub-matrix combination sequentially through the second vector register.

[0183] Optionally, the first determining unit 103 is specifically configured to:

[0184] For each target element combination, determine the matrix operation sub-result corresponding to the target element combination according to the target element combination and all elements of the sixth sub-matrix;

[0185] Determine the matrix operation result corresponding to any sub - matrix combination according to the results of each matrix operator.

[0186] Optionally, the second determination unit 104 is specifically configured to:

[0187] For any sub - matrix combination, determine the target position corresponding to the sub - matrix combination according to the position of the first sub - matrix included in the sub - matrix combination in the first matrix and the position of the second sub - matrix included in the sub - matrix combination in the second matrix;

[0188] Determine the matrix multiplication operation result according to the matrix operation results corresponding to each sub - matrix combination and the target positions corresponding to each sub - matrix combination.

[0189] Please refer to Figure 11 , Figure 11 which is a schematic structural diagram of an electronic device provided in an embodiment of the present application. As Figure 11 shown, the electronic device 11 provided in this embodiment may include: a processor 110, a memory 111, and a computer program 112 stored in the memory 111 and executable on the processor 110, such as the program corresponding to the method for determining the matrix multiplication operation result. When the processor 110 executes the computer program 112, it implements the steps in the method embodiment for determining the matrix multiplication operation result as described above, such as Figure 1 the S101 - S104 shown. Or, when the processor 110 executes the computer program 112, it implements the functions of each module / unit in the device embodiment for determining the matrix multiplication operation result, such as Figure 10 the functions of the units 101 - 104 shown.

[0190] Exemplarily, the computer program 112 may be divided into one or more modules / units. One or more modules / units are stored in the memory 111 and executed by the processor 110 to complete the present application. One or more modules / units may be a series of computer program instruction segments capable of performing specific functions, and these instruction segments are used to describe the execution process of the computer program 112 in the electronic device 11. For example, the computer program 112 may be divided into a matrix acquisition unit 101, a matrix determination unit 102, a first determination unit 103, and a second determination unit 104. For the specific functions of each unit, please refer to Figure 10 the relevant descriptions in the corresponding embodiments, which will not be elaborated here.

[0191] Those skilled in the art can understand that Figure 11 is only an example of the electronic device 11, and does not constitute a limitation on the electronic device 11. It may include more or fewer components than shown in the figure, or combine some components, or different components.

[0192] The processor 110 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0193] The memory 111 may be an internal storage unit of the electronic device 11, such as the hard disk or memory of the electronic device 11. The memory 111 may also be an external storage device of the electronic device 11, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, or a flash card equipped on the electronic device 11, etc. Further, the memory 111 may also include both an internal storage unit and an external storage device of the electronic device 11. The memory 111 is used to store computer programs and other programs and data required by the electronic device. The memory 111 may also be used to temporarily store data that has been output or is to be output.

[0194] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the above division of each functional unit is used as an example. In actual applications, the above functions can be allocated to different functional units according to needs, that is, the internal structure of the device for determining the result of matrix multiplication operation is divided into different functional units to complete all or part of the functions described above. Each functional unit in the embodiment can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit are only for the convenience of mutual distinction and do not limit the protection scope of this application. The specific working process of the units in the above system can refer to the corresponding process in the foregoing method embodiment and will not be elaborated here.

[0195] The embodiment of this application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps in the foregoing method embodiments can be implemented.

[0196] An embodiment of the present application provides a computer program product. When the computer program product runs on a terminal device, the terminal device implements the steps in each of the above method embodiments.

[0197] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0198] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0199] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included within the protection scope of the present application.

Claims

1. A method for determining the result of a matrix multiplication operation, characterized in that: include: Get the first matrix and the second matrix; Determine one or more submatrix combinations according to the first matrix and the second matrix, wherein one submatrix combination includes a first submatrix corresponding to the first matrix and a second submatrix corresponding to the second matrix; a plurality of the first submatrices are obtained by dividing the first matrix into blocks according to the number of storable elements of the first vector register, and a plurality of the second submatrices are obtained by dividing the second matrix into blocks according to the number of storable elements of the second vector register; Determine a matrix operation result corresponding to each of the sub-matrix combinations using the first vector register and the second vector register; The matrix multiplication result of the first matrix and the second matrix is ​​determined according to the matrix operation result corresponding to each sub-matrix combination.

2. The method according to claim 1, characterized in that Before determining one or more sub-matrix combinations according to the first matrix and the second matrix, the method further includes: Determine a first number of elements included in the first matrix in a first direction, and / or determine a second number of elements included in the second matrix in a second direction; Determining whether the first matrix and the second matrix meet a preset operation condition according to the first number and / or the second number, and the number of storable elements of the first vector register and / or the number of storable elements of the second vector register; If it is determined that the first matrix and the second matrix satisfy the preset operation condition, the step of determining one or more sub-matrix combinations based on the first matrix and the second matrix is ​​performed.

3. The method according to claim 2, characterized in that The method further comprises: determining a third number of the first sub-matrix according to the number of storable elements of the first vector register and the first number; According to the third number, performing block processing on the first matrix to obtain the third number of the first sub-matrices; determining a fourth number of the second sub-matrix according to the number of storable elements of the second vector register and the second number; According to the fourth number, the second matrix is ​​processed in blocks to obtain the fourth number of second sub-matrices.

4. The method according to claim 1, characterized in that: The using the first vector register and the second vector register to determine the matrix operation result corresponding to each of the sub-matrix combinations includes: For any of the sub-matrix combinations, read in all elements of the first sub-matrix in any of the sub-matrix combinations through the first vector register and read in all elements of the second sub-matrix in the sub-matrix combination through the second vector register; A matrix operation result corresponding to any of the sub-matrix combinations is determined according to the elements of the first vector register and the elements of the second vector register.

5. The method according to claim 4, characterized in that The step of reading all elements of the first submatrix in any submatrix combination through the first vector register includes: Arrange the first submatrices in any of the submatrix combinations in a first direction-based order to obtain a third submatrix in any of the submatrix combinations; Setting a fourth submatrix that is identical to the third submatrix at the end of the third submatrix in the first direction to obtain a fifth submatrix; Obtain a sliding window that can store the same number of elements as the number of elements in the first matrix; Determine, according to the sliding window and the fifth submatrix, each target element combination corresponding to the first submatrix in any of the submatrix combinations; Each target element combination is read in sequentially through the first vector register.

6. The method according to claim 5, characterized in that The step of reading all elements of the second submatrix in any submatrix combination through the second vector register includes: Arrange the second submatrix in any of the submatrix combinations in a second direction-based order to obtain a sixth submatrix of the submatrix combination; All elements of the sixth submatrix in any of the submatrix combinations are read in sequence through the second vector register.

7. The method according to claim 6, characterized in that Determining a matrix operation result corresponding to any of the sub-matrix combinations according to the elements of the first vector register and the elements of the second vector register includes: For each target element combination, determine a matrix operator result corresponding to the target element combination according to the target element combination and all elements of the sixth submatrix; The matrix operation result corresponding to any of the sub-matrix combinations is determined according to the matrix operation sub-results.

8. The method according to any one of claims 1 to 7, characterized in that: Determining the matrix multiplication result of the first matrix and the second matrix according to the matrix operation result corresponding to each sub-matrix combination includes: For any of the sub-matrix combinations, determining a target position corresponding to the sub-matrix combination according to a position of the first sub-matrix included in the sub-matrix combination in the first matrix and a position of the second sub-matrix included in the sub-matrix combination in the second matrix; The matrix multiplication result is determined according to the matrix operation results corresponding to each of the sub-matrix combinations and the target positions corresponding to each of the sub-matrix combinations.

9. A device for determining the result of a matrix multiplication operation, characterized in that: include: A matrix acquisition unit, used to acquire a first matrix and a second matrix; a matrix determination unit, configured to determine one or more submatrix combinations according to the first matrix and the second matrix, wherein one submatrix combination includes a first submatrix corresponding to the first matrix and a second submatrix corresponding to the second matrix; a plurality of the first submatrices are obtained by dividing the first matrix into blocks according to the number of storable elements of the first vector register, and a plurality of the second submatrices are obtained by dividing the second matrix into blocks according to the number of storable elements of the second vector register; A first determining unit, configured to determine a matrix operation result corresponding to each of the sub-matrix combinations by using the first vector register and the second vector register; The second determining unit is used to determine the matrix multiplication result of the first matrix and the second matrix according to the matrix operation result corresponding to each sub-matrix combination.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the processor implements the steps of the method for determining a matrix multiplication result according to any one of claims 1 to 8.

11. A computer program product, characterized in that When the computer program product is executed by a processor, the steps of the method for determining a matrix multiplication result according to any one of claims 1 to 8 are implemented.

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