Time sequence scene-oriented chip architecture level power consumption evaluation method

Abstract

The invention provides a time sequence scene-oriented chip architecture level power consumption evaluation method, which comprises the following steps of: S100, generating an original data set by utilizing micro-architecture design parameters of a chip to be designed and adding simulation excitation; removing redundant data in the original data set, merging to obtain a preprocessed data set, and training a preset LSTM-based power consumption prediction model; and adjusting the micro-architecture design parameters and the ESL model, regenerating input features, and inputting the input features into the trained LSTM-based power consumption prediction model to obtain a power consumption prediction result. According to the method, the multi-dimensional features are introduced, the influence of different workloads and architecture configurations on the power consumption is comprehensively considered, and the time sequence processing capability of the LSTM model is utilized, so that the time dependency relationship in power consumption fluctuation can be effectively captured, and the power consumption prediction precision is remarkably improved, especially in a dynamically changing time sequence scene.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and particularly relates to a chip architecture-level power consumption evaluation method for time series scenarios. Background Art

[0002] With the increasing complexity of the functions and scales of network processing and artificial intelligence (AI) chips, power consumption has become a key constraint in future processor architecture design. Especially in high-performance computing and data-intensive tasks, power consumption not only directly affects the energy efficiency performance of the chip, but also relates to the heat dissipation, stability of the system and the sustainability of applications. Therefore, in the early stage of chip design, especially at the high-level abstraction stage, accurately quantifying the processor power consumption becomes particularly important. Especially in working scenarios with significant time series feature dependencies such as network packet switching, fully exploring and utilizing time series features can significantly improve the accuracy of power consumption prediction.

[0003] In 2009, Hewlett-Packard Laboratories proposed an analytical model for power consumption, area, and timing of multi-core and many-core architectures - McPAT. This analytical model is based on the CMOS transistor power consumption theoretical equation P = αCV dd ΔVf clk to construct the model. As Figure 2 shown, McPAT uses XML as the input interface to specify the configuration information of the multi-core architecture and the activity statistics generated by the performance simulator. Then, through the XML interface, the chip structure is determined to implement an internal chip representation for power consumption, area, and timing analysis. Finally, power consumption calculation is performed through the model established by McPAT. As Figure 3 shown, it is the modeling method used by McPAT, which adopts a hierarchical modeling method. That is, after obtaining the internal chip representation, the chip is divided into architecture-level, circuit-level, and process-level components. Then, at the process level, by defining the power consumption of logic gates and traces, the power consumption of the circuit level and the architecture level is deduced backwards. McPAT conducts accuracy tests on multiple processor architectures, and the relative error is between 10% and 27%.

[0004] In 2019, ZHOU et al. proposed a new machine learning-based architecture-level power consumption modeling framework PRIMAL, which can perform fast and accurate power consumption estimation at the RTL level or the SystemC level. As Figure 3As shown, it is the modeling and workflow of PRIMAL. The entire modeling process can also be divided into a characterization stage and a modeling stage. The characterization stage is the core content of this paper and can be roughly divided into: (1) feature encoding; (2) encoding mapping. Feature encoding is used to characterize the signal information of the circuit, and encoding mapping is used to characterize the circuit structure information. The constructed features are used for the training and prediction of a convolutional neural network (CNN). Finally, in the per-cycle power consumption estimation of the RISC-V processor core, a 35-fold acceleration (compared to the average power consumption analysis of RTL under PTPX) and an error of 5.2% are achieved. In the case of the NoC router, using the cycle approximation trace information of SystemC simulation, an error of 4.5% can be achieved.

[0005] In 2022, Yu et al. proposed a microarchitecture power consumption modeling framework called McPAT-Calib, which combines McPAT and machine learning calibration methods and can quickly and accurately estimate the power consumption of different benchmarks under different CPU configurations. As Figure 4 shown, it is the overall modeling process of McPAT-Calib. First, Yu et al. extended the process node of McPAT to 7nm. Then, a wide range of feature sources, namely microarchitecture design parameters, statistical information of performance simulators, prediction results of McPAT, etc., were selected as the inputs of the machine learning model. Since there may be a collinearity problem among the selected features, they proposed an automatic feature selection algorithm to improve the quality of the features. Yu et al. also used an artificial intelligence sampling method to enhance the representativeness of the samples, reduce the modeling cost, and improve the modeling speed. Finally, the XGBoost model was used to handle the non-linearity between the features and the power consumption labels. McPAT-Calib used 15 different BOOM configurations and 80 different benchmark tests for accuracy evaluation, and its accuracy was approximately between 3% and 6%.

[0006] Regarding the above architecture-level power models, there are the following limitations:

[0007] 1. The traditional analytical model McPAT is only accurate for modeling relatively regular circuits, such as RAM. For circuits whose specific implementation methods are unknown, McPAT may lead to a decrease in accuracy due to omitting many modeling details.

[0008] 2. McPAT uses an empirical model for highly customized circuits, that is, through a large number of power consumption analyses using the EDA tool chain and then curve fitting. This method has too high a modeling cost, and the model may not be accurate.

[0009] 3. PRIMAL does achieve good prediction accuracy and speed. However, due to the uniqueness of its feature construction method, PRIMAL is more suitable for RTL modeling. Moreover, PRIMAL does not fully consider the impact of different architecture configurations on power consumption.

[0010] 4. McPAT-Calib combines McPAT and machine learning calibration methods and can estimate the power consumption of different workloads under different CPU configurations. However, due to the large errors in McPAT itself, the feature information extracted from it cannot guarantee accuracy.

[0011] Existing methods have not been specifically optimized for chip power consumption prediction in time series scenarios, so it is difficult to directly apply them to complex time series power consumption analysis tasks. Summary of the Invention

[0012] To solve the above problems existing in the prior art, the present invention provides a chip architecture-level power consumption evaluation method for time series scenarios. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0013] A chip architecture-level power consumption evaluation method for time series scenarios includes:

[0014] S100, using the microarchitecture design parameters of the chip to be designed, and by adding simulation stimuli to the ESL model and the gate-level netlist, generating an original data set; the ESL model is the simulation model of the chip to be designed; the gate-level netlist represents the circuit structure of the chip to be designed;

[0015] S200, removing redundant data in the original data set, and then merging the data in the original data set according to the time steps of the LSTM to obtain a preprocessed data set;

[0016] S300, using the preprocessed data set to train a preset LSTM-based power consumption prediction model to obtain a trained LSTM-based power consumption prediction model;

[0017] S400, adjusting the microarchitecture design parameters and the ESL model, and using the adjusted microarchitecture design parameters and ESL model to regenerate input features, and inputting the input features into the trained LSTM-based power consumption prediction model to obtain a power consumption prediction result.

[0018] Advantageous Effects:

[0019] 1. The present invention takes into account both the impact of different workloads on power consumption and the impact of different architecture configurations on power consumption. The statistical information of the ESL model can characterize the impact of different workloads on circuit power consumption, while the micro-architecture design parameters are used to characterize the impact of different architecture configurations on circuit power consumption. At the architecture level, both the statistical information of the performance simulator and the micro-architecture design parameters are used as features for model training.

[0020] 2. The present invention uses a feature selection algorithm to reduce the data volume of the original dataset, thereby reducing the complexity of the model, and improving the training speed and accuracy of the model. The present invention uses a feature selection method based on the L2 penalty term, which can be embedded in the model optimization process, effectively alleviating the problem of multicollinearity between features, and retaining features that make a subtle contribution to the model performance.

[0021] 3. The present invention uses LSTM to process time series-related scenarios, thereby improving the prediction accuracy of the model. The power consumption evaluation method of the present invention is designed specifically for time series-related scenarios. Therefore, by extracting features with time series characteristics to construct a dataset, and using the LSTM model for training and prediction, the power consumption prediction accuracy of chips with time series scenarios can be effectively improved.

[0022] The present invention will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0023] Figures 1 - 4 is a schematic diagram of the prior art solution;

[0024] Figure 5 is a flowchart of a chip architecture-level power consumption evaluation method for time series scenarios provided by the present invention;

[0025] Figure 6 is a schematic diagram of the implementation process of the chip architecture-level power consumption evaluation method for time series scenarios provided by the present invention;

[0026] Figure 7 is a schematic diagram of the structure of a power consumption prediction model based on LSTM provided by the present invention;

[0027] Figure 8 is a schematic diagram of the structure of the Crossbar circuit provided by the present invention;

[0028] Figure 9 is a schematic diagram of the prediction error of the power consumption prediction model provided by the present invention. Detailed Embodiments

[0029] The present invention will be further described in detail below with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0030] Combined with Figure 5 and Figure 6 , the present invention provides a chip architecture-level power consumption evaluation method for time series scenarios, including:

[0031] S100, using the microarchitecture design parameters of the chip to be designed, and by adding simulation stimuli to the ESL model and the gate-level netlist, generating an original dataset; the ESL model is the simulation model of the chip to be designed; the gate-level netlist represents the circuit structure of the chip to be designed;

[0032] Among them, the microarchitecture design parameters include frequency, the number of storage units, and hardware algorithms.

[0033] In a specific embodiment of the present invention, S100 includes:

[0034] S110, adjusting the ESL model and the gate-level netlist according to the microarchitecture design parameters, and sending the simulation stimuli into the adjusted ESL model and gate-level netlist to obtain the output simulation results;

[0035] Among them, the simulation results output by the ESL model include the Hamming distance of key signals, the data depth information of storage units, the delay information of input / output ports, and the throughput rate of input / output port signals.

[0036] S120, taking the simulation results output by the ESL model and the architecture design parameters as original features, and taking the simulation results output by the gate-level netlist as the labels of the original features;

[0037] S130, corresponding the original features and labels one by one to form original data, and combining all the original data to form an original dataset.

[0038] Refer to Figure 6 , the original dataset of this application can be divided into two parts. The first part is feature data, that is, the input data of the machine learning model; the second part is label data, that is, the power consumption data used to correct the power consumption model. The acquisition of label data is similar to other modeling frameworks, mainly relying on EDA tools, and the process is relatively fixed.

[0039] The input data of this application mainly consists of two parts: the statistical information of the performance simulator and the microarchitecture design parameters. The statistical information of the performance simulator (ESL model) can characterize the impact of different workloads on the circuit power consumption. Such features have significant time series characteristics, which help the model to more accurately fit the power consumption, thereby improving the prediction accuracy. The microarchitecture design parameters are used to characterize the impact of different architecture configurations on the circuit power consumption. The specific features selected in this application are shown in Table 1:

[0040] Table 1 Machine learning input features for model training

[0041]

[0042] (1) Critical signal Hamming distance: The Hamming distance can be used to quantify the amplitude of signal changes. The greater the difference between signals, it may mean more flips and higher power consumption. Therefore, this feature can reflect the severity of signal changes inside the chip and directly affect power consumption. Also, the Hamming distance changes over time, so it has corresponding changes at each moment and has obvious time series characteristics. The calculation of the Hamming distance is shown in formula (1), where X i and Y i represent signal values, and N represents the signal bit width.

[0043]

[0044] (2) Data depth information of storage units: The data depth of storage units determines the amount of data to be processed in each access or operation. A larger data depth usually means more capacitors need to be charged and discharged, thus affecting power consumption. Also, the data depth of storage units may change at different times, especially during multiple read and write processes. For example, the access pattern of the cache changes with the execution stage of the program or data access changes, so it also has time series characteristics.

[0045] (3) Delay information of input and output ports: Delay information is crucial for power consumption prediction because longer delays affect the state holding and waiting time in each processing stage, thus affecting power consumption. Also, the delay changes dynamically over time. Especially during data transmission and processing, the reception delay of the input port and the transmission delay of the output port fluctuate with the change of the system state and have obvious time series characteristics.

[0046] (4) Throughput rate of input and output port signals: The throughput rate is closely related to the chip's workload, bandwidth requirements, and data transmission efficiency. A higher throughput rate usually means more data needs to be transmitted and processed, which will directly increase power consumption. The change in the throughput rate can also reflect the change in the system's load and thus affect power consumption. The throughput rate changes over time and usually has different values in different operation cycles or clock cycles. For example, the data flow may be higher at some moments and lower at other moments, and this volatility gives it obvious time series characteristics.

[0047] (5) Frequency: The higher the frequency, the shorter the time required for the chip to execute each operation. However, it also means that more energy is needed for signal switching and state updating per second, thus increasing power consumption. Usually, power consumption is proportional to the square of the frequency. Therefore, increasing the frequency will lead to a significant increase in power consumption.

[0048] (6) The number of storage units. The more storage units there are, the larger the area of the module. Under the same load condition, the power consumption generated is also more.

[0049] (7) Hardware algorithms: The impact of different hardware algorithms on power consumption depends on their computational complexity and execution methods. More complex algorithms require more computing resources and data transmission, which will result in higher power consumption.

[0050] In summary, the features extracted from the performance emulator can reflect the impact of different workloads on circuit power consumption, and they all change over time, being able to reveal the changing patterns in the time series. The features extracted from the microarchitecture design parameters are mainly used to capture the non-linear relationship between different circuit configurations and power consumption. Finally, the generated dataset format is shown in Table 2. Among them, T1 to TM are the number of samples, Signal1_hd to Hardware_algorithm are the feature data under this module, P1 to PM are the power consumption labels at the corresponding cycle level, and HD, MD, HA are the specific values corresponding to different types of features.

[0051] Table 2 Explanation of the format of the machine learning dataset

[0052] Samples Signal1_hd Memory_depth … Hardware_algorithm Power T1 HD(11) MD(12) … HA(1N) P1 T2 HD(21) MD(22) … HA(2N) P2 … … … … … … TM HD(M1) MD(M2) … HA(MN) PM

[0053] S200, remove the redundant data in the original dataset, and then merge the data in the original dataset according to the time steps of LSTM to obtain the preprocessed dataset;

[0054] In a specific embodiment of the present invention, S200 includes:

[0055] S210, use the ridge regression model to remove the redundant data in the original dataset to obtain a de-redundant dataset;

[0056] Feature selection is an important step in data preprocessing, which can significantly reduce the model complexity and improve the training efficiency. Feature selection methods are usually divided into wrapper methods, filtering methods, and embedding methods. The present invention adopts a feature selection method based on the L2 penalty term, that is, a penalty term is added to the optimizer, making the weight iteration process tend to the 0 value. After training is completed, the features with non-zero weights are retained, so as to achieve the purpose of feature selection.

[0057] The principle of feature selection based on the L2 penalty term is as follows:

[0058] Use the gradient algorithm to update the weights, and formula (2) is the method for updating its weights. Among them, θ is the weight vector to be iterated, t represents the number of iterations, η represents the learning rate, and J(θ) is the loss error. Then, formula (3) can be obtained by adding a penalty term based on L2 to the optimizer. Among them, λ represents the regularization coefficient.

[0059]

[0060] It is not difficult to see from formula (3) that each time the L2 penalty term also pulls the weights towards zero, making the weight iteration process tend towards zero, thus retaining the features with non-zero weights. And the farther the weights are from zero, the greater the penalty of the L2 penalty term; when the weights approach zero, the strength of the L2 penalty term weakens. Therefore, under the influence of the L2 penalty term, the parameters will be more balanced and the model will be more stable.

[0061] In a specific embodiment of the present invention, S210 includes:

[0062] S211, at the t-th time, calculate the weight value of the t-th ridge regression model using the loss error of the (t - 1)-th time, and update the (t - 1)-th ridge regression model with this weight value and use it as the t-th ridge regression model;

[0063] Assume that the Hamming distance of the key signal, the data depth information of the storage unit, the delay information of the input and output ports, and the throughput rate dimension of the input and output port signals are all 1. Then, a data set with a feature dimension of 4 can be constructed. Then, use the feature selection method (ridge regression) based on the L2 penalty term for feature selection. The number of iterations t, such as 20 times; the learning rate η, such as 0.1, can be set before feature selection.

[0064] The mathematical expression of ridge regression is as follows:

[0065] y = b + w1x1 + w2x2 + w3x3 + w4x4 #(4)

[0066] Among them, y represents the predicted value, x1 to x4 represent the above four input features, w1 to w4 represent the weights corresponding to the 4 features, and b represents the bias term or intercept.

[0067] In this embodiment, the ridge regression model is adopted, and its weight value refers to formula (3), which is expressed as:

[0068]

[0069] In the formula, θ (t) is the weight value of the t-th ridge regression model, η is the learning rate, J(θ (t-1) ) is the loss error of the (t - 1)-th time, λ is the regularization coefficient, and θ (t-1) is the weight of the (t - 1)-th ridge regression model.

[0070] S212, at the t-th time, train the t-th ridge regression model with the merged data set to obtain the predicted value corresponding to each input feature at the t-th time;

[0071] S213. Calculate the loss error at the t-th time by using the predicted value corresponding to each input feature and the true value corresponding to the input feature at the t-th time.

[0072] S214. Repeat S211 to S213 until the maximum number of iterations is reached or the loss error meets the requirements, and obtain the trained ridge regression model.

[0073] S215. Check the weights of the trained ridge regression model, and remove the input features corresponding to the weights of 0 from the original data set to obtain a redundant-reduced data set.

[0074] After the ridge regression model is trained, check the weights of the ridge regression model. When the weight corresponding to the input feature is 0, delete the feature. For example, if the weights [w1, w2, w3, w4] of the ridge regression model are [0, 0.5, 0, 0.3], then the Hamming distance of the key signal and the delay information of the input and output ports are deleted.

[0075] This embodiment uses a feature selection algorithm at the architecture level, effectively reducing the complexity of the model, and improving the model training speed and prediction accuracy.

[0076] S220. Merge the features in the redundant-reduced data set according to the time steps of the LSTM to obtain a preprocessed data set.

[0077] By observing the relationship between the data set and the power consumption and the circuit state, it is not difficult to find that:

[0078] In the data set samples, two special situations may occur: 1) The features are the same but the labels are different; 2) The features are different but the labels are the same. This phenomenon does not stem from the problem of the samples themselves, but because the factors affecting power consumption are very diverse. Since this application cannot take all possible factors affecting power consumption changes as features into the model, this situation will occur. If this phenomenon is not specially processed, it may have a negative impact on the accuracy of the model.

[0079] For scenarios with time series characteristics, the power consumption fluctuation of the circuit within a time window is closely related to the activities in the previous few time periods.

[0080] Based on the above two situations, the present invention selects to use LSTM as the final power consumption prediction model. The specific reasons are as follows:

[0081] Before using LSTM, it is necessary to merge the samples in the original data set according to the time steps of LSTM to obtain a preprocessed data set. The input data in this data set is as follows Figure 7As shown, it is a two-dimensional data of (n, m), where n represents the sequence length (i.e., time step), and m represents the feature dimension. This LSTM-based processing method can effectively eliminate the two situations where the features are the same but the labels are different, and the features are different but the labels are the same. LSTM is very suitable for dealing with problems with time series characteristics because it can effectively capture and model the long-term dependencies in the sequence.

[0082] The method of this embodiment for eliminating the two situations where the features are the same but the labels are different, and the features are different but the labels are the same. Based on the time steps of LSTM, the original feature data is constructed into the two-dimensional time series data required by LSTM, effectively eliminating the two situations where the features are the same but the labels are different, and the features are different but the labels are the same.

[0083] S300, training a preset LSTM-based power consumption prediction model using the preprocessed data set to obtain a trained LSTM-based power consumption prediction model;

[0084] In a specific embodiment of the present invention, S300 includes:

[0085] S310, in the current training round, inputting the samples in the preprocessed data set into the LSTM-based power consumption prediction model trained in the previous training round to obtain the power consumption prediction results corresponding to each input feature in the current round;

[0086] Wherein, the LSTM-based power consumption prediction model includes an LSTM, two fully connected layers, and an output layer connected in sequence;

[0087] The structure of the LSTM-based power consumption prediction model constructed by the present invention is as Figure 7 shown. The model takes two-dimensional time series data with the shape of (sequence length, feature dimension) as input. First, the input data passes through an LSTM layer with 32 hidden units to extract the dynamic features of the time series and generate a feature vector of size 32. Subsequently, this feature vector is sequentially passed to two fully connected layers, which respectively contain 16 and 8 neurons, and both use the ReLU activation function to further extract and compress the features. Finally, a scalar value is output through a fully connected layer with a linear activation as the power consumption prediction result.

[0088] The structural parameters of the LSTM-based power consumption prediction model are shown in Table 3. Among them, the sequence length of the LSTM input data is 48, and this setting is closely related to the chip data transmission law to be predicted in this application. The total number of parameters of the model is 128m + 4897, where m represents the feature dimension, and the feature dimensions of different modules are different.

[0089] Table 3 Detailed configuration of the LSTM power consumption model

[0090]

[0091]

[0092] In this step, at the current training round, the input features in the preprocessed dataset are input into the LSTM included in the power consumption prediction model constructed by the LSTM trained in the previous training round to obtain the feature vectors output by all LSTMs; the feature vectors are passed to two fully connected layers for feature extraction and compression, and finally the power consumption prediction results corresponding to each input feature in the current training round are output through the output layer.

[0093] S320. Use the power consumption prediction results corresponding to each input feature in the training round and the labels corresponding to the input features to calculate the loss function of the current training round.

[0094] S330. Repeat S310 to S320 until the maximum number of iterations is reached or the loss function meets the requirements, and obtain the trained power consumption prediction model based on LSTM.

[0095] S400. Adjust the microarchitecture design parameters and the ESL model, and use the adjusted microarchitecture design parameters and ESL model to regenerate the input features, and input the input features into the trained power consumption prediction model based on LSTM to obtain the power consumption prediction results.

[0096] The process of regenerating the input features in this embodiment is the same as the process of generating the features in the original dataset and then preprocessing, which will not be elaborated here.

[0097] In a specific embodiment of the present invention, after S400, the chip architecture-level power consumption evaluation method for the time series scenario further includes:

[0098] Use the evaluation index MAPE to evaluate the power consumption prediction results of S400.

[0099] This application selects the Crossbar circuit in the network switching chip for experiments. The crossbar network is used to implement the temporary storage of data frames and send them to the destination port. Horizontally, the data frames sent from the sending bus are moved to the corresponding cross-node buffer area according to their destination port list and unicast / multicast identification to implement the temporary storage of data frames; vertically, through column selection, a node is selected from different cross-nodes sending to the same destination port to send the data frame.

[0100] The overall block diagram of the crossbar network is as Figure 8As shown, each Crossbar cross-node is equipped with two 2KB RAMs. These two RAMs are controlled by ping-pong operation, so that a cross-node can receive new data frames while outputting, improving the bus utilization efficiency and externally appearing as a single RAM. To avoid network congestion caused by multicast blocking, four 2KB RAMs can be set in a cross-node, with two for unicast storage and the other two for multicast storage.

[0101] This application extracts feature data from the performance simulator and microarchitecture design parameters, specifically including the following 8 feature types: Hamming distance of the Crossbar output port, Hamming distance of the RAM input signal, depth information of the RAM, output port delay, output port throughput, number of RAMs, clock frequency, and column selection algorithm. Through the EDA toolchain, power consumption simulation is performed on the Crossbar to obtain label data, thereby constructing a dataset.

[0102] Take the feature selection based on the L2 penalty term as the feature selection algorithm in this embodiment.

[0103] Convert the original dataset into the input data shape required by LSTM, that is, two-dimensional time series data of (48, 128), where 48 represents the sequence length of LSTM, and 128 is the sum of all dimensions of the 8 feature types mentioned in (1).

[0104] When training the LSTM, feature selection is automatically performed during the training process through the feature selection algorithm based on the L2 penalty term.

[0105] When the model training is completed, power consumption prediction can be performed on new input features. The evaluation metric used in this application is MAPE (Mean Absolute Percentage Error). It represents the average absolute percentage error between the predicted value and the true value. A smaller MAPE value means a smaller average relative error between the predicted value and the true value, indicating better prediction ability of the model. Where n represents the number of samples; y i represents the i-th actual power consumption value; represents the i-th predicted power consumption value; is the average value of the true values.

[0106]

[0107] As Figure 9 shown, Figure 9 This application selects the error situation between the true value and the predicted value in 500 cycles. The experimental results show that the prediction error MAPE of this application can reach 2.151%, indicating that the method of this application has high prediction accuracy.

[0108] The present invention proposes a chip architecture-level power consumption evaluation method for time series scenarios. In S100, using the microarchitecture design parameters of the chip to be designed and adding simulation stimuli thereto, an original data set is generated; redundant data in the original data set is removed and then merged to obtain a preprocessed data set, and then a preset LSTM-based power consumption prediction model is trained; the microarchitecture design parameters and the ESL model are adjusted, and input features are regenerated, and the input features are input into the trained LSTM-based power consumption prediction model to obtain a power consumption prediction result. By introducing multi-dimensional features, the present invention comprehensively considers the influence of different workloads and architecture configurations on power consumption, and utilizes the time series processing ability of the LSTM model to effectively capture the time-dependent relationship in power consumption fluctuations, thereby significantly improving the power consumption prediction accuracy, especially in dynamically changing time series scenarios.

[0109] Although the present application has been described in connection with various embodiments herein, however, in implementing the claimed present application, those skilled in the art can understand and realize other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality of cases.

[0110] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A chip architecture-level power consumption evaluation method for time series scenarios, characterized in that: include: S100, uses the microarchitecture design parameters of the chip to be designed and generates the original data set by adding simulation stimulus to the ESL model and gate-level netlist; The ESL model is a simulation model of the chip to be designed; the gate-level netlist represents the circuit structure of the chip to be designed; S200, removing redundant data in the original data set, and then merging the data in the original data set according to the time step of LSTM to obtain a preprocessed data set; S300, using the preprocessed data set to train a preset LSTM-based power consumption prediction model to obtain a trained LSTM-based power consumption prediction model; S400, adjusting the micro-architecture design parameters and the ESL model, and regenerating input features using the adjusted micro-architecture design parameters and the ESL model, and inputting the input features into a trained LSTM-based power consumption prediction model to obtain a power consumption prediction result.

2. The chip architecture level power consumption evaluation method for time series scenarios according to claim 1 is characterized in that: S100 includes: S110, adjusting the ESL model and the gate-level netlist according to the micro-architecture design parameters, and sending the simulation stimulus to the adjusted ESL model and the gate-level netlist to obtain an output simulation result; S120, using the simulation results output by the ESL model and the architecture design parameters as original features, and using the simulation results output by the gate-level netlist as labels of the original features; S130, original features and labels are matched one by one to form original data, and all original data are combined into an original data set.

3. The chip architecture level power consumption evaluation method for time series scenarios according to claim 2 is characterized in that: The micro-architecture design parameters include frequency, number of memory cells and hardware algorithms.

4. The chip architecture level power consumption evaluation method for time series scenarios according to claim 2 is characterized in that: The simulation results output by the ESL model include the Hamming distance of key signals, data depth information of storage units, delay information of input and output ports, and throughput of input and output port signals.

5. The chip architecture level power consumption evaluation method for time series scenarios according to claim 1 is characterized in that: S200 includes: S210, using a ridge regression model to remove redundant data in the original data set to obtain a de-redundant data set; S220, merging the features in the de-redundant data set according to the time step of LSTM to obtain a preprocessed data set.

6. The chip architecture level power consumption evaluation method for time series scenarios according to claim 5 is characterized in that: S210 includes: S211, at the tth time, using the loss error of the t-1th time to calculate the weight value of the tth ridge regression model, and using the weight value to update the t-1th ridge regression model and use it as the tth ridge regression model; S212, at the tth time, training the tth ridge regression model with the merged data set to obtain the prediction value corresponding to each input feature at the tth time; S213, calculating the t-th loss error using the predicted value corresponding to each input feature at the t-th time and the true value corresponding to the input feature; S214, repeat S211 to S213 until the maximum number of iterations is reached or the loss error meets the requirements, and a trained ridge regression model is obtained; S215, checking the weights of the trained ridge regression model, and removing the input features corresponding to the weights of 0 from the original data set to obtain a de-redundant data set.

7. The chip architecture level power consumption evaluation method for time series scenarios according to claim 6 is characterized in that: The weight value in S221 is expressed by the formula: In the formula, θ (t) is the weight value of the t-th ridge regression model, η is the learning rate, J(θ (t-1) ) is the loss error of the t-1th time, λ is the regularization coefficient, θ (t-1) is the weight of the t-1th ridge regression model.

8. The chip architecture level power consumption evaluation method for time series scenarios according to claim 1 is characterized in that: S300 includes: S310, in the current training round, input the samples in the preprocessed data set into the LSTM power consumption prediction model trained in the previous training round to obtain the power consumption prediction result corresponding to each input feature in the current round; The LSTM-based power consumption prediction model includes sequentially connected LSTMs, two-level fully connected layers, and an output layer; S320, calculating the loss function of the current training round using the power consumption prediction result corresponding to each input feature of the current training round and the label corresponding to the input feature; S330, repeat S310 to S320 until the maximum number of iterations is reached or the loss function meets the requirements, and a trained LSTM-based power consumption prediction model is obtained.

9. The chip architecture level power consumption evaluation method for time series scenarios according to claim 8, characterized in that: S310 includes: In the current training round, the input features in the preprocessed data set are input into the LSTM included in the LSTM trained in the previous training round to build the power consumption prediction model, and the feature vectors of all LSTM outputs are obtained; the feature vectors are passed to two fully connected layers for feature extraction and compression, and finally the power consumption prediction results corresponding to each input feature of the current training round are output through the output layer.

10. The chip architecture level power consumption evaluation method for time series scenarios according to claim 1, characterized in that: After S400, the chip architecture-level power consumption evaluation method for time series scenarios further includes: The evaluation index MAPE is used to evaluate the power consumption prediction results of S400.

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