Clock system, chip system, design method, related device and design equipment

Abstract

The embodiment of the invention provides a clock system, a chip system, a design method, a related device and design equipment, and the clock system comprises a clock grid located on a first chip, the clock grid at least comprises an encrypted clock grid region, the encrypted clock grid region corresponds to a chip projection region of a second chip on the first chip, and the encrypted clock grid region corresponds to the chip projection region of the second chip on the first chip. The clock grid density of the encrypted clock grid area is higher than the clock grid density when the clock grid is initially constructed; wherein the first metal wire in the encrypted clock grid area is provided with a plurality of first contact points, and the first metal wire is used for connecting a clock load of the first chip; and the plurality of second contact points are located on the second chip, the second contact points are connected with the first contact points to obtain the clock signals transmitted by the first contact points, and the second contact points are used for being connected with a clock load of the second chip. According to the embodiment of the invention, the design complexity of the clock system can be reduced, and the performance of the clock system is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular, to a clock system, a chip system, a design method, related devices, and a design device. Background Art

[0002] With the development of integrated circuits towards miniaturization, high performance, and low power consumption, the planar 2D (two-dimensional) packaging technology has gradually become difficult to meet the requirements. The 3D (three-dimensional) packaging technology, with its integration advantages in the vertical direction, has become an important development direction in the field of semiconductor packaging. Specifically, the 3D packaging technology stacks multiple chips in the vertical direction to reduce the interconnection length between chips, thereby reducing the delay of signal transmission, and further improving the data transmission rate and the overall performance of the chips.

[0003] A chip system using the 3D packaging technology includes multiple chips stacked in the vertical direction. To ensure that the chips can work in the correct timing, it is necessary to design the clock system of the chip system to provide and distribute clock signals by the clock system. Therefore, the design of the clock system is crucial for the chip system and directly affects the stability and performance of the chip system.

[0004] Since there are multiple chips in the chip system using the 3D packaging technology, the design of the clock system needs to consider the cross-chip clock signal transmission. In this context, how to reduce the design complexity of the clock system and improve the performance of the clock system has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] In view of this, the embodiments of the present application provide a clock system, a chip system, a design method, related devices, and a design device to reduce the design complexity of the clock system and improve the performance of the clock system.

[0006] To achieve the above object, the embodiments of the present application provide the following technical solutions.

[0007] In a first aspect, the embodiments of the present application provide a clock system applied to a chip system. The chip system includes multiple chips stacked on top of each other. The multiple chips include a first chip and at least one second chip, and the chip area of the second chip is less than or equal to that of the first chip. The clock system includes:

[0008] A clock grid located in the first chip, the clock grid at least includes an encrypted clock grid area, the encrypted clock grid area corresponds to the chip projection area of the second chip in the first chip, and the clock grid density of the encrypted clock grid area is higher than the clock grid density when the clock grid is initially constructed; wherein, a plurality of first contact points are provided on the first metal wire of the encrypted clock grid area, and the first metal wire is used to connect the clock load of the first chip;

[0009] A plurality of second contact points located in the second chip, the second contact points are connected to the first contact points to obtain the clock signal transmitted by the first contact points, and the second contact points are used to connect the clock load of the second chip.

[0010] In a second aspect, an embodiment of the present application provides a chip system, including:

[0011] A plurality of stacked chips, the plurality of chips include a first chip and at least one second chip, and the chip area of the second chip is less than or equal to that of the first chip;

[0012] And, the clock system as described in the first aspect above.

[0013] In a third aspect, an embodiment of the present application provides a design method, including:

[0014] Determine the first chip and at least one second chip among the plurality of stacked chips, wherein the chip area of the second chip is less than or equal to that of the first chip;

[0015] Initially construct a clock grid in the first chip;

[0016] Determine the chip projection area of the second chip corresponding to the first chip;

[0017] Increase the density of the clock grid in the chip projection area to form an encrypted clock grid area;

[0018] For the first metal wire in the encrypted clock grid area, set first contact points for transmitting clock signals to the second chip to obtain a plurality of first contact points in the encrypted clock grid area; the first metal wire is used to connect the clock load of the first chip;

[0019] Determine the second contact points corresponding to the first contact points in the second chip in the encrypted clock grid area to obtain a plurality of second contact points in the second chip; the second contact points are used to connect the clock load of the second chip;

[0020] Connect the first contact points and the second contact points.

[0021] In a fourth aspect, an embodiment of the present application provides a design device, including:

[0022] A chip determination module, configured to determine a first chip and at least one second chip among a plurality of stacked chips, where the chip area of the second chip is less than or equal to that of the first chip;

[0023] A preliminary clock grid construction module, configured to preliminarily construct a clock grid on the first chip;

[0024] A chip projection area determination module, configured to determine the chip projection area corresponding to the second chip on the first chip;

[0025] A density increase module, configured to increase the density of the clock grid within the chip projection area to form an encrypted clock grid area;

[0026] A first contact point determination module, configured to set a first contact point for the first metal wire within the encrypted clock grid area for transmitting a clock signal to the second chip, obtaining a plurality of first contact points within the encrypted clock grid area; the first metal wire is used to connect the clock load of the first chip;

[0027] A second contact point determination module, configured to determine the second contact points corresponding to the first contact points within the encrypted clock grid area on the second chip, obtaining a plurality of second contact points within the second chip; the second contact points are used to connect the clock load of the second chip;

[0028] A connection configuration module, configured to connect the first contact points to the second contact points.

[0029] In a fifth aspect, an embodiment of the present application provides a design device, including a memory and a processor, where the memory stores computer execution instructions, and the processor calls the computer execution instructions to execute the design method as described in the third aspect above.

[0030] In a sixth aspect, an embodiment of the present application provides a storage medium storing computer execution instructions, and when the computer execution instructions are executed, the design method as described in the third aspect above is implemented.

[0031] In a seventh aspect, an embodiment of the present application provides a computer program product, including computer execution instructions, and when the computer execution instructions are executed, the design method as described in the third aspect above is implemented.

[0032] The clock system provided by the embodiments of the present application is applied to a chip system having multiple chips stacked on top of each other, and the chip area of the second chip among the multiple chips is less than or equal to that of the first chip; thus, the clock grid of the clock system is located on the first chip, and the clock grid area corresponding to the chip projection area of the first chip for the second chip is an encrypted clock grid area where the clock grid density is increased, that is, the density of the clock grid corresponding to the chip projection area of the first chip for the second chip is increased; furthermore, a plurality of first contact points are provided on the first metal wire connecting the clock load in the encrypted clock grid area, and the second chip is provided with second contact points corresponding to the first contact points. Thus, by connecting the second contact points to the first contact points, the second contact points can obtain the clock signals transmitted by the first contact points and transmit the clock signals to the clock load of the second chip connected to the second contact points. That is to say, in the second chip, the second contact points are responsible for distributing the clock signals transmitted from the first contact points to the clock load of the second chip to enable the second chip to share the clock signals provided by the clock grid of the first chip. Therefore, the clock system provided by the embodiments of the present application can greatly simplify the design complexity of the clock system and improve the performance of the clock system by increasing the density design of the clock grid in the chip projection area of the second chip in the first chip, and using the first contact points of the first metal wire in the encrypted clock grid area with increased density and the second contact points corresponding to the second chip for cross-chip transmission of clock signals.

[0033] Specifically, the second chip realizes sharing the clock signals provided by the clock grid of the first chip by setting second contact points connected to the first contact points, without the need to set a complex clock grid in the second chip, which can greatly simplify the design of the clock grid; moreover, the clock signals are transmitted between the first chip and the second chip through the connection of the first contact points and the second contact points. The path for the contact points to transmit the clock signals is short and the loss is low, ensuring the integrity and correct timing of the cross-chip transmission of clock signals and improving the performance of the clock system. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0035] Figure 1 It is an example diagram of a 3D packaging structure.

[0036] Figure 2A It is an example diagram of a clock grid.

[0037] Figure 2BIt is an example diagram of the clock system of the chip.

[0038] Figure 3A It is an example diagram of sharing clock signals across chips.

[0039] Figure 3B It is another example diagram of sharing clock signals across chips.

[0040] Figure 4 It is a flowchart of the design method provided by the embodiments of the present application.

[0041] Figure 5A It is an example diagram of initially constructing a clock grid on the first chip.

[0042] Figure 5B It is a top view of the 3D packaged chip.

[0043] Figure 5C It is an example diagram of adding the first metal wire and clock grid buffer within the chip projection area.

[0044] Figure 5D It is an example diagram of constructing a clock generation source and a general clock network.

[0045] Figure 6A It is an example diagram of setting the first contact point.

[0046] Figure 6B It is an example diagram of the connection of the contact points.

[0047] Figure 6C It is another example diagram of the connection of the contact points.

[0048] Figure 6D It is yet another example diagram of the connection of the contact points.

[0049] Figure 7A It is an example diagram of the wiring of the clock load of the first chip.

[0050] Figure 7B It is an example diagram of the wiring of the clock load of the second chip.

[0051] Figure 8 It is an example diagram of sharing clock signals across chips in the clock system provided by the embodiments of the present application.

[0052] Figure 9 It is a block diagram of the design device provided by the embodiments of the present application. Detailed implementation manners

[0053] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0054] In a chip system adopting 3D packaging technology, the interconnection between chips can adopt different connection methods, including but not limited to face-to-face (Face to Face) connection and face-to-back (Face to Back) connection, etc.

[0055] Among them, the face-to-face connection means that the front sides (such as metal layers) of two chips face each other and are connected through metal and bonding pads, that is, the front sides of the two chips are interconnected through metal bonding; the face-to-face connection mainly relies on metal bonding to provide low-resistance electrical connection, allowing signals and power to be transmitted between different chips. As a connection method used in the face-to-face connection, the DBI (Direct Bond Interconnect) technology can be used for the face-to-face connection. Specifically, DBI realizes the interconnection between chips through direct metal-to-metal contact (such as copper-to-copper bonding), allowing signals and power to be transmitted between chips. At the same time, DBI can reduce signal attenuation and distortion and ensure stable signal transmission.

[0056] It should be noted that the DBI technology is mainly applied to 3D packaging structures that require high-density electrical interconnection, especially in 3D packaging structures with face-to-face connections. Among them, the 3D packaging structure can be regarded as the packaging structure of a chip system adopting 3D packaging technology; the DBI technology realizes the electrical interconnection between chips through direct metal contact, allowing a large number of connection points to be created in a very small space, thereby improving the integration and performance of the circuit; at the same time, through direct metal-to-metal contact, DBI provides low-resistance electrical connection, which helps to reduce power loss and improve signal transmission efficiency; at the same time, the DBI technology can reduce signal attenuation and distortion during transmission, ensuring high-speed and high-quality signal transmission, which is particularly important for high-frequency signal transmission; further, the connection tightness and simplicity of the DBI technology help to reduce parasitic capacitance and parasitic inductance and optimize high-frequency signal transmission.

[0057] Face-to-back connection means that the front and back sides (such as the silicon substrate layer) of two chips face each other, that is, the front side (such as the metal layer) of one chip faces the back side (such as the silicon substrate layer) of the other chip, and they are connected through TSV (Through Silicon Via). As a connection method used in face-to-back connection, TSV technology enables circuits to connect multiple chip layers (i.e., chips at multiple levels) in the vertical direction by opening through-holes inside the chip. TSV technology can shorten the signal connection path and improve the performance of the chip system, especially under the requirements of high performance and high integration.

[0058] For ease of understanding, taking the face-to-face connection used for inter-chip interconnection as an example, Figure 1 an exemplary diagram of a 3D packaging structure is shown, as Figure 1 shown, the two interconnected chips in the 3D packaging structure include an upper chip 110 and a lower chip 120. Among them, the upper chip 110 is the chip located in the upper layer among the two interconnected chips, and the lower chip 120 is the chip located in the lower layer among the two interconnected chips. That is, the two interconnected chips are packaged in a vertically stacked (i.e., stacked up and down) form, with the upper chip located in the upper layer of the stack and the lower chip located in the lower layer of the stack.

[0059] It should be noted that the upper and lower relationships between the upper chip and the lower chip mainly refer to the relative hierarchical relationship of the chips in the vertical stack. That is to say, the upper chip and the lower chip can correspond to any two interconnected chips and their relative hierarchical relationships among the multiple vertically stacked chips, and are not limited to the 3D packaging structure with only two layers of stacking.

[0060] It should be further noted that the chip located at the top of the multiple vertically stacked chips is called the top die, and the top die can be an example of the upper chip, corresponding to the upper chip at the top; the chip located at the bottom of the multiple vertically stacked chips is called the bottom die, and the bottom die can be an example of the lower chip, corresponding to the lower chip at the bottom. The bottom die can be connected to the substrate in the packaging structure to dock external signals through the substrate.

[0061] For face-to-face connection, the metal layer of the upper chip 110 faces downwards, facing the metal layer of the lower chip 120, and the metal layer of the lower chip 120 faces upwards, facing the metal layer of the upper chip 110; specifically, in combination with Figure 1As shown, the upper chip 110 includes the silicon base layer 111 and the metal layer 112 of the upper chip, and the lower chip 120 includes the silicon base layer 121 and the metal layer 122 of the lower chip; in the vertical direction, the metal layer 112 of the upper chip is located below the silicon base layer 111 of the upper chip and is bonded to the metal layer 122 of the lower chip, while the metal layer 122 of the lower chip is located above the silicon base layer 121 of the lower chip, facing the metal layer 112 of the upper chip and is bonded to the metal layer 112 of the upper chip.

[0062] Further, in Figure 1 the example, the metal layer of the upper chip and the metal layer of the lower chip can be bonded by DBI technology. For example, the metal layer of the upper chip and the metal layer of the lower chip are connected through the metal bonding 130 of DBI technology, that is, the metal bonding 130 connects the metal layer of the upper chip and the metal layer of the lower chip; there are metal bonding connection points 140 between the metal layer of the upper chip and the metal layer of the lower chip and the metal bonding 130 respectively. The metal bonding connection points 140 are, for example, micro-bumps. The micro-bumps vertically connect the two face-to-face connected chips through DBI technology (such as the metal bonding of DBI technology) to achieve physical and electrical connections between the metal layers of the two chips.

[0063] It should be noted that for any chip, the silicon base layer is the basic structure of the chip, mainly made of single crystal silicon. It is the physical substrate for manufacturing semiconductor devices, and the transistors and other electronic components of the chip are formed on the silicon base layer; the metal layer is used to connect the electronic components (such as transistors, etc.) in the silicon base layer to form a circuit network inside the chip.

[0064] Further, as shown in Figure 1 the figure, the 3D packaging structure is also provided with a substrate 150, through-silicon vias 160, and solder balls 170; among them, the substrate 150 provides mechanical support for the 3D packaging structure and an interface for connecting to the outside; in the face-to-face connected 3D packaging structure, the through-silicon vias 160 are used to realize the connection between the bottom chip (i.e., the bottommost chip among the vertically stacked multiple chips) and the substrate, that is, the through-silicon vias provided in the bottom chip lead out signals from the bottom chip and are connected to the substrate to connect to the outside interface through the substrate to realize the connection with external signals; the solder balls 170 can be ball grid arrays, which are used to provide mechanical and electrical connections between the 3D packaging structure and the circuit board.

[0065] It should be noted that Figure 1 the face-to-face connection is taken as an example to illustrate the 3D packaging structure. The 3D packaging structure is not limited to the face-to-face connection of chip interconnection. It can also be a face-to-back connection, or even a multi-layer stacking form such as a combination of face-to-face connection and face-to-back connection. The embodiments of the present application are not limited.

[0066] Regardless of whether the inter-chip connection is face-to-face, back-to-back, or any other connection method, 3D packaging technology improves the performance and computing density of the chip system by stacking multiple chips vertically. For example, by stacking multiple chips related to computing and storage functions using 3D packaging technology, the integration of computing resources and storage resources in the chip system can be enhanced, thereby improving the computing density and performance of the chip system, making it suitable for chip designs in HPC (High Performance Computing), especially for high-performance CPU (Central Processing Unit) designs. For example, taking the stacking of processor resources (a form of computing resources) and cache resources (a form of storage resources) as an example, using 3D packaging technology, the CPU cache chip can be stacked on top of the main processor chip for packaging to increase the storage buffer density and improve the performance of the chip system.

[0067] To ensure that the chips in the chip system can operate in the correct timing, the chip system needs to design a clock system. Among them, the clock system is the part of the chip system that generates, distributes, and controls clock signals. The clock system can ensure that the chips in the chip system can operate in the correct timing, thereby achieving the correct transmission and processing of data.

[0068] In terms of the distribution of clock signals, the clock system can achieve the distribution of clock signals through a clock mesh. That is, the clock mesh is a structure in the clock system used to distribute clock signals, and it realizes the distribution of clock signals through grid-like clock lines. Specifically, the clock mesh structure forms one or more grid-like conductive layers inside the chip to evenly distribute clock signals to each flip-flop and other clock-sensitive components within the chip. In the design of the clock system of the chip system, the clock mesh structure is a key technology for realizing the distribution of global clock signals and plays a crucial role in ensuring the integrity of clock signals, reducing the clock signal path delay, and minimizing clock skew.

[0069] For ease of understanding, Figure 2A An exemplary example diagram of the clock mesh is shown, such as Figure 2A As shown, the clock mesh 210 includes: a clock mesh metal layer 211 and a clock mesh buffer 212.

[0070] The clock grid metal layer 211, i.e., the metal layer in the clock grid, is used to form a grid-like conductive path; the clock grid metal layer 211 can be a two-layer metal layer structure, and both of the two metal layers are selected with a relatively high physical level; the two-layer metal layer structure of the clock grid metal layer can include: the first clock grid metal layer and the second clock grid metal layer, and the level of the second clock grid metal layer is higher than that of the first clock grid metal layer;

[0071] The first clock grid metal layer can arrange multiple first metal wires connecting clock loads (such as clock-sensitive components like registers and clock gating units), that is, the multiple first metal wires arranged in the first clock grid metal layer are used to connect clock loads; in the first clock grid metal layer, the multiple first metal wires can be arranged in parallel to ensure the stable distribution of clock signals in the clock grid. Of course, the multiple first metal wires can also be arranged in a staggered manner, and whether the multiple first metal wires are arranged in parallel or in a staggered manner depends on the specific clock grid design requirements;

[0072] The second clock grid metal layer can arrange multiple second metal wires intersecting with the first metal wires. The multiple second metal wires arranged in the second clock grid metal layer may not be directly connected to the clock loads, but serve as a support structure of the clock grid (i.e., the grid structure supporting the clock grid) to assist the first metal wires in completing the distribution of clock signals; in the second clock grid metal layer, the multiple second metal wires can be arranged in parallel. Of course, the multiple second metal wires can also be arranged in a staggered manner, depending on the specific clock grid design requirements;

[0073] The first metal wire intersects with the second metal wire, and since the first metal wire and the second metal wire are arranged on different layers, the intersection point of the first metal wire and the second metal wire refers to the intersection part of the first metal wire and the second metal wire on different layers; that is, the intersection point of the first metal wire and the second metal wire does not refer to the actual electrical connection of the wires, but the staggered part of the wires on different metal layers in the physical layout; the intersection point of the first metal wire and the second metal wire can be connected through an interlayer connection method such as metal bonding; the intersection point of the first metal wire and the second metal wire is a key part of the clock grid and serves as the location for placing the clock grid buffer.

[0074] Exemplarily, in combination with Figure 2A as shown, the first metal wire can be a horizontal metal wire 2111 arranged in the horizontal direction (the horizontal metal wire is shown as Figure 2A the thickened horizontal line), and the second metal wire can be a vertical metal wire 2112 arranged in the vertical direction (the vertical metal wire is shown as Figure 2Aas shown by the thick vertical lines); that is to say, in the two-layer structure of the clock grid metal layer, the lower-level clock grid first metal layer arranges multiple horizontal metal wires in the horizontal direction, and the higher-level clock grid second metal layer arranges multiple vertical metal wires in the vertical direction. Thus, the clock loads on the chip (such as clock-sensitive components like registers and clock gating units) can be connected to the lower-level horizontal metal wires, while the higher-level vertical metal wires are not directly connected to the clock loads but serve as the support structure of the clock grid and assist the horizontal metal wires in completing the clock signal distribution. Furthermore, the intersection points formed by the horizontal metal wires and the vertical metal wires in the physical layout are the positions for placing the clock grid buffers.

[0075] Through the setting of the two-layer metal layer structure with a relatively higher physical level of the clock grid metal layer, the clock grid metal layer can reduce resistance and parasitic capacitance, thereby improving the signal transmission efficiency. That is to say, the two metal wires of the clock grid metal layer have a relatively higher level, and a smaller resistivity and higher performance can be obtained.

[0076] It should be noted that the first metal wire connecting the clock load being a horizontal metal wire is only an example, and the second metal wire used to support the clock grid and assist in completing the clock signal distribution being a vertical metal wire is only an example. For example, in the case where it is ensured that the first metal wire and the second metal wire can cross to effectively distribute the clock signal, the embodiments of the present application do not limit the arrangement manner of the first metal wire in the clock grid first metal layer and the arrangement manner of the second metal wire in the clock grid second metal layer; for example, the first metal wire can be arranged in an inclined or diagonal form in the clock grid first metal layer, as long as it is ensured that when the second metal wire is arranged in the clock grid second metal layer, there is an overlapping part (i.e., an intersection point) with the first metal wire arranged in an inclined or diagonal form in the clock grid first metal layer.

[0077] The clock grid buffer 212, that is, the buffer in the clock grid, is located at the intersection point of the clock grid, that is, the intersection point of the first metal wire (such as a horizontal metal wire) and the second metal wire (such as a vertical metal wire), and is used to drive the clock grid and enhance the driving force of the clock signal in the clock grid; the clock grid buffer can have a relatively strong driving ability to ensure the stability of the clock signal and reduce the attenuation of the clock signal.

[0078] Taking the example that the intersection point of the first metal wire and the second metal wire is connected by an interlayer connection method such as metal bonding, the clock grid buffer can be connected to the entrance or exit of the interlayer connection structure corresponding to the intersection point to realize the setting of the clock grid buffer at the intersection point.

[0079] The clock grid buffer 212 has an effectively covered chip area, that is, the chip area that the clock signal can reach after being driven and transmitted by the clock grid buffer 212. The chip area is the clock load area 220 covered by the clock grid buffer 212. Each clock grid buffer has a corresponding clock load area, which indicates the chip area to which the clock signal driven by the clock grid buffer can be effectively distributed; the clock load area 220 can be set with a clock sensitive component 230 connected to the clock grid (for example, the clock sensitive component is connected to the first metal wire of the clock grid metal layer, such as a horizontal metal wire). The clock sensitive component 230, such as a register 231, a clock gating unit 232, etc., is the target object to which the clock grid needs to distribute the clock signal.

[0080] Depend on Figure 2A It can be seen that the clock grid is a grid-like structure formed by a clock grid metal layer, and a clock grid buffer is set at the intersection of the grid. The clock grid is evenly distributed inside the chip to ensure that the clock signal can be distributed to each clock-sensitive component (i.e., clock load) of the chip with lower delay and deviation.

[0081] Furthermore, the clock signal can be generated by a clock source of the clock system, and the clock signal generated by the clock source can be distributed to a clock grid buffer in the clock grid, and then the clock grid buffer drives the clock signal to the clock sensitive component in the corresponding clock load area. For further understanding, Figure 2B The example diagram of the clock system of the chip is shown in FIG. Figure 2A and Figure 2B As shown, the chip's clock system Figure 2A In addition to the clock grid shown, it also includes:

[0082] A clock source 240 is a core component in a clock system that generates a clock signal, such as a clock generation circuit composed of a phase-locked loop or a crystal oscillator that generates a clock signal;

[0083] A common clock network 250, including a common clock buffer 251 and a common clock network metal layer 252;

[0084] The common clock buffer 251 is a buffer in the common clock network, which is used to receive the clock signal generated by the clock source, and amplify and distribute it to multiple clock grid buffers of the clock grid; multiple common clock buffers can be cascaded to sequentially transmit the clock signal from the clock source to the clock grid buffers of the clock grid;

[0085] The general clock network metal layer 252, namely the metal traces in the general clock network, is used to transmit clock signals between the clock generation source and general clock buffers, between general clock buffers, and between general clock buffers and clock mesh buffers.

[0086] It should be noted that the transmission path of the general clock network 250 is tree-shaped or chain-shaped. By cascading two-level or multi-level general clock buffers, the clock signal is sequentially transmitted from the clock generation source to the clock mesh buffers of the clock mesh. The general clock network can cover a large area of the chip, but it cannot guarantee a uniform clock signal distribution. Therefore, a clock mesh with a mesh structure is required to achieve a uniform distribution of clock signals. That is to say, the general clock network can be regarded as the primary distribution network of clock signals, with a relatively low signal strength and a relatively large distribution range. For example, the clock network is responsible for transmitting the clock signal from the clock generation source to the clock mesh buffers and amplifying the clock signal using general clock buffers during the transmission process. The clock mesh can be regarded as the final distribution network (mesh network) of clock signals, which is responsible for uniformly distributing the clock signal to each clock-sensitive component of the chip. Specifically, through the clock mesh buffers set at each intersection of the clock mesh, the clock signal is driven to the clock-sensitive components in the corresponding clock load area to provide a stable and low-deviation clock signal and ensure the synchronization of clock-sensitive components.

[0087] For a chip system using 3D packaging, since the chip system includes multiple chips (such as multiple chips at different physical levels), the clock system design of the chip system needs to consider cross-chip clock signal transmission. At this time, if the clock system adopts a clock mesh design, a design of sharing the clock signal of the clock generation source across chips can be considered, that is, sharing one or more clock signals between interconnected chips (such as between multiple chips stacked and interconnected using 3D packaging), and the distributed design of the clock signal to the clock-sensitive components in each chip sharing the clock signal is implemented using the above clock mesh structure. Among them, the shared clock signal can refer to that the source of the clock signal is located in one of the interconnected chips (such as two interconnected chips), and the other chips among the interconnected chips also use this clock signal.

[0088] For the sake of easy understanding, taking the upper-layer chip and the lower-layer chip that are interconnected as an example, Figure 3A An exemplary diagram showing the sharing of clock signals across chips is shown, as Figure 3AAs shown, the clock generation source 240 is located in the lower chip 120; in the lower chip, the clock signal generated by the clock generation source 240 passes through the general clock network of the lower chip (general clock buffers and general clock network metal layers) to drive the clock grid buffer array of the lower chip (the clock grid buffer array is composed of clock grid buffers at each intersection of the clock grid). The clock grid buffer array of the lower chip drives the enhanced clock signal to the clock grid metal layer of the lower chip, forming the clock grid structure of the lower chip;

[0089] At the same time, the clock signal generated by the clock generation source 240 is transmitted from the lower chip 120 to the upper chip 110 through the metal bonding 130, that is, there is a branch path for the clock signal generated by the clock generation source 240 to be transmitted from the lower chip 120 to the upper chip 110. This branch path connects the lower chip 120 and the upper chip 110 through the metal bonding 130; in the upper chip, the clock signal transmitted by the metal bonding 130 passes through the general clock network of the upper chip to drive the clock grid buffer array of the upper chip. The clock grid buffer array of the upper chip drives the enhanced clock signal to the clock grid metal layer of the upper chip, forming the clock grid structure of the upper chip.

[0090] It can be seen that in Figure 3A the example, the upper chip and the lower chip share the same clock signal, and the clock signal comes from the clock generation source of the lower chip. At the same time, the upper chip and the lower chip respectively construct their own independent clock grid structures to drive the clock-sensitive components of the upper chip and the lower chip respectively.

[0091] However, the above method of sharing clock signals across chips has problems of relatively high design complexity and relatively low clock system performance. Specifically, each interconnected chip constructs its own independent clock grid structure, resulting in relatively high design complexity, and the clock signal starts to branch from the clock generation source, making it difficult to balance the clock delay of the shared clock signal between chips (such as the clock delay between the upper chip and the lower chip in the above example), reducing the clock system performance of the chip system using 3D packaging technology; furthermore, the above method of sharing clock signals across chips will also generate relatively large clock skew and resource waste, further affecting the clock system performance.

[0092] For further understanding, Figure 3B an exemplary another example diagram of sharing clock signals across chips is shown. This example is used to illustrate the timing problem of clock signals across chips. Combining Figure 3A and Figure 3BAs shown in the figure, the clock signal is generated by the clock generation source 240 of the lower chip 120. The clock signal needs to pass through the following clock signal path from the lower chip 120 to the upper chip 110: clock generation source 240 → metal bonding 130 → general clock network 311 of the upper chip → clock grid buffer array 312 of the upper chip → terminal register 313 of the upper chip; for easy identification and distinction, the general clock network of the upper chip is labeled as 311;

[0093] There are multiple levels of signal distribution in the above clock signal path, and each level of signal distribution may introduce delays, especially the cross-chip clock signal transmission delay introduced by the metal bonding 130. At the same time, the general clock network 311 and the clock grid buffer array 312 of the upper chip will further accumulate the transmission time of the clock signal. Therefore, the delay of the clock signal path of the clock load (such as the terminal register 313) of the upper chip is relatively long, and the increase in the delay of the clock signal path will cause the clock signals of the upper chip to arrive out of sync, affecting the cross-chip timing performance, and thus reducing the clock system performance.

[0094] Specifically, the starting register 321 in the lower chip 120 is the starting point of the cross-chip timing path and is used to store data signals. The clock input terminal of the starting register 321 receives the clock pulse of the clock signal from the lower chip 120 and triggers data transmission according to the synchronization of the clock; the terminal register 313 in the upper chip 110 is the end point of the cross-chip timing path and is used to receive the data signals transmitted from the starting register. The terminal register depends on the synchronization of the clock signal of the upper chip 110 to ensure that the data signals can be transmitted to the terminal register in the correct timing;

[0095] It should be noted that the timing path is the data transmission path between one register and another, including the data signal path and the corresponding clock signal path; among them, the data signal path is the path for the starting register to output data, passing through the intermediate logic unit (such as an adder, a comparator), and the cross-chip channel (such as metal bonding), and transmitted to the terminal register; the clock signal path refers to the clock signal transmission path from the clock generation source to the clock load, such as the clock signal transmission paths from the clock generation source to the starting register and the terminal register. The clock signal path is used to trigger the operation of the register;

[0096] Thus, in Figure 3B the example, the timing path is: starting register 321 → metal bonding 330 for transmitting data between the upper chip and the lower chip → terminal register 313;

[0097] The clock signal path of the starting register 321 in the lower chip is as follows: clock generation source 240 → general clock network 322 of the lower chip → clock grid buffer array 323 of the lower chip → starting register 321 of the lower chip; for easy identification and distinction, the general clock network of the lower chip is labeled as 322;

[0098] Combined with the clock signal path of the terminal register 313 in the upper chip, it can be seen that the clock signal paths of the starting register 321 and the terminal register 313 are different. That is, the clock signal path of the starting register 321 involves the independent clock grid structure of the lower chip, while the clock signal path of the terminal register 313 involves the cross-chip path and the independent clock grid structure of the upper chip. This makes it difficult to keep the delays of the clock signal paths of the starting register 321 and the terminal register 313 consistent, resulting in the clock signals between the upper chip and the lower chip being out of sync and causing a decline in timing performance. That is to say, the clock signal path of the starting register is relatively short, and the clock signal path of the terminal register is relatively long, including the additional delay of the cross-chip metal bonding. As a result, the trigger point of the clock signal of the starting register is earlier than that of the terminal register, which leads to timing errors in the terminal register, and the data signal may not be able to be transmitted to the terminal register in the correct timing.

[0099] Furthermore, the clock signal paths of the lower chip and the upper chip start to diverge from the clock generation source, resulting in fewer common paths for the clock signal paths of the lower chip and the upper chip. Thus, there are significant physical design differences in the clock signal paths of the lower chip and the upper chip, which are extremely likely to cause delay deviations in the clock grids of the lower chip and the upper chip. Especially, the influence of electrical noise or signal fluctuations (variation deviations) is amplified, further increasing the clock deviation, reducing the performance of the clock grid, and affecting the timing convergence across chips.

[0100] Furthermore, the upper chip needs to set up an independent clock grid structure, which requires placing a large number of clock grid buffers in the upper chip and planning complex high-level metal grid traces, occupying valuable high-level metal resources. The large occupation of high-level metal resources in the upper chip may affect the performance of the power network of the upper chip (the high-level metal resources of the upper chip are crucial for the power network performance of the upper chip); in addition, the independent clock grid design of the upper chip will increase the power consumption of the upper chip, possibly leading to difficulties in system thermal management.

[0101] Further, in the interconnection of chips (such as in the face-to-face connection of chips), the metal layers of the upper chip and the lower chip are relatively close, and the clock signal transmitted in the high-level metal traces of the clock grid may cause a coupling capacitance effect; that is, parasitic capacitance may be generated between adjacent metal layers due to the proximity, and high-frequency clock signals are easily affected by the coupling capacitance, resulting in signal waveform distortion or interference, which affects the quality of the clock signal.

[0102] Based on this, the embodiments of the present application consider improving the clock system design based on the clock grid, reducing the design complexity of the clock system and improving the clock system performance while realizing cross-chip shared clock signals.

[0103] Next, from the perspectives of the improved structure of the clock system and the design method of the clock system, the design scheme of the improved clock system provided by the embodiments of the present application will be described in combination.

[0104] As an optional implementation, Figure 4 An optional flowchart of the design method provided by the embodiments of the present application is exemplarily shown. This design method can be used for the clock system design of a chip system adopting 3D packaging technology. As an optional implementation, this design method can be executed by a design device, and the design device includes but is not limited to a terminal device or a server device, and can be any computer device that can be used by chip designers for chip design.

[0105] It should be noted that the connection relationship described in the following design method refers to the connection relationship configured in the design stage, rather than the actual physical connection. The actual physical connection needs to be generated after chip production and manufacturing based on the connection relationship configured in the design stage.

[0106] Referring to Figure 4 , the design method may include the following steps.

[0107] Step S410, determine a first chip and at least one second chip among a plurality of stacked chips, wherein the chip area of the second chip is less than or equal to that of the first chip.

[0108] In 3D packaging, a plurality of chips are stacked vertically, including but not limited to two chips stacked vertically, or more than two chips stacked vertically. For the connection between chips, the embodiments of the present application support face-to-face connection or face-to-back connection.

[0109] The chip areas of multiple stacked chips can be different. As an alternative implementation, embodiments of the present application can determine the chip with the largest chip area as the first chip, and one or more second chips other than the first chip; that is, the multiple stacked chips can include the first chip and at least one second chip. From the perspective of chip area, the chip area of the second chip is less than or equal to that of the first chip, that is, the chip area of the second chip should not be greater than that of the first chip.

[0110] In an alternative implementation, in 3D packaging, the chip area of the upper-layer chip stacked above is less than or equal to that of the lower-layer chip stacked below; that is, from a top-down perspective, the upper-layer chip is within the range of the lower-layer chip. Thus, the bottom chip (i.e., the bottommost lower-layer chip) among the multiple stacked chips can be used as the first chip, and at least one upper-layer chip stacked above the bottom chip can be used as the second chip.

[0111] It should be noted that embodiments of the present application support stacking one or more layers of second chips above the first chip. If more than one layer of second chips is stacked above the first chip, when the first chip and the adjacent second chip adopt a face-to-face connection, the second chips (such as between the first layer of second chips and the second layer of second chips stacked above the first chip) can adopt a back-to-back connection, and the back-to-back connection can use through-silicon vias (TSV) to achieve vertical interconnection between chips. That is, when one layer of second chips is stacked above the first chip, embodiments of the present application can use 3D packaging technology to package two chips and support the face-to-face connection method; when more than one layer of second chips is stacked above the first chip, embodiments of the present application can use 3D packaging technology to package more than two chips and support a chip interconnection method that combines face-to-face connection and back-to-back connection.

[0112] Step S420: Initially construct a clock grid on the first chip.

[0113] In embodiments of the present application, the first chip is the chip where the clock generation source is located and can be regarded as the clock master chip, and the second chip provides a clock signal based on the clock grid structure of the first chip. Embodiments of the present application can initially construct a clock grid on the first chip.

[0114] In an alternative implementation, when initially constructing the clock grid in the embodiments of the present application, multiple initial first metal wires (such as multiple initial horizontal metal wires) and multiple initial second metal wires (such as multiple initial vertical metal wires) can be constructed on the first chip, and the initial first metal wires and the initial second metal wires are located at different levels of the clock grid metal layer. For example, the initial first metal wires are located on the first clock grid metal layer, and the initial second metal wires are located on the second clock grid metal layer. The level of the second clock grid metal layer in the clock grid metal layer is higher than that of the first clock grid metal layer. Furthermore, in terms of spatial layout, the initial first metal wires (such as the initial horizontal metal wires) and the initial second metal wires (such as the initial vertical metal wires) intersect, and there are initial intersection points of the initial first metal wires (such as the initial horizontal metal wires) and the initial second metal wires (such as the initial vertical metal wires) (i.e., the initial intersection points of the clock grid). By placing the initial clock grid buffers at the initial intersection points, the clock grid can be initially constructed on the first chip.

[0115] For ease of description, the first metal wires when initially constructing the clock grid are referred to as initial first metal wires, such as initial horizontal metal wires; the second metal wires when initially constructing the clock grid are referred to as initial second metal wires, such as initial vertical metal wires; the intersection points of the initial horizontal metal wires and the initial vertical metal wires are referred to as initial intersection points, and the clock grid buffers placed at the initial intersection points are referred to as initial clock grid buffers.

[0116] Exemplarily, taking the first metal wires as horizontal metal wires and the second metal wires as vertical metal wires as an example, Figure 5A An exemplary diagram showing the initial construction of the clock grid on the first chip is shown. As Figure 5A shown, the embodiments of the present application can define the initial spacing between the initial vertical metal wires 510 and the initial spacing between the initial horizontal metal wires 520 to uniformly plan the clock grid. It can be understood that the initial spacing between the initial vertical metal wires 510 is the initial horizontal spacing of the initial vertical metal wires in the horizontal direction, denoted as W; the initial spacing between the initial horizontal metal wires 520 is the initial vertical spacing of the initial horizontal metal wires in the vertical direction, denoted as H.

[0117] In an alternative implementation, the initial horizontal pitch W and the initial vertical pitch H during the initial construction of the clock grid should take into account both the clock signal transmission efficiency and the resource utilization rate. It can be understood that if the initial horizontal pitch W and the initial vertical pitch H are set too small, then to cover a larger chip area, it may be necessary to increase the number of initial horizontal metal wires, the number of initial vertical metal wires, and the number of initial clock grid buffers, resulting in wasted resources and increased power consumption; if the initial horizontal pitch W and the initial vertical pitch H are set too large, then it may cause uneven distribution of clock signals on the chip, resulting in an increase in clock skew. Therefore, it is necessary to comprehensively consider the clock signal transmission efficiency and the resource utilization rate to set the initial horizontal pitch W and the initial vertical pitch H. In an alternative implementation, the initial horizontal pitch W and the initial vertical pitch H can be set to a uniform pitch so that the clock grid is symmetrically distributed, reducing the non-uniformity of the signal path length, thereby reducing the clock skew.

[0118] Furthermore, after defining the initial horizontal pitch and the initial vertical pitch, the embodiments of the present application can plan a plurality of initial horizontal metal wires and a plurality of initial vertical metal wires of the clock grid metal layer according to the initial horizontal pitch and the initial vertical pitch, and place an initial clock grid buffer 530 at the intersection of the initial horizontal metal wire and the initial vertical metal wire to form a preliminarily constructed clock grid with a uniform distribution on the first chip.

[0119] The above takes the initial horizontal metal wire and the initial vertical metal wire as examples to illustrate the method of initially constructing the clock grid. The embodiments of the present application do not limit the arrangement manner of the initial first metal wires and the initial second metal wires when constructing the initial clock network, as long as there is an overlapping part between the initial first metal wires and the initial second metal wires in the physical space to form an initial intersection point. That is to say, the embodiments of the present application can define the initial pitch between the initial first metal wires and the initial pitch between the initial second metal wires, and thus plan a plurality of initial first metal wires and a plurality of initial second metal wires of the clock grid metal layer according to the initial pitch between the initial first metal wires and the initial pitch between the initial second metal wires, and place an initial clock grid buffer at the initial intersection point of the initial first metal wire and the initial second metal wire to form a preliminarily constructed clock grid on the first chip.

[0120] Step S430, determine the chip projection area of the second chip corresponding to the first chip.

[0121] Since the chip area of the second chip is less than or equal to that of the first chip, there is a projection area of the second chip on the first chip, and this projection area is within the first chip. For example, if the chip area of the upper chip is less than or equal to that of the lower chip, then from a top-down perspective, the upper chip is within the range of the lower chip, and thus there is a projection area corresponding to the second chip within the lower chip. For the convenience of description, the projection area of the second chip on the first chip is referred to as the chip projection area.

[0122] For the convenience of understanding, Figure 5B An exemplary top view of the chips in a 3D package is shown, such as Figure 5B shown. The area of the upper chip 110 does not exceed the area of the lower chip 120. Thus, from a top-down perspective, the outline of the upper chip is within the boundary of the lower chip. That is to say, the chip area of the lower chip is larger, while the chip area of the upper chip is smaller. The upper chip is completely stacked within the range of the lower chip and does not exceed the boundary of the lower chip. Exemplarily, the lower chip, such as the bottom chip, can be set as the main processor chip for providing the main computing function; the upper chip can be set as the cache chip for providing high-performance cache or acceleration module. Figure 5B The example can be that the chips are connected face-to-face or back-to-back.

[0123] Furthermore, if there is more than one second chip, the embodiments of the present application can respectively determine the projection areas of each second chip on the first chip, so as to obtain the corresponding projection areas of each second chip on the first chip. The corresponding projection areas of more than one second chip on the first chip can partially overlap or completely overlap, and thus are regarded as the chip projection area corresponding to the second chip on the first chip as a whole.

[0124] In other possible implementations, the embodiments of the present application can also support that the area of the second chip is equal to that of the first chip, and the first chip is the bottom chip or any layer chip in the stacked multiple chips. Thus, the projection area of the second chip on the first chip corresponds to the chip area of the first chip. That is, when the areas of the second chip and the first chip are equal, the entire chip area of the first chip is regarded as the chip projection area.

[0125] Step S440: Increase the density of the clock grid within the chip projection area to form an encrypted clock grid area.

[0126] In the embodiments of the present application, in the above-mentioned chip projection area, by increasing the density of the clock grid, an encrypted clock grid area can be formed, that is, the clock grid density of the encrypted clock grid area is higher than the clock grid density when the clock grid is initially constructed, so as to improve the clock signal driving ability and signal distribution efficiency of the clock grid in the chip projection area of the first chip, so that the clock grid (i.e., the encrypted clock grid area) in the chip projection area can serve the clock load requirements of the first chip (such as the lower-layer chip) and at least one second chip (such as one or more upper-layer chips stacked on the lower-layer chip) at the same time.

[0127] In an alternative implementation, the embodiments of the present application can increase the density of the clock grid metal layer in the chip projection area, including but not limited to increasing the density of the first metal wires of the clock grid metal layer, and / or increasing the density of the second metal wires of the clock grid metal layer, so as to add intersections of the clock grid (referred to as newly added intersections) in the chip projection area, and then place newly added clock grid buffers at the newly added intersections to form an encrypted clock grid area, so as to improve the clock signal driving ability of the clock grid in the chip projection area.

[0128] In a further alternative implementation, the first metal wires (such as horizontal metal wires) of the clock grid metal layer are used to connect clock loads. In the above-mentioned chip projection area of the first chip (that is, the second chip is in the chip projection area corresponding to the first chip), by increasing the density of the first metal wires (such as horizontal metal wires), newly added first metal wires can be formed. Furthermore, the newly added first metal wires and the initial second metal wires can form newly added intersections. By arranging newly added clock grid buffers at the newly added intersections, an encrypted clock grid area with an increased clock grid density can be formed in the chip projection area.

[0129] In other alternative implementations, the embodiments of the present application can also increase the density of the second metal wires (such as vertical metal wires) in the above-mentioned chip projection area of the first chip, so as to form newly added second metal wires. Furthermore, the newly added second metal wires and the initial first metal wires can form newly added intersections. By arranging newly added clock grid buffers at the newly added intersections, an encrypted clock grid area can be formed.

[0130] In other alternative implementations, in the above-mentioned chip projection area of the first chip, the present application embodiment can also increase the density of the first metal wires (such as horizontal metal wires) and the density of the second metal wires (such as vertical metal wires) simultaneously to form new first metal wires and new second metal wires. Furthermore, new crossovers are formed between the new first metal wires and the initial second metal wires as well as the new second metal wires, and new crossovers are formed between the new second metal wires and the initial first metal wires as well as the new first metal wires. New clock grid buffers are arranged at these new crossovers to form a densified clock grid area.

[0131] That is to say, the way to increase the density of the clock grid metal layer can be at least one of the means such as increasing the density of the first metal wires (such as horizontal metal wires) and increasing the density of the second metal wires (such as vertical metal wires). As long as it can be ensured that after the density of the clock grid metal layer is increased, there are new crossovers where new clock grid buffers can be placed to improve the clock signal driving ability of the clock grid within the chip projection area.

[0132] In an alternative implementation, the number of the new first metal wires and / or the new second metal wires has a positive correlation with the number of the at least one second chip, that is, the more the number of the second chips, the more the number of the new first metal wires and / or the new second metal wires, so as to ensure that the densified clock grid area has sufficient clock signal driving ability to cope with a larger number of second chips. In an alternative implementation, the increase multiple of the density of the first metal wires and / or the second metal wires in the chip projection area of the first chip has a positive correlation with the number of the second chips, that is, the more the number of the second chips, the larger the increase multiple of the density of the first metal wires and / or the second metal wires in the chip projection area; the increase multiple of the density of the metal wires in the chip projection area is expressed as the proportional relationship between the number of the metal wires in the chip projection area after the increase and the number of the initial metal wires in the chip projection area.

[0133] As an alternative implementation, taking the increase in the density of the first metal wires (such as horizontal metal wires) as an example, the alternative implementation methods for increasing the density of the clock grid metal layer will be described below.

[0134] In an alternative implementation, the first metal wires connecting the clock loads can be horizontal metal wires. The present application embodiment can perform density increase processing on the horizontal metal wires in the chip projection area of the first chip and correspondingly increase the clock grid buffers, thereby improving the clock signal driving ability and avoiding complex adjustments to the vertical metal wires with higher levels, reducing the design difficulty.

[0135] Thus, taking the increase in the first metal wires as an example, the increase multiple of the density of the first metal wires within the chip projection area is expressed as the proportional relationship between the number of the first metal wires after the increase within the chip projection area (i.e., the sum of the newly added first metal wires and the initial first metal wires within the chip projection area) and the number of the initial first metal wires within the chip projection area; for example, the number of the first metal wires after the increase within the chip projection area, divided by, the number of the initial first metal wires within the chip projection area.

[0136] In an alternative implementation, embodiments of the present application may reduce the pitch between the first metal wires within the chip projection area based on the number of the second chips, so as to increase the density of the first metal wires within the chip projection area. In an alternative implementation, the reduction ratio of the pitch between the first metal wires within the chip projection area may be negatively correlated with the number of the second chips; wherein, the reduction ratio of the pitch between the first metal wires within the chip projection area is expressed as the proportional relationship between the reduced pitch between the first metal wires within the chip projection area and the initial pitch between the first metal wires within the chip projection area; thus, the more the number of the second chips, the smaller the reduction ratio of the pitch between the first metal wires within the chip projection area, and correspondingly, the smaller the reduced pitch between the first metal wires within the chip projection area.

[0137] In an alternative implementation, the reduction ratio of the pitch between the first metal wires within the chip projection area may be expressed as: 1 / (k + 1), where k represents the number of the second chips; that is to say, the reduction ratio is the reciprocal of the sum of the number of the second chips plus 1.

[0138] Exemplarily, assuming that the number of the second chips is k and the first metal wires are horizontal metal wires, the vertical pitch between the horizontal metal wires within the chip projection area is adjusted from the initial vertical pitch H to H / (k + 1), that is, the reduction ratio of the vertical pitch between the horizontal metal wires is 1 / (k + 1). For example, assuming that the number of the second chips is 1, the reduction ratio of the vertical pitch between the horizontal metal wires is 1 / 2, and thus the vertical pitch between the horizontal metal wires within the chip projection area is adjusted from the original initial vertical pitch H to H / 2; for example, if the number of the second chips is 2, the reduction ratio of the vertical pitch between the horizontal metal wires is 1 / 3, and thus the vertical pitch between the horizontal metal wires within the chip projection area is adjusted from the original initial vertical pitch H to H / 3, and so on.

[0139] In an alternative implementation, for adjacent initial first metal wires within the chip projection area, embodiments of the present application can add new first metal wires at intervals corresponding to the reduction ratio between adjacent initial first metal wires, that is, the new first metal wires are arranged between adjacent initial first metal wires at intervals corresponding to the reduction ratio, so as to increase the number of new first metal wires corresponding to the number of second chips between adjacent initial first metal wires, thereby reducing the spacing between the first metal wires within the chip projection area, and further increasing the density of the first metal wires within the chip projection area.

[0140] Exemplarily, taking the first metal wire as a horizontal metal wire as an example, assuming the number of second chips is 1 and the corresponding reduction ratio is 1 / 2, embodiments of the present application can add a horizontal metal wire at the position of the H / 2 spacing between adjacent initial horizontal metal wires within the chip projection area, so as to add 1 new horizontal metal wire corresponding to the number of second chips between adjacent initial horizontal metal wires.

[0141] For ease of understanding, Figure 5C An exemplary diagram showing the addition of first metal wires and clock grid buffers within the chip projection area is shown, as Figure 5C shown. Taking the chip area of the second chip being smaller than that of the first chip as an example, the clock grid of the first chip is divided into: an encrypted clock grid area 501 and a normal clock grid area 502; the encrypted clock grid area 501 corresponds to the chip projection area in the first chip, the normal clock grid area 502 corresponds to the non-chip projection area in the first chip, and the clock grid density of the encrypted clock grid area is higher than that of the normal clock grid area;

[0142] Taking the first metal wire as a horizontal metal wire and the second metal wire as a vertical metal wire as an example, in Figure 5CIn the example, multiple initial horizontal metal wires 520, i.e., multiple initial horizontal metal wires when initially constructing the clock grid, are shared by the encrypted clock grid region and the normal clock grid region. Moreover, additional horizontal metal wires 521 are added between adjacent initial horizontal metal wires 520 in the encrypted clock grid region, and the number of additional horizontal metal wires added between adjacent initial horizontal metal wires corresponds to the number of second chips. Thus, in addition to the initial clock grid buffers 530, the encrypted clock grid region also has additional clock grid buffers 531, and the additional clock grid buffers 531 are arranged at the additional intersection points of the additional horizontal metal wires 521 and the initial vertical metal wires 510. For the convenience of illustration, the horizontal metal wires shown in black in the figure represent the initial horizontal metal wires, the horizontal metal wires shown in white represent the additional horizontal metal wires, the clock grid buffers shown in white represent the initial clock grid buffers, and the clock grid buffers shown in black represent the additional clock grid buffers.

[0143] Further combined with Figure 5C As shown in Figure 5C the example, the normal clock grid region and the encrypted clock grid region share the initial horizontal metal wires 520, and the vertical spacing between the initial horizontal metal wires in the normal clock grid region remains the initial vertical spacing H. Assuming that the number of second chips is 1 (for example, the first chip is the lower-layer chip and there is one upper-layer chip stacked on top of the lower-layer chip), then within the chip projection area (corresponding to the encrypted clock grid region), the reduction ratio of the vertical spacing between the horizontal metal wires is 1 / 2. Thus, additional horizontal metal wires can be added at the position of the H / 2 spacing between adjacent initial horizontal metal wires within the chip projection area, so as to add 1 additional horizontal metal wire corresponding to the number of second chips between adjacent initial horizontal metal wires. At the same time, within the chip projection area, based on the additional horizontal metal wires, additional intersection points of the additional horizontal metal wires and the initial vertical metal wires can be formed. By arranging additional clock grid buffers at the additional intersection points, the density of the clock grid within the chip projection area can be increased to form an encrypted clock grid region. Furthermore, the clock signal driving ability within the chip projection area is correspondingly improved, and the clock load requirements within the chip projection area of the first chip (such as the lower-layer chip) and the clock load requirements of 1 second chip (such as 1 upper-layer chip) can be satisfied simultaneously.

[0144] Similarly, by way of example, taking the first metal wire as the horizontal metal wire, assuming the number of the second chips is 2 and the corresponding reduction ratio is 1 / 3, thus in the embodiments of the present application, new horizontal metal wires can be added at intervals of H / 3 between adjacent initial horizontal metal wires within the chip projection area, that is, new horizontal metal wires are added at the positions of H / 3 and 2H / 3 between adjacent initial horizontal metal wires respectively, so as to add 2 new horizontal metal wires corresponding to the number of the second chips between adjacent initial horizontal metal wires, thereby forming new intersection points between the new horizontal metal wires and the initial vertical metal wires, and new clock grid buffers are arranged at the new intersection points, then the clock signal driving ability within the chip projection area is correspondingly improved, and the clock load requirements within the chip projection area of the first chip (such as the lower-layer chip) and the clock load requirements of 2 upper-layer chips can be satisfied simultaneously.

[0145] And so on, assuming the number of the second chips is k, then in the embodiments of the present application, new horizontal metal wires can be added at intervals of H / (k + 1) between adjacent initial horizontal metal wires within the chip projection area, so as to add k new horizontal metal wires corresponding to the number of the second chips k between adjacent initial horizontal metal wires, thereby correspondingly increasing the new intersection points between the new horizontal metal wires and the initial vertical metal wires, and new clock grid buffers are arranged at the new intersection points to support the clock load within the chip projection area of the first chip and the clock load requirements of k second chips.

[0146] That is to say, for each additional layer of the second chips (such as each additional stack of upper-layer chips on top of the lower-layer chip), the newly added first metal wires (such as newly added horizontal metal wires) within the chip projection area of the first chip increase proportionally, and the new intersection points between the newly added first metal wires (such as newly added horizontal metal wires) and the initial second metal wires (such as initial vertical metal wires) are correspondingly increased. New clock grid buffers are correspondingly added at the new intersection points, then the clock signal driving force can be correspondingly improved, ensuring that the clock signals within the chip projection area of the first chip can cope with the clock load requirements within the chip projection area of the first chip and the clock load requirements of each second chip, and realizing the guarantee of the uniformity of clock signal distribution and the improvement of the driving force.

[0147] It should be noted that regardless of whether the method of increasing the density of the clock grid metal layer is to increase the density of the first metal wires (such as horizontal metal wires), or to increase the density of the second metal wires (such as vertical metal wires), or both are adopted, a densified clock grid area will be formed in the chip projection area of the first chip, and the clock grid density in the densified clock grid area is higher than that in the normal clock grid area. The above is only an example of the densified clock grid area by increasing the density of the first metal wires (such as horizontal metal wires), and it should not be a limitation of the densified clock grid area.

[0148] It should be further noted that Figure 5C an example is given with the chip area of the second chip being smaller than that of the first chip. When the chip areas of the second chip and the first chip are equal, the entire chip area of the first chip is the chip projection area. Correspondingly, the entire chip area of the first chip is the densified clock grid area. At this time, all the clock grids of the first chip are in the densified clock grid area, and there is no normal clock grid area.

[0149] It can be seen that the densified clock grid area corresponds to the second chip in the chip projection area of the first chip, and an initial clock grid buffer and a newly added clock grid buffer are provided in the densified clock grid area. The initial clock grid buffer is located at the initial intersection points of the densified clock grid area, and the newly added clock grid buffer is set at the newly added intersection points of the densified clock grid area.

[0150] In the densified clock grid area, the initial intersection points are the intersection points of the initial first metal wires and the initial second metal wires of the clock grid in the chip projection area when the clock grid is initially constructed; the newly added intersection points are the newly added intersection points corresponding to the newly added first metal wires and / or newly added second metal wires of the clock grid in the chip projection area after the clock grid is initially constructed.

[0151] Based on different densification implementation methods of the densified clock grid area, there may be newly added first metal wires and / or newly added second metal wires in the densified clock grid area. Thus, the densified clock grid area may include:

[0152] the initial first metal wires, the initial second metal wires of the clock grid in the chip projection area, and the initial clock grid buffer corresponding to the initial intersection points of the initial first metal wires and the initial second metal wires;

[0153] the newly added first metal wires and / or newly added second metal wires of the clock grid in the chip projection area;

[0154] Add a new clock grid buffer corresponding to the new intersection point of the first metal wire and the initial second metal wire, and / or add a new clock grid buffer corresponding to the new intersection point of the first metal wire and the new second metal wire, and / or add a new clock grid buffer corresponding to the new intersection point of the initial first metal wire and the new second metal wire.

[0155] Step S450: On the first chip, construct a clock generation source and a general clock network for the clock grid.

[0156] Through step S440, the embodiment of the present application can perform density increase processing on the clock grid within the chip projection area of the first chip to form an encrypted clock grid area. Thus, when the chip area of the second chip is smaller than that of the first chip, the clock grid on the first chip can be divided into an encrypted clock grid area and a general clock grid area. Furthermore, the embodiment of the present application can construct a clock generation source and a general clock network for the clock grid, thereby establishing a path for driving each clock grid buffer (including each initial clock grid buffer and each new clock grid buffer) from the clock generation source.

[0157] In an alternative implementation, the first chip can be provided with a clock generation source, and the clock generation source drives each initial clock grid buffer and each new clock grid buffer in the clock grid through the general clock network. Among them, the general clock network includes a plurality of cascaded general clock buffers and a general clock network metal layer for transmitting clock signals. Thus, the clock signal generated by the clock generation source can be signal-enhanced through the cascaded general clock buffers and transmitted through the general clock network metal layer to be transmitted to each initial clock grid buffer and each new clock grid buffer.

[0158] Exemplarily, Figure 5D An exemplary diagram showing the construction of a clock generation source and a general clock network is illustrated. Taking the horizontal metal wires and vertical metal wires of the clock grid metal layer as an example, in combination with Figure 5C and Figure 5D as shown, in the clock grid, the horizontal metal wires and vertical metal wires are distributed in a grid pattern and are divided into an encrypted clock grid area 501 and a general clock grid area 520. For related content, reference can be made to Figure 5CPart; As can be seen from the figure, the arrangement and connection of the clock grid buffers can present a symmetric H-shaped structure, that is, the clock signal is transmitted along the horizontal metal wires and vertical metal wires, forming a symmetric driving path, so as to ensure the symmetry and uniformity of the clock signal transmission and reduce the clock skew. Furthermore, in the embodiment of the present application, a clock generation source 240 can be set on the first chip to generate a clock signal, and the clock signal is transmitted through the common clock network metal layer 252 and the cascaded common clock buffers 251, and finally transmitted to each initial clock grid buffer 530 and each newly added clock grid buffer 531 in the encrypted clock grid area 501, as well as each initial clock grid buffer 530 in the common clock grid area 502, so as to drive each clock grid buffer from the clock generation source.

[0159] Step S460: Set a first contact point for transmitting the clock signal to the second chip on the first metal wire in the encrypted clock grid area, and obtain a plurality of first contact points in the encrypted clock grid area.

[0160] In the embodiment of the present application, the first metal wire is used to connect the clock load. For the first metal wire in the chip projection area of the first chip, that is, for the first metal wire in the encrypted clock grid area, the first metal wire serves not only the clock load of the first chip but also the clock load of the second chip. Therefore, in addition to connecting the clock load of the first chip, the first metal wire in the chip projection area also needs to connect the clock load of the second chip. In order to enable the clock load of the second chip to also obtain the clock signal through the encrypted clock grid area, in the chip projection area of the first chip (i.e., in the encrypted clock grid area), the embodiment of the present application designs a contact point for the first metal wire to transmit the clock signal to the second chip. For the sake of convenience of description, the contact point set on the first metal wire in the chip projection area of the first chip is called the first contact point.

[0161] That is to say, the first metal wire in the chip projection area of the first chip (such as the lower chip) is originally used to connect the clock load of the first chip, and the second chip (such as the upper chip) cannot directly connect to the first metal wire of the first chip. Therefore, a first contact point is arranged for the first metal wire in the chip projection area to simulate and reproduce the shape and function of the first metal wire of the first chip in the second chip, so that the clock load of the second chip can be connected to the clock grid of the first chip through the connection path with the first contact point. That is, each first contact point of the first metal wire in the chip projection area of the first chip is equivalent to a connection interface, which is the connection point of the connection path of the clock load of the second chip in the first chip and reproduces the function of the first metal wire of the clock grid of the first chip.

[0162] Since the chip projection area of the first chip corresponds to the encrypted clock grid area, the settings within the encrypted clock grid area described below are equivalent to the settings within the chip projection area. In an alternative implementation, embodiments of the present application may set multiple first contact points for each first metal wire in the encrypted clock grid area (including each initial first metal wire and each newly added first metal wire in the encrypted clock grid area); for example, embodiments of the present application may define a contact point pitch, and thereby set multiple first contact points for each first metal wire in the encrypted clock grid area according to the contact point pitch; that is to say, multiple first contact points are set for one first metal wire within the encrypted clock grid area, and the first contact points are equally spaced on the first metal wire according to the contact point pitch.

[0163] As a key design parameter in embodiments of the present application, the contact point pitch should be reasonably designed to ensure the wiring consistency of the clock loads of the first chip and the second chip (such as the lower-layer chip and the upper-layer chip). Specifically, the first contact points simulate the functions of the first metal wires of the first chip for the second chip (such as the upper-layer chip), and the wiring consistency of the clock loads of the first chip and the second chip (such as the lower-layer chip and the upper-layer chip) should be maintained as much as possible. Based on this, if the distribution of the first contact points is uneven, it may lead to inconsistent wiring lengths between the clock loads of the upper-layer chip and the first contact points, thereby generating deviations in the winding resistivity and capacitance and affecting clock synchronization. For example, if the contact point pitch is set too large, it may lead to too long wiring (the wiring distance from the clock load of the second chip to the first contact point is too long), increasing the winding resistivity and capacitance and causing the clock delay and deviation to become larger; if the contact point pitch is set too small, although the wiring length can be shorter, reducing the winding resistivity and capacitance, the over-dense arrangement of the first contact points may also increase the design complexity, that is, the over-dense first contact points will result in an increase in the number of first contact points and the wiring complexity, increasing the design cost.

[0164] In summary, in an alternative implementation, embodiments of the present application may equally space the first contact points on each first metal wire in the encrypted clock grid area to simulate the structure of the first metal wire of the first chip for the second chip, so that the connection point positions of the clock loads of the second chip are the same as those of the first metal wire of the first chip, thereby ensuring that the wiring lengths of the clock loads of the first chip and the second chip are more uniform and facilitating clock synchronization.

[0165] In an alternative implementation, embodiments of the present application can determine the contact point pitch according to the clock load distribution of the second chip and the routing of the first metal wire from the clock load of the second chip to the encrypted clock grid area, and the contact point pitch can be dynamically adjusted. For example, embodiments of the present application can, based on the above clock load distribution and routing, through circuit simulation, calculate the routing resistivity and capacitance of the wire connecting the clock load of the second chip to the first contact point, and calculate the clock delay and clock deviation of the clock signal reaching each clock load of the second chip; if the calculation result indicates a relatively high overall delay, then the layout of the global first contact points needs to be optimized (i.e., global optimization), and if the calculation result indicates a relatively high local delay, it means that the connection density of the local clock load is too high, and the corresponding layout of the first contact points needs to be optimized (i.e., local optimization);

[0166] When performing global optimization, since the overall delay of the clock load of the second chip is relatively high, it indicates that the wires connecting the clock load to the first contact points are generally too long. Therefore, the contact point pitch can be reduced and the number of first contact points can be increased, thereby shortening the wire length from the clock load of the second chip to the first contact points and reducing the routing resistivity and capacitance;

[0167] When performing local optimization, since the delay of the clock load in a partial area of the second chip is relatively high, it may be caused by too long a wire connecting the clock load in this area to the first contact point or interference from other clock loads. At this time, the first contact points corresponding to this area on the first chip can be densely arranged (i.e., increasing the number of first contact points corresponding to this area on the first chip), shortening the wire length of the clock load, and reducing the local routing resistivity and capacitance;

[0168] In each circuit simulation, by calculating the routing resistivity and capacitance, and calculating the clock delay and clock deviation of the clock signal reaching each clock load of the second chip, embodiments of the present application can perform a global optimization or a local optimization, thereby adjusting the contact point pitch; then, after adjusting the contact point pitch, the circuit simulation is performed again, and this iterative adjustment is repeated until the clock delay and clock deviation meet the set design requirements.

[0169] That is to say, in the definition and setting of the contact point pitch of the first contact points, embodiments of the present application can, through circuit simulation means, evaluate the clock delay and clock deviation of the clock signal corresponding to the contact point pitch reaching each clock load of the second chip, thereby iteratively adjusting the contact point pitch until the clock delay and clock deviation meet the design requirements, ensuring that when the second chip reuses the first metal wire in the encrypted clock grid area of the first chip, the clock delay and deviation of the clock load meet the performance requirements.

[0170] Exemplarily, taking the first metal wire connecting the clock load as a horizontal metal wire as an example, Figure 6AAn exemplary diagram showing an example of setting the first contact points is presented. As Figure 6A shown, assuming that the contact point pitch is defined as P, each horizontal metal wire (including the initial horizontal metal wire and the newly added horizontal metal wire) in the encrypted clock grid region 501 is provided with a plurality of first contact points 610 at equal intervals with the contact point pitch P. By way of example, the contact point pitch P can be 5 micrometers and can be adjusted by simulation means.

[0171] In an alternative implementation, for chip - to - chip connection using metal bonding based on face - to - face connection, the first contact points set on the first metal wire in the encrypted clock grid region of the first chip can be metal bonding contact points, that is, connected from the first metal wire in the encrypted clock grid region of the first chip (such as the lower - layer chip) to the contact points of the second chip (such as the upper - layer chip) in a metal bonding manner. Of course, the embodiments of the present application also support face - to - back connection for chip - to - chip connection. Correspondingly, for chip - to - chip connection using TSV (through - silicon via) based on face - to - back connection, the first contact points set on the first metal wire in the encrypted clock grid region of the first chip can be the contact points corresponding to TSV, that is, connected from the first metal wire in the encrypted clock grid region of the first chip (such as the lower - layer chip) to the contact points of the second chip (such as the upper - layer chip) in a TSV manner.

[0172] In a further alternative implementation, within the chip projection area of the first chip (i.e., within the encrypted clock grid region), the embodiments of the present application support setting a plurality of first contact points for each first metal wire, and also support setting first contact points for some first metal wires while not setting first contact points for other first metal wires. That is to say, the present application supports setting first contact points for all or some of the first metal wires within the chip projection area of the first chip (i.e., within the encrypted clock grid region), and for any first metal wire with first contact points set, a plurality of first contact points are evenly set at a set contact point pitch.

[0173] Through step S460, the embodiments of the present application can obtain a plurality of first contact points within the chip projection area of the first chip, and these first contact points form a first contact point array; for example, the first contact points set on all the first metal wires within the chip projection area form a first contact point array, or the first contact points set on some first metal wires form a first contact point array.

[0174] Step S470: Determine the second contact points corresponding to the first contact points in the encrypted clock grid region in the second chip to obtain a plurality of second contact points within the second chip.

[0175] Step S480: Connect the first contact points and the second contact points.

[0176] As an alternative implementation, after designing multiple first contact points within the chip projection area of the first chip in the embodiments of the present application, the multiple first contact points within the chip projection area of the first chip can be respectively projected onto the second chip to obtain the projection points of each first contact point on the second chip, thereby determining multiple projection points corresponding to the multiple first contact points on the second chip; the projection points corresponding to the first contact points on the second chip can be regarded as the contact points within the second chip for connecting to the first contact points. For ease of description, the contact points within the second chip are referred to as second contact points.

[0177] In an alternative implementation, multiple second contact points within the second chip form a second contact point array, and the second contact point array corresponds to the first contact point array; for example, after forming a first contact point array within the chip projection area of the first chip in the embodiments of the present application, the first contact point array can be vertically projected into the second chip to form a second contact point array of the second chip.

[0178] The second contact points within the second chip can be regarded as the contact points directly connected to the clock load of the second chip. After the clock load of the second chip is connected to the second contact points, it is connected to the first contact points in the encrypted clock grid area of the first chip (such as through metal bonding between the first chip and the second chip) through the second contact points, thereby enabling the transfer of the clock signal of the first chip to the second chip.

[0179] For ease of understanding, Figure 6B an exemplary connection example diagram of the contact points is shown, such as Figure 6BAs shown, the chip area of the first chip 601 is larger than that of the second chip 602. The chip projection area of the second chip 602 on the first chip 601 corresponds to the encrypted clock grid area 501 in the clock grid of the first chip 601, and the non-chip projection area of the first chip 601 corresponds to the normal clock grid area 502 in the clock grid. The encrypted clock grid area 501 increases the clock grid density by increasing the density of the clock grid metal layer and the density of the clock grid buffer. Moreover, multiple first contact points 610 are respectively arranged at equal intervals on each horizontal metal wire in the encrypted clock grid area 501, thereby forming a first contact point array in the encrypted clock grid area 501. The projection points of the first contact points 610 on the second chip 602 serve as the second contact points 620 in the second chip 602, so that multiple second contact points 620 are arranged in the second chip, forming a second contact point array in the second chip. The first contact points 610 located on the first chip and the second contact points 620 located on the second chip can be connected through corresponding contact point connections 630 based on the connection manner between the first chip and the second chip. For example, in 3D packaging, based on the face-to-face connection between the first chip and the second chip, the first contact points 610 located on the first chip and the second contact points 620 located on the second chip can be connected through metal bonding posts (a connection form of the contact point connection 630).

[0180] In an alternative implementation, the embodiment of the present application can implement the connection between the second contact points in the second chip and the first contact points in the encrypted clock grid area in the first chip based on the chip interconnection connection manner between the first chip and the second chip. For example, for a face-to-face connection, the second contact points and the first contact points are connected through metal bonding (such as metal bonding posts). In a specific example, for the bottom chip and the top chip using a face-to-face connection, the first contact points in the encrypted clock grid area of the bottom chip can be connected to the second contact points in the top chip through metal bonding.

[0181] Metal bonding can directly penetrate the interconnected chips. Connecting the first contact point and the second contact point through metal bonding can eliminate the need for additional metal traces, reduce design complexity, and also reduce the coupling capacitance between the high-level metals of the upper and lower chips. Specifically, in 3D packaging, a relatively large coupling capacitance effect may occur between the high-level metal grids of the upper and lower chips, resulting in problems such as affecting the transmission quality of clock signals, signal distortion, and abnormal clock synchronization. Through the design of the contact points of metal bonding (corresponding to the first contact point of the first chip and the second contact point of the second chip) and the metal bonding pillars, the vertical connection points are transformed into direct point-to-point connections, which can avoid the use of metal traces, thereby reducing the coupling capacitance effect and improving the quality of clock signals. Further, the structure of the connection method of metal bonding is relatively simple, the cost is low, and it can be arranged in a high density. Furthermore, by increasing the number of contact points (the first contact point and the second contact point) of metal bonding, the clock load corresponding to the clock signal can be effectively dispersed, further reducing the capacitance effect and improving the transmission performance of the clock signal.

[0182] Of course, the embodiments of the present application can also support face-to-back connection. Correspondingly, the second contact point and the first contact point are connected by TSV ( Figure 6B An example of the connection of the contact points). In a specific example, for the bottom chip and the upper chip using face-to-back connection, the first contact point in the encrypted clock grid area of the bottom chip can be connected to the second contact point in the upper chip through TSV.

[0183] In a further optional implementation, a first contact point in the first chip can be correspondingly connected to a second contact point in the second chip. That is to say, the embodiments of the present application support the one-to-one connection between the first contact point and the second contact point. For example, a first contact point of the lower chip is connected to a corresponding second contact point of the upper chip to ensure the consistency of the clock grids of the upper and lower chips. Exemplarily, for the face-to-face connection of the first chip and the second chip, the embodiments of the present application support the one-to-one connection between the first contact point in the first chip and the second contact point in the second chip, and the one-to-one connection between the first contact point and the second contact point is realized through high-density metal bonding.

[0184] For the convenience of further understanding, taking the one-to-one connection of the contact points of a first chip and a second chip realized by metal bonding as an example, Figure 6C An exemplary diagram showing another connection example of the contact points is shown in combination with Figure 6B and Figure 6CAs shown, a first contact point 610 in a horizontal metal wire in the encrypted clock grid region of the first chip 601 is correspondingly connected to a second contact point 620 in the second chip 602 through a metal bonding post 631; that is to say, in this embodiment, the metal bonding post is the part for vertical connection between chips, responsible for transmitting the clock signal from the first contact point of the first chip to the correspondingly connected second contact point in the second chip in a metal bonding manner, ensuring one-to-one connection of the contact points between the first chip and the second chip and reducing signal interference. It should be noted that using metal bonding posts for cross-chip connection between contact points in a vertical connection manner can avoid the situation where metal traces may introduce a large coupling capacitance between the upper and lower layers of the upper and lower chips, thereby avoiding the degradation of the clock signal quality and improving the transmission quality of the clock signal.

[0185] In a further optional implementation, a first contact point in the first chip can be correspondingly connected to multiple second contact points in the second chip; that is to say, the embodiments of the present application support the corresponding connection of a first contact point to multiple second contact points. In an optional implementation, if the first chip and the second chip are connected in a face-to-back manner, chip-to-chip connection cannot be directly achieved through metal bonding and through-silicon vias (TSVs) are required to achieve chip-to-chip connection; that is, in a face-to-back connection, through-silicon vias are used for vertical signal transmission across chips. Since the layout cost of through-silicon vias is high and the density is low, if the one-to-one connection method of the first contact point and the second contact point is adopted, the number of through-silicon vias and the design cost will be significantly increased. Therefore, the embodiments of the present application support connecting a first contact point to multiple second contact points through through-silicon vias, thereby reducing the number of through-silicon vias and lowering the cost. Further, when achieving a one-to-many connection of the first contact point of the first chip and the second contact point of the second chip through through-silicon vias, the layout of the metal wires can be optimized to reduce additional coupling capacitance and signal loss.

[0186] In summary, in an optional implementation, for the face-to-face connection of the first chip and the second chip, the embodiments of the present application support the one-to-one connection of the first contact point and the second contact point and are connected through a metal bonding method, which has the characteristics of high density, low cost, and low capacitance; for the face-to-back connection of the first chip and the second chip, through-silicon vias are required to achieve cross-chip signal transmission. At this time, the embodiments of the present application support the one-to-many connection of the first contact point and the second contact point to reduce the number of through-silicon vias used, lower the cost, and optimize the clock signal sharing performance of the clock grid.

[0187] In a further alternative implementation, for 3D packaging of more than two layers of chips (such as 3D packaging of three layers of chips or 3D packaging of more than three layers of chips), that is, one first chip and at least two second chips, the embodiments of the present application support the hierarchical transmission of clock signals from the first chip to multiple second chips.

[0188] Exemplarily, taking the first chip as the bottom chip and multiple second chips stacked on top of the bottom chip as an example, in the implementation of hierarchical transmission of clock signals, the first contact point of the first chip transmits the clock signal to the corresponding second contact point connected in the adjacent second chip. Based on the face-to-face connection or back-to-back connection between the first chip and the second chip, the embodiments of the present application support one-to-one connection or one-to-many connection of the contact points between the first chip and the adjacent second chip; there is also a corresponding connection of the second contact points between adjacent second chips, that is, the second contact points of adjacent second chips, based on the inter-chip connection method (face-to-face connection or back-to-back connection), have one-to-one connection or one-to-many connection of the second contact points. Thus, adjacent second chips can transmit the clock layer by layer through the connected second contact points, realizing the hierarchical transmission of the clock signal from the bottom first chip to each upper second chip and achieving the sharing of the clock signal among all chips.

[0189] For ease of understanding, taking the 3D packaging of three layers of chips as an example, Figure 6D Exemplarily shows another connection example diagram of contact points, as Figure 6D shown, the first chip is the bottom chip 641 in the 3D packaging (the bottom chip is Figure 1 an example of a lower layer chip in an example), and two upper layer chips are stacked on top of the bottom chip. That is, there are two second chips in this example, specifically, two upper layer chips stacked on top of the bottom chip, which are divided into the middle layer chip 642 and the top layer chip 643;

[0190] The bottom chip 641 is adjacent to the middle layer chip 642 and adopts a face-to-face connection. The inter-chip connection can be realized through metal bonding points and metal bonding posts. Thus, the first contact point 610 of the bottom chip 641 uses the metal bonding post 631 to connect the second contact point 620 of the middle layer chip 642, and through a one-to-one connection method, one first contact point 610 of the bottom chip 641 corresponds to and connects one second contact point 620 of the middle layer chip 642 to enable the middle layer chip 642 to share the clock grid of the bottom chip 641;

[0191] The middle layer chip 642 and the top layer chip 643 are connected back-to-back, and cannot be directly connected by metal bonding. Therefore, through-silicon vias (TSVs) are required to transmit signals. As a result, for the clock signal of the bottom layer chip 641 to reach the top layer chip 643, it needs to go through multiple layers of connections. That is, the bottom layer chip 641 and the middle layer chip 642 are connected to the contact points through metal bonding pillars, and the middle layer chip 642 and the top layer chip 643 are connected to the contact points through the through-silicon via 160. Furthermore, a second contact point of the middle layer chip 642 is connected to multiple second contact points of the top layer chip 643 through the through-silicon via 160 (the contact points of each layer of chips are shown as the blackened parts in the figure). Thus, after the second contact point of the middle layer chip 642 obtains the clock signal transmitted by the first contact point of the bottom layer chip 641 through the metal bonding pillar 631, it is then transmitted to the second contact points connected in the top layer chip 643 through the through-silicon via 160, so as to indirectly share the clock grid of the bottom layer chip 641 by the top layer chip 643.

[0192] That is to say, in the implementation of the layer-by-layer transmission of the clock signal from the first chip to multiple second chips, for the 3D packaging of at least three layers of chips, the first contact point of the first chip is directly connected to the second contact point of the adjacent second chip (not limited to one-to-one connection or one-to-many connection, depending on the inter-chip connection method between the first chip and the adjacent second chip), so that the first contact point of the first chip can directly transmit the clock signal to the second contact point of the adjacent second chip; for the second chip that is not adjacent to the first chip, the first contact point of the first chip and the second contact point of the non-adjacent second chip are indirectly connected, that is, the first chip performs intermediate transmission of the clock signal through the intermediate second chip between it and the non-adjacent second chip, so as to achieve an indirect connection between the first contact point of the first chip and the second contact point of the non-adjacent second chip, and realize the indirect transmission of the clock signal to the second contact point of the non-adjacent second chip.

[0193] After the first contact point within the chip projection area of the first chip is connected to the second contact point within the second chip, the embodiment of the present application can transmit the clock signal from the first contact point to the second contact point (for example, the adjacent second chip of the first chip directly transmits the clock signal, and the non-adjacent second chip indirectly transmits the clock signal), so that the second contact point in the second chip can transmit the clock signal to the clock load in the second chip, realizing that at least one of the stacked multiple chips shares the clock grid of the first chip, and constructing the clock system provided by the embodiment of the present application.

[0194] After constructing the clock system, the embodiment of the present application can connect the first metal wire in the clock grid of the first chip to the clock load of the first chip; and connect the second contact point of the second chip to the clock load of the second chip to meet the clock signal requirements of the clock loads of the first chip and the second chip.

[0195] In an alternative implementation, Figure 7A An exemplary wiring example diagram of the clock load of the first chip (such as the lower-layer chip) is shown, in combination with Figure 7A As shown, the embodiments of the present application can adopt the principle of connecting nearby, and connect the clock load of the first chip to the first metal wire in the clock grid of the first chip nearby.

[0196] It should be noted that the clock grid of the first chip includes an encrypted clock grid area and may further include a general clock grid area. Whether it is for the encrypted clock grid area or the general clock grid area, the clock load of the first chip is connected to the nearest first metal wire nearby. At this time, the connection position of the first metal wire to which the clock load is connected may be located in the encrypted clock grid area or in the general clock grid area, depending on the distance between the clock load and the nearest first metal wire.

[0197] As Figure 7A shown, the clock load 711 of the first chip located in the encrypted clock grid area 501 is connected nearby to the first metal wire (which may be the initial first metal wire or a newly added first metal wire) in the encrypted clock grid area 501; the clock load 712 of the first chip located in the general clock grid area 502 is connected nearby to the first metal wire (the initial first metal wire) in the general clock grid area 502.

[0198] Each clock load (such as a register or a gating unit, etc.) of the first chip is directly connected to the nearest first metal wire (such as a horizontal metal wire) through the principle of connecting nearby, which can avoid too long or complex routing and ensure the shortest signal transmission path.

[0199] In an alternative implementation, the embodiments of the present application can determine the projection distance between the vertical projection point of the clock load of the first chip and the first metal wire (such as a horizontal metal wire), so as to use the first metal wire (such as a horizontal metal wire) corresponding to the minimum projection distance as the first metal wire (such as a horizontal metal wire) to which the clock load is connected nearby, in order to reduce the routing distance of the clock load, reduce the resistance and capacitance of the routing, and effectively reduce the delay and deviation of the clock signal.

[0200] Of course, connecting nearby is only an alternative implementation manner for the embodiments of the present application to connect the clock load of the first chip to the first metal wire. The embodiments of the present application can also support other connection manners, including but not limited to specified connection (the clock load is connected to a specified first metal wire), centralized connection (multiple clock loads are centrally connected to a certain first metal wire), etc.

[0201] In an alternative implementation, Figure 7BThe wiring diagram of the clock load of the second chip (such as the upper chip) is shown as an example. Figure 7B As shown, the embodiment of the present application can also adopt the principle of nearest connection to connect the clock load of the second chip to the second contact point of the second chip nearest to reduce the wiring length of the connection from the clock load of the second chip to the second contact point, thereby reducing the resistance and capacitance of the winding. For example, the clock load 721 of the second chip is nearest to the second contact point 620 of the second chip.

[0202] It should be noted that, in the second chip (such as the upper chip), since the second contact point is the projection point of the first contact point in the first chip, the clock load of the second chip needs to receive the clock signal transmitted by the first contact point of the first chip through the second contact point. Therefore, compared with the method of directly connecting to the first metal wire (such as the horizontal metal wire) of the clock grid of the first chip, the connection path of receiving the clock signal transmitted by the first contact point through the second contact point is longer, and there is a certain signal delay and quality loss; based on this, the embodiment of the present application should try to shorten the connection distance from the clock load of the second chip to the second contact point, so as to shorten the connection path of the clock load of the second chip through the second contact point and the first contact point, thereby improving the transmission performance of the clock signal. Therefore, the embodiment of the present application considers connecting the clock load of the second chip to the second contact point of the second chip as close as possible to shorten the above connection path.

[0203] Further, in order to further shorten the length of the connection path, the embodiment of the present application may also consider locally encrypting the first contact point to increase the density of the corresponding projected second contact point, thereby providing closer connection points for more clock loads of the second chip; for example, in the area where the clock loads of the second chip are dense, multiple clock loads may need to be connected to adjacent second contact points. If the spacing between the second contact points is too large, the winding paths of the clock loads may cross or extend each other, resulting in increased wiring complexity and signal interference. Therefore, the embodiment of the present application may consider locally encrypting the first contact points in the area where the clock loads of the second chip are dense in the projection area corresponding to the first chip, so that after the first contact points are projected to the second chip, the density of the projection points (i.e., the second contact points) in the area where the clock loads of the second chip are dense can be increased to shorten the winding distance between the clock loads of the second chip and the second contact points. For example, the embodiment of the present application may increase the density of the first contact points in the corresponding area of ​​the first chip according to the connection requirements of the clock loads in the area where the clock loads of the second chip are dense, so as to distribute the first contact points as densely as possible, so that the density of the second contact points corresponding to the projection to the second chip is increased, and then the connection length between the clock load and the nearest second contact point can be shortened as much as possible, optimizing the signal quality.

[0204] Based on this, in an alternative implementation, the area where the first metal wire sets the first contact points can be divided into a first contact point dense area and a first contact point non-dense area, and the density of the first contact points in the first contact point dense area is greater than that in the first contact point non-dense area; the first contact point dense area corresponds to the projected area of the clock load dense area of the second chip on the first chip; that is, for the projected area of the clock load dense area of the second chip on the first chip, for the part of the first metal wire in this projected area, the embodiments of the present application perform encryption processing (density increase processing) on the first contact points, thereby reducing the pitch of the first contact points and making the first contact points more dense; furthermore, the arrangement of the first contact points corresponding to the first contact point dense area projected onto the second contact points of the second chip can be more dense, and more and closer connectable second contact points can be provided for the clock load of the clock load dense area of the second chip.

[0205] Further, after constructing the clock system and connecting the clock loads, the embodiments of the present application can perform circuit simulation according to the RC values of all the path traces in the clock network, including: the path from the clock generation source to the ordinary clock buffer, and all the RC data of the wire winding of all the clock loads in the upper and lower chips; furthermore, according to the simulation results, parameters such as the pitch of the metal wires of the clock grid, the number of clock grid buffers, and the pitch of the contact points can be adjusted, or locally targeted adjustments can be made to achieve an optimized simulation result, and the design of the clock system can be adjusted accordingly to obtain optimized clock system performance. Among them, the RC value refers to the product of the resistance (R) and capacitance (C) in the circuit, that is, the time constant.

[0206] In an alternative implementation, circuit simulation is a performance evaluation method for the clock grid design provided by the embodiments of the present application, used to analyze the design performance of the clock network of the clock system and verify whether the design meets the preset indicators; the embodiments of the present application can use circuit simulation to evaluate the clock signal quality, including but not limited to clock signal delay and clock signal deviation, and then use the evaluated clock signal quality to determine whether the clock network designed by the clock system meets the performance requirements, such as whether it meets the threshold of clock signal delay and the threshold of clock signal deviation; if the clock network evaluated by the circuit simulation does not meet the performance requirements, such as the clock signal delay is greater than 2 ns (nanoseconds) or the clock signal deviation is greater than 5 ps (picoseconds), then it is necessary to return to the design stage of the clock system, adjust the design parameters of the clock grid such as the pitch of the metal wires of the clock grid, the number of clock grid buffers, and the pitch of the contact points, and perform circuit simulation again until the performance requirements are met.

[0207] In a further alternative implementation, the circuit simulation should cover the paths from the clock generation source to each clock load (the clock loads of the first chip and the second chip), including:

[0208] The path from the clock generation source to the clock grid buffer, such as the path from the clock generation source to multiple cascaded general clock buffers and then to each clock grid buffer (including each newly added clock grid buffer and each general clock grid buffer), as well as the resistance and capacitance information of the associated traces;

[0209] The path from the clock grid buffer to the clock grid metal layer, such as the path from the clock grid buffer to the first metal wire (such as a horizontal metal wire) it drives, as well as the resistance and capacitance information of the associated traces;

[0210] The connection path between the first contact point and the second contact point, such as the path of the first contact point and the second contact point connected by metal bonding or through - silicon via (TSV), as well as the associated resistance and capacitance information, which involves cross - chip clock signal transmission;

[0211] The connection path of the clock load of the chip, such as the connection path from the clock load of the second chip (such as the upper - layer chip) to the second contact point, and the connection path from the clock load of the first chip (such as the lower - layer chip) to the first metal wire (such as a horizontal metal wire).

[0212] Based on the above - mentioned paths from the clock generation source to each clock load, embodiments of this application determine the clock signal delay and clock signal deviation from each clock load to the clock generation source through circuit simulation. Thus, within the threshold range of the clock signal delay (such as within 2 ns), with the goal of minimizing the clock signal delay, and within the threshold range of the clock signal deviation (such as within 5 ps), with the goal of minimizing the clock signal deviation, iteratively adjust the design parameters of the clock grid, such as the spacing of the metal wires of the clock grid, the number of clock grid buffers, and the contact point spacing, until the above goals are met. Among them, the clock signal deviation from a clock load to the clock generation source is: the difference between the maximum clock signal delay and the minimum clock signal delay from this clock load to the clock generation source.

[0213] Specifically, the smaller the spacing between the metal wires of the clock grid, the higher the density of the metal wires of the clock grid. The resistance between the metal wires is in a parallel relationship, and the total resistivity is lower, resulting in reduced delay and faster clock signal propagation speed. However, too small a spacing between the metal wires will increase the consumption of metal resources and may affect the utilization rate of routing resources. The more the number of clock grid buffers, the stronger the driving force and the smaller the signal attenuation. However, too many clock grid buffers will increase the power consumption, and it is necessary to balance the relationship between the driving force and the power consumption. The smaller the contact point spacing, the shorter the connection path, and the smaller the resistance and capacitance of the wire winding. However, reducing the contact point spacing requires additional resources and may introduce signal interference problems in overly dense areas. Therefore, during the circuit simulation process, it is necessary to comprehensively consider the adjustment of different design parameters of the clock grid to ensure high-quality distribution and performance optimization of the clock signal while meeting the requirements.

[0214] In a further optional implementation, the clock signal skew is mainly affected by the imbalance of local delays. In the area with clock signal skew, the spacing between the metal wires of the clock grid can be reduced to reduce the signal delay in this area; or in the projection area of the first chip corresponding to the high-density clock load area of the second chip, the layout of the first contact points can be encrypted, so that the density of the corresponding projected second contact points increases, thereby shortening the connection path of the clock load of the second chip; or clock grid buffers can be added on the path with a large clock signal skew to enhance the driving force and reduce the delay; or the layout of the clock load can be adjusted to make its distribution more uniform and reduce the load concentration in the local area.

[0215] In the clock system finally constructed in the embodiment of the present application, the clock grid is only constructed on the first chip (such as the bottom chip), and the clock signal is transmitted to the second chip (such as the upper chip) through the first contact point array. Thus, the first chip and the second chip (such as the upper and lower chips) can share a three-dimensional clock grid, avoiding the need to separately construct a clock grid in the second chip (such as the upper chip) and simplifying the design complexity of the clock system.

[0216] Furthermore, the embodiment of the present application is applicable to the face-to-face packaging of the upper and lower chips. The direct connection between the contact points (between the first contact point and the second contact point) for transmitting the clock signal between the upper and lower chips is realized by using metal bonding, reducing the design cost and being suitable for cross-chip connection with high-density clock loads.

[0217] Furthermore, the embodiment of the present application is applicable to the face-to-back packaging of the upper and lower chips. The connection between the contact points (between the first contact point and the second contact point) for transmitting the clock signal between the upper and lower chips is realized by using through-silicon vias, and the connection range of the metal wires of the upper chip is extended through the one-to-many connection between the first contact point and the second contact point, thereby being applicable to the case of complex multi-layer chip stacking.

[0218] Of course, using the first chip as the bottom chip is only an optional implementation. Among multiple stacked chips, as long as the chip area of the second chip is less than or equal to that of the first chip and there is a projection area on the first chip, the first chip can be used as the clock master chip. By constructing an encrypted clock grid buffer array, the clock loads of other chips can be uniformly driven. At this time, the first chip can be any layer chip with the largest chip area in a multi-layer chip package. Of course, if the chip areas of multiple stacked chips are equal, any layer of chip can be used as the first chip, not necessarily the bottom layer chip, so that the clock grid can be set on any layer of chip. For example, the clock grid can be arranged on the middle layer chip, and clock signals can be distributed to the bottom chip and the top chip through through-silicon vias (TSVs).

[0219] Furthermore, from the perspective of the structure of the clock system provided by the embodiments of the present application, in combination with Figure 6B and Figure 6C as shown, the clock system provided by the embodiments of the present application may include:

[0220] A clock grid located on the first chip 601, the clock grid at least includes an encrypted clock grid area 501, the encrypted clock grid area corresponds to the chip projection area of the second chip 602 on the first chip, and the clock grid density of the encrypted clock grid area is higher than the clock grid density when the clock grid is initially constructed. Among them, a plurality of first contact points are provided on the first metal wire of the encrypted clock grid area, and the first metal wire is used to connect the clock load of the first chip to transmit the clock signal to the clock load of the first chip;

[0221] A plurality of second contact points located on the second chip 602, the second contact points are connected to the first contact points to obtain the clock signal transmitted by the first contact points, and the second contact points are used to connect the clock load of the second chip.

[0222] It can be seen that the clock system provided by the embodiments of the present application is applied to a chip system having multiple chips stacked on top of each other, and the chip area of the second chip among the multiple chips is less than or equal to that of the first chip; thus, the clock grid of the clock system is located on the first chip, and the clock grid area corresponding to the chip projection area of the first chip of the second chip is an encrypted clock grid area where the clock grid density is increased, that is, the density of the clock grid corresponding to the chip projection area of the second chip on the first chip is increased; furthermore, a plurality of first contact points are provided on the first metal wire connecting the clock load in the encrypted clock grid area, and the second chip is provided with second contact points corresponding to the first contact points. Thus, by connecting the second contact points to the first contact points, the second contact points can obtain the clock signal transmitted by the first contact points and transmit the clock signal to the clock load of the second chip connected to the second contact points. That is to say, in the second chip, the second contact points are responsible for distributing the clock signal transmitted from the first contact points to the clock load of the second chip to realize that the second chip shares the clock signal provided by the clock grid of the first chip. Therefore, the clock system provided by the embodiments of the present application can greatly simplify the design complexity of the clock system and improve the performance of the clock system by increasing the density design of the clock grid in the chip projection area of the second chip in the first chip and using the first contact points of the first metal wire in the encrypted clock grid area with increased density and the second contact points corresponding to the second chip to transmit the clock signal across chips.

[0223] Specifically, the second chip realizes sharing the clock signal provided by the clock grid of the first chip by setting second contact points connected to the first contact points, without the need to set a complex clock grid in the second chip, which can greatly simplify the design of the clock grid; moreover, the clock signal is transmitted between the first chip and the second chip through the connection of the first contact points and the second contact points. The path for the contact points to transmit the clock signal is short and the loss is low, ensuring the integrity and correct timing of the clock signal transmitted across chips and improving the performance of the clock system.

[0224] For the further structure of the clock system, reference can be made to the foregoing description and will not be elaborated here.

[0225] Next, an example will be given to illustrate the timing of the clock system provided by the embodiments of the present application to illustrate the clock signal quality advantage of the clock system provided by the embodiments of the present application in transmitting the clock signal across chips.

[0226] As an optional implementation, Figure 8 Exemplarily, an example diagram of sharing the clock signal across chips of the clock system provided by the embodiments of the present application is shown, in combination with Figure 3B and Figure 8As shown in the figure, taking the first chip as the lower-layer chip 120 and the second chip as the upper-layer chip 110 as an example, the clock grid buffer array 323 within the chip projection area of the lower-layer chip 120 is encrypted, and multiple first contact points 610 are provided on the horizontal metal wires; at the same time, the upper-layer chip 110 does not need to set a clock grid buffer array, but instead, based on the projection points of the first contact points 610 on the second chip, multiple second contact points 620 are set, and the first contact points and the second contact points are connected by metal bonding posts 631; thus, the clock signal path of the lower-layer chip 120 is: clock generation source 240 → general clock network 322 of the lower-layer chip → clock grid buffer array 323 of the lower-layer chip → start register 321 of the lower-layer chip;

[0227] The clock signal path of the upper-layer chip 120 is: clock generation source 240 → general clock network 322 of the lower-layer chip → clock grid buffer array 323 of the lower-layer chip → first contact point 610 → metal bonding post 631 → second contact point 620 → terminal register 313 of the upper-layer chip;

[0228] It can be seen that the clock signal path of the upper-layer chip 120 shares a part with that of the lower-layer chip 110, avoiding an additional clock path, and can reduce clock latency; that is to say, the clock loads of the upper and lower-layer chips share the same grid structure, reducing the latency variation of different paths and minimizing the impact of the variation deviation on the clock synchronization performance.

[0229] The clock system provided by the embodiment of the present application constructs a three-dimensional clock grid structure. Among them, the first chip (such as the lower-layer chip) constructs a complete clock grid, and the second chip (such as the upper-layer chip) shares the clock grid of the first chip (such as the lower-layer chip). Through the clock grid buffer array with increased density in the chip projection area of the first chip (such as the lower-layer chip), the clock load of the entire chip system is driven, greatly simplifying the design of the clock system, improving the performance of the clock system, and at the same time reducing power consumption. Especially in the face-to-face type 3D package, the embodiment of the present application can utilize the high density and low coupling capacitance characteristics of metal bonding to achieve the goal of efficiently and low-latency cross-chip transmission of clock signals, reducing the interference of cross-chip clock signal transmission, and further improving the performance of clock signals.

[0230] Furthermore, the embodiment of the present application also provides a chip system, including:

[0231] A plurality of stacked chips, the plurality of chips including a first chip and at least one second chip, and the chip area of the second chip is less than or equal to that of the first chip;

[0232] And a clock system, which is the clock system provided by the embodiment of the present application.

[0233] Among them, the clock load of the first chip is connected to (for example, proximally connected to) the first metal wire of the clock grid of the clock system, and the clock grid is located in the first chip; the clock load of the second chip is connected to (for example, proximally connected to) the second contact point of the second chip, and the second contact point is connected to the first contact point provided on the first metal wire of the encrypted clock grid area of the clock grid.

[0234] The relevant structure of the clock system can be referred to the previous description and will not be elaborated here.

[0235] Furthermore, the embodiment of the present application further provides a design device, which can be regarded as a functional module required for a design device (any computer device that can be used by chip designers for chip design) to implement the design method provided by the embodiment of the present application. The following description can be correspondingly referred to the above description.

[0236] As an alternative implementation, Figure 9 Exemplarily shows an optional block diagram of the design device provided by the embodiment of the present application. Refer to Figure 9 , the device may include:

[0237] A chip determination module 910, configured to determine a first chip and at least one second chip among a plurality of stacked chips, wherein the chip area of the second chip is less than or equal to that of the first chip;

[0238] A clock grid preliminary construction module 920, configured to preliminarily construct a clock grid on the first chip;

[0239] A chip projection area determination module 930, configured to determine the chip projection area corresponding to the second chip on the first chip;

[0240] A density increase module 940, configured to increase the density of the clock grid within the chip projection area to form an encrypted clock grid area;

[0241] A first contact point determination module 950, configured to set a first contact point for transmitting a clock signal to the second chip on the first metal wire within the encrypted clock grid area, to obtain a plurality of first contact points within the encrypted clock grid area; the first metal wire is used to connect the clock load of the first chip;

[0242] A second contact point determination module 960, configured to determine the second contact points corresponding to the first contact points within the encrypted clock grid area on the second chip, to obtain a plurality of second contact points within the second chip; the second contact points are used to connect the clock load of the second chip;

[0243] A connection configuration module 970, configured to connect the first contact points and the second contact points.

[0244] As an alternative implementation, the density increasing module 940 is used to increase the density of the clock grid within the chip projection area, and forming an encrypted clock grid area includes:

[0245] Increase the density of the clock grid metal layer within the chip projection area to add intersection points of the clock grid within the chip projection area, obtaining newly added intersection points;

[0246] Place newly added clock grid buffers at the newly added intersection points to form an encrypted clock grid area.

[0247] As an alternative implementation, the density increasing module 940 is used to increase the density of the clock grid metal layer within the chip projection area to add intersection points of the clock grid within the chip projection area, and obtaining newly added intersection points includes:

[0248] Add a first metal wire and / or a second metal wire within the chip projection area to add newly added intersection points of the clock grid within the chip projection area;

[0249] Wherein, the clock grid is composed of a first metal wire, a second metal wire, and clock grid buffers placed at the intersection points of the first metal wire and the second metal wire. The first metal wire is used to connect clock loads, and the second metal wire is used to support the grid structure of the clock grid.

[0250] In an alternative implementation, the number of the newly added first metal wires and / or the newly added second metal wires has a positive correlation with the number of the at least one second chip.

[0251] In an alternative implementation, the initially constructed clock grid includes an initial first metal wire, an initial second metal wire, and an initial clock grid buffer located at the intersection point of the initial first metal wire and the initial second metal wire;

[0252] The newly added intersection points include:

[0253] Newly added intersection points of the newly added first metal wire and the initial second metal wire, and / or newly added intersection points of the newly added first metal wire and the newly added second metal wire, and / or newly added intersection points of the initial first metal wire and the newly added second metal wire.

[0254] In an alternative implementation, the density increasing module 940 is used to add a first metal wire within the chip projection area to add newly added intersection points of the clock grid within the chip projection area, and includes:

[0255] For adjacent initial first metal wires within the chip projection area, between the adjacent initial first metal wires, at intervals corresponding to the reduction ratio, add first metal wires to form newly added intersection points of the newly added first metal wire and the initial second metal wire;

[0256] Wherein, the reduction ratio is the ratio of the reduced pitch between the first metal wires in the encrypted clock grid region to the initial pitch between the initial first metal wires; and the reduction ratio has a negative correlation with the number of the at least one second chip.

[0257] In an alternative implementation, the first contact point determination module 950 for setting, for the first metal wires in the encrypted clock grid region, first contact points for transmitting clock signals to the second chip includes:

[0258] Determining the contact point pitch, and setting first contact points on the first metal wires at the contact point pitch, such that the first contact points are evenly spaced on the first metal wires;

[0259] Wherein, the contact point pitch is determined based on the clock load distribution of the second chip and the routing of the clock load of the second chip to the first metal wires in the encrypted clock grid region, so that the clock delay and clock skew of the clock signal reaching each clock load of the second chip meet the set design requirements.

[0260] In an alternative implementation, the first contact point determination module 950 for setting, for the first metal wires in the encrypted clock grid region, first contact points for transmitting clock signals to the second chip further includes:

[0261] Dividing the region where the first contact points are set on the first metal wires into a first contact point dense region and a first contact point non-dense region; wherein, the first contact point dense region corresponds to the projection region of the clock load dense region of the second chip on the first chip;

[0262] Increasing the first contact point density of the first contact point dense region, such that the first contact point density of the first contact point dense region is greater than that of the first contact point non-dense region.

[0263] In an alternative implementation, the connection configuration module 970 for connecting the first contact points to the second contact points includes:

[0264] Connecting one first contact point to one second contact point correspondingly;

[0265] Or, connecting one first contact point to multiple second contact points correspondingly.

[0266] In an alternative implementation, the connection configuration module 970 for connecting one first contact point to one second contact point correspondingly includes: when the first chip and the second chip are connected face to face, connecting one first contact point to one second contact point correspondingly through metal bonding.

[0267] In an alternative implementation, the connection configuration module 970 for correspondingly connecting one first contact point to a plurality of second contact points includes: when the first chip and the second chip are connected back-to-back, correspondingly connecting one first contact point to a plurality of second contact points through through-silicon vias.

[0268] In an alternative implementation, the at least one second chip includes a plurality of second chips stacked on top of the first chip; the connection configuration module 970 for connecting the first contact point to the second contact point includes:

[0269] For the first chip and an adjacent second chip, connecting the first contact point to the second contact point of the adjacent second chip in a one-to-one connection or a one-to-many connection of the first contact point and the second contact point;

[0270] For the first chip and a non-adjacent second chip, performing intermediate transmission of a clock signal through an intermediate second chip to indirectly connect the first contact point to the second contact point of the non-adjacent second chip, wherein the second contact points between adjacent second chips are connected, and are connected in a one-to-one connection or a one-to-many connection of the second contact point and the second contact point.

[0271] In an alternative implementation, the design device provided in the embodiments of the present application can also be used for:

[0272] After forming an encrypted clock grid region, on the first chip, constructing a clock generation source and a general clock network for the clock grid; the clock generation source generates a clock signal, and the general clock network includes a plurality of cascaded general clock buffers and a general clock network metal layer for transmitting the clock signal;

[0273] Wherein, the clock signal generated by the clock generation source is signal-enhanced through a plurality of cascaded general clock buffers and transmitted through the general clock network metal layer to be transmitted to each clock grid buffer of the clock grid.

[0274] In an alternative implementation, the design device provided in the embodiments of the present application can also be used for: connecting the clock load of the first chip to the first metal wire of the clock grid in the vicinity; connecting the clock load of the second chip to the second contact point in the vicinity.

[0275] In an alternative implementation, the design device provided in the embodiments of the present application can also be used for:

[0276] After connecting the clock load of the first chip to the first metal wire in the vicinity and connecting the clock load of the second chip to the second contact point in the vicinity, based on the paths from the clock generation source to the respective clock loads, the clock signal quality is evaluated using circuit simulation; using the evaluated clock signal quality, it is determined whether the clock network meets the performance requirements; if the clock network does not meet the performance requirements, the design parameters of the clock grid are iteratively adjusted until the clock grid meets the performance requirements.

[0277] In an alternative implementation, the chip area of the second chip is smaller than that of the first chip; the area of the clock grid in the non-chip projection area of the first chip is the ordinary clock grid area, and the clock grid density of the encrypted clock grid area is higher than that of the ordinary clock grid area;

[0278] Among them, the ordinary clock grid area includes: the initial first metal wire, the initial second metal wire of the clock grid in the non-chip projection area, and the initial clock grid buffer located at the initial intersection of the initial first metal wire and the initial second metal wire.

[0279] The embodiments of the present application further provide a design device for executing the design method provided by the embodiments of the present application. This design device can be any computer device for chip design that can be used by chip designers, and is not limited to terminal devices or server devices; in an alternative implementation, the design device may include: a memory and a processor. The memory stores one or more computer-executable instructions, and the processor calls the one or more computer-executable instructions to execute the design method provided by the embodiments of the present application.

[0280] The embodiments of the present application further provide a storage medium storing computer-executable instructions, and when the computer-executable instructions are executed (such as when executed by a processor), the design method provided by the embodiments of the present application is implemented.

[0281] The embodiments of the present application further provide a computer program product including computer-executable instructions, and when the computer-executable instructions are executed (such as when executed by a processor), the design method provided by the embodiments of the present application is implemented.

[0282] The above describes multiple embodiment solutions provided by the embodiments of the present application. The various alternative ways described in each embodiment solution can be combined and cross-referenced with each other without conflict, thereby extending multiple possible embodiment solutions, and all of these can be considered as the embodiment solutions disclosed and made public by the embodiments of the present application.

[0283] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A clock system, characterized in that: Applied to a chip system, the chip system comprises a plurality of stacked chips, the plurality of chips comprises a first chip and at least one second chip, the chip area of ​​the second chip is smaller than or equal to the first chip; The clock system comprises: A clock grid located in the first chip, the clock grid at least comprising an encrypted clock grid area, the encrypted clock grid area corresponding to the chip projection area of ​​the second chip on the first chip, and the clock grid density of the encrypted clock grid area is higher than the clock grid density when the clock grid is initially constructed; wherein a first metal wire in the encrypted clock grid area is provided with a plurality of first contact points, and the first metal wire is used to connect the clock load of the first chip; A plurality of second contact points are located on the second chip, the second contact points are connected to the first contact points to obtain the clock signal transmitted by the first contact points, and the second contact points are used to connect the clock load of the second chip.

2. The clock system according to claim 1, characterized in that: The encrypted clock grid area is provided with an initial clock grid buffer and a newly added clock grid buffer, the initial clock grid buffer is located at an initial intersection of the encrypted clock grid area, and the newly added clock grid buffer is provided at a newly added intersection of the encrypted clock grid area.

3. The clock system according to claim 2, characterized in that: The initial intersection point is an intersection point of an initial first metal wire and an initial second metal wire of the clock grid within the chip projection area when the clock grid is initially constructed; The newly added intersections are newly added intersections corresponding to newly added first metal wires and / or newly added second metal wires added to the clock grid within the chip projection area after the clock grid is initially constructed; The clock grid is composed of a first metal wire, a second metal wire, and a clock grid buffer placed at the intersection of the first metal wire and the second metal wire. The first metal wire is used to connect the clock load, and the second metal wire is used to support the grid structure of the clock grid.

4. The clock system according to claim 3, characterized in that: The encrypted clock grid area includes: The clock grid includes an initial first metal wire, an initial second metal wire, and an initial clock grid buffer corresponding to an initial intersection of the initial first metal wire and the initial second metal wire in the chip projection area; The clock grid adds a first metal conductor and / or adds a second metal conductor in the chip projection area; A newly added clock grid buffer corresponding to a newly added intersection of the newly added first metal wire and the initial second metal wire, and / or, a newly added clock grid buffer corresponding to a newly added intersection of the newly added first metal wire and the newly added second metal wire, and / or, a newly added clock grid buffer corresponding to a newly added intersection of the initial first metal wire and the newly added second metal wire.

5. The clock system according to claim 4, characterized in that: The number of the newly added first metal wires and / or the newly added second metal wires is positively correlated with the number of the at least one second chip.

6. The clock system according to claim 5, characterized in that: The newly added intersection is the intersection of the newly added first metal wire and the initial second metal wire; the newly added first metal wire is arranged between adjacent initial first metal wires at intervals corresponding to the reduction ratio; The reduction ratio is: the ratio of the reduced spacing between the first metal wires in the encrypted clock grid area to the initial spacing between the initial first metal wires; and the reduction ratio is negatively correlated with the number of the at least one second chip.

7. The clock system according to any one of claims 3 to 6, characterized in that: The initial first metal wires and the newly added first metal wires in the encrypted clock grid area are respectively provided with a plurality of first contact points.

8. The clock system according to claim 7, characterized in that: The first contact points of the first metal wire are distributed at equal intervals with a set contact point spacing; Among them, the contact point spacing is determined based on the clock load distribution of the second chip and the winding condition of the first metal wire from the clock load of the second chip to the encrypted clock grid area, so that the clock delay and clock deviation of the clock signal reaching each clock load of the second chip meet the set design requirements.

9. The clock system according to claim 7, characterized in that: The area where the first metal wire is provided with the first contact point is divided into a first contact point dense area and a first contact point non-dense area, and the first contact point density in the first contact point dense area is greater than that in the first contact point non-dense area; The first contact point dense area corresponds to the clock load dense area of ​​the second chip in the projection area of ​​the first chip.

10. The clock system according to any one of claims 3 to 6, characterized in that: The chip area of ​​the second chip is smaller than that of the first chip; the clock grid further comprises: a common clock grid area; the common clock grid area corresponds to the non-chip projection area of ​​the second chip on the first chip, and the clock grid density of the encrypted clock grid area is higher than the clock grid density of the common clock grid area; The common clock grid area includes: an initial first metal conductor, an initial second metal conductor of the clock grid in the non-chip projection area, and an initial clock grid buffer located at an initial intersection of the initial first metal conductor and the initial second metal conductor.

11. The clock system according to any one of claims 2 to 6, characterized in that: The second contact point is a projection point of the first contact point on the second chip.

12. The clock system according to claim 11, characterized in that: One first contact point is correspondingly connected to one second contact point, or one first contact point is correspondingly connected to multiple second contact points.

13. The clock system according to claim 12, characterized in that: The first chip and the second chip are connected face to face, and a first contact point is connected to a corresponding second contact point through metal bonding; Alternatively, the first chip and the second chip are connected in a face-to-back manner, and one first contact point is correspondingly connected to a plurality of second contact points through silicon vias.

14. The clock system according to claim 12, characterized in that: The at least one second chip comprises a plurality of second chips stacked on the first chip; The first chip is connected to an adjacent second chip by a one-to-one connection between a first contact point and a second contact point, or a one-to-many connection; The first chip and the non-adjacent second chip perform intermediate transmission of clock signals through the middle second chip, wherein the second contact points between adjacent second chips are connected and are connected in a one-to-one connection between the second contact points or a one-to-many connection.

15. The clock system according to claim 1, characterized in that: Also includes: A clock source and a common clock network located in the first chip; the clock source generates a clock signal, and the common clock network includes a plurality of cascaded common clock buffers and a common clock network metal layer for transmitting the clock signal; The clock signal generated by the clock source is enhanced by a plurality of cascaded common clock buffers and transmitted by a common clock network metal layer to be transmitted to each clock grid buffer of the clock grid.

16. The clock system according to any one of claims 3 to 6, characterized in that: The first metal wire is a horizontal metal wire, the second metal wire is a vertical metal wire, the first chip is a bottom chip among a plurality of stacked chips, and the at least one second chip is stacked on the bottom chip.

17. A chip system, characterized in that: include: A plurality of stacked chips, the plurality of chips comprising a first chip and at least one second chip, wherein the chip area of ​​the second chip is smaller than or equal to that of the first chip; And, a clock system as described in any one of claims 1-16.

18. The chip system according to claim 17, characterized in that: The clock load of the first chip is connected to the first metal conductor in the clock grid of the clock system, and the clock grid is located on the first chip; the clock load of the second chip is connected to the second contact point set on the second chip, and the second contact point is connected to the first contact point set in the first metal conductor in the encrypted clock grid area in the clock grid.

19. A design method, characterized in that: include: Determining a first chip and at least one second chip among a plurality of stacked chips, wherein a chip area of ​​the second chip is smaller than or equal to that of the first chip; Initially build the clock grid on the first chip; Determine a chip projection area of ​​the second chip corresponding to the first chip; Increase the density of the clock grid within the chip projection area to form an encrypted clock grid area; For the first metal wire in the encrypted clock grid area, a first contact point for transmitting a clock signal to the second chip is provided, so as to obtain a plurality of first contact points in the encrypted clock grid area; the first metal wire is used to connect the clock load of the first chip; Determine a second contact point corresponding to the first contact point in the encrypted clock grid area in the second chip, and obtain a plurality of second contact points in the second chip; the second contact point is used to connect the clock load of the second chip; Connect the first contact point to the second contact point.

20. The method according to claim 19, characterized in that The step of increasing the density of the clock grid in the chip projection area to form an encrypted clock grid area includes: Increasing the density of the clock grid metal layer in the chip projection area to add a new intersection point of the clock grid in the chip projection area to obtain a new intersection point; New clock grid buffers are placed at the newly added intersections to form an encrypted clock grid area.

21. The method according to claim 20, characterized in that The method of increasing the density of the clock grid metal layer in the chip projection area to add a new intersection point of the clock grid in the chip projection area includes: Adding a first metal wire and / or a second metal wire in the chip projection area to add a new intersection of the clock grid in the chip projection area; The clock grid is composed of a first metal wire, a second metal wire, and a clock grid buffer placed at the intersection of the first metal wire and the second metal wire. The first metal wire is used to connect the clock load, and the second metal wire is used to support the grid structure of the clock grid.

22. The method according to claim 21, characterized in that The number of the newly added first metal wires and / or the newly added second metal wires is positively correlated with the number of the at least one second chip.

23. The method according to claim 21, characterized in that The initially constructed clock grid includes an initial first metal conductor, an initial second metal conductor, and an initial clock grid buffer located at a cross point of the initial first metal conductor and the initial second metal conductor; The newly added intersections include: A newly added intersection point between the newly added first metal wire and the initial second metal wire, and / or a newly added intersection point between the newly added first metal wire and the newly added second metal wire, and / or a newly added intersection point between the initial first metal wire and the newly added second metal wire.

24. The method according to claim 23, characterized in that The step of adding a first metal wire in the chip projection area to add a new intersection of the clock grid in the chip projection area includes: For adjacent initial first metal wires within the chip projection area, a first metal wire is added between the adjacent initial first metal wires at intervals corresponding to the reduction ratio to form a new intersection between the new first metal wire and the initial second metal wire; The reduction ratio is: the ratio of the reduced spacing between the first metal wires in the encrypted clock grid area to the initial spacing between the initial first metal wires; and the reduction ratio is negatively correlated with the number of the at least one second chip.

25. The method according to claim 19, characterized in that The first metal wire in the encrypted clock grid area is provided with a first contact point for transmitting a clock signal to the second chip, and the plurality of first contact points in the encrypted clock grid area are obtained, including: Determine a contact point spacing, and set first contact points on the first metal wire at the contact point spacing so that the first contact points are distributed at equal intervals on the first metal wire; Among them, the contact point spacing is determined based on the clock load distribution of the second chip and the winding condition of the first metal wire from the clock load of the second chip to the encrypted clock grid area, so that the clock delay and clock deviation of the clock signal reaching each clock load of the second chip meet the set design requirements.

26. The method according to claim 25, characterized in that The first metal wire in the encrypted clock grid area is provided with a first contact point for transmitting a clock signal to the second chip, and obtaining a plurality of first contact points in the encrypted clock grid area also includes: Divide the area where the first metal wire sets the first contact point into a first contact point dense area and a first contact point non-dense area; wherein the first contact point dense area corresponds to the projection area of ​​the clock load dense area of ​​the second chip on the first chip; The first contact point density of the first contact point dense area is increased so that the first contact point density of the first contact point dense area is greater than that of the first contact point non-dense area.

27. The method according to claim 19, characterized in that The connecting the first contact point with the second contact point comprises: Connecting a first contact point to a corresponding second contact point; Alternatively, one first contact point is correspondingly connected to a plurality of second contact points.

28. The method according to claim 27, characterized in that The step of correspondingly connecting a first contact point to a second contact point comprises: When the first chip and the second chip are connected face to face, a first contact point is connected to a corresponding second contact point through metal bonding; The step of correspondingly connecting a first contact point to a plurality of second contact points comprises: When the first chip and the second chip are connected in a face-to-back manner, one first contact point is connected to a plurality of second contact points via through silicon vias.

29. The method according to claim 19, characterized in that The at least one second chip includes a plurality of second chips stacked on the first chip; and the connecting the first contact point with the second contact point includes: For a first chip and an adjacent second chip, the first contact point is connected to the second contact point of the adjacent second chip in a one-to-one connection or a one-to-many connection; For a first chip and a non-adjacent second chip, an intermediate transmission of a clock signal is performed through the intermediate second chip to indirectly connect the first contact point with the second contact point of the non-adjacent second chip, wherein the second contact points between adjacent second chips are connected and are connected in a one-to-one connection between the second contact points or a one-to-many connection.

30. The method according to claim 19, characterized in that After forming the encrypted clock grid region, the method further includes: On the first chip, a clock source and a common clock network are constructed for the clock grid; the clock source generates a clock signal, and the common clock network includes a plurality of cascaded common clock buffers and a common clock network metal layer for transmitting the clock signal; The clock signal generated by the clock source is enhanced by a plurality of cascaded common clock buffers and transmitted by a common clock network metal layer to be transmitted to each clock grid buffer of the clock grid.

31. The method according to claim 30, characterized in that Also includes: Connecting the clock load of the first chip to the first metal conductor of the clock grid; Connect the clock load of the second chip to the second contact point as close as possible.

32. The method according to claim 31, characterized in that Also includes: After the clock load of the first chip is connected to the first metal wire as close as possible, and the clock load of the second chip is connected to the second contact point as close as possible, the quality of the clock signal is evaluated using circuit simulation based on the path from the clock source to each clock load; Use the assessed clock signal quality to determine whether the clock network meets performance requirements; If the clock network does not meet the performance requirements, the design parameters of the clock grid are iteratively adjusted until the clock grid meets the performance requirements.

33. The method according to claim 23, characterized in that The chip area of ​​the second chip is smaller than that of the first chip; the area of ​​the clock grid in the non-chip projection area of ​​the first chip is a common clock grid area, and the clock grid density of the encrypted clock grid area is higher than the clock grid density of the common clock grid area; The common clock grid area includes: an initial first metal conductor, an initial second metal conductor of the clock grid in the non-chip projection area, and an initial clock grid buffer located at an initial intersection of the initial first metal conductor and the initial second metal conductor.

34. A design device, characterized in that include: A chip determination module, used to determine a first chip and at least one second chip among a plurality of stacked chips, wherein a chip area of ​​the second chip is smaller than or equal to that of the first chip; A clock grid preliminary construction module, used for preliminary construction of a clock grid in the first chip; A chip projection area determination module, used to determine a chip projection area corresponding to the second chip on the first chip; A density increasing module, used to increase the density of the clock grid within the chip projection area to form an encrypted clock grid area; A first contact point determination module is used to set a first contact point for transmitting a clock signal to a second chip for a first metal wire in the encrypted clock grid area, so as to obtain a plurality of first contact points in the encrypted clock grid area; the first metal wire is used to connect a clock load of the first chip; A second contact point determination module is used to determine a second contact point corresponding to a first contact point in the encrypted clock grid area in the second chip, and obtain a plurality of second contact points in the second chip; the second contact point is used to connect a clock load of the second chip; The connection configuration module is used to connect the first contact point with the second contact point.

35. A design device, characterized in that It comprises a memory and a processor, wherein the memory stores computer-executable instructions, and the processor calls the computer-executable instructions to execute the design method as described in any one of claims 19-33.

36. A storage medium, characterized in that The computer-executable instructions are stored, and when the computer-executable instructions are executed, the design method as described in any one of claims 19-33 is implemented.

37. A computer program product, characterized in that It comprises computer-executable instructions, which, when executed, implement the design method as described in any one of claims 19-33.

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