Sampling rate conversion device, chip and electronic equipment

Abstract

The invention provides a sampling rate conversion device, a chip and electronic equipment, and the device comprises a processor, a first path selector, a second path selector, at least two sampling rate converters (SRC), a data source module and a data output module, the processor is respectively connected with the data source module, the first path selector, the second path selector and the data output module; the at least two SRCs are respectively connected with the first path selector and the second path selector, the first path selector is further connected with the data source module, and the second path selector is further used for being connected with the data output module; the processor is used for determining a target SRC in the at least two SRCs according to an original data stream transmitted by the data source module, and controlling the first path selector and the second path selector to be communicated with the target SRC; and the target SRC is used for performing sampling rate conversion processing on the original data stream to obtain a target data stream, and outputting the target data stream through the data output module. The flexibility of sampling rate conversion can be improved.

Description

Technical Field

[0001] This application relates to the technical field of sampling rate conversion, and particularly to a sampling rate conversion device, a chip, and an electronic device. Background Art

[0002] In audio applications, there are scenarios where multiple sampling rates coexist. In order to match the inherent sampling rate of the target device or to meet specific sound quality requirements, it is necessary to perform sampling rate conversion on the acquired audio data.

[0003] The process of sampling rate conversion usually includes steps such as interpolation, filtering, and decimation. In related technologies, the resampling accuracy is improved by optimizing algorithms, or the implementation efficiency of sampling rate conversion is improved by optimizing filter design. However, the resampling accuracy or the implementation efficiency of resampling in the above methods is fixed. In actual applications, different audio application scenarios have different requirements for sampling rate conversion. In the face of complex and changeable audio application scenarios, the flexibility of the above methods is poor. Summary of the Invention

[0004] Embodiments of this application provide a sampling rate conversion device, a chip, and an electronic device, which are used to solve the problem of poor flexibility of existing sampling rate conversion methods.

[0005] In a first aspect, embodiments of this application provide a sampling rate conversion device, including:

[0006] A processor, a first path selector, a second path selector, at least two sampling rate converters SRC, a data source module, and a data output module, where

[0007] The processor is respectively connected to the data source module, the first path selector, the second path selector, and the data output module;

[0008] At least two SRCs are respectively connected to the first path selector and the second path selector. The first path selector is further connected to the data source module, and the second path selector is further used to be connected to the data output module;

[0009] The processor is used to determine a target SRC among at least two SRCs according to the original data stream transmitted by the data source module, and control the first path selector and the second path selector to be connected to the target SRC;

[0010] The target SRC is used to perform sampling rate conversion processing on the original data stream to obtain a target data stream, and output the target data stream through the data output module.

[0011] In a possible implementation manner, the SRC includes an upsampling module, a low-pass filter, and a downsampling module, where

[0012] The low-pass filter is connected to the upsampling module and the downsampling module respectively;

[0013] The upsampling module is used to perform upsampling processing on the original data stream to obtain an upsampled data stream;

[0014] The low-pass filter is used to perform low-pass filtering on the upsampled data stream to obtain a filtered data stream;

[0015] The downsampling module is used to perform downsampling processing on the filtered data stream to obtain a target data stream.

[0016] In a possible implementation, the number of low-pass filters is at least two, and at least two low-pass filters are connected in series.

[0017] In a possible implementation, at least two SRCs include a low-pass filter, and an upsampling module and a downsampling module corresponding to each SRC. Among them,

[0018] The low-pass filter is connected to the upsampling module and the downsampling module corresponding to each SRC respectively.

[0019] In a possible implementation, the data source module is specifically used to transmit the original data stream to be processed and data stream information to the processor. The data stream information includes the sampling rate, number of channels, bit width, and audio format of the original data stream;

[0020] The processor is specifically used to determine the target SRC among at least two SRCs according to the original data stream, and control the first path selector and the second path selector to communicate with the target SRC;

[0021] The data source module is also used to transmit the original data stream to the target SRC through the first path selector;

[0022] The target SRC is used to perform sampling rate conversion processing on the original data stream according to the data stream information to obtain a target data stream, and transmit the target data stream to the data output module through the second path selector;

[0023] The data output module is used to output the target data stream.

[0024] In a possible implementation, at least two SRCs include a hardware SRC and a software SRC. Among them,

[0025] The hardware SRC is an SRC implemented by a circuit;

[0026] The software SRC is an SRC implemented by software.

[0027] In a possible implementation, the processor is specifically used for:

[0028] Determine the sampling rate conversion requirement according to the original data stream;

[0029] According to the sampling rate conversion requirements, relevant parameters are determined. The relevant parameters include at least one of the following: signal-to-noise ratio (SNR), total harmonic distortion plus noise (THD+N), delay, frequency response, and computational complexity.

[0030] According to the relevant parameters, a target SRC is determined from the hardware SRC and the software SRC.

[0031] In a possible implementation, at least two SRCs include at least two scenario SRCs.

[0032] In a possible implementation, the processor is specifically configured to:

[0033] Determine a target scenario according to the original data stream;

[0034] Determine a target SRC from at least two scenario SRCs according to the target scenario;

[0035] Control the data output module to perform format conversion processing on the target data stream according to the target data stream.

[0036] In a second aspect, an embodiment of the present application provides a sampling rate conversion chip, including the sampling rate conversion device according to any one of the first aspect.

[0037] In a third aspect, an embodiment of the present application provides an electronic device, including the sampling rate conversion device according to any one of the first aspect.

[0038] In the sampling rate conversion device, chip, and electronic device provided by the embodiments of the present application, the processor is respectively connected to the data source module, the first path selector, the second path selector, and the data output module; at least two SRCs are respectively connected to the first path selector and the second path selector, the first path selector is further connected to the data source module, and the second path selector is further configured to be connected to the data output module; the processor is configured to determine a target SRC from at least two SRCs according to the original data stream transmitted by the data source module, and control the first path selector and the second path selector to be connected to the target SRC; the target SRC is configured to perform sampling rate conversion processing on the original data stream to obtain a target data stream, and output the target data stream through the data output module. By designing at least two SRCs, the processor can select a target SRC that matches the original data stream from at least two SRCs according to the sampling rate conversion requirements of the original data stream, and use the target SRC to perform sampling rate conversion processing on the original data stream, improving the flexibility of sampling rate conversion. Description of the Drawings

[0039] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0040] Figure 1 Schematic diagram of the application scenario provided by the embodiment of the present application;

[0041] Figure 2 Schematic diagram of the structure of the sampling rate conversion device provided by the embodiment of the present application;

[0042] Figure 3 Schematic architecture of SRC provided by the embodiment of the present application Figure 1 ;

[0043] Figure 4 Schematic architecture of SRC provided by the embodiment of the present application Figure 2 ;

[0044] Figure 5 Schematic structure of SRC provided by the embodiment of the present application Figure 1 ;

[0045] Figure 6 Schematic structure of SRC provided by the embodiment of the present application Figure 2 ;

[0046] Figure 7 Schematic structure of SRC provided by the embodiment of the present application Figure 3 ;

[0047] Figure 8 Schematic diagram of the sampling rate conversion example provided by the embodiment of the present application.

[0048] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0049] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] It should be noted that in the embodiments of the present application, some industry-existing solutions such as certain software, components, models, etc. may be mentioned. They should be regarded as exemplary, and their purpose is only to illustrate the feasibility in the implementation of the technical solution of the present application, but it does not mean that the applicant has already or necessarily used this solution.

[0051] Figure 1 This is a schematic diagram of the application scenario provided by the embodiment of the present application. Please refer to Figure 1 , which includes an input signal, a sample rate convertor (SRC), and an output signal. The sample rate convertor performs sample rate conversion processing on the input signal to obtain the output signal.

[0052] In audio applications, the input signal can be a Digital Versatile Disc (DVD) audio signal, a Frequency Modulation (FM) audio signal, an MP3 (MPEG Audio Layer III) audio signal, a call audio signal, an audio signal of a third-party device or a chip, etc., collected by an audio acquisition device.

[0053] The sample rate convertor can be a hardware SRC or a software SRC.

[0054] The output signal is the signal after sample rate conversion processing. The output signal corresponds to the input signal, and the sample rate of the output signal is different from that of the input signal.

[0055] In the related art, the resampling accuracy is improved by optimizing the algorithm, or the implementation efficiency of sample rate conversion is improved by optimizing the filter design. However, in the above methods, the resampling accuracy or the implementation efficiency of resampling is fixed, and the calculation process of the filter coefficients is more complex, and the hardware implementation area is larger. However, in practical applications, different audio application scenarios have different requirements for sample rate conversion. When facing complex and changeable audio application scenarios, the above methods have poor flexibility, and the hardware cost of module implementation is large.

[0056] In the embodiment of the present application, according to the original data stream, a target SRC that matches the original data stream can be selected from at least two SRCs, and the target SRC is used to perform sample rate conversion processing on the original data stream to obtain the target data stream. In the above process, when facing different sample rate conversion requirements, the SRC that best matches the sample rate conversion requirements can be selected from multiple SRCs for sample rate conversion, which improves the flexibility of sample rate conversion. And by designing multiple SRCs, the filter coefficients corresponding to each SRC are less, reducing the implementation cost of the sample rate conversion module.

[0057] The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0058] Figure 2The structural schematic diagram of the sampling rate conversion device provided by the embodiment of the present application is as follows. Figure 2 As shown, the device includes: a processor 21, a first path selector 22, a second path selector 23, at least two SRCs 24, a data source module 25, and a data output module 26.

[0059] Among them, the processor 21 is respectively connected to the data source module 25, the first path selector 22, the second path selector 23, and the data demand module 26; at least two SRCs 24 are respectively connected to the first path selector 22 and the second path selector 23, the first path selector 22 is further connected to the data source module 25, and the second path selector 23 is further used to be connected to the data output module 26; the processor 21 is used to determine a target SRC among at least two SRCs according to the original data stream transmitted by the data source module 25, and control the first path selector 22 and the second path selector 23 to be connected to the target SRC; the target SRC is used to perform sampling rate conversion processing on the original data stream to obtain a target data stream, and output the target data stream through the data output module 26.

[0060] The processor 21 can be responsible for executing control logic and algorithm calculations. For example, the processor 21 can be a central processing unit (CPU), an audio digital signal processor (ADSP), etc. The processor 21 is used to determine a target SRC among at least two SRCs 24 according to the original data stream, and control the first path selector 22 and the second path selector 23 to be connected to the target SRC. The processor can also control the data output module 26 to perform format conversion processing on the target data stream.

[0061] The path selector can be a kind of switching device, which is used to select a specific path among multiple input / output paths for data transmission. The first path selector 22 can be connected to the data source module 25 and the target SRC, and transmit the original data stream to the target SRC; the second path selector 23 can be connected to the target SRC and the data output module 26, and transmit the target data stream to the data output module 26.

[0062] At least two SRCs 24 can be a kind of digital signal processing device, which is used to perform sampling rate conversion processing on the original data stream, and each SRC has different sampling rate conversion capabilities or characteristics. The SRC can convert the sampling rate of the original data stream into a target sampling rate, and the sampling rate conversion process can include steps such as interpolation, filtering, and decimation.

[0063] At least two SRCs 24 may include a hardware SRC and a software SRC. Among them, the hardware SRC is an SRC implemented through a circuit; the software SRC is an SRC implemented through software, and the processor for running the software SRC may be a Digital Signal Processor (DSP), a Sensorhub type processor, etc. The chip implementation forms on which the hardware SRC and the software SRC depend may be a System on Chip (SOC) and its companion chips, a Microcontroller Unit (MCU), etc.

[0064] Optionally, at least two of the at least two SRCs 24 include at least two scenario SRCs. The scenario SRCs may be a call scenario SRC, a music playback scenario SRC, a recording scenario SRC, etc. The requirements for sample rate conversion of each scenario SRC are different, and each scenario SRC may be a hardware SRC or a software SRC.

[0065] The data source module 25 may be a device or component that provides the original data stream. The original data stream can be obtained in various ways. For example, ambient sound and voice input are collected through a microphone; audio data of other devices is received through Bluetooth or wireless technology; audio data of other devices is received through a wired connection; audio data is obtained through a network, such as an online music service, a radio station, etc.; audio data is obtained through a storage device, such as audio files in the internal storage of the device or an external Secure Digital Memory Card (SD) in formats such as MP3, Advanced Audio Coding (AAC), Free Lossless Audio Codec (FLAC), etc.; audio data received through FM technology, audio data decoded by an Application Processor (AP), etc. The data source module 25 is used to transmit the original data stream to be processed and the data stream information to the processor 21. The data stream information includes the sample rate, number of channels, bit width, and audio format of the original data stream.

[0066] The data output module 26 can be a component responsible for transmitting the target data stream to an external device or storage medium. For example, the data output module 26 can receive and process multimedia data such as digital audio and video. For example, the data output module can be a speaker, a display, a hard disk drive, etc. The data output module 26 is used to output the target data stream and perform format conversion processing on the target data stream. The format conversion processing can be encoding format conversion processing on the target data stream, etc. For example, converting uncompressed Pulse Code Modulation (PCM) audio to compressed formats such as MP3, AAC, FLAC, or converting audio in one compressed format to another compressed format.

[0067] The target SRC is the SRC among at least two SRCs 24 that is used to perform sampling rate conversion processing on the original data stream. The target SRC can be determined by the processor 21 according to the sampling rate conversion requirements of the original data stream.

[0068] The target data stream is the data stream after sampling rate conversion of the original data stream.

[0069] Next, the working process of the sampling rate conversion device will be described: The data source module 25 transmits the original data stream to be processed and data stream information to the processor 21. The data stream information includes the sampling rate, number of channels, bit width, and audio format of the original data stream. The processor 21 selects an SRC that matches the original data stream from at least two SRCs 24 as the target SRC, and controls the first path selector 22 and the second path selector 23 to be connected to the target SRC. The data source module transmits the original data stream to the target SRC through the first path selector 22. The target SRC performs sampling rate conversion processing on the original data stream according to the data stream information to obtain the target data stream, and transmits the target data stream to the data output module 26 through the second path selector 23. The data output module 26 outputs the target data stream and performs format conversion processing on the target data stream, such as adjusting the encoding format of the target data stream, etc.

[0070] The sampling rate conversion device provided by the embodiment of the present application has a processor connected to a data source module, a first path selector, a second path selector, and a data output module respectively; at least two SRCs are connected to the first path selector and the second path selector respectively, the first path selector is also connected to the data source module, and the second path selector is also used to be connected to the data output module; the processor is used to determine a target SRC from at least two SRCs according to the original data stream transmitted by the data source module, and control the first path selector and the second path selector to communicate with the target SRC; the target SRC is used to perform sampling rate conversion processing on the original data stream to obtain a target data stream, and output the target data stream through the data output module. By designing at least two SRCs, the processor can select a target SRC that matches the original data stream from at least two SRCs according to the sampling rate conversion requirements of the original data stream, and use the target SRC to perform sampling rate conversion processing on the original data stream, improving the flexibility of sampling rate conversion.

[0071] Based on any of the above embodiments, the sampling rate conversion device of the embodiment of the present application will be introduced in detail below with reference to the accompanying drawings.

[0072] Figure 3 It is a schematic architecture of the SRC provided by the embodiment of the present application Figure 1 As shown in 3, at least two SRCs 24 include a hardware SRC and a software SRC. For example, SRC 1 among at least two SRCs 24 is a hardware SRC, and SRC2 among at least two SRCs 24 is a software SRC. Among them, the hardware SRC is an SRC implemented by a circuit, and the software SRC is an SRC implemented by software.

[0073] The hardware SRC and the software SRC have different characteristics in terms of signal-to-noise ratio (SNR), total harmonic distortion plus noise (THD+N), delay, frequency response, computational complexity, etc.

[0074] Among them, SNR is used to measure the ratio of the useful signal to the noise signal in the target data stream. The higher the SNR, the better the audio auditory effect after sampling rate conversion.

[0075] THD+N is used to measure the difference between the original data stream and the target data stream, including the effects of harmonic distortion and noise. The lower the THD+N, the smaller the distortion and noise of the audio signal after sampling rate conversion.

[0076] Delay is used to measure the impact of the sampling rate conversion process on the transmission speed of the audio signal. The lower the delay, the smaller the impact of the sampling rate conversion process on the real-time performance of the audio signal.

[0077] The frequency response is used to measure the gain difference of the audio signal after sample rate conversion at different frequencies. A flat frequency response indicates that the audio signal after sample rate conversion is more realistic.

[0078] The computational complexity is used to measure the complexity of the conversion between the original sample rate and the target sample rate. The greater the computational complexity, the stronger the computational ability required for the sample rate conversion device. Among them, the original sample rate is the sample rate corresponding to the original data stream, and the target sample rate is the sample rate corresponding to the target data stream. When the ratio between the original sample rate and the target sample rate is not an integer multiple, the computational complexity is large; when the ratio between the original sample rate and the target sample rate is an integer multiple, the computational complexity is small.

[0079] Generally, the SNR of software SRC is lower, and the SNR of hardware SRC is higher; the THD+N of software SRC is larger, and the THD+N of hardware SRC is smaller; the delay of software SRC is longer, and the delay of hardware SRC is shorter; the frequency response of software SRC may have uneven problems, affecting the sound quality, and hardware SRC has a more flat frequency response; the computational ability of software SRC is generally weaker, and the computational ability of hardware SRC is stronger.

[0080] When at least two SRCs include a hardware SRC and a software SRC, the processor determines the target SRC between the hardware SRC and the software SRC according to the original data stream. The original data stream is subjected to sample rate conversion processing using the target SRC to obtain the target data stream.

[0081] The target SRC can be determined in the following way: The processor determines the sample rate conversion requirement according to the original data stream, and determines the relevant parameters according to the sample rate conversion requirement. The relevant parameters include at least one of the following: SNR, THD+N, delay, frequency response, computational complexity; the target SRC is determined between the hardware SRC and the software SRC according to the relevant parameters.

[0082] The processor analyzes the sample rate conversion requirement of the original data stream according to the original data stream, determines the values of the relevant parameters, and selects the SRC that best matches the relevant parameters of the original data stream among at least two SRCs as the target SRC.

[0083] For example, the requirements for sample rate conversion of the original data stream may include: high SNR requirement, small THD+N requirement, short delay requirement, high frequency response requirement, etc. Then the processor selects the SRC that can better meet the above requirements among at least two SRCs as the target SRC, and the target SRC can be a hardware SRC.

[0084] For example, when the original data stream needs to convert the sampling rate from 44.1 kHz to a series of sampling rates of 48 kHz (8 / 16 / 32 / 48 / 96 / 192 kHz), or from a series of sampling rates of 48 kHz to 44.1 kHz, the original sampling rate and the target sampling rate are not integer multiples, and the computational complexity of the sampling rate conversion is relatively large. Then, the processor selects the SRC with stronger processing power from at least two SRCs as the target SRC, and the target SRC can be a hardware SRC.

[0085] For example, when the original data stream needs to convert the sampling rate among a series of sampling rates of 44.1 kHz (11.025 / 22.05 / 44.1 / 88.2 / 176.4 kHz), or convert the sampling rate among a series of sampling rates of 48 kHz (8 / 16 / 32 / 48 / 96 / 192 kHz), the original sampling rate and the target sampling rate are integer multiples, and the computational complexity of the sampling rate conversion is relatively small. Then, the processor selects the SRC whose processing power can meet the current computational complexity from at least two SRCs as the target SRC, and the target SRC can be a software SRC.

[0086] In a possible implementation, at least two SRCs include at least two scenario SRCs. The scenario SRCs can be a call scenario SRC, a music playback scenario SRC, a recording scenario SRC, etc. The requirements for sampling rate conversion of each scenario SRC are different, and each scenario SRC can be a hardware SRC or a software SRC. The following specifically introduces the case where at least two SRCs include at least two scenario SRCs in conjunction with the accompanying drawings.

[0087] Figure 4 Schematic architecture of the SRC provided by the embodiment of the present application Figure 2 , where at least two SRCs 24 include multiple scenario SRCs. For example, SRC 1 in at least two SRCs 24 is a scenario 1 SRC, SRC 2 in at least two SRCs 24 is a scenario 2 SRC,..., and SRC n in at least two SRCs 24 is a scenario n SRC, where n is a positive integer greater than or equal to 2.

[0088] The sampling rate conversion characteristics of each scenario SRC are different, and the scenario SRC can be designed according to the specific requirements of different scenarios.

[0089] The scenario SRC can be designed by the following method: determine whether each application scenario is a software SRC or a hardware SRC, and then design the scenario SRC according to the scenario requirements and the device operating environment.

[0090] Based on the relevant parameters required for each scenario, it is possible to determine whether the current scenario is a hardware SRC or a software SRC. For example, in a voice call scenario, the requirements for SNR / THD+N are relatively low, while the requirements for latency are relatively high. Therefore, the SRC corresponding to the voice call scenario can be a software SRC. In a music playback scenario, the requirements for SNR / THD+N are relatively high, and there are no obvious requirements for latency. Therefore, the SRC for the music playback scenario can be a hardware SRC. In a recording scenario, the requirements for SNR / THD+N are relatively low, and there are no obvious requirements for latency. Therefore, the SRC corresponding to the recording call scenario can be a software SRC. In a scenario where software is further required to process the target data stream, the SRC corresponding to this scenario can be a software SRC.

[0091] Furthermore, the SRC for each scenario can be designed according to the specific requirements of the relevant parameters during the sampling rate conversion process in the current scenario and the operating environment of the device.

[0092] For example, in a call scenario, the sampling rate of the original data stream can be 8 / 16 / 32 / 48 kHz, etc. When performing sampling rate conversion, the requirements for SNR / THD+N are relatively low, while the requirements for latency are relatively high. Therefore, the SRC for the call scenario can be designed to have average computing power and SNR / THD+N performance, and have little impact on the real-time performance of sampling rate conversion for the target data stream.

[0093] For example, in a music playback scenario, the sampling rate of the original data stream can be 44.1 / 48 / 96 / 192 kHz, etc. When performing sampling rate conversion, the requirements for SNR / THD+N are relatively high, and there are no obvious requirements for latency. Therefore, the SRC for the music playback scenario can be designed to have average computing power, high SNR / THD+N performance, and average impact on the real-time performance of sampling rate conversion for the target data stream.

[0094] For example, in a recording scenario, the sampling rate of the original data stream can be 8 / 16 / 32 / 48 kHz, etc. When performing sampling rate conversion, the requirements for SNR / THD+N are relatively low, and there are no obvious requirements for latency. Therefore, the SRC for the recording scenario can be designed to have average computing power, average SNR / THD+N performance, and average impact on the real-time performance of sampling rate conversion for the target data stream.

[0095] For example, when the sampling rate conversion device is running on a processor with relatively strong processing capabilities, the number of software SRCs can be increased, and the number of hardware SRCs can be reduced. Using the idle computing power of the processor to run software SRCs can reduce the implementation area of the hardware SRC and optimize the implementation complexity of the sampling rate conversion device.

[0096] For example, in a low-power scenario, the number of hardware SRCs can be increased and the number of software SRCs can be reduced. The hardware SRC has the characteristic of low power consumption. In a low-power scenario, especially in a non-power-down area, using the hardware SRC for sample rate conversion can avoid the additional power consumption caused by frequently starting and stopping the SRC module.

[0097] When at least two of the SRCs include at least two scenario SRCs, the processor determines a target SRC from the at least two scenario SRCs according to the original data stream. The target SRC is used to perform sample rate conversion processing on the original data stream to obtain a target data stream.

[0098] The target SRC can be determined in the following manner: The processor determines a target scenario according to the original data stream, and selects the scenario SRC that best matches the current sample rate conversion requirement from the at least two scenario SRCs as the target SRC.

[0099] The sample rate conversion device provided by the embodiments of the present application designs at least two SRCs. The at least two SRCs include a hardware SRC and a software SRC, or the at least two SRCs include at least two scenario SRCs. The processor selects a target SRC that matches the original data stream from the at least two SRCs according to the original data stream, and uses the target SRC to perform sample rate conversion processing on the original data stream to obtain a target data stream, so that when facing different sample rate conversion requirements, the SRC that best matches the sample rate conversion requirement can be selected from multiple SRCs for sample rate conversion, improving the flexibility of sample rate conversion.

[0100] The structure of the SRC will be further introduced below with reference to the accompanying drawings.

[0101] Figure 5 Schematic structure of the SRC provided by the embodiments of the present application Figure 1 . As Figure 5 shown, for any one SRC, it includes: an upsampling module, a low-pass filter, and a downsampling module.

[0102] Among them, the low-pass filter is respectively connected to the upsampling module and the downsampling module; the upsampling module is used to perform upsampling processing on the original data stream to obtain an upsampled data stream; the low-pass filter is used to perform low-pass filtering processing on the upsampled data stream to obtain a filtered data stream; the downsampling module is used to perform downsampling processing on the filtered data stream to obtain a target data stream.

[0103] When the ratio of the original sampling rate corresponding to the original data stream to the target sampling rate corresponding to the target data stream is not an integer, a higher intermediate sampling rate needs to be used for conversion. That is, the original data stream is upsampled by a factor of L through an upsampling module, and then the filtered data stream is downsampled by a factor of M through a downsampling module to achieve an L / M fractional sampling rate conversion. Here, L and M are positive integers, and the ratio of the original sampling rate to the target sampling rate is the same as the ratio of L to M, i.e., original sampling rate / target sampling rate = L / M.

[0104] The upsampling process can be carried out as follows: The upsampling module determines the upsampling factor L based on the original sampling rate and the target sampling rate, and inserts L - 1 new data points between every two adjacent data points of the original data stream to obtain the upsampled data stream. The new data points can be calculated through linear interpolation, polynomial interpolation, window function interpolation, or other interpolation algorithms.

[0105] The low-pass filtering process can be carried out as follows: The low-pass filter determines the cut-off frequency based on the original sampling rate and the target sampling rate, removes the high-frequency part above the cut-off frequency, and retains the low-frequency part to obtain the filtered data stream.

[0106] The downsampling process can be carried out as follows: The downsampling module determines the downsampling factor M based on the original sampling rate and the target sampling rate, and extracts one data point from every M data points of the filtered data stream to obtain the target data stream. The downsampling module can also dynamically adjust the extraction interval according to the local characteristics (such as frequency, amplitude, etc.) of the filtered data stream to obtain the target data stream.

[0107] Figure 6 Schematic structure of the SRC provided by the embodiment of the present application Figure 2 As Figure 6 shown, for any SRC, it includes: an upsampling module, at least two low-pass filters, and a downsampling module. Among them, the number of low-pass filters is at least two, and the at least two low-pass filters are connected in series.

[0108] The processes of upsampling through the upsampling module and downsampling through the downsampling module are similar to the corresponding processes in Figure 5 and will not be elaborated here.

[0109] Furthermore, by connecting multiple low-pass filters in series, each low-pass filter can be optimized for different frequency ranges, and the output of the previous low-pass filter is used as the input of the next low-pass filter, which can further reduce aliasing noise, optimize the smoothness of the target data stream, and improve the audio quality after sampling rate conversion.

[0110] Figure 7 Schematic structure of the SRC provided by the embodiment of the present application Figure 3 AsFigure 7 As shown, it includes: an upsampling module, a low-pass filter, and a downsampling module. At least two SRCs include a low-pass filter, and an upsampling module and a downsampling module corresponding to each SRC. Among them, the low-pass filter is respectively connected to the upsampling module and the downsampling module corresponding to each SRC.

[0111] Each SRC has a corresponding upsampling module and a downsampling module. For example, SRC1 corresponds to upsampling module 1 and downsampling module 1, SRC2 corresponds to upsampling module 2 and downsampling module 2, and so on.

[0112] The processes of upsampling through the upsampling module and downsampling through the downsampling module in each SRC are similar to the corresponding processes in Figure 5 and will not be elaborated here.

[0113] Furthermore, the upsampling modules of each SRC are all connected to the same low-pass filter, which can optimize the utilization of hardware resources, reduce unnecessary repeated configurations, simplify the system design, and improve the efficiency of sampling rate conversion.

[0114] In a possible implementation manner, the SRC structures shown above Figure 5 、 Figure 6 and Figure 7 can be combined to further improve the flexibility of the sampling rate conversion device. For example, when the sampling rate conversion device includes four SRCs, the first SRC can be in the structure shown in Figure 5 , and use one low-pass filter to perform low-pass filtering on the upsampled data stream; the second SRC can be in the structure shown in Figure 6 , and use multiple low-pass filters to perform low-pass filtering on the upsampled data stream; the third SRC and the fourth SRC can be in the structure shown in Figure 7 , and share one low-pass filter to perform low-pass filtering on the upsampled data stream.

[0115] In each SRC, the filter coefficients can be generated based on interpolation techniques (such as linear interpolation, polynomial interpolation, etc.), or can be generated based on other techniques. The embodiments of the present application do not limit the generation method of the filter coefficients.

[0116] In each SRC, each filter can perform low-pass filtering on the upsampled data stream in a polyphase form, that is, each filter can be decomposed into multiple sub-filters, and each sub-filter processes a subset of the upsampled data stream.

[0117] In each SRC, the sample rate conversion process can be implemented synchronously, i.e., there is a fixed mathematical relationship (such as an integer multiple relationship) between the original sample rate and the target sample rate, or it can be implemented asynchronously, i.e., there is no fixed mathematical relationship between the original sample rate and the target sample rate.

[0118] Figure 8 It is a schematic diagram of the sample rate conversion example provided by the embodiments of this application. As Figure 8 shown, the sample rate conversion device is deployed in a TV chip. At least two SRCs include a call scenario SRC, a recording scenario SRC, a voice wake-up scenario SRC, and a playback scenario SRC. Among them, the call scenario SRC, the recording scenario SRC, and the voice wake-up scenario SRC are deployed on the processor, and the playback scenario SRC is deployed on the hardening module.

[0119] The processor in the TV chip has relatively strong capabilities, and the call scenario, the recording scenario, and the voice wake-up scenario have relatively low requirements for SNR / THD+N. Therefore, the call scenario SRC, the recording scenario SRC, and the voice wake-up scenario SRC are software SRCs and run on the processor; the playback scenario has relatively high requirements for SNR / THD+N, so the playback scenario SRC is a hardware SRC.

[0120] The processing processes of using the call scenario SRC, the recording scenario SRC, and the voice wake-up scenario SRC to perform sample rate conversion on the original data stream are similar. Taking the use of the call scenario SRC to perform sample rate conversion on the original data stream as an example, the sample rate conversion process is as follows: when the scenario SRC corresponding to the original data stream is the call scenario SRC, the processor controls the first path selector and the second path selector to connect to the call scenario SRC, sends the original data stream to the call scenario SRC, the call scenario SRC performs sample rate conversion processing on the original data stream to obtain the target data stream, and sends the target data stream to the data output module.

[0121] The process of using the playback scenario SRC to perform sample rate conversion processing on the original data stream is as follows: when the scenario SRC corresponding to the original data stream is the playback scenario SRC, the processor controls the first path selector and the second path selector to connect to the playback scenario SRC in the hardening module, sends the original data stream to the playback scenario SRC in the hardening module, the playback scenario SRC performs sample rate conversion processing on the original data stream to obtain the target data stream, and sends the target data stream to the processor. The processor controls the data output module to receive the target data stream.

[0122] The sampling rate conversion device provided by the embodiment of the present application has a processor connected to a data source module, a first path selector, a second path selector, and a data output module respectively; at least two SRCs are respectively connected to the first path selector and the second path selector, the first path selector is further connected to the data source module, and the second path selector is further used to be connected to the data output module; the processor is configured to determine a target SRC from at least two SRCs according to the original data stream transmitted by the data source module, and control the first path selector and the second path selector to be connected to the target SRC; the target SRC is used to perform sampling rate conversion processing on the original data stream to obtain a target data stream, and output the target data stream through the data output module. By designing at least two SRCs, the processor can select a target SRC that matches the original data stream from at least two SRCs according to the sampling rate conversion requirements of the original data stream, and use the target SRC to perform sampling rate conversion processing on the original data stream, improving the flexibility of sampling rate conversion.

[0123] The embodiment of the present application provides a chip, including the sampling rate conversion device, and the specific implementation manner and technical effect are similar to those shown in the above embodiment, and will not be elaborated here.

[0124] The embodiment of the present application provides an electronic device, including the sampling rate conversion device, and the specific implementation manner and technical effect are similar to those shown in the above embodiment, and will not be elaborated here.

[0125] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only to be considered as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0126] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

[0127] In the present application, "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article represents an "or" relationship between the front and back associated objects.

[0128] "At least one of the following" or a similar expression refers to any combination of these items, including any combination of a single item or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where each of a, b, and c can itself be an element or a set containing one or more elements.

[0129] "At least one" in this application means one or more. "Multiple" means two or more. The descriptions such as first, second, etc. that appear in the embodiments of this application are only for illustration and to distinguish the described objects, without an order, nor do they represent a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application. For example, the first threshold and the second threshold are only for distinguishing different thresholds, rather than indicating differences in the magnitudes, priorities, or importance levels of these two thresholds.

[0130] In this application, "exemplary", "in some embodiments", "in other embodiments", etc. are used to give examples, provide illustrations, or make explanations. Any embodiment or design solution described as "exemplary" in this application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of the word "exemplary" is intended to present concepts in a specific manner.

[0131] In this application, "(of)", "corresponding", "corresponding to", and "associated" can sometimes be used interchangeably. It should be noted that when not emphasizing their differences, the meanings they convey are the same. In the embodiments of this application, communication and transmission can sometimes be used interchangeably. It should be noted that when not emphasizing the differences, the meanings they convey are the same. For example, transmission can include sending and / or receiving, and can be a noun or a verb.

[0132] "Equal to" in this application can be used in combination with "less than" or with "greater than", but not simultaneously with both "less than" and "greater than". When "equal to" is used in combination with "less than", the technical solution adopted for "less than" applies. When "equal to" is used in combination with "greater than", the technical solution adopted for "greater than" applies.

[0133] Finally, it should be noted that: After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present invention. The present invention is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include well-known common general knowledge or conventional technical means in the technical field not disclosed in the present invention. It is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A sampling rate conversion device, characterized in that: include: A processor, a first channel selector, a second channel selector, at least two sampling rate converters SRC, a data source module and a data output module, wherein: The processor is respectively connected to the data source module, the first path selector, the second path selector and the data output module; The at least two SRCs are connected to the first path selector and the second path selector respectively, the first path selector is also connected to the data source module, and the second path selector is also used to connect to the data output module; The processor is used to determine a target SRC among the at least two SRCs according to the original data stream transmitted by the data source module, and control the first path selector and the second path selector to be connected to the target SRC; The target SRC is used to perform sampling rate conversion processing on the original data stream to obtain a target data stream, and output the target data stream through the data output module.

2. The device according to claim 1, characterized in that The SRC includes an up-sampling module, a low-pass filter and a down-sampling module, wherein: The low-pass filter is connected to the up-sampling module and the down-sampling module respectively; The up-sampling module is used to perform up-sampling processing on the original data stream to obtain an up-sampled data stream; The low-pass filter is used to perform low-pass filtering on the up-sampled data stream to obtain a filtered data stream; The down-sampling module is used to perform down-sampling processing on the filtered data stream to obtain the target data stream.

3. The device according to claim 2, characterized in that The number of the low-pass filters is at least two, and at least two low-pass filters are connected in series.

4. The device according to claim 2, characterized in that The at least two SRCs include a low-pass filter, and an up-sampling module and a down-sampling module corresponding to each SRC, wherein: The low-pass filter is respectively connected to the up-sampling module and the down-sampling module corresponding to each SRC.

5. The device according to any one of claims 1 to 4, characterized in that: The data source module is specifically used to transmit the original data stream to be processed and data stream information to the processor, wherein the data stream information includes the sampling rate, number of channels, bit width, and audio format of the original data stream; The processor is specifically configured to determine a target SRC among the at least two SRCs according to the original data stream, and control the first path selector and the second path selector to be connected to the target SRC; The data source module is also used to transmit the original data stream to the target SRC through the first path selector; The target SRC is used to perform sampling rate conversion processing on the original data stream according to the data stream information to obtain the target data stream, and transmit the target data stream to the data output module through the second path selector; The data output module is used to output the target data stream.

6. The device according to any one of claims 1 to 5, characterized in that: The at least two SRCs include a hardware SRC and a software SRC, wherein: The hardware SRC is an SRC implemented by a circuit; The software SRC is an SRC implemented by software.

7. The device according to claim 6, characterized in that The processor is specifically used for: According to the original data stream, determine the sampling rate conversion requirement; Determine relevant parameters according to the sampling rate conversion requirement, wherein the relevant parameters include at least one of the following: signal-to-noise ratio SNR, total harmonic distortion plus noise THD+N, delay, frequency response, and calculation amount; According to the relevant parameters, a target SRC is determined among the hardware SRC and the software SRC.

8. The device according to any one of claims 1 to 5, characterized in that: The at least two SRCs include at least two scene SRCs.

9. The device according to claim 8, characterized in that The processor is specifically used for: Determine a target scene according to the original data stream; According to the target scene, determining the target SRC in the at least two scenes SRC; According to the target data stream, the data output module is controlled to perform format conversion processing on the target data stream.

10. A chip, characterized in that: The invention comprises the sampling rate conversion device as described in any one of claims 1 to 9.

11. An electronic device, characterized in that: The invention comprises the sampling rate conversion device as described in any one of claims 1 to 9.

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