Sensitive amplifier
By increasing the gate voltage of M5 during the pre-charging stage of the sensitive amplifier and increasing the power supply voltage of the clamp circuit through the voltage characteristics across the capacitor, the problem of limited read access time of the traditional sensitive amplifier is solved, and high-speed reading and high-efficiency charging are achieved.
Patent Information
- Application Number
- CN202510372999.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2025-06-27
AI Technical Summary
The traditional voltage-mode sensitive amplifiers limit the voltage swing of the node MAT voltage due to the use of PMOS tubes connected to the diode on the memory cell branch, thereby limiting the read access time.
By utilizing the characteristic that the capacitance voltage cannot change suddenly in the pre-charging stage, the gate voltage of M5 is increased to 2VDD, and the current of M5 is increased, thereby accelerating the charging speed of Cb l. At the same time, through the principle that the voltage across the capacitor cannot suddenly change, the power supply voltage of M7 and M8 of the clamping circuit is increased, thereby increasing the gate voltage of M5 and M6.
High-speed reading of sensitive amplifiers is realized, which avoids the time waste that may be caused by the use of fixed precharge time, and overcomes the problem of reserved too long precharge time due to uncertain size of the bit line parasitic load capacitance.
Smart Images
Figure CN120220746A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of memory chip circuits, and specifically to a sense amplifier. Background Art
[0002] Flash Memory has been widely used due to its non-volatility, earthquake resistance, and low power consumption. Obviously, fast access and low power consumption are key requirements for Flash Memory. Especially with the increasing market demand for portable electronic devices, such as PDAs, mobile phones, etc., in order to reduce the power consumption of portable devices, the system operating voltage is getting lower and lower. Correspondingly, as one of the important peripheral circuits of Flash Memory, the Sense Amplifier also needs to meet the requirements of low voltage and high-speed reading. Currently, according to the comparison method of the reference current and the memory cell current, the sense amplifier can be roughly divided into two categories. One is the voltage-mode sense amplifier;
[0003] However, due to the use of PMOS transistors connected in diode form on the memory cell branch in the traditional voltage-mode sense amplifier, the voltage swing of the node MAT is limited, which further limits the read access time. Therefore, we propose a sense amplifier. Summary of the Invention
[0004] The purpose of the present invention is to provide a sense amplifier.
[0005] To achieve the above purpose, the present invention provides the following technical solution: A sense amplifier, the sense amplifier includes clamping devices M5, M7, M9, and PREB. The PREB is used to control the precharge signal. When PREB is ready to perform a read operation, it is represented as PREB = 1, and then it controls V(E) = 0, V(VDDH) = 0, and the voltage difference between the left and right of the capacitor C1 is VDD. The PREB performs current control on the clamping devices M5, M7, and M9.
[0006] As a further solution of the present invention: When PREB starts precharging, it means that when PREB = 0, the potential of V(E) rises, and due to the fact that the voltage difference across the capacitor cannot change suddenly, V(VDDH) = 2VDD.
[0007] As a further solution of the present invention: When PREB = 0, the gate voltage of M5 is 2VDD.
[0008] As a further solution of the present invention: When PREB = 0, the current of the clamping device M5 increases, thereby increasing the output of the Cbl current.
[0009] As a further solution of the present invention: the sense amplifier further includes V(DR). During the process of PREB = 0, when V(DR) is greater than the threshold voltage of M9, M5 is turned off to end the pre-operation.
[0010] As a further solution of the present invention: the sense amplifier further includes a capacitor, a clamping device M8, and a clamping device M6. By the principle that the voltage across the capacitor cannot change suddenly, the power supply voltages of the clamping devices M7 and M8 are increased, thereby increasing the gate voltages of the corresponding clamping devices M5 and M6.
[0011] Adopting the above technical solution, compared with the prior art, the beneficial effects of the present invention are as follows:
[0012] 1. In the pre-charging stage of the present invention, by utilizing the characteristic that the voltage across the capacitor cannot change suddenly, the gate voltage of M5 is increased to 2VDD, increasing the current of M5, thereby accelerating the charging speed of Cb l. Compared with the traditional pre-charging method, this design avoids the time waste that may be caused by using a fixed pre-charging time, and also overcomes the problem of reserving an overly long pre-charging time due to the uncertainty of the bit-line parasitic load capacitance and the need to consider many uncertain factors.
[0013] 2. By the principle that the voltage across the capacitor cannot change suddenly, the power supply voltages of M7 and M8 in the clamping circuit are increased in the present invention, thereby increasing the gate voltages of M5 and M6, increasing the opening degree of the channel, accelerating the pre-charging speed, and realizing the high-speed reading of the sense amplifier.
[0014] Other advantages, objectives, and features of the present invention will be described to some extent in the subsequent specification, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 It is the circuit diagram of the sense amplifier in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0016] The following further describes the specific embodiments of the present invention with reference to the drawings. It should be noted here that the description of these embodiments is for helping to understand the present invention, but does not limit the present invention.
[0017] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0018] Embodiment 1:
[0019] Please refer to the attachedFigure 1 , a sense amplifier according to the present invention, the sense amplifier includes clamping devices M5, M7, M9 and a PREB signal for controlling a precharge signal. PREB is used to control the precharge signal. PREB is ready for a read operation, expressed as PREB = 1, and further controls V(E) = 0, V(VDDH) = 0. The voltage difference between the left and right of capacitor C1 is VDD. PREB performs current control on clamping device M5, clamping device M7, and clamping device M9.
[0020] Specific working process: Precharge preparation stage (PREB = 1) When the PREB signal is 1 and the circuit is in a state ready for a read operation, the node voltages V(E) = 0, V(VDDH) = 0, and a voltage difference of VDD is formed across capacitor C1. This stage sets the initial conditions for subsequent precharge operations. Precharge stage (PREB = 0) Voltage change and increase in the gate voltage of M5 When PREB becomes 0, precharge starts, and the voltage of V(E) becomes VDD. Since the voltage difference across the capacitor cannot change abruptly, the voltage of V(VDDH) associated with the capacitor becomes 2VDD. This voltage change causes the gate voltage of M5 in the clamping device to reach 2VDD. Charging process After the gate voltage of M5 rises to 2VDD, its current becomes larger. This larger current charges Cb l (bit line capacitor), causing the voltage at the DR point to rise rapidly. End judgment of precharge As the charging process progresses, when V(DR) is greater than the threshold voltage of M9, M5 turns off and the precharge operation ends.
[0021] Furthermore, based on the principle that the voltage across the capacitor cannot change abruptly, the power supply voltages of M7 and M8 in the clamping circuit are increased, thereby increasing the gate voltages of M5 and M6, increasing the channel opening degree, accelerating the precharge speed, and achieving high-speed reading of the sense amplifier.
[0022] Embodiment 2:
[0023] Based on Embodiment 1, please refer to the appendix Figure 1As shown, when PREB starts precharging, it means that when PREB = 0, V(E) = VDD. And due to the fact that the voltage difference across the capacitor cannot change abruptly, V(VDDH) = 2VDD. When PREB = 0, the gate voltage of M5 is 2VDD. When PREB = 0, the current of the clamping device M5 increases, thereby increasing the output of the Cb l current. The sense amplifier also includes V(DR). During the process when PREB = 0, when V(DR) is greater than the threshold voltage of M9, M5 is turned off and the pre-operation ends. The sense amplifier also includes a capacitor, a clamping device M8, and a clamping device M6. By the principle that the voltage across the capacitor cannot change abruptly, the power supply voltages of the clamping devices M7 and M8 are increased, thereby increasing the gate voltages of the corresponding clamping devices M5 and M6 of the clamping devices M7 and M8.
[0024] Furthermore, in the precharging stage, by utilizing the characteristic that the capacitor voltage cannot change abruptly, the gate voltage of M5 is raised to 2VDD, increasing the current of M5, thus accelerating the charging speed of Cb l. Compared with the traditional precharging method, this design avoids the time waste that may be caused by using a fixed precharging time, and also overcomes the problem of reserving an overly long precharging time due to the uncertainty of the bit line parasitic load capacitance size and the need to consider many uncertain factors.
[0025] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification only illustrates the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.
Claims
1. A sensitive amplifier, characterized in that: The sensitive amplifier includes clamping devices M5, M7, M9 and a PREB signal for controlling the precharge signal. When the precharge signal PREB=1, V(E)=0, V(VDDH)=0, and the left and right voltage difference of the capacitor C1 is VDD. When the precharge signal PREB=1, the V(E) potential rises, V(VDDH) is charged to the 2VDD potential, and the left and right voltage difference of the capacitor C1 is VDD. Through the principle that the voltage across the capacitor cannot change suddenly, the power supply voltage of M7 and M8 of the clamping circuit is increased, thereby increasing the gate voltage of M5 and M6, increasing the degree of opening of the channel, speeding up the precharge speed, and realizing high-speed reading of the sensitive amplifier.
2. A sensitive amplifier according to claim 1, characterized in that: When the PREB starts precharging, it means that when PREB=0, and because the voltage difference across the capacitor cannot change suddenly, V(VDDH)=2VDD.
3. A sensitive amplifier according to claim 2, characterized in that: When PREB=0, the gate voltage of M5 is 2VDD.
4. A sensitive amplifier according to claim 1, characterized in that: When PREB=0, the current of the clamping device M5 increases, thereby increasing the output of the Cbl current.
5. A sensitive amplifier according to claim 1, characterized in that: The sense amplifier also includes V(DR). When V(DR) is greater than the threshold voltage of M9 during PREB=0, M5 is turned off to end the pre-operation.
6. A sensitive amplifier according to claim 1, characterized in that: The sensitive amplifier also includes a capacitor, a clamping device M8 and a clamping device M6. The power supply voltage of the clamping device M7 and the clamping device M8 is increased based on the principle that the voltage across the capacitor cannot change suddenly, thereby increasing the gate voltage of the clamping device M5 and the clamping device M6 corresponding to the clamping device M7 and the clamping device M8.