Data strobe signal control method and memory element using same

Abstract

A method of controlling a data strobe signal for use in a memory element is provided. The memory element includes a receiver circuit having a differential amplifier, an auxiliary control circuit, and a data gate control circuit. The control method comprises the following steps: amplifying a first data strobe signal and a second data strobe signal received from a memory controller by using the differential amplifier to generate a third data strobe signal and a fourth data strobe signal; utilizing the auxiliary control circuit to generate a deactivation control signal using the first data strobe signal and the second data strobe signal; and deactivating the data gate control circuit in response to the deactivation control signal in a high logic state.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 395,798 (i.e., the priority date is "December 26, 2023"), the content of which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to an electronic circuit. In particular, it relates to a method for controlling a data strobe signal and a memory element using the method. Background Art

[0003] LPDDR4 (Low Power Double Data Rate 4) memory is a mobile version of DDR4 (Double Data Rate 4) memory. A memory controller can control data access of an LPDDR4 memory via an instruction control signal, a data signal, and a data strobe signal. However, when a write data strobe (WDQS) function of the memory controller is turned off, the logical state of the data strobe signal from the memory controller may be affected by interference thereon, because the interference is amplified by a differential amplifier in a circuit receiver of the LPDDR4 memory, resulting in a malfunction or failure of the LPDDR4 memory control circuit. Therefore, a method for controlling a data strobe signal and a memory element using the method are needed to solve the above problems.

[0004] The above "Prior Art" description only provides background art and does not admit that the above "Prior Art" description discloses the subject matter of the present disclosure, does not constitute prior art of the present disclosure, and any description of the above "Prior Art" should not be taken as any part of this case. Summary of the Invention

[0005] An embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array, a control circuit, and a receiver circuit. The control circuit is configured to control data access of the memory cell array. The receiver circuit is configured to receive a first data strobe signal and a second data strobe signal from a memory controller. The receiver circuit includes a differential amplifier, an auxiliary control circuit, and a data strobe control circuit. The differential amplifier is configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. The auxiliary control circuit is configured to use the first data strobe signal and the second data strobe signal to generate a deactivation control signal. The data strobe control circuit is configured to generate a first output data strobe signal and a second output data strobe signal according to the deactivation control signal, the third data strobe signal, and the fourth data strobe signal.

[0006] Another embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array, a control circuit, and a receiver circuit. The control circuit is configured to control data access of the memory cell array. The receiver circuit is configured to receive a first data strobe signal and a second data strobe signal from a memory controller. The receiver circuit includes a differential amplifier, an auxiliary control circuit, and a data strobe control circuit. The differential amplifier is configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. The auxiliary control circuit is configured to generate a disable control signal using a fifth data strobe signal and a sixth data strobe signal respectively generated from the first data strobe signal and the second data strobe signal. The data strobe control circuit is configured to generate a first output data strobe signal and a second output data strobe signal according to the disable control signal, the third data strobe signal, and the fourth data strobe signal.

[0007] Another embodiment of the present disclosure provides a method for controlling data strobe signals used in a memory element. The memory element includes a receiver circuit having a differential amplifier, an auxiliary control circuit, and a data strobe control circuit. The control method includes the following steps: amplifying, by the differential amplifier, a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal; generating, by the auxiliary control circuit, a disable control signal using the first data strobe signal and the second data strobe signal; and disabling, in response to the disable control signal in a high logic state, the data strobe control circuit.

[0008] The technical features and advantages of the present disclosure have been outlined quite extensively above, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those of ordinary skill in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be quite easily used as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure defined by the appended claims. Description of the Drawings

[0009] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and the claims. The present disclosure should also be understood as being associated with the element numbers of the drawings, and the element numbers of the drawings represent similar elements throughout the description.

[0010] Figure 1It is a block diagram schematically showing an electronic component according to an embodiment of the present disclosure.

[0011] Figure 2 It is a circuit diagram schematically showing a receiver circuit according to an embodiment of the present disclosure.

[0012] Figures 3A to 3F It is a waveform diagram schematically showing a data strobe signal during a write operation according to an embodiment of the present disclosure.

[0013] Figure 4 It is a circuit diagram schematically showing a receiver circuit according to another embodiment of the present disclosure.

[0014] Figure 5A It is a circuit diagram schematically showing Figure 4 an auxiliary control circuit according to an embodiment of

[0015] Figures 5B to 5F It is an equivalent circuit diagram schematically showing an auxiliary control circuit under different conditions Figure 5A of

[0016] Figure 6 It is another circuit diagram schematically showing Figure 4 an auxiliary control circuit according to an embodiment of

[0017] Figure 7 It is a flowchart schematically showing a control method for a data strobe signal used in a memory element according to an embodiment of the present disclosure.

[0018] Among them, the reference numerals are explained as follows:

[0019] 100: Electronic component

[0020] 11: Instruction control signal

[0021] 110: Memory controller

[0022] 12: Data signal

[0023] 120: Memory element

[0024] 121: Interface circuit

[0025] 1211: Receiver circuit

[0026] 122: Control circuit

[0027] 123: Memory cell array

[0028] 13: Data strobe signal

[0029] 14: Data strobe signal

[0030] 15: Bus

[0031] 200: Receiver Circuit

[0032] 202: Differential Amplifier

[0033] 240A: On-Chip Terminator

[0034] 240B: On-Chip Terminator

[0035] 302: Interference

[0036] 304: Interference

[0037] 306: Interference

[0038] 400: Receiver Circuit

[0039] 402: Differential Amplifier

[0040] 404: Data Strobe Control Circuit

[0041] 4041: Voltage Divider

[0042] 406: Auxiliary Control Circuit

[0043] 408A: On-Chip Terminator

[0044] 408B: On-Chip Terminator

[0045] 500: Auxiliary Control Circuit

[0046] 500B: Equivalent Auxiliary Control Circuit

[0047] 500C: Equivalent Auxiliary Control Circuit

[0048] 500D: Equivalent Auxiliary Control Circuit

[0049] 500E: Equivalent Auxiliary Control Circuit

[0050] 500F: Equivalent Auxiliary Control Circuit

[0051] 600: Auxiliary Control Circuit

[0052] 604: Amplifier

[0053] 606: Amplifier

[0054] 700: Control Method

[0055] 710: Step

[0056] 720: Step

[0057] 730: Step

[0058] 740: Step

[0059] DCS: Deactivation Control Signal

[0060] DQS_c, DQS_t: Data strobe signals

[0061] DQS_c’, DQS_t’: Amplified data strobe signals

[0062] DQS_c”, DQS_t”: Data strobe signals

[0063] *DQS_c, *DQS_t: Data strobe signals

[0064] GND: Ground

[0065] N1 to N3: Nodes

[0066] Q1 to Q4: Transistors

[0067] R1 to R2: Resistors

[0068] R DS : Source-drain resistance value

[0069] T: Clock period

[0070] t(n - 4), t(n - 3), t(n - 2), t(n - 1): Time

[0071] t0 to t6: Time

[0072] tWPRE: Duration

[0073] VA: Specific voltage

[0074] VDD: Power supply voltage

[0075] VN2: Voltage

[0076] VrefDQS: Reference voltage Detailed implementation manners

[0077] The following describes specific examples of components and configurations to simplify the embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, when it is described that the first component is formed on the second component, it may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between various embodiments and / or the configurations discussed.

[0078] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, without departing from the teachings of the inventive concept of the present disclosure, the first element, component, region, layer or section discussed below may be referred to as the second element, component, region, layer or section.

[0079] References to "an example" or "an embodiment" in the specification mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present disclosure. Thus, the phrases "in an example" or "in an embodiment" appearing in various places in the specification are not necessarily all referring to the same example. Furthermore, in one or more examples, the particular features, structures, or characteristics may be combined in any suitable manner.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0081] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptive terms used herein may be interpreted accordingly. Additionally, it should be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0082] It should be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

[0083] It should be understood that when an element or layer is referred to as being “formed on” another element or layer, it can be directly or indirectly formed on the other element or layer. That is, for example, intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly formed on” another element, there are no intervening elements or layers. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

[0084] Figure 1 is a block diagram illustrating an electronic component 100 according to an embodiment of the present disclosure.

[0085] In some embodiments, the electronic component 100 may include a memory controller 110 and a memory element 120, as Figure 1 shown. The memory controller 110 can be implemented by a central processing unit (CPU), a microprocessor, a digital signal processor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a radio frequency integrated circuit (RFIC).

[0086] In some embodiments, the memory element 120 may be a dynamic random access memory (DRAM). In other embodiments, other types of memories may be used. For purposes of description, the present disclosure may focus on, for example, double data rate synchronous dynamic random access memory (DDR SDRAM) such as LPDDR4, but the scope of the embodiments is not limited to any particular memory technology or standard.

[0087] In some embodiments, the memory element 120 may include an interface circuit 121, a control circuit 122, and a memory cell array 123. The interface circuit 121 may be configured to transmit and receive a plurality of data signals 12 via the bus 15, and receive a plurality of instruction control signals 11, data strobe signals DQS_c and DQS_t from the memory controller 110 via the bus 15. In other words, the interface circuit 121 may include a TX circuit (not explicitly shown) for the data signal 12, and an RX circuit (not explicitly shown) for the instruction control signal 11, data signal 12, and data strobe signals DQS_c and DQS_t.

[0088] In some embodiments, the data strobe signal DQS_c may be a complementary signal of the data strobe signal DQS_t. For example, when the data strobe signal DQS_t is in a high logic state (e.g., 1), the data strobe signal DQS_c is in a low logic state (e.g., 0). When the data strobe signal DQS_t is in a low logic state (e.g., 0), the data strobe signal DQS_c is in a high logic state (e.g., 1). In some embodiments, if a write data strobe (WDQS) function of the memory controller 110 is not enabled or not properly implemented, the logic states of the data strobe signals DQS_t and DQS_c may be the same.

[0089] In some embodiments, the RX circuit for the data strobe signals DQS_c and DQS_t may be referred to as Figure 1 a receiver circuit 1211 as shown. The receiver circuit 1211 may be configured to correct the data strobe signals DQS_c and DQS_t with inappropriate logic states and / or timings to generate data strobe signals 13 and 14. The data strobe signals 13 and 14 may be data strobe signals (e.g., *DQS_c and *DQS_t) having corrected logic states that conform to the LPDDR4 standard defined by the JEDEC Solid State Technology Association (i.e., abbreviated as JEDEC).

[0090] In some embodiments, the control circuit 122 may perform a read operation or a write operation according to an instruction control signal 11 and data strobe signals 13 and 14. For example, during a write operation, the memory element 120 may receive a write instruction (e.g., including the instruction control signal 11 and the data signal 12) from the memory controller 110 through the bus 15. Then, the control circuit 122 may store the received data in the memory cell array 123. During a read operation, the memory element 120 may receive a read instruction signal (e.g., the instruction control signal 11) from the memory controller 110 through the bus 15. Then, the control circuit 122 may access data from each memory cell of the memory cell array 123 and transmit those bits of the data (e.g., the data signal 12) to the memory controller 110 through the bus 15.

[0091] Figure 2 is a circuit schematic diagram illustrating a receiver circuit 200 according to an embodiment of the present disclosure. Figures 3A to 3E is a waveform schematic diagram illustrating a data strobe signal during a write operation according to an embodiment of the present disclosure. Please refer to Figure 1 、 Figure 2 and Figures 3A to 3E 。

[0092] In some embodiments, Figure 1 the receiver circuit 1211 shown may be implemented using Figure 2 the receiver circuit 200 shown. The receiver circuit 200 may include a differential amplifier 202 configured to amplify data strobe signals DQS_c and DQS_t to generate data strobe signals *DQS_c and *DQS_t. Additionally, the negative input terminal and the positive input terminal of the differential amplifier 202 may be coupled to on-die terminators (ODT) 204A and 204B respectively. The on-die terminators 204A and 204B may be configured to suppress interference on the received data strobe signals DQS_c and DQS_t.

[0093] For example, the receiver circuit 200 may receive data strobe signals DQS_c and DQS_t at its positive input terminal (e.g., +) and negative input terminal (e.g., -), respectively, to generate data strobe signals *DQS_c and *DQS_t. In some embodiments, the amplitudes of the data strobe signals DQS_c and DQS_t may be between 50mv and 100mv, which may not have sufficient voltage levels (e.g., 0.6V or 1.1V for LPDDR4 DRAM) for the control circuit 122 to perform a write operation or a read operation. The amplitudes of the data strobe signals *DQS_c and *DQS_t may be approximately 0.6V or 1.1V, and the control circuit 122 may perform a write operation or a read operation according to the command control signal 11 and the data strobe signals *DQS_c and *DQS_t.

[0094] In some embodiments, assuming that the memory element 120 is an LPDDR4 DRAM and the memory controller 110 follows the LPDDR4 standard (e.g., the write data strobe (WDQS) function is enabled), when the memory controller 110 issues a write command to the memory element 120, at time t0, before the memory controller 110 issues a write preamble to the memory element 120, the data strobe signals DQS_t and DQS_c should be kept in the low logic state and the high logic state, respectively. The duration tWPRE of the write preamble may last for two clock cycles (e.g., from time t0 to time t4) until the control circuit 122 receives data (e.g., data signal 12) at time t4, and the data strobe signals DQS_t and DQS_c may change during the duration tWPRE of the write preamble, as Figure 3A shown.

[0095] However, in some cases, the WDQS function of the memory controller 110 may not be enabled or may not be properly implemented, resulting in the logic states of the data strobe signals DQS_t and DQS_c being uncertain during a period of time (e.g., the time interval from time t(n - 4) to time t0) before the control circuit 122 receives the write preamble at time t0.

[0096] For example, as Figure 3A shown, the time interval between every two adjacent time points from t(n - 4) to t6 may be half a clock cycle T / 2. In other words, two time intervals (e.g., from t0 to t2) may constitute a clock cycle T.

[0097] At time t0, the memory controller 110 issues a write preamble. If the WDQS function is turned off, as Figure 3AAs shown, during a period of time (e.g., from time t(n - 4) to time t0) before the write preamble is sent at time t0, the logical states of the data strobe signals DQS_t and DQS_c may be uncertain. This situation can cause the control circuit 122 to malfunction during a write operation.

[0098] More specifically, within the duration before time t0, there are four conditions for the logical states of the data strobe signals DQS_t and DQS_c. Under the first condition, the WDQS function of the memory controller 110 may not be enabled, and the data strobe signals DQS_t and DQS_c may remain in the low logic state during a duration before the control circuit 122 receives the write preamble at time t0, as Figure 3B shown. Since the first condition does not meet the requirements of the write operation of the JEDEC - defined LPDDR4 standard, the first condition can cause the control circuit 122 to malfunction during the write operation.

[0099] Under the second condition, the WDQS function of the memory controller 110 may not be enabled, and the data strobe signals DQS_t and DQS_c may remain in the high logic state during a duration before the control circuit 122 receives the write preamble at time t0, as Figure 3C shown. Since the second condition does not meet the requirements of the write operation of the JEDEC - defined LPDDR4 standard, the second condition can cause the control circuit 122 to malfunction during the write operation.

[0100] Under the third condition, the WDQS function of the memory controller 110 may be enabled, and the data strobe signals DQS_t and DQS_c remain in the low logic state and the high logic state respectively during a duration before the control circuit 122 receives the write preamble at time t0, as Figure 3D shown. Since the third condition meets the requirements of the write operation defined by JEDEC for the LPDDR4 standard, the third condition will not cause the control circuit 122 to malfunction during the write operation.

[0101] Under the fourth condition, the WDQS function of the memory controller 110 may be enabled, and the data strobe signals DQS_t and DQS_c remain in the high logic state and the low logic state respectively during a duration before the control circuit 122 receives the write preamble at time t0, as Figure 3E shown. Since the fourth condition meets the JEDEC - defined LPDDR4 standard, the fourth condition will not cause the control circuit 122 to malfunction during the write operation.

[0102] Now please refer to Figure 2。In some embodiments, the resistance values of ODT 204A and 204B can vary among multiple preset resistance values, which can include 40 ohms, 60 ohms, 80 ohms, 120 ohms, 240 ohms, and an open circuit resistance value, and they are determined by the setting values of the corresponding mode registers in the memory element 120 set by the memory controller 110. Additionally, when the WDQS function is turned off, the memory controller 110 may set the mode registers corresponding to ODT 204A and 204B to a specific value (e.g., 0), such that ODT 204A and 204B are turned off to act as an open circuit. In this case, the amplitude of the interference received by the receiver circuit 1211 will not be suppressed. Figure 2 The differential amplifier 202 shown amplifies the data strobe signals DQS_t and DQS_c and the interference on the data strobe signals DQS_t and DQS_c. In some embodiments, the amplitude of the data strobe signals DQS_t and DQS_c can be approximately between 300 mV and 600 mV, and the amplitude of the interference on the data strobe signals DQS_t and DQS_c can be approximately between 80 mV and 170 mV.

[0103] When the data strobe signals DQS_t and DQS_c are in the low logic state and the WDQS function is turned off, the amplified interference can reach an amplitude similar to that of the data strobe signals DQS_t and DQS_c in the high logic state. Therefore, the amplified interference will be more likely to cause the data strobe signals DQS_t and DQS_c to change from the low logic state to the high logic state, potentially resulting in malfunction or failure of the control circuit 122.

[0104] Please refer to Figure 3F , the interferences 302 and 304 are on the data strobe signal DQS_t, and the interference 306 is on the data strobe signal DQS_c. The interferences 302 and 306 can have an amplitude higher than a specific voltage VA (e.g., approximately 90 mV), and the interference 304 can have an amplitude lower than the specific voltage VA. More specifically, when the amplitude of the interference on the data strobe signal DQS_t or DQS_c is higher than the specific voltage VA (such as the interferences 302 and 306), the amplified interference will cause the data strobe signals DQS_t and DQS_c to change from the low logic state to the high logic state, potentially resulting in malfunction or failure of the control circuit 122. Figure 4 The receiver circuit 400 shown provides a solution to this problem, and its details will be further discussed.

[0105] Figure 4 is a circuit schematic diagram illustrating the receiver circuit 400 according to another embodiment of the present disclosure.

[0106] In some embodiments, Figure 1The illustrated receiver circuit 1211 can be implemented using Figure 4 the illustrated receiver circuit 400. The receiver circuit 400 can include a differential amplifier 402, a data strobe (DQS) control circuit 404, and an auxiliary control circuit 406. In some other embodiments, the receiver circuit 400 may further include ODTs 408A and 408B coupled to the negative input terminal (-) and the positive input terminal (+) of the differential amplifier 402. The ODTs 408A and 408B can be similar Figure 2 to the illustrated ODTs 204A and 204B, and the details thereof will not be repeated herein.

[0107] In some embodiments, the differential amplifier 402 can be configured to amplify data strobe signals DQS_c and DQS_t (e.g., input data strobe signals) to generate data strobe signals DQS_c” and DQS_t”.

[0108] In some embodiments, the DQS control circuit 404 can include a voltage divider 4041 configured to divide a clock signal by a preset multiple to generate a divided clock signal. Thus, the DQS control circuit 404 can control the delay time and phase of the data strobe signals DQS_c” and DQS_t” to generate data strobe signals *DQS_c and *DQS_t. Additionally, the data strobe signals *DQS_c and *DQS_t can be respectively referred to as Figure 1 data strobe signals 13 and 14.

[0109] In some embodiments, the auxiliary control circuit 406 can be configured to generate a deactivation control signal DCS according to the data strobe signals DQS_c and DQS_t received by the receiver circuit 400. Specifically, when both data strobe signals DQS_c and DQS_t are in the low logic state (e.g., “0”), the deactivation control signal DCS generated by the auxiliary control circuit 406 is in the high logic state (e.g., “1”). Otherwise, when the logic states of the data strobe signals DQS_c and DQS_t are any combination of (0, 1), (1, 0), and (1, 1), the deactivation control signal DCS generated by the auxiliary control circuit 406 is in the low logic state. The relationship between the logic states of the data strobe signals DQS_c and DQS_t and the deactivation control signal DCS is shown in Table 1 below.

[0110] DQS_c DQS_t DCS 0 0 1 0 1 0 1 0 0 1 1 0

[0111] Table 1

[0112] In some embodiments, in response to the disable control signal DCS being in a high logic state, the DQS control circuit 404 turns off the voltage divider 4041. This can prevent the logic states of the data strobe signals *DQS_t and *DQS_c from being affected by the logic state changes of the data strobe signals DQS_t” and DQS_c” caused by interference, ensuring that they remain in a low logic state. This helps prevent malfunctions or failures of the control circuit 122 (e.g., including a command decoder) that receives the data strobe signals *DQS_t and *DQS_c. In response to the disable control signal DCS being in a low logic state, the DQS control circuit 404 enables the voltage divider 4041 and outputs the data strobe signals DQS_c” and DQS_t” as the data strobe signals *DQS_c and *DQS_t. This allows the control circuit 122 that receives the data strobe signals *DQS_t and *DQS_c to operate normally, such as performing a memory operation on the memory element 120.

[0113] Figure 5A is a circuit schematic diagram illustrating Figure 4 the auxiliary control circuit of the embodiment of. Figures 5B to 5F is an equivalent circuit schematic diagram illustrating in different situations Figure 5A the auxiliary control circuit of.

[0114] In some embodiments, Figure 4 the auxiliary control circuit 406 shown can be implemented using Figures 5A - 5F the auxiliary control circuit 500 shown. The auxiliary control circuit 500 can include transistors Q1 to Q4 and resistors R1 and R2. Transistors Q1-Q2 are P-type transistors, and transistors Q3-Q4 are N-type transistors. Transistor Q1 can have a gate electrically connected to the data strobe signal DQS_c, a drain electrically connected to node N2, and a source electrically connected to node N1. Transistor Q2 can have a gate electrically connected to the data strobe signal DQS_t, a drain electrically connected to node N2, and a source electrically connected to node N1.

[0115] Transistor Q3 can have a gate electrically connected to the data strobe signal DQS_c, a drain electrically connected to node N3, and a source electrically connected to ground (i.e., GND). Transistor Q4 can have a gate electrically connected to the data strobe signal DQS_t, a drain electrically connected to node N3, and a source electrically connected to ground (i.e., GND). Additionally, resistor R1 is connected between nodes N2 and N3, and resistor R2 is connected between the power supply voltage VDD and node N1. Node N2 can be used as an output terminal of the auxiliary control circuit 500 that outputs the disable control signal DCS.

[0116] In some embodiments, assuming that R is a reference resistance value, the source-drain resistance value (R DS ) when transistors Q1 - Q4 are conducting is 0.1R, and the source-drain resistance value (R DS ) when transistors Q1 - Q4 are cutoff is approximately 1000R, or higher. For simplicity, assume that the source-drain resistance value of transistors Q1 - Q4 in the cutoff (OFF) state is 1000R. In some embodiments, the range of the reference resistance value R can be between several tens of kiloohms (kΩ) and several megaohms (MΩ), but the present disclosure is not limited thereto. Additionally, the resistance value of resistor R1 can be approximately equal to R, and the resistance value of resistor R2 can be approximately between 2R and 10R. For simplicity, in the following embodiments, the resistance value of resistor R2 is 10R.

[0117] In some embodiments, when the memory element is an LPDDR4 memory, the power supply voltage VDD can be approximately equal to 1.1V, and the reference voltage VrefDQS of the data strobe signals DQS_t and DQS_c is 0.5VDD = 0.55V.

[0118] Specifically, the logic states of the data strobe signals DQS_t and DQS_c are determined by their amplitudes. For example, when the amplitude of the data strobe signal DQS_t or DQS_c is equal to or higher than the reference voltage VrefDQS, the data strobe signal DQS_t or DQS_c can be regarded as logic "1". When the amplitude of the data strobe signal DQS_t or DQS_c is lower than the reference voltage VrefDQS, the data strobe signal DQS_t or DQS_c can be regarded as logic "0". The detailed operations of the auxiliary control circuit 500 described in the following paragraphs can be accompanied by Figures 3B to 3E the four conditions of the data strobe signals DQS_t and DQS_c shown in

[0119] In the first condition, the WDQS function of the memory controller 110 can be not enabled, and during a duration before the control circuit 122 receives a write preamble at time t0, the data strobe signals DQS_t and DQS_c remain in the low logic state (i.e., DQS_t = 0 and DQS_c = 0), as shown in Figure 3B . At this time, transistors Q1 and Q2 are fully conducting, and transistors Q3 and Q4 are fully cutoff. Therefore, the equivalent resistance values of transistors Q1 and Q2 can be set to 0.1R, and the equivalent resistance values of transistors Q3 and Q4 can be set to 1000R, as shown in Figure 5BAs shown. In other words, since the resistance values of transistors Q1 and Q2 are shunted, the equivalent resistance values of transistors Q1 and Q2 are both 0.05R. Similarly, since the resistance values of transistors Q3 and Q4 are shunted, the equivalent resistance values of transistors Q3 and Q4 are both 500R. The equivalent auxiliary control circuit 500B can be regarded as a voltage divider, and the voltage VN2 of the deactivation control signal DCS at the output terminal (i.e., node N2) of the auxiliary control circuit 500 can be calculated by formula (1):

[0120]

[0121] Since 0.98VDD is approximately equal to 1.089V higher than the reference voltage VrefDQS (e.g., 0.55V), the deactivation control signal DCS at node N2 is in the high logic state (i.e., logic "1").

[0122] Under the second condition, the WDQS function of the memory controller 110 may not be enabled, and the data strobe signals DQS_t and DQS_c remain in the high logic state (i.e., DQS_t = 1 and DQS_c = 1) for a duration before the control circuit 122 receives the write preamble at time t0, as Figure 3C shown. At this time, transistors Q1 and Q2 are completely cut off, and transistors Q3 and Q4 are completely turned on. Therefore, the equivalent resistance values of transistors Q1 and Q2 can be set to 1000R, and the equivalent resistance values of transistors Q3 and Q4 can be set to 0.1R, as Figure 5C shown. In other words, since the resistance values of transistors Q1 and Q2 are shunted, the equivalent resistance values of transistors Q1 and Q2 are both 500R. Similarly, since the resistance values of transistors Q3 and Q4 are shunted, the equivalent resistance values of transistors Q3 and Q4 are both 0.05R. The equivalent auxiliary control circuit 500C can be regarded as a voltage divider, and the voltage VN2 of the deactivation control signal DCS at the output terminal (i.e., node N2) of the auxiliary control circuit 500 can be calculated by formula (2):

[0123]

[0124] Since 0.002VDD is approximately equal to 0V, which is lower than the reference voltage VrefDQS (e.g., 0.55V), the deactivation control signal DCS at node N2 is in the low logic state (i.e., logic "0").

[0125] Under the third condition, the WDQS function of the memory controller 110 can be enabled, and during a duration before the control circuit 122 receives a write preamble at time t0, the data strobe signals DQS_t and DQS_c are respectively maintained at a low logic state and a high logic state (i.e., DQS_t = 0 and DQS_c = 1), as Figure 3D shown. At this time, the transistors Q1 and Q4 are completely cut off, and the transistors Q2 and Q3 are completely turned on. Therefore, the equivalent resistance values of the transistors Q1 and Q4 can be set to 1000R, and the equivalent resistance values of the transistors Q2 and Q3 can be set to 0.1R, as Figure 5D shown. In other words, since the resistance values of the transistors Q1 and Q2 are shunted, the equivalent resistance values of the transistors Q1 and Q2 are approximately 0.1R. Similarly, since the resistance values of the transistors Q3 and Q4 are shunted, the equivalent resistance values of the transistors Q3 and Q4 are approximately 0.1R. The equivalent auxiliary control circuit 500D can be regarded as a voltage divider, and the voltage VN2 of the disable control signal DCS at the output terminal (i.e., node N2) of the auxiliary control circuit 500 can be calculated by formula (3):

[0126]

[0127] Since 0.098VDD is approximately equal to 0.1V, which is lower than the reference voltage VrefDQS (e.g., 0.55V), the disable control signal DCS at node N2 is in a low logic state (i.e., logic "0").

[0128] Under the fourth condition, the WDQS function of the memory controller 110 can be enabled, and during a duration before the control circuit 122 receives a write preamble at time t0, the data strobe signals DQS_t and DQS_c are respectively maintained at a high logic state and a low logic state (i.e., DQS_t = 1 and DQS_c = 0), as Figure 3D shown. At this time, the transistors Q2 and Q3 are completely cut off, and the transistors Q1 and Q4 are completely turned on. Therefore, the equivalent resistance values of the transistors Q2 and Q3 can be set to 1000R, and the equivalent resistance values of the transistors Q1 and Q4 can be set to 0.1R, as Figure 5E shown. In other words, since the resistance values of the transistors Q1 and Q2 are shunted, the equivalent resistance values of the transistors Q1 and Q2 are approximately 0.1R. Similarly, since the resistance values of the transistors Q3 and Q4 are shunted, the equivalent resistance values of the transistors Q3 and Q4 are approximately 0.1R. The equivalent auxiliary control circuit 500E can be regarded as a voltage divider, and the voltage VN2 of the disable control signal DCS at the output terminal (i.e., node N2) of the auxiliary control circuit 500 can be calculated by formula (4):

[0129]

[0130] Since 0.098VDD is approximately equal to 0.1V, which is lower than the reference voltage VrefDQS (e.g., 0.55V), the disable control signal DCS at node N2 is in the low logic state (i.e., logic "0").

[0131] Under the fifth condition, the data strobe signals DQS_t and DQS_c typically flip every half clock cycle, and the voltage levels of the data strobe signals DQS_t and DQS_c can be equal to 0.5VDD at the crossover point. The crossover point can refer to the crossover point of the rising edge of the data strobe signal DQS_t and the falling edge of the data strobe signal DQS_c, or the crossover point of the rising edge of the data strobe signal DQS_c and the falling edge of the data strobe signal DQS_t. Therefore, transistors Q1 to Q4 are in the conducting state, and the equivalent resistance values of transistors Q1 to Q4 can be set to 0.1R, as Figure 5E shown. In other words, since the resistance values of transistors Q1 and Q2 are shunted, the shunt resistance values of transistors Q1 and Q2 are approximately 0.05R. Similarly, since the resistance values of transistors Q3 and Q4 are shunted, the shunt resistance values of the shunted transistors Q3 and Q4 are approximately 0.05R. The equivalent auxiliary control circuit 500F can be regarded as a voltage divider, and the voltage VN2 of the disable control signal DCS at the output terminal (i.e., node N2) of the auxiliary control circuit 500 can be calculated by formula (5):

[0132]

[0133] Since 0.095VDD is approximately equal to 0.1V, which is lower than the reference voltage VrefDQS (e.g., 0.55V), the disable control signal DCS at node N2 is in the low logic state (i.e., logic "0").

[0134] In view of the foregoing Figures 5A to 5F embodiment, when the data strobe signals DQS_t and DQS_c are in the low logic state (i.e., the first condition), the disable control signal DCS generated by the auxiliary control circuit 500 is in the high logic state. Therefore, Figure 4 the DQS control circuit 404 shown can be disabled in response to the disable control signal DCS being in the high logic state, and thus will not cause a malfunction or failure of the command decoder (not shown) in the control circuit 122. When the data strobe signals DQS_t and DQS_c are in any of the second to fifth states, the disable control signal DCS generated by the auxiliary control circuit 500 is in the low logic state, so the command decoder in the control circuit 122 can operate normally.

[0135] Figure 6 is another circuit schematic diagram, illustratingFigure 4 The auxiliary control circuit of the embodiment.

[0136] In some embodiments, Figure 4 The auxiliary control circuit 406 shown can be implemented using Figure 6 The auxiliary control circuit 600 shown. The auxiliary control circuit 600 may include transistors Q1 to Q4, resistors R1 and R2, and amplifiers 604 and 606. Transistors Q1-Q2 are P-type transistors, and transistors Q3-Q4 are N-type transistors. Transistor Q1 may have a gate electrically connected to the data strobe signal DQS_c, a drain electrically connected to node N2, and a source electrically connected to node N1. Transistor Q2 may have a gate electrically connected to the data strobe signal DQS_t, a drain electrically connected to node N2, and a source electrically connected to node N1.

[0137] Transistor Q3 may have a gate electrically connected to the data strobe signal DQS_c, a drain electrically connected to node N3, and a source electrically connected to ground (i.e., GND). Transistor Q4 may have a gate electrically connected to the data strobe signal DQS_t, a drain electrically connected to node N3, and a source electrically connected to ground (i.e., GND). Additionally, resistor R1 is connected between nodes N2 and N3, and resistor R2 is connected between the power supply voltage VDD and node N1. Node N2 may be used as an output terminal of the auxiliary control circuit 500 for outputting the disable control signal DCS.

[0138] In some embodiments, the memory element 120 may operate using a power supply voltage of 0.6V or 1.1V. However, the amplitude of the data strobe signals DQS_c and DQS_t from the memory controller 110 is between 50mv and 100mv, and their voltage levels are not sufficient for the control circuit 122 to perform write or read operations on the memory element 120. Additionally, since the threshold voltages of transistors Q1 to Q4 can be between 0.5V and 0.7V, the amplitudes of the data strobe signals DQS_c and DQS_t are not sufficient to turn on transistors Q1 to Q4. The amplitudes of the amplified data strobe signals DQS_c' and DQS_t' generated by amplifiers 604 and 606 can be between 0.6V and 1.1V, and their voltage levels are sufficient for the control circuit 122 to perform write or read operations on the memory element 120 and are sufficient to turn on transistors Q1 to Q4.

[0139] More specifically, Figure 6 The auxiliary control circuit 600 shown can be similar to Figure 5AThe auxiliary control circuit 500 shown is different in that transistors Q1 and Q3 are controlled by a data strobe signal DQS_c’, and transistors Q2 and Q4 are controlled by a data strobe signal DQS_t’. Since the data strobe signals DQS_c’ and DQS_t’ have sufficient amplitude to turn on transistors Q1 to Q4, therefore Figure 6 the operation of the auxiliary control circuit 600 shown can be similar to Figure 5A the operation of the auxiliary control circuit 500 shown, the details of which can be referred to Figures 5B - 5F the embodiments of

[0140] Figure 7 is a flowchart illustrating a method for controlling data strobe signals used in a memory element according to an embodiment of the present disclosure. Please refer to Figure 1 、 Figure 4 、 Figures 5A - 5F and Figure 7 。

[0141] Step 710: Amplify a first data strobe signal (e.g., DQS_c) and a second data strobe signal (e.g., DQS_t) received from a memory controller (e.g., memory controller 110) using a differential amplifier (e.g., differential amplifier 402) to respectively generate a third data strobe signal (e.g., DQS_c”) and a fourth data strobe signal (e.g., *DQS_t”). For example, Figure 4 the differential amplifier 402 of the receiver circuit 400 shown is configured to amplify the first data strobe signal and the second data strobe signal to generate the third data strobe signal and the fourth data strobe signal. In other words, the amplitudes of the third data strobe signal and the fourth data strobe signal are higher than the amplitudes of the first data strobe signal and the second data strobe signal.

[0142] Step 720: Use a first data strobe signal (e.g., DQS_c) and a second data strobe signal (e.g., DQS_t) using an auxiliary control circuit (e.g., auxiliary control circuit 406) to generate a disable control signal DCS. For example, when the first data strobe signal and the second data strobe signal are in the first condition (e.g., DQS_t = 0 and DQS_c = 0), the disable control signal DCS generated by the auxiliary control circuit 500 (or auxiliary control circuit 600) is in a high logic state. When the first data strobe signal and the second data strobe signal are in any one of the second to fifth conditions, the disable control signal DCS generated by the auxiliary control circuit 500 (or auxiliary control circuit 600) is in a low logic state.

[0143] Step 730: In response to the deactivation control signal DCS being in a high logic state (e.g., “1”), deactivate a data strobe control circuit (e.g., data strobe control circuit 404). For example, in response to the deactivation control signal DCS being in a high logic state, the DQS control circuit 404 turns off the voltage divider 4041. This can prevent the logic states of the data strobe signals *DQS_t and *DQS_c from being affected by the logic state changes of the data strobe signals DQS_t” and DQS_c” caused by interference, ensuring that they remain in a low logic state. This helps prevent malfunctions or failures of the control circuit 122 (e.g., including a command decoder) that receives the data strobe signals *DQS_t and *DQS_c.

[0144] Step 740: In response to the deactivation control signal DCS being in a low logic state (e.g., “0”), use a control circuit (e.g., control circuit 122) to perform a write operation on a memory element (e.g., memory element 120) using the third data strobe signal (e.g., DQS_c”) and the fourth data strobe signal (e.g., DQS_t”). For example, in response to the deactivation control signal DCS being in a low logic state, the DQS control circuit 404 enables the voltage divider 4041 and outputs the data strobe signals DQS_c” and DQS_t” as the data strobe signals *DQS_c and *DQS_t. This allows the control circuit 122 that receives the data strobe signals *DQS_t and *DQS_c to operate normally, for example, by performing a write operation on the memory element 120.

[0145] An embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array, a control circuit, and a receiver circuit. The control circuit is configured to control data access to the memory cell array. The receiver circuit is configured to receive a first data strobe signal and a second data strobe signal from a memory controller. The receiver circuit includes a differential amplifier, an auxiliary control circuit, and a data strobe control circuit. The differential amplifier is configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. The auxiliary control circuit is configured to use the first data strobe signal and the second data strobe signal to generate a deactivation control signal. The data strobe control circuit is configured to generate a first output data strobe signal and a second output data strobe signal based on the deactivation control signal, the third data strobe signal, and the fourth data strobe signal.

[0146] In some embodiments, in response to the first data strobe signal and the second data strobe signal satisfying a first condition, the deactivation control signal generated by the auxiliary control circuit is in a high logic state.

[0147] In some embodiments, the first condition indicates that the first data strobe signal and the second data strobe signal are in a low logic state.

[0148] In some embodiments, in response to the disable control signal being in the high logic state, the data strobe control circuit is disabled, and the first output data strobe signal and the second output data strobe signal generated by the data strobe control circuit remain in the low logic state.

[0149] In some embodiments, in response to the first data strobe signal and the second data strobe signal not satisfying the first condition, the disable control signal generated by the auxiliary control circuit is in a low logic state.

[0150] In some embodiments, in response to the disable control signal being in the low logic state, the data strobe control circuit is activated to generate the first output data strobe signal and the second output data strobe signal using the third data strobe signal and the fourth data strobe signal.

[0151] In some embodiments, the auxiliary control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor has a gate connected to the first data strobe signal, a drain electrically connected to a first node, and a source electrically connected to a second node. The second transistor has a gate electrically connected to the second data strobe signal, a drain electrically connected to the first node, and a source electrically connected to the second node. The third transistor has a gate electrically connected to the first data strobe signal, a drain electrically connected to a third node, and a source grounded. The fourth transistor has a gate electrically connected to the second data strobe signal, a drain electrically connected to the third node, and a source grounded. The first resistor is coupled between the second node and the third node. The second resistor is coupled between a power supply voltage and the first node. The disable control signal is generated at the second node.

[0152] In some embodiments, a first resistance value of the first resistor is less than a second resistance value of the second resistor.

[0153] In some embodiments, when the first transistor, the second transistor, the third transistor, and the fourth transistor have the first resistor and the second resistor in a conducting state and a cutoff state, respectively, the second resistance value is much higher than the first resistance.

[0154] In some embodiments, the first resistance value and the second resistance value refer to a first drain-source resistance value and a second drain-source resistance value of the first transistor, the second transistor, the third transistor, and the fourth transistor in the conducting state and the cutoff state, respectively.

[0155] In some embodiments, in response to the first data strobe signal and the second data strobe signal being equal to half of the supply voltage, the first transistor, the second transistor, the third transistor, and the fourth transistor have the first resistance value in the conducting state.

[0156] In some embodiments, when the first transistor, the second transistor, the third transistor, and the fourth transistor are in the conducting state, the disable control signal is in the low logic state.

[0157] Another embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array, a control circuit, and a receiver circuit. The control circuit is configured to control data access of the memory cell array. The receiver circuit is configured to receive a first data strobe signal and a second data strobe signal from a memory controller. The receiver circuit includes a differential amplifier, an auxiliary control circuit, and a data strobe control circuit. The differential amplifier is configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal. The auxiliary control circuit is configured to generate a disable control signal using a fifth data strobe signal and a sixth data strobe signal respectively generated from the first data strobe signal and the second data strobe signal. The data strobe control circuit is configured to generate a first output data strobe signal and a second output data strobe signal according to the disable control signal, the third data strobe signal, and the fourth data strobe signal.

[0158] In some embodiments, in response to the first data strobe signal and the second data strobe signal satisfying a first condition, the disable control signal generated by the auxiliary control circuit is in a high logic state.

[0159] In some embodiments, the first condition indicates that the first data strobe signal and the second data strobe signal are in a low logic state.

[0160] In some embodiments, in response to the disable control signal being in the high logic state, the data strobe control circuit is disabled, and the first output data strobe signal and the second output data strobe signal remain in the low logic state.

[0161] In some embodiments, in response to the first data strobe signal and the second data strobe signal not satisfying the first condition, the disable control signal generated by the auxiliary control circuit is in the low logic state.

[0162] In some embodiments, in response to the disable control signal being in the low logic state, the data strobe control circuit is enabled to use the third data strobe signal and the fourth data strobe signal to generate the first output data strobe signal and the second output data strobe signal.

[0163] In some embodiments, the auxiliary control circuit includes a first amplifier, a second amplifier, a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first amplifier is configured to amplify the first data strobe signal to generate a first amplified data strobe signal. The second amplifier is configured to amplify the second data strobe signal to generate a second amplified data strobe signal. The first transistor has a gate electrically connected to the first amplified data strobe signal, a drain electrically connected to a first node, and a source electrically connected to a second node. The second transistor has a gate electrically connected to the second amplified data strobe signal, a drain electrically connected to the first node, and a source electrically connected to the second node. The third transistor has a gate electrically connected to the first data strobe signal, a drain electrically connected to a third node, and a source grounded. The fourth transistor has a gate electrically connected to the second data strobe signal, a drain electrically connected to the third node, and a source grounded. The first resistor is coupled between the second node and the third node. The second resistor is coupled between a power supply voltage and the first node. The disable control signal is generated at the second node.

[0164] In some embodiments, a first resistance value of the first resistor is less than a second resistance value of the second resistor.

[0165] In some embodiments, an amplitude of the first amplified data strobe signal and the second amplified data strobe signal is higher than a threshold voltage of the first transistor, the second transistor, the third transistor, and the fourth transistor.

[0166] In some embodiments, when the first transistor, the second transistor, the third transistor, and the fourth transistor are in a conducting state and a cutoff state respectively with the first resistance value and the second resistance value, the second resistance value is much higher than the first resistance value.

[0167] In some embodiments, the first resistance value and the second resistance value refer to a first drain-source resistance value and a second drain-source resistance value of the first transistor, the second transistor, the third transistor, and the fourth transistor in the on state and the off state, respectively.

[0168] In some embodiments, in response to the first data strobe signal and the second data strobe signal being equal to half of the supply voltage, the first transistor, the second transistor, the third transistor, and the fourth transistor have the first resistance value in the on state.

[0169] In some embodiments, when the first transistor, the second transistor, the third transistor, and the fourth transistor are in the on state, the disable control signal is in the low logic state.

[0170] Another embodiment of the present disclosure provides a method for controlling data strobe signals used in a memory element. The memory element includes a receiver circuit having a differential amplifier, an auxiliary control circuit, and a data strobe control circuit. The control method includes the following steps: amplifying a first data strobe signal and a second data strobe signal received from a memory controller by the differential amplifier to generate a third data strobe signal and a fourth data strobe signal; using the first data strobe signal and the second data strobe signal by the auxiliary control circuit to generate a disable control signal; and disabling the data strobe control circuit in response to the disable control signal being in a high logic state.

[0171] In some embodiments, the memory element further includes a control circuit, and the control method further includes: using the third data strobe signal and the fourth data strobe signal by the control circuit in response to the disable control signal being in the low logic state to perform a write operation on the memory element.

[0172] In some embodiments, in response to the first data strobe signal and the second data strobe signal satisfying a first condition, the disable control signal generated by the auxiliary control circuit is in the high logic state.

[0173] In some embodiments, the first condition indicates that the first data strobe signal and the second data strobe signal are in the low logic state.

[0174] In some embodiments, in response to the disable control signal being in the high logic state, the data strobe control circuit is disabled, and a first output data strobe signal and a second output data strobe signal generated by the data strobe control circuit remain in the low logic state.

[0175] In some embodiments, in response to the first data strobe signal and the second data strobe signal not satisfying the first condition, the disable control signal generated by the auxiliary control circuit is in the low logic state.

[0176] In some embodiments, in response to the disable control signal being in the low logic state, the data strobe control circuit is enabled to generate the first output data strobe signal and the second output data strobe signal using the third data strobe signal and the fourth data strobe signal.

[0177] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the disclosure as defined by the claims. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes or combinations thereof.

[0178] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that can be used in accordance with the present disclosure and have the same function or achieve substantially the same result as the corresponding embodiments described herein are included in the claims of the present application.

Claims

1. A memory element, comprising: a memory cell array; a control circuit configured to control data access to the memory cell array; as well as A receiver circuit is configured to receive a first data strobe signal and a second data strobe signal from a memory controller, wherein the receiver circuit comprises: a differential amplifier configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal; an auxiliary control circuit configured to use the first data strobe signal and the second data strobe signal to generate a disable control signal; as well as A data strobe control circuit is configured to generate a first output data strobe signal and a second output data strobe signal according to the disable control signal, the third data strobe signal and the fourth data strobe signal.

2. The memory device of claim 1, wherein in response to the first data strobe signal and the second data strobe signal satisfying a first condition, the disable control signal generated by the auxiliary control circuit is in a high logic state.

3. The memory device of claim 2, wherein the first condition indicates that the first data strobe signal and the second data strobe signal are in a low logic state.

4. The memory element of claim 3, wherein in response to the disable control signal being in the high logic state, the data strobe control circuit is disabled and the first output data strobe signal and the second output data strobe signal generated by the data strobe control circuit remain in the low logic state.

5. The memory device of claim 2, wherein in response to the first data strobe signal and the second data strobe signal not satisfying the first condition, the disable control signal generated by the auxiliary control circuit is in a low logic state.

6. The memory element of claim 5, wherein in response to the disable control signal being in the low logic state, the data strobe control circuit is enabled to generate the first output data strobe signal and the second output data strobe signal using the third data strobe signal and the fourth data strobe signal.

7. The memory device as claimed in claim 4, wherein the auxiliary control circuit comprises: a first transistor having a gate connected to the first data strobe signal, a drain electrically connected to a first node, and a source electrically connected to a second node; a second transistor having a gate electrically connected to the second data strobe signal, a drain electrically connected to the first node, and a source electrically connected to the second node; a third transistor having a gate electrically connected to the first data strobe signal, a drain electrically connected to a third node, and a source grounded; a fourth transistor having a gate electrically connected to the second data strobe signal, a drain electrically connected to the third node, and a source grounded; a first resistor coupled between the second node and the third node; as well as a second resistor coupled between a power supply voltage and the first node; The disable control signal is generated at the second node. 8 . The memory device as claimed in claim 7 , wherein a first resistance value of the first resistor is smaller than a second resistance value of the second resistor.

9. The memory element as claimed in claim 8, wherein when the first transistor, the second transistor, the third transistor and the fourth transistor have the first resistance and the second resistance in an on state and an off state respectively, the second resistance value is much higher than the first resistance.

10. The memory element as claimed in claim 9, wherein the first resistance value and the second resistance value refer to a first drain-source resistance value and a second drain-source resistance value of the first transistor, the second transistor, the third transistor and the fourth transistor in the on state and the off state respectively.

11. The memory element of claim 9, wherein in response to the first data strobe signal and the second data strobe signal being equal to half the power supply voltage, the first transistor, the second transistor, the third transistor, and the fourth transistor have the first resistance value in the on state. 12 . The memory device of claim 11 , wherein the disable control signal is in the low logic state when the first transistor, the second transistor, the third transistor, and the fourth transistor are in the on state.

13. A memory element comprising: a memory cell array; a control circuit configured to control data access to the memory cell array; as well as A receiver circuit is configured to receive a first data strobe signal and a second data strobe signal from a memory controller, wherein the receiver circuit comprises: a differential amplifier configured to amplify the first data strobe signal and the second data strobe signal to generate a third data strobe signal and a fourth data strobe signal; an auxiliary control circuit configured to generate a disable control signal using a fifth data strobe signal and a sixth data strobe signal generated from the first data strobe signal and the second data strobe signal, respectively; as well as A data strobe control circuit is configured to generate a first output data strobe signal and a second output data strobe signal according to the disable control signal, the third data strobe signal and the fourth data strobe signal.

14. The memory device of claim 13, wherein in response to the first data strobe signal and the second data strobe signal satisfying a first condition, the disable control signal generated by the auxiliary control circuit is in a high logic state.

15. The memory device of claim 14, wherein the first condition indicates that the first data strobe signal and the second data strobe signal are in a low logic state.

16. The memory element of claim 15, wherein in response to the disable control signal being in the high logic state, the data strobe control circuit is disabled and the first output data strobe signal and the second output data strobe signal remain in the low logic state.

17. The memory device as claimed in claim 15, wherein the auxiliary control circuit comprises: a first amplifier configured to amplify the first data strobe signal to generate a first amplified data strobe signal; a second amplifier configured to amplify the second data strobe signal to generate a second amplified data strobe signal; a first transistor having a gate electrically connected to the first amplified data strobe signal, a drain electrically connected to a first node, and a source electrically connected to a second node; a second transistor having a gate electrically connected to the second amplified data strobe signal, a drain electrically connected to the first node, and a source electrically connected to the second node; a third transistor having a gate electrically connected to the first data strobe signal, a drain electrically connected to a third node, and a source grounded; a fourth transistor having a gate electrically connected to the second data strobe signal, a drain electrically connected to the third node, and a source grounded; a first resistor coupled between the second node and the third node; as well as a second resistor coupled between a power supply voltage and the first node; The disable control signal is generated at the second node. 18 . The memory device as claimed in claim 17 , wherein a first resistance value of the first resistor is smaller than a second resistance value of the second resistor. 19 . The memory device as claimed in claim 17 , wherein an amplitude of the first amplified data strobe signal and the second amplified data strobe signal is higher than a threshold voltage of the first transistor, the second transistor, the third transistor, and the fourth transistor.

20. The memory element of claim 17, wherein when the first transistor, the second transistor, the third transistor and the fourth transistor have the first resistance value and the second resistance value in an on state and an off state respectively, the second resistance value is much higher than the first resistance value.

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