Memory

Abstract

The embodiment of the invention provides a memory, which comprises a logic chip and a plurality of layers of memory chips stacked along a third direction, the memory chip comprises a plurality of memory structures arranged along a first direction and a second direction, and the logic chip comprises a plurality of sense amplifiers arranged along the second direction; the ith bit line in the first storage structure is connected with the ith bit line in the fourth storage structure, and is connected to one end of the corresponding sense amplifier; the ith bit line in the third storage structure is connected with the ith bit line in the second storage structure and is connected to the other end of the corresponding sense amplifier; i is an odd number or an even number; wherein the first storage structure and the third storage structure are adjacent in the third direction; the fourth storage structure and the third storage structure are located on the same storage chip and are adjacent in the first direction; the second storage structure and the fourth storage structure are adjacent in the third direction; the second storage structure and the first storage structure are located on the same storage chip and are adjacent in the first direction.

Description

[0001] Cross - reference to related applications

[0002] This disclosure claims priority to a Chinese patent application filed with the Chinese Patent Office on December 27, 2023, with application number 202311841372.2 and application title "A Memory", the entire content of which is incorporated herein by reference. Technical field

[0003] This disclosure relates to the field of semiconductor technology, and particularly to a memory. Background art

[0004] Dynamic Random Access Memory (DRAM) writes data to the memory by storing charge in the capacitors of the memory cells, and reads data from the memory by reading the charge in the capacitors of the memory cells. In DRAM, multiple sense amplifiers are respectively connected to the bit line BL and the reference bit line BLB. During the data read operation, the sense amplifier is used to amplify the voltage difference between the bit line BL and the reference bit line BLB. However, there is a large parasitic capacitance between the bit lines, which has an adverse effect on the memory performance. Summary of the invention

[0005] Embodiments of this disclosure provide a memory, including a logic chip and multiple layers of memory chips stacked along a third direction. The memory chips include multiple memory structures arranged along a first direction and a second direction. The memory structure has multiple bit lines arranged along the second direction. The logic chip includes multiple sense amplifiers arranged along the second direction. The first direction, the second direction, and the third direction intersect pairwise;

[0006] The i - th bit line in the first memory structure is connected to the i - th bit line in the fourth memory structure and is connected to one end of the corresponding sense amplifier;

[0007] The i - th bit line in the third memory structure is connected to the i - th bit line in the second memory structure and is connected to the other end of the corresponding sense amplifier; i is odd or even;

[0008] Wherein, the first memory structure and the third memory structure are adjacent in the third direction; the fourth memory structure and the third memory structure are located in the same memory chip and are adjacent in the first direction; the second memory structure and the fourth memory structure are adjacent in the third direction; the second memory structure and the first memory structure are located in the same memory chip and are adjacent in the first direction.

[0009] In some embodiments, when i is an even number, the (i + 1)-th bit line in the first storage structure is connected to the (i + 1)-th bit line in the third storage structure; the (i + 1)-th bit line in the second storage structure is connected to the (i + 1)-th bit line in the fourth storage structure;

[0010] When i is an odd number, the (i - 1)-th bit line in the first storage structure is connected to the (i - 1)-th bit line in the third storage structure; the (i - 1)-th bit line in the second storage structure is connected to the (i - 1)-th bit line in the fourth storage structure.

[0011] In some embodiments, the memory further includes a fifth storage structure and a sixth storage structure;

[0012] The i-th bit line in the third storage structure is further connected to the k-th bit line in the fifth storage structure;

[0013] The i-th bit line in the fourth storage structure is further connected to the k-th bit line in the sixth storage structure;

[0014] Wherein, the fifth storage structure and the sixth storage structure are located on the same storage chip and are adjacent in the first direction, the fifth storage structure and the third storage structure are adjacent in the third direction, the sixth storage structure and the fourth storage structure are adjacent in the third direction, and k is an odd number or an even number.

[0015] In some embodiments, the memory further includes a seventh storage structure and an eighth storage structure;

[0016] The k-th bit line in the fifth storage structure is further connected to the k-th bit line in the eighth storage structure;

[0017] The k-th bit line in the sixth storage structure is further connected to the k-th bit line in the seventh storage structure;

[0018] Wherein, the seventh storage structure and the eighth storage structure are located on the same storage chip and are adjacent in the first direction, the seventh storage structure and the fifth storage structure are adjacent in the third direction, the eighth storage structure and the sixth storage structure are adjacent in the third direction.

[0019] In some embodiments, both i and k are even numbers, or both i and k are odd numbers, or one of i is an odd number or an even number and the other of k is an odd number or an even number.

[0020] In some embodiments, the memory further includes a ninth storage structure and a tenth storage structure; in the first direction, the ninth storage structure is located on a side of the fourth storage structure away from the third storage structure, and the tenth storage structure is located on a side of the sixth storage structure away from the fifth storage structure;

[0021] The m-th bit line of the fourth storage structure is connected to the m-th bit line of the tenth storage structure;

[0022] The m-th bit line of the sixth storage structure is connected to the m-th bit line of the ninth storage structure;

[0023] Wherein, the i is one of odd or even, and the m is the other of odd or even.

[0024] In some embodiments, the memory further includes an eleventh storage structure and a twelfth storage structure; in the first direction, the eleventh storage structure is located on a side of the second storage structure away from the first storage structure, and the twelfth storage structure is located on a side of the eighth storage structure away from the seventh storage structure;

[0025] The m-th bit line of the second storage structure is connected to the m-th bit line of the fourth storage structure;

[0026] The m-th bit line of the sixth storage structure is connected to the m-th bit line of the eighth storage structure.

[0027] In some embodiments, denote the bit line connection manner among the first storage structure, the second storage structure, the third storage structure, the fourth storage structure, the fifth storage structure, the sixth storage structure, the seventh storage structure, and the eighth storage structure as a first twisting manner; denote the bit line connection manner among the second storage structure, the fourth storage structure, the sixth storage structure, the eighth storage structure, the ninth storage structure, the tenth storage structure, the eleventh storage structure, and the twelfth storage structure as a second twisting manner;

[0028] In the first direction, the twisting manners between adjacent storage structures alternate between the first twisting manner and the second twisting manner.

[0029] In some embodiments, the memory is a dynamic random access memory, and the logic chip is located within a first wafer;

[0030] All the multi-layer storage chips are located within a second wafer, and the multi-layer storage chips are connected through through-silicon vias; or, the multi-layer storage chips are respectively located within different wafers, and the multi-layer storage chips are connected through a hybrid bonding manner.

[0031] An embodiment of the present disclosure provides a memory, which includes a logic chip and multiple layers of memory chips stacked in a third direction. The memory chips include multiple memory structures arranged in a first direction and a second direction. The memory structures have multiple bit lines arranged in the second direction. The logic chip includes multiple sense amplifiers arranged in the second direction. The first direction, the second direction, and the third direction intersect pairwise. The i-th bit line in the first memory structure is connected to the i-th bit line in the fourth memory structure and is connected to one end of the corresponding sense amplifier. The i-th bit line in the third memory structure is connected to the i-th bit line in the second memory structure and is connected to the other end of the corresponding sense amplifier. i is an odd number or an even number. Among them, the first memory structure and the third memory structure are adjacent in the third direction. The fourth memory structure and the third memory structure are located in the same memory chip and are adjacent in the first direction. The second memory structure and the fourth memory structure are adjacent in the third direction. The second memory structure and the first memory structure are located in the same memory chip and are adjacent in the first direction. Based on this connection method, the parasitic capacitance between bit lines can be reduced, the system noise can be reduced, so that the bit lines in the memory structures adjacent to a certain memory structure can cancel the adverse effects between the bit lines in this memory structure, ensuring the accuracy of data transmission by the bit lines. At the same time, since the adverse effects are cancelled, the bit lines can be made closer, reducing the distance between the bit lines, which is also beneficial to the high integration of the memory and improves the storage density. Description of the Drawings

[0032] Figure 1 is a schematic structural diagram of a DRAM provided by an embodiment of the present disclosure;

[0033] Figure 2 is a schematic composition structure diagram of a memory provided by an embodiment of the present disclosure Figure 1 ;

[0034] Figure 3 is a schematic composition structure diagram of a memory provided by an embodiment of the present disclosure Figure 2 ;

[0035] Figure 4 is a schematic composition structure diagram of a memory provided by an embodiment of the present disclosure Figure 3 ;

[0036] Figure 5 is a schematic composition structure diagram of a memory provided by an embodiment of the present disclosure Figure 4 ;

[0037] Figure 6 is a schematic composition structure diagram of a memory provided by an embodiment of the present disclosure Figure 5 。 Detailed Embodiments

[0038] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than limiting the disclosure. In addition, it should be noted that for the convenience of description, only parts related to the relevant disclosure are shown in the drawings.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0040] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0041] It should be noted that the terms "first / second / third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0042] Before further elaborating on the embodiments of the present disclosure, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are applicable to the following explanations:

[0043] Dynamic Random Access Memory (DRAM);

[0044] Sense Amplifier (SA);

[0045] Hybrid Bonding (HP);

[0046] Contact Pad (PAD);

[0047] Sense Margin;

[0048] Bit Line (BL);

[0049] CELL MAT.

[0050] See Figure 1 , which is a schematic structural diagram of a DRAM provided by the embodiments of the present disclosure. As Figure 1As shown, a logic chip and an array chip are included in the DRAM; among them, the array chip includes a plurality of memory structures (denoted as CELL MAT), and each memory structure includes a plurality of memory cells (not shown in the figure) for storing data and a plurality of bit lines, and one or more memory cells are connected to one bit line. The logic chip includes a plurality of sense amplifiers SA, and each sense amplifier SA is connected to the bit line BL and the reference bit line BLB respectively from two memory structures.

[0051] In Figure 1 , two memory structures are shown, namely memory structure CELL MAT1 and memory structure CELLMAT2, and 4 bit lines BL are shown in each memory structure respectively. As Figure 1 shown, an even-numbered bit line in the memory structure CELL MAT1 and an even-numbered bit line in the memory structure CELL MAT2 are used as references to each other and are connected to the same sense amplifier SA. Here, the bit line used as a reference is denoted as the reference bit line BLB. It can be understood that during different data readout processes, the bit line and the reference bit line can exchange identities, Figure 1 which is only an example.

[0052] As Figure 1 shown, the first even-numbered bit line BL<0> in the memory structure CELL MAT2 and the first even-numbered reference bit line BLB<0> in the memory structure CELLMAT1 are both connected to the sense amplifier BLSA<0>; the second even-numbered bit line BL<2> in the memory structure CELL MAT2 and the second even-numbered reference bit line BLB<2> in the memory structure CELL MAT1 are both connected to the sense amplifier BLSA<2>. The odd-numbered bit lines BL<1> and BL<3> in the memory structure CELL MAT2 can be used as references to the bit lines in other memory structures; the odd-numbered reference bit lines BLB<1> and BLB<3> in the memory structure CELL MAT1 can be used as references to the bit lines in other memory structures.

[0053] In Figure 1 the shown memory, there is very large noise between bit lines, which affects the sensing margin and thus affects the increase in storage density; the overall parasitic capacitance of a bit line includes the parasitic capacitance between bit lines and the parasitic capacitance between the bit line and the rest of the conductive substances in the memory. Especially in the 4F2 structure, since the parasitic capacitance between the bit line and other bit lines accounts for an increasing proportion of the overall parasitic capacitance of the bit line, the problem becomes more serious, restricting the integration degree of the memory.

[0054] Based on this, embodiments of the present disclosure provide a memory. In this memory, bit lines are connected in a twisted manner. Based on this twisted connection method, the parasitic capacitance between bit lines can be reduced, system noise can be decreased, the sensing margin can be increased, such that the bit lines in a storage structure adjacent to a certain storage structure can cancel out the adverse effects between the bit lines in this storage structure, ensuring the accuracy of data transmission by the bit lines. At the same time, since the adverse effects are cancelled out, the bit lines can be made closer, reducing the distance between the bit lines, which is also beneficial to the high integration of the memory and improves the storage density.

[0055] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0056] In an embodiment of the present disclosure, refer to Figure 2 , which shows a schematic composition structure of a memory provided by an embodiment of the present disclosure. Figure 1 As Figure 2 shown, the memory includes a logic chip LC and multiple layers of storage chips AC stacked along a third direction. The storage chip AC includes multiple storage structures CELL MAT arranged along a first direction and a second direction. The storage structure CELLMAT has multiple bit lines BL arranged along the second direction. The logic chip LC includes multiple sense amplifiers SA arranged along the second direction. The first direction, the second direction, and the third direction intersect pairwise.

[0057] The i-th bit line BLB in the first storage structure CELL MAT1 with the i-th bit line BL in the fourth storage structure CELL MAT4 Connect and connect to one end of the corresponding sense amplifier BLSA;

[0058] The i-th bit line BLB in the third storage structure CELL MAT3 with the i-th bit line BL in the second storage structure CELL MAT2 Connect and connect to the other end of the corresponding sense amplifier BLSA; i is odd or even;

[0059] Among them, the first storage structure CELL MAT1 and the third storage structure CELL MAT3 are adjacent in the third direction; the fourth storage structure CELL MAT4 and the third storage structure CELL MAT3 are located in the same memory chip AC-2 and are adjacent in the first direction; the second storage structure CELL MAT2 and the fourth storage structure CELL MAT4 are adjacent in the third direction; the second storage structure CELLMAT2 and the first storage structure CELL MAT1 are located in the same memory chip AC-1 and are adjacent in the first direction.

[0060] It should be noted that the embodiments of the present disclosure relate to semiconductor technologies, such as DRAM circuits, etc., which use multi-layer stacking and twisted bit lines to eliminate noise and are applied to various memories.

[0061] As Figure 2 shown, the extending direction of the bit line BL is denoted as the first direction, the arranging direction of the bit line BL is denoted as the second direction, and the stacking direction of the memory chip AC and the logic chip LC is denoted as the third direction. In this embodiment, taking the case where the first direction, the second direction, and the third direction are perpendicular to each other pairwise as an example, and for the convenience of description, the first direction is regarded as the left-right direction, the second direction is regarded as the front-back direction, and the third direction is regarded as the up-down direction.

[0062] It should also be noted that the bit lines in two adjacent storage structures CELL MAT adjacent along the first direction are at least partially reference to each other. The bit lines in two adjacent storage structures CELL MAT are respectively denoted as the bit line BL and the reference bit line BLB. It can be understood that in different cases, the bit line BL and the reference bit line BLB can exchange identities. In this embodiment, the reference bit line BLB is also directly referred to as the bit line BLB.

[0063] In this embodiment, each storage structure includes multiple storage units. One bit line is connected to multiple storage units and is connected to the corresponding sense amplifier. Taking the storage structure having N bit lines and the sorting of the bit lines in the storage structure starting from 0 as an example, i is an odd or even number greater than or equal to 0 and less than N.

[0064] In the embodiments of the present disclosure, mainly taking i as an even number as an example to illustrate each specific implementation manner, the case where i is an odd number is the same as the case where i is an even number, so the same description is omitted.

[0065] As Figure 2 shown, the bit line BLB in the first storage structure CELL MAT1 and the bit line BL in the second storage structure CELL MAT2 For mutual reference, both are connected to the same sense amplifier SA; the bit line BLB in the third storage structure CELL MAT3 and the bit line BL in the fourth storage structure CELL MAT4 For mutual reference, both are connected to the same sense amplifier SA, where i is odd or even. That is, two odd-bit bit lines or two even-bit bit lines with the same sorting in adjacent memory structures are for mutual reference.

[0066] Figure 2 The figure shows two-layer memory chips AC, denoted as the first memory chip AC-1 and the second memory chip AC-2 respectively. The first memory chip AC-1 includes a first memory structure CELL MAT1 and a second memory structure CELL MAT2, and the second memory chip AC-2 includes a third memory structure CELL MAT3 and a fourth memory structure CELL MAT4. In the drawings of the embodiments of the present disclosure, only four bit lines in each memory structure are shown as examples. In practice, each memory structure may include a greater number of bit lines. Similarly, each memory chip may also include a greater number of memory structures, and the memory may include more layers of memory chips. Among them, the first memory structure CELL MAT1 is directly above the third memory structure CELL MAT3, the second memory structure CELL MAT2 is directly above the fourth memory structure CELL MAT4, the fourth memory structure CELL MAT4 is located at the lower right of the first memory structure CELL MAT1, and the third memory structure CELL MAT3 is located at the lower left of the second memory structure CELL MAT2.

[0067] The connection lines from the bit lines in each memory structure to the sense amplifier are called bit line connection lines. As Figure 2 shown, the bit line BLB<0> in the first memory structure CELL MAT1 is connected to the bit line BL<0> in the fourth memory structure CELL MAT4 through the first bit line connection line 101 and is connected to one end of the sense amplifier BLSA<0>. The bit line BL<0> in the second memory structure CELL MAT2 is connected to the bit line BLB<0> in the third memory structure CELL MAT3 through the second bit line connection line 102 and is connected to the other end of the sense amplifier BLSA<0>. The bit line BLB<2> in the first memory structure CELL MAT1 is connected to the bit line BL<2> in the fourth memory structure CELL MAT4 through the third bit line connection line 103 and is connected to one end of the sense amplifier BLSA<2>. The bit line BL<2> in the second memory structure CELL MAT2 is connected to the bit line BLB<2> in the third memory structure CELL MAT3 through the fourth bit line connection line 104 and is connected to the other end of the sense amplifier BLSA<2>. C in the third memory structure CELL MAT3 roughly represents the parasitic capacitance between the bit lines here.

[0068] In this way, as Figure 2 As shown, for the even-bit bit lines in the storage structure, they are not directly connected to the bit lines at the corresponding positions in the storage structure adjacent in the third direction, but are "twisted" to the storage structure adjacent in the first direction of the storage structure adjacent in the third direction and serving as a reference for the even-bit bit lines. Based on this twisted connection method, the parasitic capacitance between bit lines can be reduced, the coupling noise between storage chips can be reduced, and it is ensured that the data transmitted by the bit lines is not affected by adjacent bit lines and data transmission errors do not occur.

[0069] For example, when reading data from the second storage structure CELL MAT2, assuming that in the second storage structure CELL MAT2, the data transmitted by bit line BL<0>, bit line BL<1>, and bit line BL<2> are 1 (logical high level), 0 (logical low level), and 1 respectively, then the data of bit line BLB<0>, bit line BLB<1>, and bit line BLB<2> in the first storage structure CELL MAT1 can be regarded as 0, 1, and 0 relatively; the amplification of the data of bit line BL<0> and bit line BL<2> in the second storage structure CELL MAT2 will have an adverse effect on bit line BL<1>. For example, due to the coupling effect of the parasitic capacitance, the potential of bit line BL<1> is pulled up, and then the data of bit line BL<1> may be misread or miswritten as 1. At this time, based on this "twisted" structure, bit line BL<0> in the fourth storage structure CELL MAT4 is connected to bit line BLB<0> in the first storage structure CELL MAT1, so it also shows 0. Similarly, bit line BL<2> in the fourth storage structure CELL MAT4 can also be regarded as 0. Bit line BL<0> and bit line BL<2> in the fourth storage structure CELL MAT4 also have an impact on bit line BL<1> in the second storage structure CELL MAT2. And because the data of bit line BL<0> and bit line BL<2> in the fourth storage structure CELL MAT4 is 0, this impact is opposite to the impact of bit line BL<0> and bit line BL<2> on bit line BL<1> in the second storage structure CELL MAT2, which is beneficial to at least partially offset the impact of bit line BL<0> and bit line BL<2> in the second storage structure CELL MAT2, ensuring the correct reading and writing of the data of bit line BL<1> in the second storage structure CELL MAT2. The same is true for the rest of the reading cases and will not be elaborated here.

[0070] In this way, the embodiments of the present disclosure use twisted data line interconnection to effectively eliminate noise (coupling noise between different bit lines in the same storage structure and bit line coupling noise between storage structures adjacent in the third direction), improve the sensing margin, and are beneficial to achieving a higher DRAM integration degree.

[0071] It should be noted that the attached drawings are not drawn to scale for clearly showing the structure of the memory. In reality, the distance between each memory chip in the third direction is not as far apart as shown in the figure, so the bit lines in the adjacent memory structures in the third direction can affect each other.

[0072] It should also be noted that for Figure 2 the example, the even-bit bit lines in the memory structure are twisted to compensate for the coupling noise, that is, the original bit lines are connected to the bit lines directly below, and now they are changed to be connected to the bit lines directly below the mutually referenced bit lines, "exchanging" the connection objects. Additionally, if the even-bit bit lines in the memory structure are twisted and connected to the bit lines in the memory chip on one side in the third direction, the odd-bit bit lines in this memory structure can be set not to be twisted and connected to the bit lines in the memory chip on the same side, that is, "not exchanged".

[0073] In Figure 2 On the basis of Figure 3 As shown, in some embodiments, when i is an even number, the (i + 1)-th bit line BLB<i + 1> in the first memory structure CELLMAT1 is connected to the (i + 1)-th bit line BLB<i + 1> in the third memory structure CELL MAT3; the (i + 1)-th bit line BL<i + 1> in the second memory structure CELL MAT2 is connected to the (i + 1)-th bit line BL<i + 1> in the fourth memory structure CELL MAT4.

[0074] As Figure 3 shown, in this example, the bit line BLB<1> in the first memory structure CELL MAT1 is connected to the bit line BLB<1> in the third memory structure CELL MAT3 and connected to the corresponding sense amplifier (not shown in the figure); the bit line BLB<3> in the first memory structure CELL MAT1 is connected to the bit line BLB<3> in the third memory structure CELL MAT3 and connected to the corresponding sense amplifier (not shown in the figure); the bit line BL<1> in the second memory structure CELL MAT2 is connected to the bit line BL<1> in the fourth memory structure CELL MAT4 and connected to the corresponding sense amplifier (not shown in the figure); the bit line BL<3> in the second memory structure CELL MAT2 is connected to the bit line BL<3> in the fourth memory structure CELL MAT4 and connected to the corresponding sense amplifier (not shown in the figure).

[0075] As Figure 4 shown, in some other embodiments, when i is an odd number, the (i - 1)-th bit line BLB in the first memory structure CELL MAT1 <i-1>with the (i - 1)-th bit line BLB in the third storage structure CELL MAT3 <i-1>Connection; the (i - 1)-th bit line BL in the second storage structure CELL MAT2 <i-1>with the (i - 1)-th bit line BL in the fourth storage structure CELL MAT4 <i-1>Connection

[0076] As Figure 4 shown, in this example, the first bit line BLB<1> in the first storage structure CELL MAT1 is twisted and connected to the bit line in the corresponding order in the storage structure (not shown) located at its lower left, and is connected to the corresponding sense amplifier (not shown in the figure). The twisting method of the even-numbered bit lines in Figure 3 is the same. Similarly for the third bit line BLB<3>. The first bit line BLB<1> in the third storage structure CELL MAT3 is twisted and connected to the bit line in the corresponding order in the storage structure (not shown) located at its upper left, and is connected to the corresponding sense amplifier (not shown in the figure). Similarly for the third bit line BLB<3>. The first bit line BLB<1> in the second storage structure CELL MAT2 is twisted and connected to the bit line in the corresponding order in the storage structure (not shown) located at its lower right, and is connected to the corresponding sense amplifier (not shown in the figure). Similarly for the third bit line BLB<3>. The first bit line BLB<1> in the fourth storage structure CELL MAT4 is twisted and connected to the bit line in the corresponding order in the storage structure (not shown) located at its upper right, and is connected to the corresponding sense amplifier (not shown in the figure). Similarly for the third bit line BLB<3>. The even-numbered bit line BLB<0> in the first storage structure CELL MAT1 is directly connected to the even-numbered bit line BL<0> in the third storage structure CELL MAT3 located below it. Similarly for the even-numbered bit line BLB<2>. The even-numbered bit line BLB<0> in the second storage structure CELL MAT2 is directly connected to the even-numbered bit line BL<2> in the fourth storage structure CELL MAT4 located below it. Similarly for the even-numbered bit line BLB<2>.

[0077] On the basis of Figure 2 as Figure 5 shown, the memory further includes a fifth storage structure CELL MAT5 and a sixth storage structure CELL MAT6;

[0078] The i-th bit line BLB in the third storage structure CELL MAT3 is also connected to the k-th bit line BLB in the fifth storage structure CELL MAT5 <k>Connection;

[0079] The i-th bit line BL in the fourth storage structure CELL MAT4 is also connected to the k-th bit line BL in the sixth storage structure CELL MAT6 <k>Connection;

[0080] Among them, the fifth storage structure CELL MAT5 and the sixth storage structure CELL MAT6 are located on the same storage chip AC-3 and are adjacent in the first direction. The fifth storage structure CELL MAT5 is adjacent to the third storage structure CELL MAT3 in the third direction, and the sixth storage structure CELL MAT6 is adjacent to the fourth storage structure CELL MAT4 in the third direction. k is odd or even.

[0081] Among them, both i and k are even, or both i and k are odd, or one of i is odd or even and the other of k is odd or even.

[0082] It should be noted that when both i and k are odd or even, i can be equal to k; when one of i and k is odd and the other is even, the difference between i and k can be 1. In Figure 5 , taking both i and k as even and i being equal to k as an example, the principles of the other several implementation methods are similar, and this embodiment will not be illustrated in the drawings.

[0083] Such as Figure 5 shown, the memory further includes a third storage chip AC-3, and the third storage chip AC-3 includes a fifth storage structure CELL MAT5 and a sixth storage structure CELL MAT6. The fifth storage structure CELL MAT5 is located below the third storage structure CELL MAT3, and the sixth storage structure CELL MAT6 is located below the fourth storage structure CELL MAT4.

[0084] In this example, the even-bit bit lines in the second storage chip AC-2 are twisted and connected to the even-bit bit lines in the upper first storage chip AC-1, and there is no "twist" with the bit lines in the lower third storage chip AC-3. Such as Figure 5 shown, the bit line BLB<0> in the third storage chip CELL MAT3 is connected to the bit line BLB<0> in the fifth storage chip CELL MAT5; the bit line BLB<2> in the third storage chip CELL MAT3 is connected to the bit line BLB<2> in the fifth storage chip CELL MAT5; the bit line BL<0> in the fourth storage chip CELL MAT4 is connected to the bit line BL<0> in the sixth storage chip CELL MAT6; the bit line BL<2> in the fourth storage chip CELL MAT4 is connected to the bit line BLB<2> in the sixth storage chip CELL MAT6.

[0085] It can be seen that in the connection in the third direction, the i-th bit line can be "twisted" on one side and "untwisted" on the other side.

[0086] Furthermore, such as Figure 5 As shown, in some embodiments, the memory further includes a seventh storage structure CELL MAT7 and an eighth storage structure CELL MAT8;

[0087] The k-th bit line BLB in the fifth storage structure CELL MAT5 <k>is also connected to the k-th bit line BL in the eighth storage structure CELL MAT8 <k>Connection;

[0088] The k-th bit line BLB of CELL MAT6 in the sixth storage structure <k>is also connected to the k-th bit line BLB in the seventh storage structure CELL MAT7 <k>Connection;

[0089] Among them, the seventh storage structure CELL MAT7 and the eighth storage structure CELL MAT8 are located on the same storage chip and are adjacent in the first direction. The seventh storage structure CELL MAT7 is adjacent to the fifth storage structure CELL MAT5 in the third direction, and the eighth storage structure CELL MAT8 is adjacent to the sixth storage structure CELL MAT6 in the third direction.

[0090] It should be noted that as Figure 5 shown, the memory further includes a fourth storage chip AC-4 located below the third storage chip AC-3. The fourth storage chip AC-4 includes a seventh storage structure CELL MAT7 and an eighth storage structure CELL MAT8. Among them, the seventh storage structure CELL MAT is located below the fifth storage structure CELL MAT5, and the eighth storage structure CELL MAT8 is located below the sixth storage structure CELL MAT6.

[0091] The even-bit bit lines in the fifth storage structure CELL MAT5 are twisted and connected to the even-bit bit lines in the eighth storage structure CELL MAT8, and the even-bit bit lines in the sixth storage structure CELL MAT6 are twisted and connected to the even-bit bit lines in the seventh storage structure CELL MAT7. As Figure 5 shown, the bit line BLB<0> in the fifth storage structure CELL MAT5 is connected to the bit line BL<0> in the eighth storage structure CELL MAT8; the bit line BLB<2> in the fifth storage structure CELL MAT5 is connected to the bit line BL<2> in the eighth storage structure CELL MAT8; the bit line BL<0> in the sixth storage structure CELL MAT6 is connected to the bit line BLB<0> in the seventh storage structure CELL MAT7; the bit line BL<2> in the sixth storage structure CELL MAT6 is connected to the bit line BLB<2> in the seventh storage structure CELL MAT7.

[0092] In addition, as Figure 5 shown, the odd-bit bit lines BLB<1> and BLB<3> in the third storage structure CELL MAT3 are not twisted with the bit lines in the upper first storage chip AC-1 and are twisted and connected to the bit lines in the unshown storage structure located at its lower left; the odd-bit bit lines in the fifth storage structure CELL MAT5 are twisted and connected to the bit lines in the unshown storage structure located at its upper left and are not twisted with the odd-bit bit lines in the seventh storage structure CELL MAT7 located below it. The same applies to the second, fourth, sixth, and eighth storage structures, which will not be elaborated here.

[0093] On the basis of Figure 5 as Figure 6 As shown, the memory further includes a ninth storage structure CELL MAT9 and a tenth storage structure CELL MAT10. The ninth storage structure CELL MAT9 belongs to the second storage chip AC-2, and the tenth storage structure CELL MAT10 belongs to the third storage chip AC-3. In the first direction, the ninth storage structure CELL MAT9 is located on the side of the fourth storage structure CELL MAT4 away from the third storage structure CELL MAT3, and the tenth storage structure CELL MAT10 is located on the side of the sixth storage structure CELL MAT6 away from the fifth storage structure CELL MAT5;

[0094] The m-th bit line BL of the fourth storage structure CELL MAT4 <m>With the m-th bit line BLB of the tenth storage structure CELL MAT10 <m>Connection;

[0095] The m-th bit line BL of the sixth storage structure CELL MAT <m>with the m-th bit line BLB of the ninth memory structure CELL MAT9 <m>Connection;

[0096] Wherein, i is one of odd or even, and m is the other of odd or even.

[0097] In this embodiment, on both sides along the first direction, a plurality of storage structures arranged in the same manner may be included. Similarly, in the second direction, and in the third direction, a plurality of memory chips may be stacked in the same manner.

[0098] In Figure 6 the even-numbered bit lines BL / BLB are twisted to compensate for the coupling noise between the first memory chip AC-1 and the second memory chip AC-2, and to compensate for the coupling noise between the third memory chip AC-3 and the fourth memory chip AC-4. The odd-numbered bit lines BL / BLB are also twisted between the second memory chip AC-2 and the third memory chip AC-3.

[0099] In Figure 6 the example of, i is even and m is odd. Taking the fourth storage structure CELL MAT4 as an example, the even-numbered bit line BL with the even-bit bit lines BLB in the first storage structure CELL MAT1 located at its upper left Twisted connection, in which the odd-numbered bit lines BL <m>and the odd-bit bit line BLB in the tenth storage structure CELL MAT10 located at its lower right <m>Twisted connection.

[0100] It can be seen that in the embodiments of the present disclosure, it may be that: the bit line has a twisted connection with the bit line in one of the upper and lower memory chips, and has no twisted connection with the bit line in the other; thus, for each bit line, there is a twisted connection (the top chip and the bottom chip are special cases, and there may be an odd number or an even number of bit lines without a twisted connection), thereby reducing the parasitic capacitance between bit lines, reducing the coupling noise, and ensuring the accuracy of data transmission on the bit lines.

[0101] In the embodiments of the present disclosure, it may also be that: the odd-numbered bit lines and the even-numbered bit lines in any memory structure do not simultaneously have a twisted connection with the bit lines in the same memory chip. Instead, if the even-numbered bit lines have a twisted connection with the bit lines in the upper memory chip, then the odd-numbered chips have a twisted connection with the bit lines in the lower memory chip, such as Figure 6 the third memory chip CELL MAT3 in; if the even-numbered bit lines have a twisted connection with the bit lines in the lower memory chip, then the odd-numbered chips have a twisted connection with the bit lines in the upper memory chip, such as Figure 6 the sixth memory chip CELL MAT6 in. In this way, problems such as parasitic capacitance and parasitic resistance caused by too long wiring are also avoided.

[0102] In some embodiments, as Figure 6 shown, the memory further includes an eleventh memory structure CELL MAT11 and a twelfth memory structure CELL MAT12. Among them, the eleventh memory structure CELL MAT11 belongs to the first memory chip AC-1, and the twelfth memory chip CELL MAT12 belongs to the fourth memory chip AC-1. In the first direction, the eleventh memory structure CELL MAT11 is located on the side of the second memory structure CLEE MAT2 away from the first memory structure CELL MAT1, and the twelfth memory structure CELLMAT12 is located on the side of the eighth memory structure CELL MAT8 away from the seventh memory structure CELL MAT7;

[0103] The m-th bit line BL of the second memory structure CELL MAT2 <m>with the m-th bit line BL of the fourth storage structure CELL MAT4 <m>Connection;

[0104] The m-th bit line BL of the sixth storage structure CELL MAT6 <m>with the m-th bit line BL of the eighth memory structure CELL MAT8 <m>Connection;

[0105] The m-th bit line BLB of the eleventh storage structure CELL MAT11 <m>with the m-th bit line BLB of the ninth memory structure CELL MAT9 <m>Connection;

[0106] The m-th bit line BLB of the tenth storage structure CELL MAT10 <m>with the m-th bit line BLB of the twelfth memory structure CELL MAT12 <m>Connection

[0107] Based on the foregoing Figures 2 to 6 , each storage structure may include multiple bit lines. Based on this stacked structure, the storage density can be increased, such as a 4-layer memory chip. Additionally, due to the reduction of parasitic capacitance, the distance between bit lines can be made closer in the storage structure, which further improves the storage density.

[0108] In the embodiments of the present disclosure, as Figure 6 shown, denote the bit line connection method between the first storage structure CELL MAT1, the second storage structure CELLMAT2, the third storage structure CELL MAT3, the fourth storage structure CELL MAT4, the fifth storage structure CELL MAT5, the sixth storage structure CELL MAT6, the seventh storage structure CELL MAT7, and the eighth storage structure CELL MAT8 as the first twisting method, and denote the bit line connection method between the second storage structure CELL MAT2, the fourth storage structure CELL MAT4, the sixth storage structure CELL MAT6, the eighth storage structure CELL MAT8, the ninth storage structure CELL MAT9, the tenth storage structure CELL MAT10, the eleventh storage structure CELL MAT11, and the twelfth storage structure CELL MAT12 as the second twisting method. It can be seen that in the first direction, the twisting methods between adjacent storage structures CELL MAT alternate between the first twisting method and the second twisting method. Thereby reducing the parasitic capacitance of each bit line and reducing the system noise.

[0109] In some embodiments, the logic chip LC is located in the first wafer. For the memory chip, in the first implementation manner, multiple-layer memory chips AC are all located in the second wafer, and the multiple-layer memory chips AC are electrically connected through through-silicon vias or other fixing methods; or in the second implementation manner, multiple-layer memory chips AC are respectively located in different wafers, and the multiple-layer memory chips are connected through hybrid bonding.

[0110] Take Figure 5 as an example, the four-layer memory chip can be four array chips respectively, or can be created together on one chip (silicon wafer).

[0111] It should be noted that based on different architectures, the embodiments of the present disclosure can use through-silicon vias TSV or HB to connect each memory chip, and the logic chip LC and the nearest memory chip AC to it can be connected through HB. This memory can be a DRAM.

[0112] In summary, the existing DRAM architectures currently have the following problems: very large noise, which affects the sensing margin and thus affects the increase in storage density; especially in the 4F2 structure, due to the increase in the proportion of the parasitic capacitance between bit lines in the overall parasitic capacitance of the bit lines, the problem becomes more serious. Therefore, the embodiments of the present disclosure design a new architecture to eliminate noise and at the same time provide high integration (i.e., high storage density) of DRAM. Specifically, the embodiments of the present disclosure utilize hybrid bonding technology to implement the logic chip of the peripheral circuit on one wafer (the first wafer); the DRAM (multiple memory chips) is implemented on another wafer (the second wafer) or multiple wafers to implement the WoW architecture. During the interconnection implementation process, by effectively optimizing and twisting the bit line method, for example, twisting the bit lines / reference bit lines of even or odd bits, the noise of the system can be reduced, and thus higher DRAM integration can be achieved, such as double or quadruple, or even higher.

[0113] As described above, the above are only the preferred embodiments of the present disclosure and are not used to limit the protection scope of the present disclosure.

[0114] It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element.

[0115] The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the superiority or inferiority of the embodiments.

[0116] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0117] The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0118] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0119] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claimed rights.< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. A memory, characterized in that: A logic chip and a multi-layer memory chip are stacked along a third direction, wherein the memory chip comprises a plurality of memory structures arranged along a first direction and a second direction, wherein the memory structures have a plurality of bit lines arranged along the second direction, and the logic chip comprises a plurality of sense amplifiers arranged along the second direction, wherein the first direction, the second direction and the third direction intersect each other; The i-th bit line in the first storage structure is connected to the i-th bit line in the fourth storage structure and is connected to one end of the corresponding sense amplifier; The i-th bit line in the third storage structure is connected to the i-th bit line in the second storage structure and is connected to the other end of the corresponding sense amplifier; The i is an odd number or an even number; Among them, the first storage structure is adjacent to the third storage structure in the third direction; the fourth storage structure and the third storage structure are located in the same storage chip and are adjacent to each other in the first direction; the second storage structure and the fourth storage structure are adjacent to each other in the third direction; the second storage structure and the first storage structure are located in the same storage chip and are adjacent to each other in the first direction.

2. The memory according to claim 1, characterized in that: When i is an even number, the i+1th bit line in the first storage structure is connected to the i+1th bit line in the third storage structure; the i+1th bit line in the second storage structure is connected to the i+1th bit line in the fourth storage structure; When i is an odd number, the i-1th bit line in the first storage structure is connected to the i-1th bit line in the third storage structure; the i-1th bit line in the second storage structure is connected to the i-1th bit line in the fourth storage structure.

3. The memory according to claim 1, characterized in that: The memory further includes a fifth storage structure and a sixth storage structure; The i-th bit line in the third storage structure is also connected to the k-th bit line in the fifth storage structure; The i-th bit line in the fourth storage structure is also connected to the k-th bit line in the sixth storage structure; Among them, the fifth storage structure and the sixth storage structure are located in the same storage chip and are adjacent in the first direction, the fifth storage structure and the third storage structure are adjacent in the third direction, the sixth storage structure and the fourth storage structure are adjacent in the third direction, and k is an odd number or an even number.

4. The memory according to claim 3, characterized in that: The memory also includes a seventh storage structure and an eighth storage structure; The kth bit line in the fifth storage structure is also connected to the kth bit line in the eighth storage structure; The kth bit line in the sixth storage structure is also connected to the kth bit line in the seventh storage structure; Among them, the seventh storage structure and the eighth storage structure are located in the same storage chip and are adjacent to each other in the first direction, the seventh storage structure and the fifth storage structure are adjacent to each other in the third direction, and the eighth storage structure and the sixth storage structure are adjacent to each other in the third direction.

5. The memory according to claim 3, characterized in that: The i and the k are both even numbers, or the i and the k are both odd numbers, or the i is one of an odd number or an even number, and the k is the other of an odd number or an even number.

6. The memory according to claim 4, characterized in that: The memory further includes a ninth storage structure and a tenth storage structure; in the first direction, the ninth storage structure is located on a side of the fourth storage structure away from the third storage structure, and the tenth storage structure is located on a side of the sixth storage structure away from the fifth storage structure; The mth bit line of the fourth storage structure is connected to the mth bit line of the tenth storage structure; The mth bit line of the sixth storage structure is connected to the mth bit line of the ninth storage structure; Here, the i is one of an odd number or an even number, and the m is the other of an odd number or an even number.

7. The memory according to claim 6, characterized in that: The memory further includes an eleventh storage structure and a twelfth storage structure; in the first direction, the eleventh storage structure is located on a side of the second storage structure away from the first storage structure, and the twelfth storage structure is located on a side of the eighth storage structure away from the seventh storage structure; The mth bit line of the second storage structure is connected to the mth bit line of the fourth storage structure; The m-th bit line of the sixth memory structure is connected to the m-th bit line of the eighth memory structure.

8. The memory according to claim 7, characterized in that: The bit line connection mode among the first storage structure, the second storage structure, the third storage structure, the fourth storage structure, the fifth storage structure, the sixth storage structure, the seventh storage structure and the eighth storage structure is recorded as a first twisted mode; The bit line connection mode among the second storage structure, the fourth storage structure, the sixth storage structure, the eighth storage structure, the ninth storage structure, the tenth storage structure, the eleventh storage structure and the twelfth storage structure is recorded as a second twisted mode; In the first direction, the twisting modes between adjacent storage structures are alternately the first twisting mode and the second twisting mode.

9. The memory according to any one of claims 1 to 8, characterized in that: The memory is a dynamic random access memory, and the logic chip is located in the first wafer; The multi-layer memory chips are all located in the second wafer, and the multi-layer memory chips are connected through silicon vias; or, the multi-layer memory chips are respectively located in different wafers, and the multi-layer memory chips are connected through hybrid bonding.

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