Test device of latch circuit, operation method of test device, and storage device

Abstract

A test apparatus for performing a test operation on a latch circuit including a plurality of latches is provided. The test apparatus includes: a counter configured to output test data to a test target latch selected from the plurality of latches in response to a clock signal, and increase a value of the test data in response to the clock signal; a comparison circuit configured to receive the test data output from the counter as a first input, receive test data output from the test target latch as a second input, and output a comparison signal by comparing the first input with the second input; and a determination circuit configured to generate a defect determination value indicating whether the latch circuit has a defect based on the comparison signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0193183, filed with the Korean Intellectual Property Office on December 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] One or more example embodiments of the present disclosure relate to a test apparatus for performing a test operation on a latch circuit. Background art

[0004] Memory devices can be classified as volatile memory devices and non - volatile memory devices according to whether they lose stored data when the power supply is interrupted. Non - volatile memory devices include electrically erasable and programmable flash memory devices.

[0005] Memory devices can use multiple latches to input and output data. However, if a defect occurs in any one of the multiple latches included in the memory device, the reliability of the memory device may deteriorate. Therefore, a method for accurately determining whether multiple latches in a memory device are defective is needed. Summary of the invention

[0006] One or more example embodiments of the present invention provide a test apparatus capable of accurately detecting defects occurring in multiple latches.

[0007] According to an aspect of an example embodiment of the inventive concept, there is provided a test apparatus for performing a test operation on a latch circuit including a plurality of latches, the test apparatus including: a counter configured to output test data to a test target latch selected from the plurality of latches in response to a clock signal and increase the value of the test data in response to the clock signal; a comparison circuit configured to receive the test data output from the counter as a first input, receive the test data output from the test target latch as a second input, and output a comparison signal by comparing the first input with the second input; and a determination circuit configured to generate a defect determination value indicating whether the latch circuit is defective based on the comparison signal.

[0008] According to an aspect of an exemplary embodiment of the inventive concept, there is provided an operation method of a test apparatus for performing a test operation on a latch circuit including a plurality of latches, the operation method including: outputting, by a counter of the test apparatus, test data to a test target latch selected from the plurality of latches in response to a clock signal; increasing, by the counter, a value of the test data in response to the clock signal; receiving, by a comparison circuit of the test apparatus, the test data output from the counter as a first input; receiving, by the comparison circuit, test data output from the test target latch as a second input; outputting, by the comparison circuit, a comparison signal by comparing the first input with the second input; and generating, by a determination circuit of the test apparatus, a defect determination value indicating whether the latch circuit has a defect based on the comparison signal.

[0009] According to an aspect of an exemplary embodiment of the inventive concept, there is provided a storage device including a memory cell region and a peripheral circuit region, the memory cell region including a memory cell array, and the peripheral circuit region being connected to the memory cell region. The peripheral circuit region includes a latch circuit having a plurality of latches and a test apparatus configured to perform a test operation on the latch circuit. The test apparatus includes a counter configured to output test data to a test target latch selected from the plurality of latches in response to a clock signal and increase a value of the test data in response to the clock signal; a comparison circuit configured to receive the test data output from the counter as a first input, receive test data output from the test target latch as a second input, and output a comparison signal by comparing the first input with the second input; and a determination circuit configured to generate a defect determination value indicating whether the latch circuit has a defect based on the comparison signal.

[0010] According to an aspect of an exemplary embodiment of the inventive concept, there is provided a storage device including a nonvolatile memory and a storage controller configured to control an operation of the nonvolatile memory. The nonvolatile memory includes a latch circuit and a test apparatus, the latch circuit including a plurality of latches, and the test apparatus being configured to perform a test operation on the latch circuit. The test apparatus includes: a counter configured to output test data to a test target latch selected from the plurality of latches in response to a clock signal and configured to increase a value of the test data in response to the clock signal; a comparison circuit configured to receive the test data output from the counter as a first input and receive test data output from the test target latch as a second input, and configured to output a comparison signal by comparing the first input with the second input; and a determination circuit configured to generate a defect determination value indicating whether the latch circuit has a defect based on the comparison signal. Description of the Drawings

[0011] The embodiments will be understood more clearly from the following detailed description in conjunction with the drawings, in which:

[0012] Figure 1 is a block diagram showing a latch circuit and a test device for determining whether the latch circuit has a defect according to one or more example embodiments;

[0013] Figure 2 is a block diagram showing the detailed structure of a test device and a latch circuit according to one or more example embodiments;

[0014] Figure 3 is a timing diagram showing an example of the operation of a test device according to one or more exemplary embodiments;

[0015] Figure 4 is a timing diagram showing another example of the operation of a test device according to one or more exemplary embodiments;

[0016] Figure 5 is a timing diagram showing another example of the operation of a test device according to one or more exemplary embodiments;

[0017] Figure 6 is a table showing an example of signals and data for a test device according to one or more exemplary embodiments;

[0018] Figure 7 is a table showing another example of signals and data for a test device according to one or more exemplary embodiments;

[0019] Figure 8 is a flowchart showing a method of operating a test device according to one or more exemplary embodiments;

[0020] Figure 9 is a flowchart showing a method of outputting a comparison signal in a test device according to one or more exemplary embodiments;

[0021] Figure 10 is a block diagram showing a memory device including a test device according to one or more exemplary embodiments;

[0022] Figure 11 is a block diagram showing a storage device including a test device according to one or more exemplary embodiments; and

[0023] Figure 12 is a block diagram showing an example of applying a memory device to a solid state drive (SSD) system according to one or more example embodiments. Detailed Description of the Embodiments

[0024] In the following, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 FIG. 1 is a block diagram showing a test device and a latch circuit according to one or more exemplary embodiments, where the test device determines whether the latch circuit has a defect.

[0026] Referring to Figure 1 , a test device 100 according to one or more exemplary embodiments can perform a test operation on a latch circuit 200. The test operation can include an operation for determining whether the latch circuit 200 has a defect. The test device 100 can input test data into a plurality of latches 210 included in the latch circuit 200, and can compare the test data output after passing through the plurality of latches 210 included in the latch circuit 200 with the input test data to determine whether the latch circuit 200 has a defect.

[0027] The latch circuit 200 can include a plurality of latches 210. The test device 100 can determine whether a defect occurs in the plurality of latches 210 in the latch circuit 200.

[0028] In one embodiment, the latch circuit 200 can be included in a memory device, but the embodiment is not limited thereto. Different from the above, the latch circuit 200 can be included in an electronic device other than a memory device, and the test device 100 can perform a test operation on the latch circuit 200 included in an electronic device other than a memory device.

[0029] In an embodiment, the latch circuit 200 can be provided on the same chip as the test device 100. For example, the latch circuit 200 can be provided on a memory chip, and the test device 100 can be provided on the same memory chip as the memory chip on which the latch circuit 200 is provided.

[0030] A test device 100 according to one or more exemplary embodiments can include a counter 110, a comparison circuit 120, and a determination circuit 130.

[0031] In an embodiment, the counter 110 can output test data to the latch circuit 200 in response to a clock signal. Additionally, the counter 110 can output test data to the comparison circuit 120 in response to a clock signal.

[0032] The test data can include data for determining whether the plurality of latches 210 included in the latch circuit 200 are operating normally.

[0033] In an embodiment, the counter 110 may increase the value of test data in response to a clock signal. The test device 100 may output the test data to the latch circuit 200 while increasing the value of the test data by the counter 110, so as to input all types of values of the test data that can be input into the latch circuit 200.

[0034] In an embodiment, the latch circuit 200 may transfer the test data through a test target latch selected from a plurality of latches 210. The test target latch may include a latch on which a test operation is performed using the test data. The test target latch may receive an input of the test data output from the counter 110, and may transfer the test data through an internal circuit and output the test data to the comparison circuit 120.

[0035] In an embodiment, the comparison circuit 120 may receive the test data output from the counter 110 as a first input. The comparison circuit 120 may receive the test data output from the test target latch as a second input. The comparison circuit 120 may output a comparison signal by comparing the first input with the second input. The comparison signal may indicate whether the first input is the same as the second input.

[0036] In an embodiment, the determination circuit 130 may generate a defect determination value indicating whether the latch circuit 200 has a defect based on the comparison signal.

[0037] Reference Figure 2 Describe in detail the operations of the above test device 100 and latch circuit 200.

[0038] Figure 2 is a block diagram showing a detailed structure of a test device and a latch circuit according to one or more exemplary embodiments.

[0039] Reference Figure 2 According to one or more exemplary embodiments, the test device 100 may include a counter 110, a comparison circuit 120, and a determination circuit 130.

[0040] The test device 100 may perform a test operation on the latch circuit 200 in response to a test command received from an external device (e.g., a defect detection device, a host device, etc.). The test command may include a command for performing a test operation on the latch circuit 200.

[0041] The counter 110 may store test data 111. The test data 111 may contain data for detecting a defect in any one of the first latch 210_1 to the nth latch 210_n (n is a natural number of 2 or greater), and the value of the test data 111 may be continuously changed by the counter 110.

[0042] The counter 110 can receive a clock signal CLK. The counter 110 can receive the clock signal CLK from a clock generator in the test device 100 or a clock generator in a device including the test device 100.

[0043] The counter 110 can output test data 111 in response to the clock signal CLK.

[0044] In an embodiment, the counter 110 can output the test data 111 in response to the first edge of the clock signal CLK. Here, the first edge of the clock signal CLK can be a rising edge, but the embodiment is not limited thereto. The first edge of the clock signal CLK can be a falling edge. Additionally, the second edge of the clock signal CLK can be a falling edge, but the embodiment is not limited thereto. The second edge of the clock signal CLK can be a rising edge. The following description focuses on an embodiment in which the first edge of the clock signal CLK is a rising edge and the second edge of the clock signal CLK is a falling edge.

[0045] The counter 110 can output the test data 111 to the latch circuit 200. Additionally, the counter 110 can output the test data 111 to the comparison circuit 120.

[0046] Additionally, the counter 110 can increase the value of the test data 111 in response to the clock signal CLK.

[0047] In an embodiment, the counter 110 can increase the value of the test data 111 in response to the first edge of the clock signal CLK. The counter 110 can output the test data 111 to the latch circuit 200 and the comparison circuit 120 in response to the first edge of the clock signal CLK, and at the same time can increase the value of the test data 111. Here, the counter 110 can output the test data 111 with a value that has not been increased (i.e., the value before the increase) to the latch circuit 200, and the comparison circuit 120 can store the test data 111 with the increased value therein.

[0048] In another embodiment, the counter 110 can increase the value of the test data 111 in response to the second edge of the clock signal CLK. That is, the counter 110 can increase the value of the test data 111 in response to the second edge of the clock signal CLK after outputting the test data 111 to the latch circuit 200 and the comparison circuit 120 in response to the first edge of the clock signal CLK.

[0049] In an embodiment, the counter 110 may increment the value of the test data 111 by 1 in response to the clock signal CLK. For example, if the test data 111 is 8-bit data and the value of the test data 111 stored in the counter 110 is 0x00, the counter 110 may increment the value of the test data 111 to 0x01 in response to the clock signal CLK. As described above, the counter 110 may increment the value of the test data 111 by 1 in response to the clock signal CLK, thereby outputting the test data 111 having all types of values to the latch circuit 200.

[0050] In an embodiment, if the value of the test data 111 is the maximum value, the counter 110 may change the value of the test data 111 to the minimum value in response to the clock signal CLK. For example, if the test data 111 is 8-bit data, the value of the test data 111 may have 0xFF as the maximum value and 0x00 as the minimum value. Here, if the value of the test data 111 is 0xFF, the value of the test data 111 may be the maximum value. Therefore, the counter 110 may change the value of the test data 111 to 0x00 as the minimum value in response to the clock signal CLK.

[0051] The latch circuit 200 according to one or more example embodiments may include a first latch 210_1 to an nth latch 210_n. In addition, the latch circuit 200 may further include an internal bus.

[0052] The latch circuit 200 may receive an input of the test data 111 from the counter 110. Here, the test data 111 may be input into the internal bus within the latch circuit 200. The internal bus may send the test data 111 to a test target latch selected from among the first latch 210_1 to the nth latch 210_n.

[0053] The test target latch may include the latch among the first latch 210_1 to the nth latch 210_n on which a test operation is being performed. The latch circuit 200 may select any one of the first latch 210_1 to the nth latch 210_n as the test target latch in response to a test command received from an external device. The test command may include a command for performing a test operation on the latch circuit 200 and may be sent to the test device 100 and the latch circuit 200. The internal bus may select the test target latch in response to the test command and may send the test data 111 to the selected test target latch.

[0054] In an embodiment, if the test operation on the test target latch is completed, the latch circuit 200 may change the test target latch to a latch among the first latch 210_1 to the nth latch 210_n on which the test operation has not been performed.

[0055] If test data 111 having all types of values is input to the test target latch, the latch circuit 200 may determine that the test operation on the test target latch is completed. For example, if the test data 111 is 8-bit data, when all of the test data 111 having values between 0x00 and 0xFF is input to the test target latch, the latch circuit 200 may determine that the test operation on the test target latch is completed.

[0056] If the test operation on the test target latch is completed, the latch circuit 200 may change the test target latch to a latch among the first latch 210_1 to the nth latch 210_n on which the test operation has not been performed. For example, if the test target latch is the second latch 210_2 and the test operation on the first latch 210_1 has been previously completed, once the test operation on the test target latch is completed, the latch circuit 200 may change the test target latch to any one of the third latch 210_3 to the nth latch 210_n on which the test operation has not been performed.

[0057] In an embodiment, the latch circuit 200 may change the test target latch based on the indexes of the first latch 210_1 to the nth latch 210_n. For example, the latch circuit 200 may initially select the first latch 210_1 with an index of 1 as the test target latch, and if the test operation on the test target latch is completed, may change the test target latch while incrementing the index of the test target latch by 1.

[0058] In another example, the latch circuit 200 may change the test target latch based on the addresses of the first latch 210_1 to the nth latch 210_n. For example, the latch circuit 200 may initially select the latch with an address of 0x0000 as the test target latch, and if the test operation on the test target latch is completed, may change the test target latch while incrementing the address of the test target latch by 1.

[0059] The latch circuit 200 may change the test target latch to a latch among the first latch 210_1 to the nth latch 210_n on which the test operation has not been performed until the test operation is completed for all of the first latch 210_1 to the nth latch 210_n. Accordingly, the test operation may be performed on all of the first latch 210_1 to the nth latch 210_n included in the latch circuit 200.

[0060] In an embodiment, if the value of the test data 111 received from the counter 110 is the maximum value, the latch circuit 200 may change the test target latch after the test data 111 with the maximum value passes through the test target latch. If the value of the test data 111 received from the counter 110 is the maximum value (e.g., 0xFF), the latch circuit 200 may determine that the test data 111 with values from the minimum value to the maximum value has been all input, and thus may change the test target latch. Therefore, the latch circuit 200 may cause the test data 111 with values from the minimum value to the maximum value to sequentially pass through the changed test target latch.

[0061] The comparison circuit 120 may receive a first input and a second input. The first input may include the test data 111 output from the counter 110. The second input may include the test data 111 output from the test target latch.

[0062] The comparison circuit 120 may generate and output a comparison signal based on the first input and the second input. The comparison signal may indicate the result of comparing the first input with the second input.

[0063] In an embodiment, if the first input is the same as the second input, the comparison circuit 120 may output a comparison signal having a first value (e.g., 0). If the first input is the same as the second input, the test data 111 that has passed through the test target latch may be the same as the test data 111 input to the test target latch by the counter 110. That is, if the result of the test data 111 that has passed through the test target latch is normal, the comparison circuit 120 may output a comparison signal having the first value.

[0064] On the other hand, if the first input is different from the second input, the comparison circuit 120 may output a comparison signal having a second value (e.g., 1). If the first input is different from the second input, the test data 111 that has passed through the test target latch may be different from the test data 111 input to the test target latch by the counter 110. That is, if the result of the test data 111 that has passed through the test target latch is abnormal, the comparison circuit 120 may output a comparison signal having the second value.

[0065] In an embodiment, the comparison circuit 120 may include an XOR (exclusive OR) gate configured to output a comparison signal based on the first input and the second input. The XOR gate may receive the first input and the second input, and may output the comparison signal. If the first input is the same as the second input, the XOR gate may output a comparison signal having a value of 0. On the other hand, if the first input is different from the second input, the XOR gate may output a comparison signal having a value of 1.

[0066] Determination circuit 130 may generate a defect determination value based on a comparison signal. The defect determination value may indicate whether latch circuit 200 has a defect.

[0067] In an embodiment, determination circuit 130 may count the number of times the comparison signal has a second value and may generate a defect determination value. The comparison signal having the second value may indicate that the test data 111 that has passed through the test target latch is different from the test data 111 input to the test target latch by counter 110. That is, determination circuit 130 may count the number of times the output of latch circuit 200 has an error to generate a defect determination value.

[0068] Accordingly, a defect determination value of 0 may indicate that latch circuit 200 does not have a defect. A defect determination value greater than 0 may indicate that latch circuit 200 has a defect.

[0069] In an embodiment, if comparison circuit 120 includes an XOR gate, then determination circuit 130 may accumulate the values of the comparison signal and may generate a defect determination value based on the accumulated value. In an embodiment, the defect determination value may have the value of the accumulated value.

[0070] When comparison circuit 120 includes an XOR gate, if the test data 111 that has passed through the test target latch is the same as the test data 111 input to the test target latch by counter 110, then the value of the comparison signal may be 0. Here, determination circuit 130 may accumulate the values of the comparison signal, and if there is no error in the output of latch circuit 200, the defect determination value may be 0.

[0071] On the other hand, when comparison circuit 120 includes an XOR gate, if the test data 111 that has passed through the test target latch is different from the test data 111 input to the test target latch by counter 110, then the value of the comparison signal may be 1. Here, if determination circuit 130 accumulates the values of the comparison signal and there is one or more errors in the output of latch circuit 200, the defect determination value may be 1 or greater.

[0072] Test device 100 may send the defect determination value generated by determination circuit 130 to an external device. That is, test device 100 may send the defect determination value to an external device in response to a test command received from the external device.

[0073] When using test device 100 according to the above exemplary embodiments, test operations may be performed while increasing the value of the test data by counter 110 and changing the test target latch to a latch among multiple latches 210 that has not yet been subjected to a test operation, so that it is possible to accurately determine whether the latch circuit has a defect.

[0074] Figure 3 is a timing diagram showing an example of the operation of a test device according to one or more exemplary embodiments.

[0075] Reference Figure 3 , shows a timing diagram illustrating the changes in test data, a first input, a second input, and a test target latch that are based on a clock signal CLK and input into a test device 100 according to one or more example embodiments.

[0076] In the embodiment described in reference Figure 3 , a counter 110 of the test device 100 may output test data in response to a first edge of the clock signal CLK, and may increment the value of the test data in response to the first edge of the clock signal CLK.

[0077] First, at a first time point t1 in the Figure 3 timing diagram, the counter 110 may output test data having a value of 0x00 to a comparison circuit 120 in response to a first edge of the clock signal CLK. Accordingly, the value of the first input input into the comparison circuit 120 may be 0x00.

[0078] In addition, at the first time point t1, the counter 110 may output test data having a value of 0x00 to a latch circuit 200 in response to a first edge of the clock signal CLK. Here, the test data may pass through a latch having an address of 0x0000 (which is the test target latch), and may be input into the comparison circuit 120 as a second input. Here, if the test target latch has no error, the value of the second input input into the comparison circuit 120 may be 0x00.

[0079] In addition, at the first time point t1, the counter 110 may increment the value of the test data from 0x00 to 0x01 in response to a first edge of the clock signal CLK.

[0080] At a second time point t2, the counter 110 may output test data having a value of 0x01 to the comparison circuit 120 and the latch circuit 200 in response to a first edge of the clock signal CLK. Accordingly, a first input having a value of 0x01 may be input into the comparison circuit 120. In addition, if the test target latch has no error, a second input having a value of 0x01 may be input into the comparison circuit 120. In addition, at the second time point t2, the counter 110 may increment the value of the test data from 0x01 to 0x02 in response to a first edge of the clock signal CLK.

[0081] Similarly, at the third time point t3, the fourth time point t4, and the fifth time point t5, the counter 110 may output test data to the comparison circuit 120 and the latch circuit 200, and may increase the value of the test data in response to the first edge of the clock signal CLK.

[0082] Figure 4 is a timing diagram showing another example of the operation of the test device according to one or more exemplary embodiments.

[0083] Referring Figure 4 , a timing diagram is shown that illustrates the changes in the test data, the first input, the second input, and the test target latch based on the clock signal CLK and input to the test device 100 according to one or more example embodiments.

[0084] In the embodiment described in Figure 4 described above with reference to Figure 3 In the embodiment described, the counter 110 of the test device 100 may output test data in response to the first edge of the clock signal CLK, and may increase the value of the test data in response to the first edge of the clock signal CLK. Here, the embodiment described with reference to Figure 4 shows the case where the value of the test data is the maximum value, so the value of the test data may be changed to the minimum value, and the test target latch may be changed.

[0085] First, at the first time point t1 and the second time point t2 in the Figure 4 timing diagram of Figure 3 as described above, the counter 110 may output test data to the comparison circuit 120 and the latch circuit 200, and may increase the value of the test data in response to the first edge of the clock signal CLK.

[0086] At the third time point t3, the counter 110 may output test data having a value of 0xFF to the comparison circuit 120 and the latch circuit 200 in response to the first edge of the clock signal CLK. Accordingly, a first input having a value of 0xFF may be input to the comparison circuit 120. Additionally, if there is no error in the test target latch, a second input having a value of 0xFF may be input to the comparison circuit 120.

[0087] Further, at the third time point t3, the value of the test data is 0xFF which is the maximum value, so the counter 110 may not increase the value of the test data. Here, since the value of the test data is 0xFF which is the maximum value, the counter 110 may change the value of the test data to the minimum value. That is, at the third time point t3, the counter 110 may change the value of the test data from 0xFF to 0x00 in response to the first edge of the clock signal CLK.

[0088] In addition, since the value of the test data received from the counter 110 at the third time point t3 is 0xFF which is the maximum value, the latch circuit 200 can change the test target latch after the third time point t3 when the test data with the maximum value passes through the test target latch. Here, the latch circuit 200 can change the test target latch before the fourth time point t4 when the next test data is input. In the embodiment described in Figure 4 reference, the latch circuit 200 can change the test target latch to the latch with the address 0x0001 by incrementing the address of the test target latch by 1.

[0089] Figure 5 is a timing diagram showing another example of the operation of the test device according to one or more exemplary embodiments.

[0090] Reference Figure 5 shows a timing diagram illustrating the test data, the first input, the second input, and the change of the test target latch based on the clock signal CLK and input to the test device 100 according to one or more example embodiments.

[0091] In the embodiment described in Figure 5 reference, the counter 110 of the test device 100 can output test data in response to the first edge of the clock signal CLK, and can increment the value of the test data in response to the second edge of the clock signal CLK.

[0092] First, at the first time point t1 in the Figure 5 timing diagram, the counter 110 can output the test data with the value 0x00 to the comparison circuit 120 in response to the first edge of the clock signal CLK. Therefore, the value of the first input input to the comparison circuit 120 can be 0x00.

[0093] In addition, at the first time point t1, the counter 110 can output the test data with the value 0x00 to the latch circuit 200 in response to the first edge of the clock signal CLK. Here, the test data can pass through the latch with the address 0x0000 (which is the test target latch), and can be input to the comparison circuit 120 as the second input. Here, if there is no error in the test target latch, the value of the second input input to the comparison circuit 120 can be 0x00.

[0094] Next, at the Figure 5 second time point t2 in the timing diagram, the counter 110 can increment the value of the test data from 0x00 to 0x01 in response to the second edge of the clock signal CLK.

[0095] At the third time point t3, the counter 110 can output test data with a value of 0x01 to the comparison circuit 120 and the latch circuit 200 in response to the first edge of the clock signal CLK. Thus, a first input with a value of 0x01 can be input into the comparison circuit 120. Additionally, if there is no error in the test target latch, a second input with a value of 0x01 can be input into the comparison circuit 120. Next, at the fourth time point t4, the counter 110 can increase the value of the test data from 0x01 to 0x02 in response to the second edge of the clock signal CLK.

[0096] Similarly, at the fifth time point t5, the seventh time point t7, and the ninth time point t9, the counter 110 can output test data to the comparison circuit 120 and the latch circuit 200 in response to the first edge of the clock signal CLK. Next, at the sixth time point t6, the eighth time point t8, and the tenth time point t 10 where, the counter 110 can increase the value of the test data in response to the second edge of the clock signal CLK.

[0097] Figure 6 is a table showing examples of signals and data for testing a device according to one or more exemplary embodiments.

[0098] Reference Figure 6 , shows a table illustrating examples of test data, a first input, a second input, a comparison signal, and a defect determination value according to the operation of the test device 100 according to one or more exemplary embodiments.

[0099] In the embodiment described in reference Figure 6 , the test target latch can include the latch with the address 0x0000 among the plurality of latches 210, and the first value of the comparison signal can be 0, and the second value of the comparison signal can be 1.

[0100] First, if the test data is 0x00, the first input input into the comparison circuit 120 can be the binary code 0000 0000 that is the same as the test data. Here, the second input input into the comparison circuit 120 after passing through the test target latch can be the binary code 0000 0000 that is the same as the test data. Since the first input is the same as the second input, the comparison circuit 120 can output a comparison signal with a value of 0, and this value 0 indicates that there is no error in the output of the test target latch. Since the comparison signal has a value of 0, the determination circuit 130 can maintain the defect determination value as 0.

[0101] Next, if the test data becomes 0x01 when the value of the test data is incremented by 1, the second input can be the binary code 0000 0001 that is the same as the test data. Accordingly, the comparison signal can become 0 and the defect determination value can be maintained at 0.

[0102] Next, if the test data becomes 0x02 when the value of the test data is incremented by 1, the second input can be the binary code 0000 0010 that is the same as the test data. Accordingly, the comparison signal can become 0 and the defect determination value can be maintained at 0.

[0103] Next, if the test data becomes 0x03 when the value of the test data is incremented by 1, the first input input to the comparison circuit 120 can be the binary code 0000 0011 that is the same as the test data. Here, the second input input to the comparison circuit 120 after passing through the test target latch can be the binary code 0000 0010 that is different from the test data. Since the first input is different from the second input, the comparison circuit 120 can output a comparison signal having a value of 1, and this value of 1 indicates an error in the output of the test target latch. Since the comparison signal has a value of 1, the determination circuit 130 can increment the defect determination value to 1.

[0104] In a similar manner, the test operation can be performed on the test target latch by incrementing the value of the test data by 1 until the value of the test data becomes 0xFF.

[0105] Figure 7 is a table showing another example of signals and data for testing a device according to one or more exemplary embodiments.

[0106] Reference Figure 7 , a table is shown that illustrates an example of test data, a first input, a second input, a comparison signal, and a defect determination value according to the operation of the test device 100 according to one or more exemplary embodiments.

[0107] Reference Figure 7 The described embodiment shows a case where the value of the test data is the maximum value and thus the value of the test data can be changed to the minimum value and the test target latch can be changed.

[0108] In Figure 7 the described embodiment, the test target latch can include the latch having the address 0x0003 and the latch having the address 0x0004 among the plurality of latches 210, and the first value of the comparison signal can be 0, and the second value of the comparison signal can be 1.

[0109] First, if the test data is 0xFE, the second input can be the binary code 1111 1110 that is the same as the test data. Thus, the comparison signal can become 0 and the defect determination value can be maintained at 0.

[0110] Next, if the test data becomes 0xFF by incrementing the value of the test data by 1, the first input input to the comparison circuit 120 can be the binary code 11111111 that is the same as the test data. Here, the second input input to the comparison circuit 120 after passing through the test target latch can be the binary code 11011111 that is different from the test data. Since the first input is different from the second input, the comparison circuit 120 can output a comparison signal having a value of 1, and this value of 1 indicates an error in the output of the test target latch. Since the comparison signal has a value of 1, the determination circuit 130 can increment the defect determination value to 1.

[0111] Next, since the value of the test data is 0xFF which is the maximum value, the value of the test data can be changed to 0x00 which is the minimum value. Additionally, since the test data having 0xFF as the maximum value has passed through the test target latch, the latch circuit 200 can change the test target latch to a latch having an address of 0x0004 by incrementing the address of the test target latch by 1.

[0112] Next, if the test data is 0x00, the second input can be the binary code 0000 0000 that is the same as the test data. Thus, the comparison signal can become 0 and the defect determination value can be maintained at 1.

[0113] Next, if the test data becomes 0x01 by incrementing the value of the test data by 1, the first input input to the comparison circuit 120 can be the binary code 00000001 that is the same as the test data. Here, the second input input to the comparison circuit 120 after passing through the test target latch can be the binary code 00000011 that is different from the test data. Since the first input is different from the second input, the comparison circuit 120 can output a comparison signal having a value of 1, and this value of 1 indicates an error in the output of the test target latch. Since the comparison signal has a value of 1, the determination circuit 130 can increment the defect determination value to 2.

[0114] Next, if the test data becomes 0x02 by incrementing the value of the test data by 1, the second input can be the binary code 0000 0010 that is the same as the test data. Thus, the comparison signal can become 0 and the defect determination value can be maintained at 2.

[0115] Figure 8 is a flowchart showing an operation method of a test device according to one or more exemplary embodiments.

[0116] Reference Figure 8 In operation S810, the test device 100 may output test data through the counter 110 in response to a clock signal. The counter 110 may output the test data to the comparison circuit 120 and the latch circuit 200 in response to the first edge of the clock signal.

[0117] In operation S820, the test device 100 may increase the value of the test data through the counter 110 in response to a clock signal. The counter 110 may increase the value of the test data in response to the first edge or the second edge of the clock signal. Here, if the counter 110 increases the value of the test data in response to the first edge of the clock signal, operations S810 and S820 may be performed simultaneously.

[0118] In operation S830, the test device 100 may receive the test data output from the counter 110 as a first input through the comparison circuit 120.

[0119] In operation S840, the test device 100 may receive the test data output from the test target latch as a second input through the comparison circuit 120.

[0120] In operation S850, the test device 100 may output a comparison signal by comparing the first input with the second input through the comparison circuit 120. Reference Figure 9 A method of outputting a comparison signal from the comparison circuit 120 is described in detail.

[0121] Figure 9 is a flowchart showing a method of outputting a comparison signal in a test device according to one or more exemplary embodiments.

[0122] Reference Figure 9 In operation S910, the test device 100 may determine whether the first input is the same as the second input through the comparison circuit 120. Thus, the test device 100 may determine whether there is an error in the output of the test target latch.

[0123] If the first input is determined to be the same as the second input, it indicates that there is no error in the output of the test target latch. Thus, the process may proceed to operation S920, and the test device 100 may output a comparison signal having a first value through the comparison circuit 120.

[0124] If the first input is determined to be different from the second input, it indicates that there is an error in the output of the test target latch. Thus, the process may proceed to operation S930, and the test device 100 may output a comparison signal having a second value through the comparison circuit 120.

[0125] Return reference Figure 8, in operation S860, the test device 100 may generate a defect determination value based on the comparison signal through the determination circuit 130. For example, the determination circuit 130 may count the number of times the comparison signal has a second value and may generate a defect determination value based on the counted number of times.

[0126] Figure 10 is a block diagram showing a memory device including a test device according to one or more exemplary embodiments.

[0127] Reference Figure 10 , according to one or more example embodiments, the memory device 300 may include a memory cell region 310 and a peripheral circuit region 320.

[0128] The memory cell region 310 may include a memory cell array 311.

[0129] The peripheral circuit region 320 may be connected to the memory cell region 310. The peripheral circuit region 320 may include a row decoder, control logic, page buffers, input / output circuits, a voltage generator, and the like.

[0130] In an embodiment, the peripheral circuit region 320 may include a latch circuit 321 and a test device 322.

[0131] The latch circuit 321 may include a plurality of latches. The latch circuit 321 may be included in general components (such as page buffers) of the peripheral circuit region 320.

[0132] The test device 322 may be the same as the test device 100 described above with reference to Figures 1 to 9 described.

[0133] The test device 322 may perform a test operation on the latch circuit 321 in response to a test command received from a defect detection device 400 external to the memory device 300. The test device 322 may send a defect determination value generated by performing the test operation on the latch circuit 321 to the defect detection device 400.

[0134] The defect detection device 400 may include a device for detecting an initial defect occurring in the memory device 300. After manufacturing, the memory device 300 may be inspected to detect the initial defect through the defect detection device 400. In an embodiment, the defect detection device 400 may send a test command to the memory device 300, and the memory device 300 may perform a test operation on the latch circuit 321 through the internal test device 322 in response to the test command. The memory device 300 may send a defect determination value generated by performing the test operation on the latch circuit 321 via the test device 322 to the defect detection device 400. Thus, it may be determined whether there is an initial defect in the latch circuit 321 of the memory device 300.

[0135] Here, since the memory device 300 performs a test operation on the latch circuit 321 by generating test data using the internal test device 322, the memory device 300 can perform the test operation faster than when performing the test operation by directly inputting the test data from the defect detection device 400 into the latch circuit 321.

[0136] Figure 11 is a block diagram showing a storage device including a test device according to one or more exemplary embodiments.

[0137] Reference Figure 11 , the storage system 50 may include a host device 500 and a storage device 600.

[0138] The storage system 50 may be implemented as, for example, a personal computer (PC), a data server, a network-attached storage (NAS), an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device may include a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MPEG-1 audio layer 3 (MP3) player, a handheld game console, an e-book, a wearable device, etc.

[0139] The host device 500 may communicate with the storage device 600 through various interfaces and may send requests such as read requests, programming requests, and / or erase requests to the storage device 600. In an embodiment, the host device 500 may be implemented as an application processor (AP) or a system-on-chip (SoC).

[0140] In an embodiment, the host device 500 may send a test request to the storage device 600. The test request may include a request to perform a test operation on the latch circuit 200. In an embodiment, the host device 500 may send the test request to the storage device 600 according to a power-off command received from a user. In another embodiment, if the storage device 600 is in an idle state, the host device 500 may send the test request to the storage device 600.

[0141] The storage device 600 may include a storage medium for storing data according to a request from the host device 500. For example, the storage device 600 may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. If the storage device 600 is an SSD, the storage device 600 may include a device compiled using the Non-Volatile Memory Express (NVMe) standard.

[0142] If the storage device 600 is an embedded memory or an external memory, the storage device 600 may include a device compiled according to the Universal Flash Storage (UFS) or Embedded MultiMediaCard (eMMC) standard. The host device 500 and the storage device 600 may each generate and transmit packets according to the adopted standard protocol. In an embodiment, the storage device 600 may include an embedded memory built into the storage system 50, such as an eMMC or an embedded UFS memory device. In an embodiment, the storage device 600 may include a removable external memory of the storage system 50, such as a UFS memory card, a CompactFlash (CF) memory card, a Secure Digital (SD) memory card, a microSD memory card, a miniSD memory card, an Extreme Digital (xD) memory card, or a Memory Stick.

[0143] According to one or more example embodiments, the storage device 600 may include a storage controller 610 and a non-volatile memory 620.

[0144] The storage controller 610 may control the operation of the non-volatile memory 620 through a channel. The storage controller 610 may control the non-volatile memory 620 to read data stored in the non-volatile memory 620 in response to a read request received from the host device 500. The storage controller 610 may control the non-volatile memory 620 to program data into the non-volatile memory 620 in response to a program request received from the host device 500. The storage controller 610 may control the non-volatile memory 620 to erase data stored in the non-volatile memory 620 in response to an erase request received from the host device 500.

[0145] In an embodiment, the non-volatile memory 620 may include a latch circuit 621 and a test device 622.

[0146] The latch circuit 621 may include a plurality of latches. The test device 622 may be the same as the test device 100 described above with reference to Figures 1 to 9 description.

[0147] In an embodiment, the storage controller 610 may receive a test request from the host device 500. In an embodiment, the test request may be sent from the host device 500 to the storage controller 610 according to a power-off command received from a user. In another embodiment, if the storage device 600 is in an idle state, the test request may be sent from the host device 500 to the storage controller 610.

[0148] The storage controller 610 may send a test command to the test device 622 of the non-volatile memory 620 in response to the test request received from the host device 500.

[0149] The test device 622 may perform a test operation on the latch circuit 621 in response to a test command received from the storage controller 610. The test device 622 may send a defect determination value generated by performing the test operation on the latch circuit 621 to the storage controller 610.

[0150] The storage controller 610 may send the defect determination value received from the test device 622 to the host device 500.

[0151] As described above, for example, when the storage device 600 receives a power-off command from a user or is in an idle state, the storage device 600 according to the inventive concept may periodically determine whether a defect has occurred in the latch circuit 621 by performing a test operation on the latch circuit 621.

[0152] Figure 12 FIG. is a block diagram illustrating an example in which a memory device is applied to an SSD system according to one or more example embodiments.

[0153] Reference Figure 12 , the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may exchange signals SIG with the host 1100 via a signal connector and may receive power PWR via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. The memory devices 1230, 1240, and 1250 may include vertically stacked NAND flash devices. Here, the memory devices 1230, 1240, and 1250 included in the SSD 1200 may be implemented with the embodiments described above with reference to Figure 10 described embodiments and may include the test device 100 described above with reference to Figures 1 to 9 described.

[0154] Although the inventive concept has been specifically shown and described with reference to example embodiments of the inventive concept, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims and their equivalents.

Claims

1. A test device for performing a test operation on a latch circuit, the latch circuit comprising a plurality of latches, the test device comprising: a counter configured to output test data to a test target latch selected from the plurality of latches in response to a clock signal and to increase a value of the test data in response to the clock signal; a comparison circuit configured to receive the test data output from the counter as a first input, receive the test data output from the test target latch as a second input, and output a comparison signal by comparing the first input with the second input; as well as A determination circuit is configured to generate a defect determination value indicating whether the latch circuit has a defect based on the comparison signal.

2. The test device according to claim 1, wherein: The counter is configured as: outputting the test data in response to a first edge of the clock signal; and The value of the test data is increased in response to the first edge of the clock signal.

3. The test device according to claim 1, wherein: The counter is configured as: outputting the test data in response to a first edge of the clock signal; and The value of the test data is increased in response to a second edge of the clock signal.

4. The test device according to claim 1, wherein: The counter is configured to increase a value of the test data by 1 in response to the clock signal.

5. The testing device according to claim 1, wherein: Based on the value of the test data being a maximum value, the counter is configured to change the value of the test data to a minimum value in response to the clock signal.

6. The test device according to claim 1, wherein: Based on the completion of the test operation on the test target latch, the test target latch is changed to a latch among the plurality of latches on which the test operation has not been performed.

7. The testing device according to claim 1, wherein: The comparison circuit is configured as follows: outputting the comparison signal having a first value based on that the first input is the same as the second input; as well as Based on the first input being different from the second input, the comparison signal having a second value is output.

8. The test device according to claim 7, wherein: The determination circuit is configured to count the number of times the comparison signal has the second value, and generate the defect determination value based on the counted number of times.

9. The testing device according to claim 1, wherein: The comparison circuit includes an XOR gate configured to output the comparison signal based on the first input and the second input.

10. The test device according to claim 9, wherein: The determination circuit is configured to accumulate values ​​of the comparison signal and generate the defect determination value based on the accumulated value.

11. The test device according to claim 1, wherein: The test equipment is configured as follows: performing the test operation on the latch circuit in response to a test command received from an external device; and The defect determination value is transmitted to the external device.

12. A memory device comprising: a memory cell region including a memory cell array; as well as A peripheral circuit region connected to the memory cell region, Wherein, the peripheral circuit area includes: a latch circuit comprising a plurality of latches; and a test device configured to perform a test operation on the latch circuit, and Wherein, the testing equipment comprises: a counter configured to output test data to a test target latch selected from the plurality of latches in response to a clock signal and to increase a value of the test data in response to the clock signal; a comparison circuit configured to receive the test data output from the counter as a first input, receive the test data output from the test target latch as a second input, and output a comparison signal by comparing the first input with the second input; and A determination circuit is configured to generate a defect determination value indicating whether the latch circuit has a defect based on the comparison signal.

13. The memory device of claim 12, wherein: The test equipment is configured as follows: performing the test operation on the latch circuit in response to a test command received from an external defect detection device; and The defect determination value is transmitted to the external defect detection device.

14. The memory device of claim 13, wherein: The latch circuit is configured to select any one of the plurality of latches as the test target latch in response to the test command.

15. The memory device of claim 14, wherein: Based on completion of the test operation on the test target latch, the latch circuit is configured to change the test target latch to a latch among the plurality of latches on which the test operation has not been performed.

16. The memory device of claim 15, wherein: Based on the value of the test data received from the counter being a maximum value, the latch circuit is configured to change the test target latch after the test data having the maximum value passes through and is output from the test target latch.

17. A storage device comprising: Non-volatile memory; as well as a memory controller configured to control the operation of the nonvolatile memory, Wherein, the non-volatile memory comprises: a latch circuit comprising a plurality of latches; and a test device configured to perform a test operation on the latch circuit, and Wherein, the testing equipment comprises: a counter configured to output test data to a test target latch selected from the plurality of latches in response to a clock signal and to increase a value of the test data in response to the clock signal; a comparison circuit configured to receive the test data output from the counter as a first input, receive the test data output from the test target latch as a second input, and output a comparison signal by comparing the first input with the second input; and A determination circuit is configured to generate a defect determination value indicating whether the latch circuit has a defect based on the comparison signal.

18. The storage device according to claim 17, wherein: The storage controller is configured to send a test command to the test device in response to a test request received from an external host device, wherein the test device is configured to perform the test operation on the latch circuit in response to the test command and send the defect determination value to the memory controller, and Wherein, the storage controller is configured to send the defect determination value to the external host device.

19. The storage device according to claim 18, wherein: The test request is sent from the external host device to the storage controller according to reception of a power-off command.

20. The storage device according to claim 18, wherein: The test request is sent from the external host device to the storage controller based on the storage device being in an idle state.

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