Test circuit and memory

Abstract

The embodiment of the invention provides a test circuit and a memory. The test circuit is applied to a peripheral circuit of a memory, and the memory comprises at least one group of first data output units and at least one group of second data output units. The test circuit comprises a data generation unit which is used for generating first random data to be tested and is connected with at least one group of first data output units; the data control unit is connected with the data generation unit and at least one group of second data output units; the first data control end is connected with the data generation unit and the data control unit for receiving a first control signal; the second data control end is connected with the data control unit and used for receiving a second control signal; the data generation unit is used for determining whether to invert data according to the first control signal; the data control unit is used for determining whether to invert the data according to the first control signal and the second control signal. According to the scheme, the circuit can be simplified, and resources are saved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and are related to but not limited to a test circuit and a memory. Background Art

[0002] With the high degree of integration of integrated circuits, the test method is now a constraint on the integrated circuit industry. Because early integrated circuits had few internal modules, single logical functions, and relatively simple processes, it was relatively easy to implement functional testing on a tester. However, today, the rapid growth of testing costs has reached a point that manufacturers cannot afford. With the continuous research on testing methodology, for complex and large-scale integrated circuit design projects, it is necessary to consider how to test the product in advance during the design stage of the integrated circuit product, which can greatly shorten the product testing time, thereby reducing costs and improving product competitiveness. Therefore, the design and optimization of the test circuit in the product is one of the problems that need to be solved urgently in this field. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides a test circuit and a memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a test circuit applied to a peripheral circuit of a memory; the memory includes at least one group of first data output units and at least one group of second data output units; the test circuit includes:

[0005] A data generating unit, used for generating first random data to be tested, and connected to at least one group of the first data output units;

[0006] a data control unit, connected to the data generating unit and at least one group of the second data output units;

[0007] A first data control terminal, connected to the data generating unit and the data control unit, and configured to receive a first control signal;

[0008] A second data control terminal, connected to the data control unit, and configured to receive a second control signal;

[0009] Among them, the data generation unit is used to determine whether to invert the original random data generated by the data generation unit according to the first control signal, and output it to the first data output unit as the first random data to be tested; the data control unit is used to determine whether to invert the first random data to be tested according to the first control signal and the second control signal, and output it to the second data output unit as the second random data to be tested.

[0010] In a second aspect, an embodiment of the present disclosure provides a memory, including:

[0011] Memory cell array;

[0012] At least one group of first data output units and at least one group of second data output units;

[0013] Peripheral circuit; wherein, the peripheral circuit includes any one of the above-mentioned test circuits.

[0014] In an embodiment of the present disclosure, the test circuit uses a data generation unit to generate first random data to be tested and provides it to the first data output unit; and the data control unit determines whether to invert the first random data to be tested according to the first control signal and the second control signal provided by the first data control terminal and the second data control terminal, and provides it as the second random data to be tested to the second data output unit. In this way, the test circuit only needs one data generation unit to provide random data to be tested for the first data output unit and the second data output unit respectively, which can simplify the circuit, reduce the occupation of the peripheral circuit track resources, and reduce the circuit power consumption. Description of the Drawings

[0015] Figure 1 Schematic structural diagram of an LFSR test circuit in an embodiment of the present disclosure;

[0016] Figure 2 Schematic structural diagram of a test circuit provided by an embodiment of the present disclosure;

[0017] Figure 3 Schematic structural diagram of the data control unit in the test circuit provided by an embodiment of the present disclosure;

[0018] Figure 4 Schematic structural diagram of the data selection unit in the test circuit provided by an embodiment of the present disclosure

[0019] Figure 5 Schematic structural diagram of another test circuit provided by an embodiment of the present disclosure;

[0020] Figure 6 Schematic structural diagram of the test adjustment unit in the test circuit provided by an embodiment of the present disclosure;

[0021] Figure 7 Signal waveform diagram of the test adjustment unit in the test circuit provided by an embodiment of the present disclosure;

[0022] Figure 8 Schematic structural diagram of yet another test circuit provided by an embodiment of the present disclosure;

[0023] Figure 9 Schematic structural diagram of the second position adjustment circuit in the test circuit provided by an embodiment of the present disclosure;

[0024] Figure 10The basic block diagram of the data generation unit in the test circuit provided by the embodiments of the present disclosure;

[0025] Figure 11 The structural schematic diagram of the carry-lookahead processing circuit in the test circuit provided by the embodiments of the present disclosure;

[0026] Figure 12 The structural schematic diagram of the logic control circuit in the test circuit provided by the embodiments of the present disclosure;

[0027] Figure 13 The structural schematic diagram of the sampling circuit in the test circuit provided by the embodiments of the present disclosure;

[0028] Figure 14 The signal waveform diagram of the test circuit provided by the embodiments of the present disclosure;

[0029] Figure 15 The structural schematic diagram of LDQ or UDQ in the test circuit provided by the embodiments of the present disclosure;

[0030] Figure 16 The structural schematic diagram of a memory provided by the embodiments of the present disclosure;

[0031] Figure 17 The waveform diagrams of various signals implemented by the test circuit provided by the embodiments of the present disclosure. Detailed implementation manners

[0032] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the specification of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0034] Figure 1A test circuit structure is shown. This circuit mainly consists of two Linear Feedback Shift Register (LFSR) engines and is applied to the data transmission test in X16 mode. The X16 mode refers to the mode in which data is output from all 16 input / output terminals, and these 16 input / output terminals can transmit data in parallel. Correspondingly, the input / output terminals include the lower 8-bit LDQ (Lower Data Queue, such as DQ[7:0] in DQ[15:0]) and the upper 8-bit UDQ (Upper Data Queue, such as DQ[15:8] in DQ[15:0]). In addition, the memory can also use X8 mode, X4 mode, etc. The embodiments of the present disclosure mainly relate to the test circuit in X16 mode, which can be compatible with X8 mode or X4 mode.

[0035] For the test circuit as Figure 1 shown, the first LFSR engine (LFSR1) is mainly used to generate several bits of data (for example, 128 bits) of LDQ in X16 mode. After being driven by the data bus module (BUS MDL), it is output to LDQ, and the inversion of the data generated by the LFSR engine can be controlled by the mode register MR28. Exemplarily, if MR28 is 1, the data generated by the first LFSR engine is inverted and then output; if MR28 is 0, the data is not inverted. The second LFSR engine (LFSR2) is mainly used to generate 128 bits of data of UDQ in X16 mode. After being driven by the data bus module (BUS MDL), it is output to UDQ, and the inversion of the data generated by this LFSR engine can be controlled by the mode register MR29. Exemplarily, if MR29 is 1, the data generated by the second LFSR engine is inverted and then output; if MR29 is 0, the data is not inverted. The above LFSR is an exemplary data generation unit, and various circuit structures that can generate random numbers can also be used as data generation units in the test circuit.

[0036] As Figure 1As shown in the figure, the figure includes a command decoding module (TV_CA) for decoding the input command address signal to obtain an MRR (Mode Register Read) command. The first delay module, also known as MRR_FRP (First Read Pulse), is mainly used to adjust the delay of the decoded MRR command through the TM_MRRPDL<1:0> signal in the test mode to generate an FRP_PDL (Pulse Delay) command, that is, the delayed MRR command, so as to achieve the effect of enabling the sampling signal to be sampled normally. For the second delay module (MRR_LPDL_DLY module), it mainly adjusts the delay of the FRP_PDL command through the MRR_X16_LBUSSEL signal to obtain the L_PDL / U_PDL command, so as to increase or decrease the setup / hold time of the PDL; finally, for the LPDL / UPDL COUNTER (counting module), it mainly counts the above L_PDL / U_PDL commands through an internal counter to generate control signals LPDL<15:0> and UPDL<15:0> for controlling the input of the FIFO (First Input First Output).

[0037] For the above Figure 1 test circuit, it uses two LFSR engines to generate 128-bit data for LDQ and 128-bit data for UDQ respectively, which occupies a relatively large chip area and has a relatively large circuit load, thus resulting in a large waste of power consumption. At the same time, using two LFSR engines to generate data will also increase the occupation of the lanes, which is a great waste of the already tense Layout lane resources. In addition, the above circuit simultaneously controls the delay of the FRP_PDL signal through the MRR_X16_LBUSSEL signal to generate the L_PDL command for LDQ and the U_PDL command for UDQ respectively, and it is difficult to achieve a balance between the two. In addition, since the two LFSR engines are located on both sides of the PERI (peripheral circuit) layer, it is difficult to balance the speed of data reaching LDQ and UDQ.

[0038] As Figure 2 shown, the embodiment of the present disclosure provides a test circuit 100, which is applied to the peripheral circuit of a memory; the memory includes at least one group of first data output units and at least one group of second data output units; the test circuit 100 includes:

[0039] A data generation unit 110, configured to generate first random data to be tested DATA1 and connected to at least one group of the first data output units;

[0040] A data control unit 120, connected to the data generation unit 110 and at least one group of the second data output units;

[0041] A first data control terminal 21, connected to the data generation unit 110 and the data control unit 120, for receiving a first control signal;

[0042] A second data control terminal 22, connected to the data control unit 120, for receiving a second control signal;

[0043] Wherein, the data generation unit 110 is configured to determine, according to the first control signal, whether to invert the original random data DATA0 generated by the data generation unit 110 and use it as the first random data to be measured DATA1, and output it to the first data output unit; the data control unit 120 is configured to determine, according to the first control signal and the second control signal, whether to invert the first random data to be measured DATA1 and use it as the second random data to be measured DATA2, and output it to the second data output unit.

[0044] Here, each group of first data output units may include at least one first data output unit. A group of first data output units may be used to synchronously and parallelly output a group of data, and each first output unit can output at least one bit of data each time. Similarly, each group of second data output units may include at least one second data output unit. A group of second data output units may also be used to synchronously and parallelly output a group of data, and each second output unit can output at least one bit of data each time. The above-mentioned memory may include one or more groups of first data output units and one or more groups of second data output units.

[0045] In addition, a group of first data output units and a group of second data output units can be used synchronously, that is, they can parallelly and respectively output different data; and the first data output units and the second data output units can also be used separately. For example, the first data output units are used to output data, and the second data output units stop outputting.

[0046] Exemplarily, as Figure 2 shown, the first data output unit may be LDQ, and the second data output unit may be UDQ. Each group of LDQ may include 4 or 8 LDQs, and each group of UDQ may also include 4 or 8 UDQs, for parallelly outputting the data of a memory bank or a group of memory banks.

[0047] The above-mentioned test circuit can test the data transmission path before the output unit, that is, by generating parallel random data, transmitting it to the data output unit LDQ or UDQ, and using the data output unit LDQ or UDQ for serial output, so as to realize the performance test of the data transmission path.

[0048] In the embodiments of the present disclosure, the data generation unit 110 may be the above-mentioned LFSR engine or other circuit structures, such as a true random number generation circuit, for generating random data. The data generation unit 110 may be directly connected to the above-mentioned first data output unit LDQ to output the first random data to be tested DATA1 output by the data generation unit 110 to the first data output unit LDQ.

[0049] The data generation unit 110 may use the directly generated original random data DATA0 as the above-mentioned first random data to be tested DATA1, or the data obtained by inverting the original random data DATA0 may be used as the above-mentioned first random data to be tested DATA1. That is to say, the above-mentioned first generation unit 110 may select whether to invert the original random data DATA0 according to the above-mentioned first control signal, and output the data after determining whether to invert it as the first random data to be tested DATA1 to the input end of the above-mentioned first data output unit LDQ, and then the LDQ outputs the data.

[0050] Here, the test circuit only includes a data generation unit 110, and the data generated by it also needs to be transmitted to the second data output unit UDQ. Since the data output to the first data output unit LDQ and the data output to the second data output unit UDQ may be the same or different, therefore, a data control unit 120 is also connected between the data generation unit 110 and the second data output unit UDQ in the embodiments of the present disclosure.

[0051] The data control unit 120 receives the above-mentioned first random data to be tested DATA1, determines whether to invert the first random data to be tested DATA1, and then outputs the data that has been determined to be inverted or not inverted as the second random data to be tested DATA2 to at least one group of UDQ. In one embodiment, the above-mentioned data control unit 120 may be connected to each group of UDQ (exemplarily, one group of UDQ may be all UDQ); in another embodiment, the test circuit may include multiple data control units 120, which are respectively connected to different UDQ.

[0052] The data control unit 120 determines whether to invert the first random data to be tested DATA1 based on the combination of the above-mentioned first control signal and the second control signal. Therefore, the data control unit 120 needs to be respectively connected to the above-mentioned first data control end 21 and the second data control end 22, and connected to the data generation unit 110, and then through a set of logical operation processing, output the data that has been inverted or not inverted for the first random data to be tested DATA1 as the above-mentioned second random data to be tested DATA2.

[0053] It should be noted that the above first control signal and second control signal can be provided by a mode register. For example, the read value of the receive mode register MR28 is used as the first control signal, and the read value of the mode register MR29 is used as the second control signal. For the convenience of description, in the following text and the drawings, MR28 involved represents the above first control signal, and MR29 represents the above second control signal.

[0054] In some embodiments, the data generation unit 110 includes: an inverter logic circuit;

[0055] The inverter logic circuit receives the original random data DATA0 and the first control signal MR28, and outputs the first random data to be measured DATA1.

[0056] Receives the original data DATA0 generated by the data generation unit 110 and the read value of the above mode register MR28, and outputs the first data DATA1.

[0057] In one embodiment, the inverter logic circuit may include a data selector and an inverter. The input end of the inverter receives the original data DATA0 provided to the first input end of the data selector; the original data is also provided to the second input end of the data selector; the read value of MR28 is used as the data selection signal. Exemplarily, when MR28 is "1", the inverter logic circuit outputs the inverted data of the original data DATA0 as the first data DATA1; when MR28 is "0", the inverter logic circuit outputs the non-inverted original data DATA0 as the first data DATA1.

[0058] In another embodiment, the inverter logic circuit may include three NAND gates; wherein, the input of the first NAND gate is the above original data DATA0 and the inverted data of the read value of MR28; the input of the second NAND gate is the inverted data of the original data DATA0 and the read value of MR28; the input of the third NAND gate is the outputs of the first two NAND gates; the third NAND gate outputs the above first data DATA1.

[0059] The above first data control terminal 21 and second data control terminal 22 can be used to control the inversion of the data generated by the data generation unit 110 separately or jointly. The data generated by the data generation unit 110 can be transmitted to the first data output unit LDQ, and can also be transmitted to the second data output unit UDQ through the data control unit 120. Thus, compared with a test circuit using two sets of data generation units (for example, two LFSR engines), the above test circuit provided by the embodiments of the present disclosure is effectively simplified, and can correspondingly save wire track resources, reduce power consumption, and save chip area.

[0060] In some embodiments, such asFigure 3 As shown, the data control unit 120 includes:

[0061] A control signal processing unit 121, connected to the first data control terminal 21 and the second data control terminal 22, for receiving the first control signal and the second control signal and outputting a third control signal;

[0062] A data selection unit 122, for receiving the first random data to be measured and connected to the output terminal of the control signal processing unit; the data selection unit is used to output the second random data to be measured according to the third control signal.

[0063] The above control signal processing unit 121 may be a set of logic gate circuits, for performing a logic operation on the received first control signal and second control signal to obtain a third control signal, and this third control signal is used to determine whether the data output to the second data output unit UDQ is inverted.

[0064] The data selection unit 122 may include two data paths, one for outputting the non-inverted first random data to be measured, and the other for outputting the inverted first random data to be measured. The value of the third control signal is used to select the path as the output of the second random data to be measured.

[0065] Specifically, in some embodiments, as Figure 3 shown, the control signal processing unit 121 includes:

[0066] An exclusive OR gate XOR, whose first input terminal is connected to the first data control terminal for receiving the above first control signal MR28, and the second input terminal is connected to the second data control terminal for receiving the above second control signal MR29.

[0067] A first NAND gate NAND1, whose first input terminal is connected to the output terminal of the exclusive OR gate XOR, and the second input terminal is connected to the first enable signal terminal X16_EN; the output terminal of the first NAND gate NAND1 is used to output the third control signal.

[0068] For a memory, generally only the first data output unit LDQ can be used for data output. Therefore, the test circuit in the embodiments of the present disclosure can be used to test only the path corresponding to LDQ; the second data unit UDQ can also be used for data output at the same time. Exemplarily, for the memory operation or test mode of X8, only LDQ is required for data output. For the memory operation or test mode of X16, either only LDQ can be used to output X8 data, or LDQ and UDQ can be used to output X16 data.

[0069] If only LDQ needs to be tested, there is no need to enable the data path from the data generation circuit 110 to the second data output unit UDQ, so there is no need to use the above-mentioned data control unit 120. At this time, the first enable signal terminal X16_EN of the above-mentioned first NAND gate NAND1 can be at a low level.

[0070] For the case of X16, it is necessary to enable the data path from the data generation circuit 110 to the second data output unit UDQ, so it is necessary to use the above-mentioned data control unit 120. At this time, the first enable signal terminal X16_EN of the above-mentioned first NAND gate NAND1 can be at a high level.

[0071] In an embodiment, the above-mentioned control signal processing unit 121 may further include: a first control signal inverter INV1 connected in series, or may further include a second control signal inverter INV2. The output terminal of the first control signal inverter is used to output the result UDQINV_T of the exclusive OR of the first control signal MR28 and the second control signal MR29 as the third control signal; the output terminal of the first NAND gate NAND1 or the output terminal of the second control signal inverter is used to output the inverted signal UDQINV_B of the result of the exclusive OR of the first control signal MR28 and the second control signal MR29 as the inverted signal of the third control signal.

[0072] In some embodiments, as Figure 4 shown, the data selection unit 122 includes:

[0073] A second NAND gate NAND2, whose first input terminal is used to receive the third control signal S3; the second input terminal is used to receive the first random data to be tested DATA1;

[0074] A third NAND gate NAND3, whose first input terminal is used to receive the inverted signal of the third control signal S3, and the second input terminal is used to receive the inverted signal of the first random data to be tested DATA1;

[0075] A fourth NAND gate NAND4, whose first input terminal is connected to the output terminal of the second NAND gate NAND2, whose second input terminal is connected to the output terminal of the third NAND gate NAND3, and whose output terminal is connected to the second data output unit UDQ, for outputting the second random data to be tested DATA2.

[0076] Through the above circuit, the operation result of the first control signal MR28 and the second control signal MR29 can be used to determine whether the second random data to be tested output to the second data output unit UDQ is the data after the inversion of the first random data to be tested. Specifically, it can be determined as shown in Table 1 below:

[0077]

[0078]

[0079] Table 1

[0080] The value of the first control signal MR28 can control whether the first random data to be measured is the data after inverting the original random data; the value of the second control signal MR29 combined with the value of the first control signal MR28 can control whether the second random data to be measured is the data after inverting the first random data to be measured. In this way, even with only one data generation unit, it is also convenient to control the data output to the first data output unit LDQ and the second data output unit UDQ.

[0081] In some embodiments, as Figure 5 shown, the test circuit 100 further includes:

[0082] A command decoding unit 130, configured to receive a first instruction related to testing and decode the first instruction to obtain a first instruction pulse MRR;

[0083] A test adjustment unit 140, connected to the command decoding unit 130, configured to adjust the pulse width and / or pulse position of the first instruction pulse MRR to obtain a second instruction pulse FRP_PDL; the second instruction pulse MRP_PDL is used to control the output of the first random data to be measured to the first data output unit LDQ, or to control the output of the second random data to be measured to the second data output unit UDQ.

[0084] The above test adjustment unit can adjust the pulse width of the first instruction pulse MRR. For example, it can make the pulse width of the first instruction pulse MRR wider, so as to facilitate sampling. Exemplarily, the command decoding unit 130 decodes to obtain a first instruction pulse MRR with a width of 2tck, and the test adjustment unit 140 adjusts it to a width of 4tck.

[0085] And the test adjustment unit 140 can also adjust the pulse position of the first instruction pulse MRR with a widened width, the second instruction pulse FRP_PDL, according to the test mode signal TM_MRRPDL<1:0>.

[0086] In addition, as Figure 5 shown, the test circuit further includes a data bus unit BUS MDL, which is connected to the data generation unit 110 and is used to transmit data to LDQ and the data control unit 120, etc.

[0087] In some embodiments, as Figure 6 shown, the test adjustment unit 140 includes:

[0088] The first delay circuit 141 includes an input terminal for receiving the first instruction pulse MRR, and a first clock input terminal for receiving the first clock signal PCLK and the first clock inverted signal PCLKB; the first delay circuit 141 is configured to output a plurality of delayed signals EiD (i = 0, 1, 2...) obtained by delaying the first instruction pulse MRR by half a clock cycle in sequence; wherein, the clock cycle is the cycle of the first clock signal PCLK. Exemplarily, the first delay circuit 141 may be composed of 4 latches (H Latch) connected in sequence as shown in Figure 6 shown. Figure 7 Fig. is the waveform diagram of each signal. As shown in Figure 7 shown, the period length of the first clock signal PCLK is 2tCK, which is the same as the pulse width of the original first instruction pulse MRR. The length of half a clock cycle is 1tCK, and tCK is the period length of the period of the externally input basic clock CK.

[0089] The pulse width adjustment circuit 142 includes: an OR gate OR, whose input terminals are connected to the multiple output terminals of the first delay circuit 141 for receiving the multiple delayed signals EiD, and outputting the first instruction pulse MRRD with adjusted width.

[0090] The first position adjustment circuit 143, whose input terminal is connected to the output terminal of the OR gate OR, is configured to adjust the pulse position of the first instruction pulse MRRD with adjusted width to output the second instruction pulse FRP_PDL.

[0091] It can be understood that the input signal of the pulse width adjustment circuit 142 composed of the OR gate OR is a plurality of first instruction pulses delayed in sequence, and its output signal is the width from the rising edge of the first pulse to the falling edge of the last pulse. As shown in Figure 7 shown, the first pulse E0D, the second pulse E1D, and the third pulse E2D are delayed by a width of 1tCK in sequence, so that the output signal MRRD has a width of 4tCK, thereby realizing the adjustment of the width of the first instruction pulse MRR, and the finally output second instruction pulse also has a width of 4tCK, as shown in Figure 7 shown.

[0092] The first position adjustment circuit 143 can advance or delay the position of the pulse on the basis of the pulse with adjusted width, thereby realizing position adjustment and outputting the second instruction pulse FRP_PDL.

[0093] The second instruction pulse FRP_PDL obtained by adjusting the pulse width and position of the first instruction pulse MRR can be more convenient to sample the random data to be measured by using this pulse and output it to the data output unit LDQ or UDQ.

[0094] In some embodiments, as Figure 6 shown, the first position adjustment circuit 143 includes:

[0095] A first adjustment NAND gate NAND01, whose input terminal is connected to the output terminal of the OR gate OR and the first test mode signal TM_MRRPDL<1>, and whose output terminal is connected to a first delay element DLY1; the first delay element DLY1 is used to delay the output signal of the first adjustment NAND gate NAND01 by a first delay duration. Exemplarily, the first delay element can be a delay-adjustable delay element composed of an even number of inverters, and the first delay duration can be 0.1 ns;

[0096] A second adjustment NAND gate NAND02, whose input terminal is connected to the output terminal of the OR gate OR and the inverted signal TM1B_1 of the first test mode signal;

[0097] A third adjustment NAND gate NAND03, whose input terminal is connected to the output terminal of the first delay element DLY1 and the output terminal of the second adjustment NAND gate NAND02;

[0098] A fourth adjustment NAND gate NAND04, whose input terminal is connected to the output terminal of the third adjustment NAND gate NAND03 and the second test mode signal TM_MRRPDL<0>;

[0099] A fifth adjustment NAND gate NAND05, whose input terminal is connected to the output terminal of the third adjustment NAND gate NAND03 and the inverted signal TM0B_1 of the second test mode signal, and whose output terminal is connected to a second delay element DLY2; the second delay element DLY2 is used to delay the output signal of the third adjustment NAND gate NAND03 by a second delay duration. Exemplarily, the second delay element can be a delay-adjustable delay element composed of an even number of inverters, and the second delay duration can be 0.1 ns;

[0100] A sixth adjustment NAND gate NAND06, whose input terminal is connected to the output terminal of the fourth adjustment NAND gate NAND04 and the output terminal of the second delay element DLY2; the sixth adjustment NAND gate NAND06 is used to output the second command pulse FRP_PDL.

[0101] Here, an implementation manner of the first position adjustment circuit 143 is provided. This circuit is composed of 6 NAND gates, actually includes 4 signal paths, and 2 of the signal paths can be used. As shown in Table 2 below, the signal paths can be selected through the above-mentioned first test mode signal TM_MRRPDL<1> and second test mode signal TM_MRRPDL<0>.

[0102] Exemplarily, as Figure 6Among them, the path shown by the thick line is the default path. At this time, the first test mode signal TM_MRRPDL<1> is 0, its inverted signal is 1, the second test mode signal TM_MRRPDL<0> is 0, and its inverted signal is 1. That is, the instruction pulse MRRD output by the OR gate passes through the second adjustment NAND gate NAND02 and reaches the third adjustment NAND gate NAND03, then enters the fifth adjustment NAND gate NAND05, and after being delayed by 0.1 ns by the second delay element DLY2, it reaches the sixth adjustment NAND gate NAND06, and finally outputs the second instruction pulse FRP_PDL that is neither delayed nor advanced. It can be understood that the second delay element DLY2 here is the default delay element, so the position of the finally output pulse is considered the default position.

[0103] For the second path, the first test mode signal TM_MRRPDL<1> is 1, its inverted signal is 0, the second test mode signal TM_MRRPDL<0> is 0, and its inverted signal is 1. At this time, the instruction pulse MRRD passes through the first adjustment NAND gate NAND01 and the first delay element DLY1, reaches the third adjustment NAND gate NAND03, then enters the fifth adjustment NAND gate NAND05, and after being delayed by 0.1 ns by the second delay element DLY2, it reaches the sixth adjustment NAND gate NAND06, and finally outputs the second instruction pulse FRP_PDL that is delayed by 0.1 ns relative to the default path.

[0104] For the third path, the first test mode signal TM_MRRPDL<1> is 0, its inverted signal is 1, the second test mode signal TM_MRRPDL<0> is 1, and its inverted signal is 0. At this time, the instruction pulse MRRD passes through the first adjustment NAND gate NAND01 and the first delay element DLY1, reaches the third adjustment NAND gate NAND03, then enters the fifth adjustment NAND gate NAND05, and after being delayed by 0.1 ns by the second delay element DLY2, it reaches the sixth adjustment NAND gate NAND06, and finally outputs the second instruction pulse FRP_PDL that is delayed by 0.1 ns relative to the default path.

[0105] The output delay result of the fourth path is the same as that of the first path, so this path is not used here.

[0106]

[0107] Table 2

[0108] In some embodiments, as Figure 8 shown, the test circuit 100 further includes:

[0109] Two sets of instruction counting units 150 are used to count the second instruction pulse FRP_PDL, and control the first data output unit LDQ to output the first random data to be measured or the second data output unit UDQ to output the second random data to be measured according to the counting result;

[0110] Among them, the first set of the instruction counting units 150 is connected to the test adjustment unit 140 and the first data output unit LDQ; the second set of the instruction counting units 150 is connected to the test adjustment unit 140 and the second data output unit UDQ.

[0111] The instruction counting unit 150 counts the second instruction pulse FRP_PDL, and controls a set of data to be output to LDQ or UDQ each time it counts, so that the parallel data is serially output to LDQ or UDQ in sequence. Exemplarily, a first random data to be measured generated by the data generation unit 110 is 128 bits in total and is output to 8 LDQs, and each LDQ receives 16-bit data. Therefore, the instruction counting unit 150 will perform 16 counts, so that 16-bit data is serially output to the LDQ in sequence.

[0112] In some embodiments, each set of the instruction counting units 150 includes:

[0113] A second position adjustment circuit 151 is connected to the test adjustment unit 140, and is used to receive the delay signal MRR_X16_LBUSSEL_L<1:0> or MRR_X16_LBUSSEL_U<1:0>, and adjust the second instruction pulse based on the delay signal to obtain an adjusted pulse L_PDL or U_PDL;

[0114] A counting circuit 152 is connected to the second position adjustment circuit 151, and is used to output a first counting signal LPDL<15:0> or UPDL<15:0> based on the adjusted pulse; wherein, the first counting signal is used to control the first random data to be measured to be output to the first data output unit LDQ or control the second random data to be measured to be output to the second data output unit UDQ.

[0115] Here, the first counting signal is used as an input control signal (FIFO-IN) of the first data output unit LDQ or the second data output unit UDQ, and is used for the random data to be measured to enter the data output unit. In addition, the output control end (FIFO-OUT) of the first data output unit LDQ or the second data output unit UDQ can be normally open. Therefore, after the random data to be measured enters the data output unit, it can be output through the data output unit. At this time, the difference between the read data and the random data to be measured can be determined by reading the output data of the data output unit, so as to realize the test of the data path.

[0116] In some embodiments, as Figure 9 shown, the second position adjustment circuit 151 includes:

[0117] A first delay NAND gate NAND11, whose input terminal is connected to the output terminal of the test adjustment unit 140 and the first delay signal MRR_X16_LBUSSEL_L / U<1>, and whose output terminal is connected to the third delay unit DLY3; the third delay unit DLY3 is used to delay the output signal of the first delay NAND gate NAND11 by a third delay duration;

[0118] A second delay NAND gate NAND12, whose input terminal is connected to the output terminal of the test adjustment unit 140 and the inverted signal TM1B_2 of the first delay signal;

[0119] A third delay NAND gate NAND13, whose input terminal is connected to the output terminal of the third delay unit DLY3 and the output terminal of the second delay NAND gate NAND12;

[0120] A fourth delay NAND gate NAND14, whose input terminal is connected to the output terminal of the third delay NAND gate NAND13 and the second delay signal MRR_X16_LBUSSEL_L / U<0>;

[0121] A fifth delay NAND gate NAND15, whose input terminal is connected to the output terminal of the third delay NAND gate NAND13 and the inverted signal TM0B_2 of the second delay signal, and whose output terminal is connected to the fourth delay unit DLY4; the fourth delay unit DLY4 is used to delay the output signal of the third delay NAND gate NAND13 by a fourth delay duration;

[0122] A sixth delay NAND gate NAND16, whose input terminal is connected to the output terminal of the fourth delay NAND gate NAND14 and the output terminal of the fourth delay unit DLY4; the sixth delay NAND gate NAND16 is used to output the adjustment pulse.

[0123] Similar to the above first position adjustment circuit 133, the second position adjustment circuit 151 is also composed of 6 NAND gates, and its connection method can be the same as that of the first position adjustment circuit 133 in the above embodiment. The second position adjustment circuit 151 also provides 3 available signal paths, as shown in Table 3 below. The specific signal paths similar to the above embodiment will not be elaborated here.

[0124]

[0125] Table 3

[0126] In addition, the above-mentioned counting circuit 152 can be any conventional counter in the art, which is used to count the above-mentioned adjustment pulses L_PDL or U_PDL output by the second position adjustment circuit 151 to generate corresponding first counting signals LPDL<15:0> or UPDL<15:0>. The first data output unit LDQ then receives the first random data to be measured based on the first counting signal LPDL<15:0>; the second data output unit UDQ then receives the second random data to be measured based on the first counting signal UPDL<15:0>. The specific circuit structure of the counting circuit 152 will not be elaborated here, and those skilled in the art can choose to use conventional circuits according to requirements.

[0127] In some embodiments, as Figure 10 shown, the data generation unit 110 includes: a linear feedback shift register LFSR; the linear feedback shift register LFSR includes:

[0128] A carry lookahead processing circuit 111, including: a plurality of carry lookahead units, which are used to generate the first random data LFSR<7:0> based on the initial data DFF_Ini<7:0>; wherein, the number of the carry lookahead units is the same as the number of the first random data LFSR<7:0>;

[0129] A logic control circuit 112, including a plurality of logic control units, which are used to generate parallel second random data BL_T<7:0> based on the first random data LFSR<7:0>;

[0130] A sampling circuit 113, whose input end is connected to the output end of the logic control circuit, is used to receive the second random data and sample based on the second random data to output the original random data DATA0.

[0131] The carry lookahead processing circuit 111 is a processing circuit that generates random numbers using the carry lookahead algorithm, and its data output is also used as data input. When a set of initial data is input, the carry lookahead processing circuit processes the data once each time it runs and outputs the corresponding first random data.

[0132] In some embodiments, as Figure 11 shown, each carry lookahead unit in the carry lookahead processing circuit 111 includes: a flip-flop DFF and a combinational logic circuit unit; wherein, the combinational logic circuit unit can include a combination of logic gate circuits for implementing logical operations such as "NAND", "NOR", "XOR", "XNOR", etc. The logic gates in different combinational logic circuit units can be the same or different.

[0133] The input terminal of the trigger DFF is connected to the output terminal of the combinational logic circuit unit, and the output terminal of the trigger serves as the output terminal of the carry look-ahead unit, outputting the first random data LFSR<7:0>; the signal CKD serves as the clock signal of the trigger. The signal CKD can be a frequency-divided signal of the externally input basic clock tCK.

[0134] In one embodiment, the combinational logic circuit unit includes a plurality of exclusive-OR gates, and the output terminals of the triggers of at least two carry look-ahead units are connected to the input terminals of the plurality of exclusive-OR gates, as Figure 11 shown, the connections between the output terminals and the input terminals are represented by labels 0 to 7, that is, the same number represents mutual connection. For example, a part of the combinational logic circuit unit includes 3 exclusive-OR gates. Two of the exclusive-OR gates perform exclusive-OR operations on two input data respectively, and then input to the 3rd exclusive-OR gate. In this way, the output data of this combinational logic circuit unit is the exclusive-OR result of 4 input data, and these 4 input data are the output data of 4 different carry look-ahead units respectively.

[0135] When generating pseudo-random numbers using the above LFSR, a set of initial values can be provided first and input to the input terminals of each carry look-ahead unit. After one operation, each trigger outputs the corresponding result. Since the output terminal of the trigger is connected to the input terminal of each exclusive-OR gate, the output result will be used as the next input and another operation will be performed when the next clock edge arrives, and the trigger will output the result after reprocessing. That is to say, after inputting a set of initial values, every time the clock signal CKD of the trigger jumps, a processing will be performed to obtain a new first random data. In this way, each first random data obtained after each clock arrival processing can be applied to subsequent processing.

[0136] The logic control circuit 112 further randomly processes the first random data output by the carry look-ahead processing circuit 111 to obtain the second random data, and the logic circuits of each logic control unit can be the same or different.

[0137] In some embodiments, as Figure 12 shown, each of the logic control units in the logic control circuit 112 includes at least one input terminal; each input terminal of the logic control unit is connected to the output terminal of a carry look-ahead unit 111; each of the logic control units is used to perform a logic operation on at least one of the first random data LFSR<7:0> (that is, the data composed of the data at the terminals marked 0-7 in the above Figure 11 ), to obtain a second random data BL_T<7:0>. Figure 12 The labels 0-7 of the input terminals of each logic control unit in Figure 11The marks in it are consistent and are used to represent the first random data LFSR<7:0>.

[0138] It should be noted that, as Figure 12 shown, the combinational logic of each logic control unit and the combinational logic circuit unit as Figure 11 shown are only schematic diagrams of one case. In actual applications, combinations of various other different logic gates can also be used as the above-mentioned logic control unit and combinational logic circuit unit respectively. Exemplarily, as Figure 12 shown, some of the above-mentioned logic control units include 3 exclusive-OR gates for performing exclusive-OR processing on 4 input data; some include two exclusive-OR gates, where one exclusive-OR gate is used to perform exclusive-OR processing on two input data and then output to the second exclusive-OR gate, and the second exclusive-OR gate then performs exclusive-OR processing on the output result and the third data to obtain the exclusive-OR result of 3 data; some include two inverters and one exclusive-OR gate, the two inverters respectively invert different input data and then input to the exclusive-OR gate, and the exclusive-OR gate performs exclusive-OR processing on these two inverted data to obtain the output data; some include two serially connected inverters as a buffer to output data consistent with the input. Using the above circuit, combined with its corresponding input and output, the operation as Figure 12 shown is realized.

[0139] In some embodiments, as Figure 13 shown, the sampling circuit 113 includes:

[0140] A frequency division circuit 1131, including a clock input terminal for receiving a second clock signal CK_MRR and a second clock inverted signal CKB_MRR; the frequency division circuit 113 also includes at least two output terminals for outputting at least two sampling control signals LFSR_IN0 and LFSR_IN8; wherein, the at least two sampling control signals are sequentially delayed by one sampling period; the sampling period is an integer multiple of the clock period of the second clock signal;

[0141] A sampling sub-circuit 1132, connected to at least two output terminals of the frequency division circuit 1131 and the output terminal of the logic control unit, the sampling sub-circuit 1132 is used to sample the second random data BL_T<7:0> within at least two of the sampling periods based on the at least two sampling control signals to obtain the original random data DATA0, and receive the first control signal MR28 through an inverter logic circuit in the sampling sub-circuit 1132, and determine whether to invert based on MR28 to obtain the first random data to be measured DATA1 (exemplarily, each piece of the first random data to be measured includes 8-bit data, as Figure 13 shown as DATA1<7:0>).

[0142] AsFigure 13 As shown, the frequency division circuit 1131 is composed of a plurality of sequentially connected latches (the first latch H1, the second latch H2, the third latch H3, the fourth latch H4) and several inverters and other components. The second latch H2 outputs a frequency division signal CKD of the second clock signal CK_MRR, which can be used as the clock signal of the latch in the above-mentioned carry look-ahead processing circuit 111. The frequency division signal CKD is twice the period of the second clock signal CK_MRR. This frequency division signal is inverted and then transmitted to the first AND gate AND1 and the second AND gate AND2. The signal CK2_N obtained after inverting the signal output by the fourth latch once is transmitted to the first AND gate AND1; the signal CK2D obtained after inverting twice is transmitted to the second AND gate AND2. In this way, the first AND gate AND1 combines the inverted signal CK1N of the frequency division signal and the inverted signal CK_2N of the signal output by the fourth latch to obtain the first sampling control signal LFSR_IN0; the second AND gate AND2 combines the inverted signal CK1N of the frequency division signal and the signal CK_2D obtained by inverting the signal output by the fourth latch twice to obtain the second sampling control signal LFSR_IN8, which is input to the sampling sub-circuit 1132.

[0143] The sampling sub-circuit 1132 may include a latch and an inverter logic circuit. Among them, the latch is used to sample and latch the received second random data BL_T<7:0>, and finally outputs the parallel data after removing the glitches, which is used as the original random data DATA0 generated by the LFSR; the inverter logic circuit is used to determine whether to process the original random data DATA0 according to the received MR28 control signal to generate the first random data to be tested DATA1.

[0144] The signal waveforms of the above LFSR circuit are as Figure 14 shown. For ease of description, hexadecimal numbers are used here, so that 8-bit data can be represented by two hexadecimal digits. As an example, when the initial random data DFF_Ini<7:0> is set to 5A through the trigger, the carry look-ahead processing circuit is connected to the input end of the logic control circuit through the output end of the D flip-flop, so that the logic control circuit can perform carry look-ahead calculation on the data, realize the parallelization of the dot operation, and obtain LFSR<7:0> as 0C after one processing. After another carry look-ahead calculation and processing, LFSR<7:0> is obtained as 9C... The processed data enters the logic control circuit in sequence. After LFSR<7:0>=0C passes through Figure 12After the logic control circuit 112 processes, BL_T<7:0>=30 is obtained; after LFSR<7:0>=9C is processed, BL_T<7:0>=C9 is obtained, and the subsequent processing is similar. Finally, the data enters the sampling circuit, and is sampled based on the sampling control signals LFSR_IN0 and LFSR_IN8 to obtain the original random data DATA0, and then receives the first control signal MR28 through the inverting logic circuit in the sampling sub-circuit 1132, and determines whether to invert based on MR28, and obtains the first random data to be tested DATA1.

[0145] The circuit corresponding to the above data generation unit provides an exemplary embodiment for generating random data. In practical applications, other circuit structures capable of generating pseudo-random data may also be used as the above data generation unit.

[0146] The block diagram of the above LDQ and UDQ is as follows Figure 15 As shown, since the same LDQ and UDQ are used for the read operation when the memory is used normally, the data of the above test circuit will also pass through LDQ and UDQ. Taking LDQ as an example, LDQ includes three components, a sampling circuit 1501, a first-in first-out circuit 1502 (First In First Out, referred to as: FIFO) and a parallel-to-serial conversion circuit 1503. The input end of the sampling circuit 1501 receives the data to be tested (i.e., the first random data to be tested DATA1), the control end of the sampling circuit 1501 receives the clock control signal BG2D, and the sampling circuit 1501 samples the data to be tested DATA1<7:0> and outputs it under the control of the clock control signal BG2D. The input end of the first-in first-out circuit 1502 is connected to the output end ORD of the sampling circuit, the first control end of the first-in first-out circuit 1502 receives the input control signal FIFO IN (i.e., the adjustment pulse PDL<15:0> in the above embodiment), and the second control end of the first-in first-out circuit 1502 receives the output control signal FIFOOUT. Under the control of the input control signal FIFO IN, the first-in-first-out circuit 1502 performs serial-to-parallel conversion on the output data ORD<7:0> of the sampling circuit 1501. Under the control of the output control signal FIFO OUT, the first-in-first-out circuit 1502 outputs the data BUS<3:0> obtained after the serial-to-parallel conversion (for example, 8 bits to 4 bits) to the serial-to-parallel conversion circuit 1503. After the second serial-to-parallel conversion (for example, 4 bits to 1 bit) of the serial-to-parallel conversion circuit, the data is output at the output terminal OUT. Figure 15 shown.

[0147] Through the above embodiments of the present disclosure, the circuit design of the single LFSR engine mode can be realized by utilizing the structure of the existing DDR5 data path. The specific signal waveform is as follows: Figure 16 shown.

[0148] Figure 16 The meanings of the signals are as follows:

[0149] CK_T: The reference clock, that is, the basic clock input externally.

[0150] BG2D: The clock control signal, which is turned on when outputting data as can be seen through Figure 16 ORD<7:0>: The signal output from the output terminal of the sampling circuit. LDQ has 8 bits, and after being sampled by the sampling circuit, 8-bit ORD signals are output respectively.

[0151] PDL<15:0>: That is, FIFO IN, the input control signal.

[0152] FIFO OUT, the output control signal. FIOF_OUT0 - 3 refer to the output clocks of bits 0 - 3, and so on.

[0153] BUS<3:0>: The output data after the first parallel - to - serial conversion.

[0154] ICLKN: The divided - by - four clock, with a phase difference of 0° from the reference clock.

[0155] QCLKN: The divided - by - four clock, with a phase difference of 90° from the reference clock.

[0156] IBCLKN: The divided - by - four clock, with a phase difference of 180° from the reference clock.

[0157] QBCLKN: The divided - by - four clock, with a phase difference of 270° from the reference clock.

[0158] Reference

[0159] It can be seen the changes of the signals of the above - mentioned test circuit and the input - output results. Figure 16 The beneficial effects of the test circuit in the embodiments of the present disclosure include the following three aspects:

[0160] First aspect: By using a single LFSR engine to generate 128 - bit data of LDQ and UDQ respectively, the chip area is reduced, the load and power consumption of the circuit are decreased, and the resources of the layout wire tracks are saved;

[0161] Second aspect: By using different MRR_X16_LBUSSEL_L<1:0> and MRR_X16_LBUSSEL_U<1:0> signals to independently control the delay of the FRP_PDL signal respectively, the adjustability of the FRP_PDL signal is increased, so that LPDL and UPDL corresponding to LDQ and UDQ are more easily matched;

[0162] ​

[0163] Third aspect: By adding the module MRRUDQINV to control the function of whether the UDQ data is inverted, so as to meet the requirement that the UDQ data can be inverted in the single-engine LFSR mode.

[0164] As Figure 17 shown, an embodiment of the present disclosure further provides a memory 200, including:

[0165] A memory cell array 210;

[0166] A peripheral circuit 220; wherein, the peripheral circuit 220 includes at least one group of first data output units LDQ and at least one group of second data output units UDQ, and also includes any one of the above test circuits 100.

[0167] It should be understood that "some embodiments", "an embodiment" or "one embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in an embodiment" or "in one embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the order numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0168] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0169] The above is only the implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A test circuit, characterized in that, Peripheral circuit applied to a memory; The memory includes at least one set of first data output units and at least one set of second data output units; The test circuit includes: A data generation unit, configured to generate first random data to be tested and connected to at least one set of the first data output units; A data control unit, connected to the data generation unit and at least one set of the second data output units; A first data control terminal, connected to the data generation unit and the data control unit, for receiving a first control signal; A second data control terminal, connected to the data control unit, for receiving a second control signal; Wherein, the data generation unit is configured to determine whether to invert the original random data generated by the data generation unit as the first random data to be tested and output it to the first data output unit according to the first control signal; the data control unit is configured to determine whether to invert the first random data to be tested as the second random data to be tested and output it to the second data output unit according to the first control signal and the second control signal.

2. The test circuit according to claim 1, wherein The data control unit includes: A control signal processing unit, connected to the first data control terminal and the second data control terminal, for receiving the first control signal and the second control signal and outputting a third control signal; A data selection unit, configured to receive the first random data to be tested and connected to the output terminal of the control signal processing unit; the data selection unit is configured to output the second random data to be tested according to the third control signal.

3. The test circuit according to claim 2, wherein The control signal processing unit includes: An exclusive-OR gate, whose first input terminal is connected to the first data control terminal and whose second input terminal is connected to the second data control terminal; A first NAND gate, whose first input terminal is connected to the output terminal of the exclusive-OR gate and whose second input terminal is connected to a first enable signal terminal; the output terminal of the first NAND gate is used to output the third control signal.

4. The test circuit according to claim 2, characterized in that, The data selection unit includes: A second NAND gate, whose first input terminal is used to receive the third control signal and whose second input terminal is used to receive the first random data to be tested; A third NAND gate, whose first input terminal is used to receive the inverted signal of the third control signal and whose second input terminal is used to receive the inverted signal of the first random data to be tested; A fourth NAND gate, whose first input terminal is connected to the output terminal of the second NAND gate, whose second input terminal is connected to the output terminal of the third NAND gate, and whose output terminal is connected to the second data output unit.

5. The test circuit according to claim 1, characterized in that, The test circuit further includes: A command decoding unit, configured to receive a first instruction related to testing and decode the first instruction to obtain a first instruction pulse; A test adjustment unit, connected to the command decoding unit, for adjusting the pulse width and / or pulse position of the first instruction pulse to obtain a second instruction pulse; the second instruction pulse is used to control the output of the first random data to be tested to the first data output unit or to control the output of the second random data to be tested to the second data output unit.

6. The test circuit according to claim 5, characterized in that The test adjustment unit includes: The first delay circuit includes an input terminal for receiving the first instruction pulse, and a first clock input terminal for receiving a first clock signal and a first inverted clock signal; the first delay circuit is configured to output a plurality of delayed signals obtained by delaying the first instruction pulse, with each delayed signal being delayed by half a clock cycle in sequence; wherein, the clock cycle is the period of the first clock signal; The pulse width adjustment circuit includes: an OR gate, whose input terminals are connected to the plurality of output terminals of the first delay circuit, for receiving the plurality of delayed signals and outputting the first instruction pulse with adjusted width; The first position adjustment circuit, whose input terminal is connected to the output terminal of the OR gate, is configured to adjust the pulse position of the first instruction pulse with adjusted width to output the second instruction pulse.

7. The test circuit according to claim 6, wherein The first position adjustment circuit includes: A first adjustment NAND gate, whose input terminals are connected to the output terminal of the OR gate and a first test mode signal, and whose output terminal is connected to a first delay element; the first delay element is configured to delay the output signal of the first adjustment NAND gate by a first delay duration; A second adjustment NAND gate, whose input terminals are connected to the output terminal of the OR gate and the inverted signal of the first test mode signal; A third adjustment NAND gate, whose input terminals are connected to the output terminal of the first delay element and the output terminal of the second adjustment NAND gate; A fourth adjustment NAND gate, whose input terminals are connected to the output terminal of the third adjustment NAND gate and a second test mode signal; A fifth adjustment NAND gate, whose input terminals are connected to the output terminal of the third adjustment NAND gate and the inverted signal of the second test mode signal, and whose output terminal is connected to a second delay element; the second delay element is configured to delay the output signal of the third adjustment NAND gate by a second delay duration; A sixth adjustment NAND gate, whose input terminals are connected to the output terminal of the fourth adjustment NAND gate and the output terminal of the second delay element; the sixth adjustment NAND gate is configured to output the second instruction pulse.

8. The test circuit according to claim 5, wherein The test circuit further includes: Two groups of instruction counting units, configured to count the second instruction pulse to control the first data output unit to output the first random data to be tested or control the second data output unit to output the second random data to be tested according to the counting result; Wherein, the first group of the instruction counting units is connected to the test adjustment unit and the first data output unit; the second group of the instruction counting units is connected to the test adjustment unit and the second data output unit.

9. The test circuit according to claim 8, wherein Each group of the instruction counting units includes: A second position adjustment circuit, connected to the test adjustment unit, configured to receive a first delay signal and a second delay signal, and adjust the second instruction pulse based on the first delay signal and the second delay signal to obtain an adjusted pulse; A counting circuit, connected to the second position adjustment circuit, configured to output a first counting signal based on the adjusted pulse; wherein, the first counting signal is used to control the first random data to be tested to be output to the first data output unit or control the second random data to be tested to be output to the second data output unit.

10. The test circuit according to claim 9, wherein, The second position adjustment circuit includes: The first delay NAND gate, whose input terminals are connected to the output terminal of the test adjustment unit and the first delay signal, and whose output terminal is connected to the third delay unit; the third delay unit is used to delay the output signal of the first delay NAND gate for a third delay duration; The second delay NAND gate, whose input terminals are connected to the output terminal of the test adjustment unit and the inverted signal of the first delay signal; The third delay NAND gate, whose input terminals are connected to the output terminal of the third delay unit and the output terminal of the second delay NAND gate; The fourth delay NAND gate, whose input terminals are connected to the output terminal of the third delay NAND gate and the second delay signal; The fifth delay NAND gate, whose input terminals are connected to the output terminal of the third delay NAND gate and the inverted signal of the second delay signal, and whose output terminal is connected to the fourth delay unit; the fourth delay unit is used to delay the output signal of the third delay NAND gate for a fourth delay duration; The sixth delay NAND gate, whose input terminals are connected to the output terminal of the fourth delay NAND gate and the output terminal of the fourth delay unit; the sixth delay NAND gate is used to output the adjustment pulse.

11. The test circuit according to claim 1, wherein The data generation unit includes: a linear feedback shift register; the linear feedback shift register includes: A carry lookahead processing circuit, including: a plurality of carry lookahead units, used to generate first random data based on initial data; wherein, the number of the carry lookahead units is the same as the number of the first random data; A logic control circuit, including a plurality of logic control units, used to generate parallel second random data based on the first random data; A sampling circuit, whose input terminal is connected to the output terminal of the logic control circuit, used to receive the second random data, and sample based on the second random data to output the original random data.

12. The test circuit according to claim 11, wherein The carry lookahead unit includes: a trigger and a combinational logic circuit unit; The input terminal of the trigger is connected to the output terminal of the combinational logic circuit unit, and the output terminal of the trigger serves as the output terminal of the carry lookahead unit to output the first random data; The combinational logic circuit unit includes a plurality of exclusive OR gates, and the output terminals of the triggers of at least two carry lookahead units are connected to the input terminals of the plurality of exclusive OR gates; Each of the logic control units includes at least one input terminal; each input terminal of the logic control unit is connected to the output terminal of one of the carry lookahead units; each of the logic control units is used to perform a logic operation on at least one of the first random data to obtain one of the second random data.

13. The test circuit according to claim 11, wherein The sampling circuit includes: A frequency division circuit, including a clock input terminal, used to receive a second clock signal and an inverted second clock signal; the frequency division circuit further includes at least two output terminals, used to output at least two sampling control signals; wherein, the at least two sampling control signals are sequentially delayed by one sampling period; the sampling period is an integer multiple of the clock period of the second clock signal; A sampling sub-circuit is connected to at least two output terminals of the frequency division circuit and the output terminal of the logic control unit. The sampling sub-circuit is configured to sample the second random data within at least two of the sampling periods respectively based on the at least two sampling control signals to obtain the original random data.

14. A memory, characterized in that, It includes: A storage cell array; A peripheral circuit, the peripheral circuit includes at least one group of first data output units and at least one group of second data output units, and the test circuit according to any one of claims 1 to 13.

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