Implementation method for preceding-stage PFC control of wireless charging system based on superposition of multiplication control loop and inner and outer loops

Abstract

The invention relates to a method for realizing preceding-stage PFC (power factor correction) control of a wireless charging system with superposed multiplication control loop and inner and outer loops, which adjusts the performance of the whole system through a type-2 compensator and Kalman filtering, can ensure that a voltage loop has enough bandwidth so as to meet dynamic response performance, and can ensure good power correction performance at the same time. According to the invention, the two-type compensator is used for digital operation in the DSP processor, so that the stability, the response speed, the steady-state error and other performances of the feedback control system are improved; meanwhile, the Kalman filtering algorithm is used for estimating the state of the dynamic system, the performance of the whole system is adjusted in combination with a voltage outer loop and a current inner loop in an original system, and the dynamic response of the output voltage can be improved under the condition that the bandwidth of the voltage loop is sufficient. The method is suitable for the technical field of wireless charging system power correction.

Description

Technical Field

[0001] The present invention relates to the technical field of power correction of wireless charging systems, and particularly to a method for implementing pre-stage PFC control of a wireless charging system with a multiplier control loop and superposition of internal and external loops. Background Art

[0002] The pre-stage of a wireless charging system is usually an AC-DC converter for converting the alternating current of the power grid into direct current. The harmonics generated by the system reduce the efficiency of power conversion, transmission, and utilization, cause overheating, vibration, and noise in the wireless charging device, age the insulation, shorten the service life, and even cause failures or burnouts. In order to make the input current and the grid voltage be sinusoidal waves with the same frequency and phase, the power factor be close to 1, and the harmonics meet the standard requirements, thereby reducing the harm of harmonics to the power grid and improving the utilization rate of energy, the AC-DC converter as the pre-stage of the wireless charging system is usually a PFC converter, such as a three-phase Vienna system.

[0003] Among various common PFC control strategies, a voltage loop is usually required to stabilize the output voltage. This link often includes a low-pass filter with a very low cut-off frequency (whether it is a hardware filter composed of an operational amplifier circuit or a software filter executed by a microcontroller). However, this measure to attenuate the harmonics of the output voltage reduces the dynamic response ability of the output voltage to load changes. For those application scenarios where the load is basically stable, a lower voltage loop bandwidth can meet the system requirements. However, in application scenarios where the load often changes rapidly (such as the post-stage of a wireless charging system can itself be regarded as a special load, and it will undergo some irregular changes at irregular intervals), insufficient voltage loop bandwidth will cause the output bus voltage to fluctuate greatly for a long time, which not only degrades the system control performance but also poses a hazard to the wireless charging system. Therefore, the PFC used in the wireless charging system has different technical requirements for its dynamic performance. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, and provide a method for implementing pre-stage PFC control of a wireless charging system with a multiplier control loop and superposition of internal and external loops, which adjusts the performance of the overall system through a type-II compensator and Kalman filtering, can ensure that the voltage loop has sufficient bandwidth to meet the dynamic response performance, and at the same time ensure good power correction performance.

[0005] The technical solution adopted by the present invention is: The present invention discloses a method for implementing pre-stage PFC control of a wireless charging system. A multiplier control loop is added to the original control loop of a conventional boost PFC circuit. The multiplier control loop contains a type-II compensator and a Kalman algorithm device. The implementation method includes the following steps.

[0006] S1. The power control loop samples the input voltage V in the boost PFC topology in and the inductor current I L , and after being processed by the low-pass filter in the loop, obtains V for power calculation po and I po . The two are multiplied by the multiplier in the loop to obtain the actual power value P ref ;

[0007] S2. The voltage outer loop samples the output voltage V of the boost PFC out , and the difference obtained by subtracting the reference output voltage value V outref enters the PI controller in the loop;

[0008] S3. The multiplication control loop simultaneously samples the output voltage V of the boost PFC out . The output voltage V out is adjusted in bandwidth by a type-II compensator to obtain the output value N control , and then subtracted from the bias amount N of the control value control(offset) . The obtained difference is input into the Kalman algorithm unit, and after being compensated by the Kalman filtering algorithm, the multiplier control value V control is obtained;

[0009] S4. The actual power value Pref obtained in S1 is divided by the multiplier control value V obtained in S3 control to obtain the power multiplier V m . The output value of the PI controller in the voltage outer loop in S2 is divided by I in S1 po . The obtained value is added to the power multiplier V m through the adder in the current inner loop. The added value passes through the current ratio counter K IC and the integrator triggered by the rising edge, and a triangular wave signal V ramp is obtained;

[0010] S5. The integrator sends the obtained triangular wave signal V ramp to the comparator in the current inner loop, and finally generates the pwm signal V gs required by the boost PFC switching device.

[0011] Furthermore, in step S3, the type-II compensator is an analog transconductance amplifier in the DSP processing chip, and its transfer function is

[0012]

[0013] where G EAis the gain of this amplifier. Such a type-II compensator is used to adjust and set the bandwidth of the system, reducing the noise and harmonic pollution due to the resonant cavity or switching devices in the wireless charging system.

[0014] Further, the two poles and one zero of the type-II compensator are as follows:

[0015] Zero,

[0016]

[0017] Pole 1,

[0018]

[0019] Pole 0,

[0020]

[0021] The bandwidth of the system is adjusted by adjusting the positions of the two poles and one zero.

[0022] Further, through the bilinear transformation method, the non-linear mapping of the frequency response from the s-plane (analog domain) to the z-plane (digital domain) is realized to digitalize the type-II compensator in the DSP processor. Assuming the sampling period is T, the bilinear transformation formula for mapping s to z is,

[0023]

[0024] Further, the compensation process of the Kalman algorithm in step S3 and its mathematical expressions are as follows,

[0025] a. Definition of state variables. Let the system state variable be x k , representing the voltage value after being modulated by the type-II compensator (i.e., the voltage value expected to be predicted and compensated into the modulation wave);

[0026] b. Definition of observation variables. Let the observation variable be z k , representing the digital output voltage value obtained from the type-II compensator;

[0027] c. State prediction. The state expression is

[0028]

[0029] Among them, is the predicted state at time k, A is the state transition matrix, is the state estimate at time k-1;

[0030] d. Prediction error covariance matrix. The expression is

[0031]

[0032] Among them, is the predicted error covariance matrix at time kk, Q is the process noise covariance matrix, and T is the matrix inversion symbol;

[0033] e. Measurement update, the expression is

[0034] Zk = Hxk + vk

[0035] Among them, Z k is the measurement value at time k (the digital quantity obtained from the type-II compensator), H is the observation matrix (if the state of the system directly corresponds to the observed value, it can be set to 1, usually adjusted according to actual needs), v k is the measurement noise, and a model that conforms to the system noise can be selected for application;

[0036] f. Kalman gain, the expression is

[0037]

[0038] Among them, Kk is the Kalman gain at time k, and R is the measurement noise covariance matrix;

[0039] g. State update, the expression is

[0040]

[0041] h. Error covariance matrix update, the expression is

[0042]

[0043] Among them, I is the identity matrix;

[0044] Enhance the fast response performance through the above process to meet the problem that the load of the front-stage PFC in the wireless charging system will fluctuate irregularly.

[0045] Furthermore, two low-pass filters are provided in the power control loop, which are respectively used to perform power calculation on the input current V in and the inductor current I L Apply power calculation.

[0046] Finally, replace the original PI controller with a current calculation proportionality and a rising-edge-triggered integrator provided in the current inner loop, which are used to process and calculate the values input from the multiplier control loop, the power control loop, and the voltage outer loop. Description of the Drawings

[0047] Figure 1 is the boost PFC control block diagram of the implementation method of the present invention;

[0048] Figure 2 is the waveform diagram of the PFC modulation principle;

[0049] Figure 3 is the timing diagram of the multiplier;

[0050] Figure 4 is the analog circuit diagram of the type II complementer;

[0051] Figure 5 is the full waveform display diagram of the saber simulation;

[0052] Figure 6 is the waveform diagram of the input voltage and inductor current for power correction during normal operation in the CCM mode. Detailed implementation method

[0053] The present invention provides a method for digitally reducing the harmonic components in the PFC output voltage from entering the control loop, while ensuring a sufficiently wide voltage loop bandwidth to meet the fast response performance required by the subsequent changes in the wireless charging system. The type II compensator used in this implementation method is a commonly used compensation network in control theory, mainly used to improve the stability, response speed, and steady-state error of the feedback control system. It is usually applied in analog circuit design, especially in switching power supplies (such as DC-DC converters), power factor correction (PFC) circuits, and other electronic systems that require precise control; at the same time, the Kalman filter used is a recursive Bayesian filtering algorithm for estimating the state of a dynamic system. It is an efficient state estimation algorithm that can provide the best estimate in the presence of uncertain measurement data.

[0054] In the original control loop of the conventional boost PFC circuit, a multiplier control loop is added in this implementation method. The multiplier control loop contains a type II compensator and a Kalman algorithm unit. The implementation method includes the following steps:

[0055] S1. The power control loop samples the input voltage V in and the inductor current I L in the boost PFC topology, and after being processed by the low-pass filter in the loop, obtains V po and I po for power calculation. The two are multiplied by the multiplier in the loop to obtain the actual power value P ref ;

[0056] S2. The voltage outer loop samples the output voltage V out of the boost PFC, and compares it with the reference output voltage value V outrefThe obtained difference enters the in-loop PI controller;

[0057] S3. The multiplication control loop simultaneously samples the output voltage V of the boost PFC out and outputs the voltage V out After bandwidth adjustment by a type-II compensator, the output value N is obtained control , and then it is subtracted from the offset of the control value N control(offset) . The obtained difference is input into the Kalman algorithm unit, and after compensation by the Kalman filtering algorithm, the multiplier control value V is obtained control ;

[0058] S4. Divide the actual power value Pref obtained in S1 by the multiplier control value V obtained in S3 control to obtain the power multiplier V m . Divide the output value of the PI controller in the voltage outer loop in S2 by I in S1 po . The obtained value is added to the power multiplier V m through the adder in the current inner loop. The added value passes through the current ratio counter K IC and the integrator triggered by the rising edge, and a triangular wave signal V is obtained ramp ;

[0059] S5. The integrator sends the obtained triangular wave signal V ramp to the comparator in the current inner loop, and finally generates the pwm signal V required for the boost PFC switching device gs .

[0060] In step S1, first, in the boost PFC topology, it is necessary to sample the inductor current I L , the input voltage / current V in / I in (signals at the same node, usually converted into one of the voltage / current parameters for power calculation. In the present invention, the input voltage V in is selected as the signal at this node for use) and the output voltage V out . The specific sampling method and the type of sensor used are not limited. The sampling circuit can use a simple proportional op-amp circuit, and the sensor can be a Hall sensor or a current transformer. Since the inductor current IL and the input voltage V in are AC signals, they need to be processed by a low-pass filter first. There are two low-pass filters in the power control loop of the present invention, which are respectively used to apply power calculation to the input current V in and the inductor current I L . Both of these low-pass filters are designed as a typical first-order low-pass filter, and a very small part of the output voltage ripple will exist in the input voltage V inIn the analog feedback. Usually, it is recommended that the compensated bandwidth of the converter be fixed below 20 Hz to effectively filter out the ripple up to 100 Hz. The resulting analog quantity will be received by the ADC port of the DSP, where the input voltage V in is calculated to obtain V po is the low-pass filter LPF_1, and its transfer function is

[0061] responsible for sampling and filtering the inductor current I L to obtain I po is the low-pass filter LPF_2, and its transfer function is

[0062]

[0063] As Figure 1 shown, multiply the V Po and I Po obtained in step S1 to get the actual power value P ref , and then divide by the control number V control obtained in step S3 to get the power multiplier V m ; in step S2, the output voltage V out signal enters this link through a zero-order hold ZOH, and the difference obtained by subtracting from the reference output voltage value V outref enters the PI controller. The output value of the PI controller is then divided by I po , and then added to the power multiplier V m obtained in step S4. The obtained value enters the current proportional counter K IC , and then enters a rising-edge-triggered integrator, and then outputs a triangular wave signal V ramp . In this part, the superposition value of the power multiplier V m and the output value of the "voltage outer loop", the proportional operation and the rising-edge-triggered integrator together constitute a "current inner loop" part.

[0064] In the multiplier control loop mentioned in the present invention, it is mainly used to process the output voltage V out signal, reduce the noise and harmonic pollution inside due to the resonator or switching devices in the wireless charging system through a type-II compensator, and enhance the fast response performance through the Kalman filtering process, Figure 2 shown are the key waveforms in the PFC modulation process; Figure 3 shown is when the multiplier control loop operates normally, the power correction process is realized in the CCM mode, and the timing diagram of the power multiplier value V m and each key quantity (input voltage / current and inductor current I L ).

[0065] In step S3, the type-II compensator is the analog transconductance amplifier in the DSP processing chip ( Figure 4 as shown). First, an analog type-II compensator that meets the system requirements needs to be designed. This includes determining the zero-pole positions of the compensator to ensure the required frequency response characteristics; then, converting it into an equivalent digital form. Once the conversion from the s-domain to the z-domain is completed, this digital type-II compensator can be expressed in the form of a recurrence equation.

[0066] The transfer function of the type-II compensator in the present invention is

[0067]

[0068] where G EA is the gain of this amplifier. Such a type-II compensator is used to adjust and set the bandwidth of the system, reducing the noise and harmonic pollution due to the resonant cavity or switching devices in the wireless charging system. To realize the digitization of the type-II compensator in the DSP processing chip, first, the transfer function from control to output (V out / N control ) needs to be accurately calculated, where V out is the output voltage of the PFC, and N control is the output of the error amplifier (i.e., the system control value N Figure 1 mentioned in the multiplier control loop in control , and they are the same value). The analog circuit diagram of the type-II compensator is a classic transconductance amplifier, where G EA is the gain of this error amplifier, and V nom is the rated value of the output voltage. Therefore, its output current is: Icontrol = G EA ·[Kfb·Vout - V REF = G EA ·Kfb·(Vout - Vnom)

[0069] We can calculate the control function of this type-II compensator:

[0070]

[0071] Therefore, substituting the I contro expression into the aforementioned equation gives the result:

[0072]

[0073] Finally, if C Z << C P , the above formula simplifies as follows:

[0074]

[0075] Among them, the two poles and one zero of the type-II compensator are as follows:

[0076] Zero point,

[0077]

[0078] Pole 1,

[0079]

[0080] Pole 0,

[0081]

[0082] Therefore, the present invention can adjust the bandwidth of the system by adjusting the positions of the two poles and one zero. In addition, through the bilinear transformation method, this method can map a non-linear mapping of the frequency response from the s-plane (analog domain) to the z-plane (digital domain), thereby realizing the digitization of the type-II compensator. Assuming the sampling period is T, the bilinear transformation formula for mapping s to z is

[0083]

[0084] After the transfer function of the type-II compensator is designed, R Z , R P , C P , K fb and G EA are all determined. At this time, according to the actual parameters, through the bilinear transformation function c2d of matlab, the coefficients a0, a1, b0, b 1， of the digital type-II compensator can be calculated. The following is an example of using the bilinear transformation function c2d of matlab, which is just a simple demonstration to illustrate the digitization process of the type-II compensator:

[0085]

[0086]

[0087] Then the coefficients a0, a1, b0, b1 of the digital type-II compensator can be obtained; in order to implement the type-II compensator on the DSP chip, we need to implement this compensator in C language, and we can use a form similar to implementing a digital IIR filter to implement it:

[0088]

[0089] The input of the Kalman algorithm is the value of the output voltage V out after being modulated by the type-II compensator, that is, the "control value N control”(and the bias should be removed). The output of this module is "Multiplier control value V control ", which is represented by Kalman in Figure 1 . The role of the Kalman algorithm in the present invention is to enhance the fast response performance to meet the problem that the load of the front-stage PFC in the wireless charging system will fluctuate irregularly. The compensation process of the Kalman algorithm described in step S3 and its mathematical expressions are as follows. i. Definition of state variables. Let the system state variable be x k , representing the voltage value after being modulated by the type-II compensator (i.e., the voltage value expected to be predicted and compensated into the modulation wave);

[0090] j. Definition of observation variables. Let the observation variable be z k , representing the digital output voltage value obtained from the type-II compensator;

[0091] k. State prediction. The state expression is

[0092]

[0093] where, is the predicted state at time k, A is the state transition matrix, is the state estimate at time k-1;

[0094] l. Prediction error covariance matrix. The expression is

[0095]

[0096] where, is the prediction error covariance matrix at time kk, Q is the process noise covariance matrix, and T is the matrix inversion symbol;

[0097] m. Measurement update. The expression is

[0098] Zk = Hxk + vk

[0099] where, Z k is the measurement value at time k (the digital quantity obtained from the type-II compensator), H is the observation matrix (if the state of the system directly corresponds to the observed value, it can be set to 1, usually adjusted according to actual needs), v k is the measurement noise, and a model that conforms to the system noise can be selected for application;

[0100] n. Kalman gain. The expression is

[0101]

[0102] where, K k is the Kalman gain at time k, and R is the measurement noise covariance matrix;

[0103] o. State update, with the expression

[0104]

[0105] p. Error covariance matrix update, with the expression

[0106]

[0107] where I is the identity matrix;

[0108] Enhance the fast response performance through the above process to meet the problem that the load of the front - stage PFC in the wireless charging system will have irregular fluctuations.

[0109] The following is a MATLAB code implementation framework (it is more convenient to calculate matrices in MATLAB than in C language, so it is used to verify the mathematical process. In actual DSP implementation, some other means are needed for more complex matrix operations) based on the above theory:

[0110]

[0111]

[0112]

[0113] The above process can also be implemented in C language and compiled into a DSP program for use. Specifically, it is necessary to check whether the corresponding chip's IQmath algorithm library supports the relevant calculation process. Taking the 28335 chip as an example below, an embodiment of the Kalman filtering process based on C language is provided:

[0114]

[0115]

[0116]

[0117] In order to adapt to the situation where the load of the rear - stage in the wireless charging system changes irregularly, the present invention adds a "multiplier control loop" on the basis of the original control loop of the boost PFC in the ordinary CCM mode. The "multiplier control loop" contains a type - II compensator and a Kalman algorithm to adjust the performance of the overall system, and can improve the dynamic response of the output voltage while ensuring that the voltage - loop bandwidth is sufficient.

[0118] Finally, it should be emphasized that the above description is only a preferred embodiment of the present invention and is not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for implementing the front-stage PFC control of a wireless charging system with a multiplication control loop superimposed with an inner and outer loop, characterized in that: The control method adds a multiplier control loop to the original control loop of the conventional boost PFC circuit, wherein the multiplier control loop contains a type II compensator and a Kalman algorithm. The implementation method includes the following steps: S1, power control loop for boost PFC topology input voltage V in and the inductor current I L The V for power calculation is obtained by using a low-pass filter in the loop. po and I po The two are multiplied by the multiplier inside the loop to obtain the actual power value P ref ; S2, the voltage outer loop to boost PFC output voltage V out Sampling and reference output voltage value V outref The difference obtained by subtraction enters the PI controller in the loop; S3, the multiplication control loop also controls the output voltage V of the boost PFC out Sampling, output voltage V out After bandwidth adjustment by the type II complementer, the output value N is obtained control , and then the control value offset N control(offset) Subtract the difference, and input it into the Kalman algorithm. After compensation by the Kalman filter algorithm, the multiplier control value V is obtained. control ; S4, divide the actual power value Pref obtained in S1 by the multiplier control value V obtained in S3 control Get the power multiplier V m , the output value of the PI controller in the voltage outer loop in S2 is divided by the I in S1 po The obtained value is added to the power multiplier V by the adder in the current inner loop. m The added value passes through the current proportional counter K IC After the integrator is triggered by the rising edge, a triangular wave signal V is obtained. ramp ; S5, the integrator converts the obtained triangular wave signal V ramp It is sent to the comparator in the current inner loop, and finally generates the pwm signal V required by the boost PFC switch device. gs .

2. The method for implementing the front-stage PFC control of a wireless charging system with a multiplication control loop superimposed with an inner and outer loop according to claim 1, characterized in that: In step S3, the second type compensator is an analog transconductance amplifier in the DSP processing chip, and its transfer function is Among them, G EA is the gain of this amplifier. Such a type II compensator is used to adjust and set the bandwidth of the system to reduce the noise and harmonic pollution caused by the resonant cavity or switching devices in the wireless charging system.

3. The method for realizing the front-stage PFC control of a wireless charging system with a multiplication control loop superimposed with an inner and outer loop according to claim 2, characterized in that: The two poles and one zero of the type II compensator are as follows: Zero o'clock, Pole 1, Pole 0, The bandwidth of the system is adjusted by adjusting the location of the two poles and one zero.

4. The method for realizing the front-stage PFC control of a wireless charging system with a multiplication control loop superimposed with an inner and outer loop according to claim 3, characterized in that: Through the bilinear transformation method, the nonlinear mapping is mapped from the frequency response on the s plane (analog domain) to the z plane (digital domain), realizing the digitization of the type II complement in the DSP processor. Assuming that the sampling period is T, the bilinear transformation formula from s to z is:

5. The method for realizing the front-stage PFC control of a wireless charging system with a multiplication control loop superimposed with an inner and outer loop according to claim 1, characterized in that: The compensation process of the Kalman algorithm described in step S3 and its mathematical expression are as follows: a. State variable definition, let the system state variable be x k , represents the voltage value after modulation by the type II compensator (i.e., the voltage value expected to be predicted and compensated into the modulation wave); b. Observation variable definition, let the observation variable be z k , represents the digital output voltage value obtained from the type II compensator; c. State prediction, the state expression is in, is the predicted state at time k, A is the state transfer matrix, is the state estimate at time k-1; d. The prediction error covariance matrix is ​​expressed as in, is the prediction error covariance matrix at time kk, Q is the process noise covariance matrix, and T is the inverted sign of the matrix; e. Measurement update, the expression is Zk=Hxk+vk Among them, Z k is the measurement value at time k (the digital quantity obtained from the type II compensator), H is the observation matrix (if the state of the system directly corresponds to the observation value, it can be set to 1, usually adjusted according to actual needs), vk is the measurement noise, and a model that conforms to the system noise can be selected to apply; f. Kalman gain, expressed as Where Kk is the Kalman gain at time k, and R is the measurement noise covariance matrix; g. Status update, the expression is h. Error covariance matrix update, the expression is Where I is the identity matrix; The fast response performance is enhanced through the above process to meet the problem of irregular load fluctuation of the front-stage PFC in the wireless charging system.

6. The method for realizing the front-stage PFC control of a wireless charging system with a multiplication control loop superimposed with an inner and outer loop according to claim 1, characterized in that: The power control loop is provided with two low-pass filters, which are used to control the input current V in and the inductor current I L Apply power calculations.

7. The method for realizing the front-stage PFC control of a wireless charging system with a multiplication control loop superimposed with an inner and outer loop according to claim 1, characterized in that: The original PI controller is replaced by a current calculation proportional device and a rising edge triggered integrator arranged in the current inner loop, so as to process and calculate the numerical values ​​inputted by the multiplier control loop, the power control loop and the voltage outer loop.

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