DC-DC converter and chip

Abstract

The invention provides a DC-DC converter and a chip. The DC-DC converter comprises a pulse width modulation signal generator, a lower tube conduction time generation circuit, an external frequency generation circuit, a unit gain negative feedback circuit, a first comparator, a control circuit, an upper tube, an inductor and a lower tube. The lower tube conduction time generating circuit outputs a ramp voltage to the in-phase input end of the first comparator according to the PWM signal and the lower tube conduction time ending signal; the external frequency generation circuit outputs a triangular wave voltage to the unit gain negative feedback circuit according to an external clock signal, a frequency synchronization disable signal and a lower tube conduction time ending signal; the unity gain negative feedback circuit outputs a reference voltage to the inverted input end of the first comparator according to the triangular wave voltage when the frequency synchronization enable signal is at a high level; and the first comparator outputs a lower tube conduction time ending signal to the control circuit, the lower tube conduction time generating circuit and the external frequency generating circuit respectively.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and particularly to a DC-DC converter and a chip. Background Art

[0002] In the process of the rapid development of electronic technology, the direct current to direct current (DC-DC) converter has also developed rapidly. As a switching power supply technology, the DC-DC converter has advantages such as fast dynamic response and simple control, and has a wide range of applications. In order to keep the switching frequency of the DC-DC converter constant, a phase-locked loop circuit is usually used to synchronize the switching frequency in the related technology. However, the circuit structure adopted by this switching frequency synchronization method is complex and difficult to implement.

[0003] Aiming at the problems of the complex circuit structure and large implementation difficulty in the switching frequency synchronization of the related technology, no effective technical solution has been proposed yet. Summary of the Invention

[0004] The main purpose of the present disclosure is to provide a DC-DC converter and a chip to solve the problems of the complex circuit structure and large implementation difficulty in the switching frequency synchronization of the related technology.

[0005] To achieve the above purpose, a first aspect of the present disclosure provides a DC-DC converter, including a pulse width modulation signal generator, a lower transistor conduction time generation circuit, an external frequency generation circuit, a unity gain negative feedback circuit, a first comparator, a control circuit, an upper transistor, an inductor, and a lower transistor;

[0006] The pulse width modulation signal generator is configured to output a PWM signal to the lower transistor conduction time generation circuit and the control circuit respectively according to the inductor current sampling voltage and the output voltage of the DC-DC converter;

[0007] The lower transistor conduction time generation circuit is configured to output a ramp voltage to the non-inverting input terminal of the first comparator according to the PWM signal and the lower transistor conduction time end signal output by the first comparator;

[0008] The external frequency generation circuit is configured to detect whether the input external clock signal meets the frequency synchronization requirement, generate a frequency synchronization disable signal, invert the frequency synchronization disable signal and output a frequency synchronization enable signal to the unity gain negative feedback circuit, and output a triangular wave voltage to the unity gain negative feedback circuit according to the external clock signal, the frequency synchronization disable signal, and the lower transistor conduction time end signal output by the first comparator;

[0009] The unity gain negative feedback circuit is configured to output a reference voltage to the inverting input terminal of the first comparator according to the triangular wave voltage output by the external frequency generation circuit when the frequency synchronization enable signal is at a high level;

[0010] The non-inverting input terminal of the first comparator is connected to the ramp voltage output by the lower transistor conduction time generating circuit, and the inverting input terminal of the first comparator is connected to the reference voltage output by the unity-gain negative feedback circuit. The first comparator is configured to output a lower transistor conduction time end signal to the control circuit, the lower transistor conduction time generating circuit, and the external frequency generating circuit respectively;

[0011] The control circuit is configured to output a high-side drive signal to the upper transistor and a low-side drive signal to the lower transistor according to the PWM signal and the lower transistor conduction time end signal output by the first comparator, and control the switching of the upper transistor and the lower transistor;

[0012] The control electrode of the upper transistor is connected to the high-side drive signal output by the control circuit. The first pole of the upper transistor is respectively coupled to the first end of the inductor and the first pole of the lower transistor. The second end of the inductor is connected to the input voltage, and the inductor current sampling voltage is sampled from the second pole of the upper transistor;

[0013] The control electrode of the lower transistor is connected to the low-side drive signal output by the control circuit, and the second pole of the lower transistor is grounded.

[0014] Optionally, the pulse width modulation signal generator includes an output circuit, an error amplification circuit, and a second comparator;

[0015] The output circuit is configured to generate the output voltage and the feedback voltage of the DC-DC converter, and output the feedback voltage to the error amplification circuit;

[0016] The error amplification circuit is configured to amplify the error between the feedback voltage and the reference voltage, and output a comparison voltage to the non-inverting input terminal of the second comparator;

[0017] The inverting input terminal of the second comparator is connected to the inductor current sampling voltage. The second comparator is configured to output a PWM signal to the lower transistor conduction time generating circuit and the control circuit respectively through the output terminal.

[0018] Optionally, the output circuit includes a first feedback resistor, a second feedback resistor, an output capacitor, and a load;

[0019] The first end of the first feedback resistor is respectively coupled to the second pole of the upper transistor, the first end of the output capacitor, and the first end of the load. The second end of the first feedback resistor is coupled to the first end of the second feedback resistor, and the second end of the second feedback resistor is grounded;

[0020] The second ends of the output capacitor and the load are respectively grounded.

[0021] Optionally, the error amplification circuit includes an error amplifier, a first resistor, and a first capacitor;

[0022] The non-inverting input terminal of the error amplifier is connected to the reference voltage, the inverting input terminal of the error amplifier is connected to the feedback voltage, and the output terminal of the error amplifier is respectively coupled to the non-inverting input terminal of the second comparator and the first end of the first resistor. The error amplifier is configured to output a comparison voltage to the non-inverting input terminal of the second comparator;

[0023] The second end of the first resistor is coupled to the first end of the first capacitor, and the second end of the first capacitor is grounded.

[0024] Optionally, the lower transistor conduction time generation circuit includes a first RS flip-flop, a first switch, a first current source, and a second capacitor;

[0025] The reset terminal of the first RS flip-flop is connected to the PWM signal, the set terminal of the first RS flip-flop is connected to the lower transistor conduction time end signal output by the first comparator. The first RS flip-flop is configured to control the first switch to be turned off or on according to the PWM signal and the lower transistor conduction time end signal. When the PWM signal is at a high level, the first switch is controlled to be turned off. When the lower transistor conduction time end signal is at a high level, the first switch is controlled to be turned on;

[0026] The first current source is respectively coupled to the non-inverting input terminal of the first comparator, the first end of the first switch, and the first end of the second capacitor. The first current source is configured to output a ramp voltage to the non-inverting input terminal of the first comparator and charge the second capacitor when the first switch is in the off state;

[0027] The second end of the second capacitor is respectively coupled to the second end of the first switch and the ground terminal.

[0028] Optionally, the external frequency generation circuit includes an external clock detection circuit, an OR gate, a first inverter, a second RS flip-flop, a second current source, a third current source, a second switch, a third switch, a second resistor, and a third capacitor;

[0029] The external clock detection circuit is configured to detect whether the input external clock signal contains m consecutive pulses to determine whether the external clock signal meets the frequency synchronization requirement, and output a frequency synchronization disable signal to the first input terminal of the OR gate and the input terminal of the first inverter according to the detection result, and control the third switch to be turned off or on by using the frequency synchronization disable signal, where m≥2;

[0030] The output terminal of the first inverter outputs a frequency synchronization enable signal to the unity gain negative feedback circuit;

[0031] The second input terminal of the OR gate is connected to the lower transistor conduction time end signal output by the first comparator, and the output terminal of the OR gate is coupled to the reset terminal of the second RS flip-flop;

[0032] The set terminal of the second RS flip-flop is connected to an external clock signal. The second RS flip-flop is configured to control the second switch to be turned off or on. When the second RS flip-flop outputs a low level, the second switch is turned off. When the second RS flip-flop outputs a high level, the second switch is turned on;

[0033] The second current source is respectively coupled to the first terminal of the second switch, the first terminal of the third switch, the first terminal of the third capacitor, and the unity-gain negative feedback circuit. The second current source is configured to charge the third capacitor;

[0034] The second terminal of the third switch is coupled to the first terminal of the second resistor;

[0035] The first terminal of the third current source is coupled to the second terminal of the second switch. The second terminal of the third current source is respectively coupled to the second terminal of the second resistor, the second terminal of the third capacitor, and the ground terminal. The third current source is configured to discharge the third capacitor when the second switch is in the closed state. Among them, the discharge current of the third current source to the third capacitor is greater than the charging current of the second current source to the third capacitor.

[0036] Further, when it is detected that the input external clock signal does not contain continuous m pulses, the external clock signal does not meet the frequency synchronization requirement, and the frequency synchronization disable signal is at a high level, and the third switch is turned on;

[0037] When it is detected that the input external clock signal contains continuous m pulses, the external clock signal meets the frequency synchronization requirement, and the frequency synchronization disable signal is at a low level, and the third switch is turned off.

[0038] Optionally, the external clock detection circuit includes m D flip-flops and a second inverter;

[0039] The m D flip-flops are configured to detect whether the input external clock signal contains continuous m pulses;

[0040] Among the m D flip-flops, the clock control terminals of each D flip-flop are all input with the external clock signal. The signal input terminal of the first D flip-flop is connected to a signal that is always at a high level. The output terminal of the previous D flip-flop is coupled to the signal input terminal of the next D flip-flop. The output terminal of the mth D flip-flop is coupled to the input terminal of the second inverter;

[0041] The output terminal of the second inverter outputs the frequency synchronization disable signal.

[0042] Optionally, the unity-gain negative feedback circuit includes a fourth current source, a third resistor, a voltage-controlled current source, and a fourth switch;

[0043] The fourth current source is respectively coupled to the inverting input terminal of the first comparator, the first terminal of the third resistor, the inverting input terminal of the voltage-controlled current source, and the first terminal of the fourth switch;

[0044] The non-inverting input terminal of the voltage-controlled current source is respectively coupled to the second current source and the first end of the third capacitor, and the output terminal of the voltage-controlled current source is coupled to the second end of the fourth switch;

[0045] The frequency synchronization enable signal output by the first inverter controls the fourth switch to be turned off or on;

[0046] The second end of the third resistor is grounded.

[0047] The second aspect of the present disclosure provides a chip, including the DC-DC converter according to any one of the above first aspects.

[0048] In the DC-DC converter provided by the embodiment of the present disclosure, it includes a pulse width modulation signal generator, a lower transistor conduction time generation circuit, an external frequency generation circuit, a unity gain negative feedback circuit, a first comparator, a control circuit, an upper transistor, an inductor, and a lower transistor; the external frequency generation circuit detects whether the input external clock signal meets the frequency synchronization requirement, generates a frequency synchronization disable signal, inverts the frequency synchronization disable signal and outputs a frequency synchronization enable signal to the unity gain negative feedback circuit, and outputs a triangular wave voltage to the unity gain negative feedback circuit according to the external clock signal, the frequency synchronization disable signal, and the lower transistor conduction time end signal output by the first comparator. The unity gain negative feedback circuit outputs a reference voltage to the inverting input terminal of the first comparator according to the triangular wave voltage and the frequency synchronization enable signal. When the frequency synchronization enable signal is at a high level, the frequency of the reference voltage is synchronized with the triangular wave voltage; the present disclosure combines the external frequency generation circuit and the unity gain negative feedback circuit, can realize switch frequency synchronization, has a simple circuit structure, saves chip area, reduces the difficulty of switch frequency synchronization, does not require a phase-locked loop circuit to perform switch frequency synchronization, and solves the problems of complex circuit structure and large implementation difficulty in switch frequency synchronization in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the related art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0050] Figure 1 It is a schematic diagram of a switching frequency generation circuit of an ACOT-controlled boost converter in the related art;

[0051] Figure 2 It is an exemplary circuit block diagram of the DC-DC converter provided by the first embodiment of the present disclosure;

[0052] Figure 3 Exemplary circuit diagram of the DC-DC converter provided by the second embodiment of the present disclosure;

[0053] Figure 4 Exemplary circuit diagram of the DC-DC converter provided by the embodiment of the present disclosure;

[0054] Figure 5 Exemplary circuit diagram of the external clock detection circuit provided by the embodiment of the present disclosure;

[0055] Figure 6 Exemplary working waveform diagram of the DC-DC converter provided by the embodiment of the present disclosure. Detailed implementation manners

[0056] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts also belong to the scope of protection of the present disclosure.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise clearly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0058] In all embodiments of the present disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetric, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled intermediate terminal of the MOS transistor is referred to as the control electrode, and the remaining two terminals of the MOS transistor are respectively referred to as the first electrode and the second electrode. The transistors adopted in the embodiments of the present disclosure are mainly switching transistors. In addition, for the convenience of unified description, in the context, the base of a bipolar junction transistor (BJT) is referred to as the control electrode, the emitter of the BJT is referred to as the first electrode, and the collector of the BJT is referred to as the second electrode. Additionally, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0059] In the process of the rapid development of electronic technology, DC-DC converters need to have good efficiency and fast transient response under different loads. Boost converters controlled by Adaptive Constant On Time (ACOT for short) are widely used in the industrial field due to their excellent transient response and high light-load efficiency. The ACOT-mode boost converter can adjust the on-time TON according to the input voltage VIN and the output voltage VOUT, so that the switching frequency remains approximately constant. However, in noise-sensitive systems, to strictly fix the switching frequency, an external clock signal is often required to synchronize the switching frequency of the ACOT-mode boost converter.

[0060] In the related technology, the schematic diagram of the switching frequency generation circuit of the ACOT-controlled boost converter is as Figure 1 shown. The working mode of each cycle of the boost converter is as follows: At the beginning of each switching cycle, the high-side switch power transistor (HS) conducts. When the inductor current sampling voltage V SNS is lower than the output voltage COMP of the error amplifier, the comparator CMP1 flips, the PWM signal is at a high level, the Control logic module outputs the LSON signal at a high level, the HSON signal at a low level, the HS transistor turns off, the LS transistor conducts, and the inductor current I IND starts to rise; at the same time, the R terminal of the RS1 flip-flop is at a high level, the RS1 flip-flop is reset, the output Q terminal is at a low level, the switch S1 is turned off, the ramp voltage TON_RAMP rises, and the on-time generator starts timing.

[0061] When the ramp voltage TON_RAMP is greater than the reference voltage TON_REF, the comparator CMP2 issues the signal CLK indicating the end of the on-time of the low-side switch power transistor (LS) TON , and the time difference between the rising edge of the signal CLK TON and the rising edge of the PWM signal turning high is the on-time TON of the low-side switch power transistor. When the signal CLK TON turns high, the S terminal of the RS1 flip-flop is at a high level, the RS1 flip-flop is set, the output Q terminal is at a high level, the switch S1 is closed, the ramp voltage TON_RAMP is reset to a low level, preparing for the timing of the next cycle; at the same time, the Control logic module outputs the HSON signal at a high level, the LSON signal at a low level, the LS transistor turns off, the HS transistor conducts, and the inductor current I IND starts to decrease until the inductor current sampling voltage V SNS is lower than COMP again, the comparator CMP1 flips, the LS transistor conducts, the HS transistor turns off, and a new cycle starts.

[0062] According to the following formula derivation, the on-time TON of the LS transistor can be obtained:

[0063] TON_RAMP = TON_REF

[0064]

[0065] Wherein, k1 is the current coefficient and R is the equivalent resistance;

[0066] For the inductor in the stable operating state, the volt-seconds during the switch-on (current rising section) are numerically equal to the volt-seconds during the switch-off (current falling section). The volt-seconds refer to the product of the voltage across the inductor and the switch operation time, which is the volt-second balance principle. According to the volt-second balance principle, it can be known that:

[0067] TON·VIN = TOFF·(VOUT - VIN)

[0068]

[0069] The period T can be obtained S is

[0070]

[0071] It can be seen that under theoretical conditions, the operating period of the ACOT-controlled boost converter is only related to R1 and C1 in the circuit and is a fixed value. However, in the actual circuit, TON*VIN = TOFF*(VOUT - VIN - I IND *R DSON ), where I IND is the inductor current and R DSON is the on-resistance of the upper switch. Therefore, the operating period of the ACOT-controlled boost converter will change with the load.

[0072] In related technologies, a phase-locked loop (PLL) circuit is usually used to compare the phases of the external clock signal and the internal clock signal to achieve switch frequency synchronization. The phase-locked loop mainly consists of a phase detector, a loop filter, and a voltage-controlled oscillator. By detecting the phase difference between the external clock signal and the internal clock signal and converting it into a voltage signal through the phase detector for output, after filtering by a low-pass filter, it forms the control voltage of the voltage-controlled oscillator to control the frequency of the oscillator output signal, and then feeds back the frequency and phase of the oscillator output signal to the phase detector through the feedback path. However, the ACOT-controlled boost converter does not have a fixed clock signal, and its switch frequency is variable. It adjusts the output voltage by changing the on-time, rather than having a clear and fixed switch frequency for the PLL to synchronize as in some other control modes (such as the control mode based on a fixed-frequency clock). Moreover, using a phase-locked loop circuit for switch frequency synchronization takes a long time to achieve the stability of the system frequency, increasing the design difficulty and cost of the overall system. Therefore, it is difficult to implement and the circuit structure is complex.

[0073] To solve the above problems, an embodiment of the present disclosure provides a DC-DC converter, which can be an ACOT mode boost converter; an exemplary circuit block diagram of the DC-DC converter is as follows Figure 2 shown, including a pulse width modulation signal generator, a lower transistor conduction time generation circuit, an external frequency generation circuit, a unity gain negative feedback circuit, a first comparator CMP1, a control circuit, an upper transistor HS, an inductor L, and a lower transistor LS; the upper transistor HS is the high-side power transistor, and the lower transistor LS is the low-side power transistor;

[0074] The pulse width modulation signal generator is configured to output PWM signals to the lower transistor conduction time generation circuit and the control circuit respectively according to the inductor current sampling voltage and the output voltage of the DC-DC converter;

[0075] The lower transistor conduction time generation circuit is configured to generate a ramp voltage TON_RAMP according to the PWM signal and the lower transistor conduction time end signal CLK output by the first comparator CMP1 TON , and output the ramp voltage TON_RAMP to the non-inverting input terminal of the first comparator CMP1;

[0076] The external frequency generation circuit is configured to detect whether the input external clock signal meets the frequency synchronization requirement, generate a frequency synchronization disable signal SYNC_ONB, invert the frequency synchronization disable signal SYNC_ONB and output a frequency synchronization enable signal SYNC_ON to the unity gain negative feedback circuit, and generate a triangular wave voltage SYNC_RAMP according to the external clock signal SYNC, the frequency synchronization disable signal SYNC_ONB, and the lower transistor conduction time end signal CLK output by the first comparator CMP1 TON , and output the triangular wave voltage SYNC_RAMP to the unity gain negative feedback circuit;

[0077] The unity gain negative feedback circuit is configured to output a reference voltage TON_REF to the inverting input terminal of the first comparator CMP1 according to the triangular wave voltage SYNC_RAMP output by the external frequency generation circuit when the frequency synchronization enable signal SYNC_ON is at a high level; when the frequency synchronization enable signal SYNC_ON is at a high level, the reference voltage TON_REF changes following the change of the triangular wave voltage SYNC_RAMP;

[0078] The non-inverting input terminal of the first comparator CMP1 is connected to the ramp voltage TON_RAMP output by the lower transistor conduction time generation circuit, the inverting input terminal of the first comparator CMP1 is connected to the reference voltage TON_REF output by the unity gain negative feedback circuit, and the first comparator CMP1 is configured to output the lower transistor conduction time end signal CLK to the control circuit, the lower transistor conduction time generation circuit, and the external frequency generation circuit respectively TON ;

[0079] The control circuit is configured to output a high-side drive signal HSON to the high-side transistor HS and a low-side drive signal LSON to the low-side transistor LS according to the PWM signal and the lower transistor conduction time end signal CLK output by the first comparator CMP1 TON , and control the switching of the high-side transistor HS and the low-side transistor LS;

[0080] The control electrode of the high-side transistor HS is connected to the high-side drive signal HSON output by the control circuit. The first pole of the high-side transistor HS is respectively coupled to the first end of the inductor L and the first pole of the low-side transistor LS. The second end of the inductor L is connected to the input voltage, and the inductor current sampling voltage V is sampled from the second pole of the high-side transistor HS SNS ;

[0081] The control electrode of the low-side transistor LS is connected to the low-side drive signal LSON output by the control circuit, and the second pole of the low-side transistor LS is grounded.

[0082] The present disclosure generates a triangular wave voltage SYNC_RAMP by controlling the lower transistor conduction time end signal CLK TON and the external clock signal SYNC, and feeds back the triangular wave voltage SYNC_RAMP to the reference voltage TON_REF of the lower transistor conduction time generation circuit, thereby adjusting the length of the lower transistor conduction time TON and the time when the lower transistor conduction time end signal CLK is generated in the next cycle. After several cycles of feedback adjustment, the switching frequency of the DC-DC converter is synchronized with the frequency of the external clock signal SYNC. TON The present disclosure can also adjust the phase shift between the lower transistor conduction time end signal CLK of the DC-DC converter in each cycle and the rising edge of the external clock signal SYNC after the switching frequency is synchronized by controlling the rising and falling slopes of the triangular wave voltage SYNC_RAMP.

[0083] Moreover, the present disclosure does not require the use of a PLL circuit, which reduces the difficulty of switching frequency synchronization, has a simple circuit structure, saves chip area, saves system cost, and at the same time, the phase shift is controllable after the switching frequency is synchronized, and the switching frequency synchronization speed is fast, solving the problems of complex circuit structure and large implementation difficulty in switching frequency synchronization in the related art. TON with the rising edge of the external clock signal SYNC.

[0084] And, the present disclosure does not require the use of a PLL circuit, which reduces the difficulty of switching frequency synchronization, has a simple circuit structure, saves chip area, saves system cost, and at the same time, the phase shift is controllable after the switching frequency is synchronized, and the switching frequency synchronization speed is fast, solving the problems of complex circuit structure and large implementation difficulty in switching frequency synchronization in the related art.

[0085] In an optional implementation manner of the present disclosure, as Figure 3 shown, the pulse width modulation signal generator includes an output circuit, an error amplification circuit, and a second comparator CMP2;

[0086] The output circuit is configured to generate the output voltage VOUT and the feedback voltage FB of the DC-DC converter, and output the feedback voltage FB to the error amplification circuit;

[0087] The error amplification circuit is configured to amplify the error between the feedback voltage and the reference voltage, and output a comparison voltage COMP to the non-inverting input terminal of the second comparator CMP2;

[0088] The inverting input terminal of the second comparator CMP2 is connected to the inductor current sampling voltage V SNS , and the second comparator CMP2 is configured to output a PWM signal to the lower transistor conduction time generation circuit and the control circuit through its output terminal respectively.

[0089] In an alternative embodiment of the present disclosure, as Figure 4 shown, the output circuit includes a first feedback resistor Rf1, a second feedback resistor Rf2, an output capacitor Cout, and a load R L ;

[0090] Wherein, the first end of the first feedback resistor Rf1 is respectively coupled to the second pole of the upper transistor HS, the first end of the output capacitor Cout, and the first end of the load R L , the second end of the first feedback resistor Rf1 is coupled to the first end of the second feedback resistor Rf2, and the second end of the second feedback resistor Rf2 is grounded;

[0091] The second end of the output capacitor Cout and the second end of the load R L are grounded.

[0092] The circuit schematic diagram of the switching frequency synchronization circuit provided by the embodiments of the present disclosure is as Figure 4 shown, wherein the error amplification circuit includes an error amplifier AMP, a first resistor R1, and a first capacitor C1;

[0093] The non-inverting input terminal of the error amplifier AMP is connected to the reference voltage VREF, the inverting input terminal of the error amplifier AMP is connected to the feedback voltage FB, the output terminal of the error amplifier AMP is respectively coupled to the non-inverting input terminal of the second comparator CMP2 and the first end of the first resistor R1, and the error amplifier AMP is configured to output a comparison voltage COMP to the non-inverting input terminal of the second comparator CMP2;

[0094] The second end of the first resistor R1 is coupled to the first end of the first capacitor C1, and the second end of the first capacitor C1 is grounded.

[0095] Figure 4 In, the lower transistor conduction time generation circuit includes a first RS flip-flop RS1, a first switch S1, a first current source I1, and a second capacitor C2;

[0096] The reset terminal R of the first RS flip-flop RS1 is connected to the PWM signal output by the second comparator CMP2, and the set terminal S of the first RS flip-flop RS1 is connected to the end-of-conduction time signal CLK of the lower switch output by the first comparator CMP1. TON , the first RS flip-flop RS1 is configured to, according to the PWM signal and the end-of-conduction time signal CLK of the lower switch TON , control the first switch S1 to be turned off or on. When the PWM signal is at a high level, control the first switch S1 to be turned off. When the end-of-conduction time signal CLK of the lower switch TON is at a high level, control the first switch S1 to be turned on;

[0097] The first current source I1 is respectively coupled to the non-inverting input terminal of the first comparator CMP1, the first terminal of the first switch S1, and the first terminal of the second capacitor C2. The first current source I1 is configured to output a ramp voltage TON_RAMP to the non-inverting input terminal of the first comparator CMP1 and charge the second capacitor C2 when the first switch S1 is in an off state;

[0098] The second terminal of the second capacitor C2 is respectively coupled to the second terminal of the first switch S1 and the ground terminal.

[0099] Figure 4 In

[0099] , the external frequency generation circuit includes an external clock detection circuit, an OR gate, a first inverter, a second RS flip-flop RS2, a second current source I2, a third current source I3, a second switch S2, a third switch S3, a second resistor R2, and a third capacitor C3;

[0100] The external clock detection circuit is configured to detect whether the input external clock signal SYNC includes m consecutive pulses to determine whether the external clock signal SYNC meets the frequency synchronization requirement, and respectively output a frequency synchronization disable signal to the first input terminal of the OR gate and the input terminal of the first inverter according to the detection result, and use the frequency synchronization disable signal to control the third switch S3 to be turned off or on, where m≥2; the external clock detection circuit can be a counter. After detecting m valid rising edges of the external clock signal SYNC, it is determined that the external clock signal SYNC meets the frequency synchronization requirement to avoid the input signal being an irrelevant signal other than the external clock signal SYNC. At this time, the output frequency synchronization disable signal SYNC_ONB is at a low level;

[0101] The output terminal of the first inverter outputs a frequency synchronization enable signal SYNC_ON to the unity-gain negative feedback circuit;

[0102] The second input terminal of the OR gate is connected to the end-of-conduction time signal CLK of the lower switch output by the first comparator CMP1 TON , and the output terminal of the OR gate is coupled to the reset terminal of the second RS flip-flop RS2;

[0103] The set terminal of the second RS flip-flop RS2 is connected to an external clock signal SYNC. The second RS flip-flop RS2 is configured to control the second switch S2 to be turned off or on. When the second RS flip-flop RS2 outputs a low level, the second switch S2 is turned off. When the second RS flip-flop RS2 outputs a high level, the second switch S2 is turned on;

[0104] The second current source I2 is respectively coupled to the first terminal of the second switch S2, the first terminal of the third switch S3, the first terminal of the third capacitor C3, and the unity-gain negative feedback circuit. The second current source I2 is configured to charge the third capacitor C3;

[0105] The second terminal of the third switch S3 is coupled to the first terminal of the second resistor R2;

[0106] The first terminal of the third current source I3 is coupled to the second terminal of the second switch S2. The second terminal of the third current source I3 is respectively coupled to the second terminal of the second resistor R2, the second terminal of the third capacitor C3, and the ground terminal. The third current source I3 is configured to discharge the third capacitor C3 when the second switch S2 is in the on state. Among them, the discharge current of the third capacitor C3 by the third current source I3 is greater than the charging current of the third capacitor C3 by the second current source I2.

[0107] In an optional embodiment of the present disclosure, when it is detected that the input external clock signal SYNC does not contain consecutive m pulses, the external clock signal SYNC does not meet the frequency synchronization requirement, the frequency synchronization disable signal is at a high level, and the third switch S3 is turned on;

[0108] When it is detected that the input external clock signal SYNC contains consecutive m pulses, the external clock signal SYNC meets the frequency synchronization requirement, the frequency synchronization disable signal is at a low level, and the third switch S3 is turned off.

[0109] In an optional embodiment of the present disclosure, the external clock detection circuit includes m D flip-flops and a second inverter;

[0110] The m D flip-flops are configured to detect whether the input external clock signal SYNC contains consecutive m pulses;

[0111] Among the m D flip-flops, the clock control terminals of each D flip-flop are all input with the external clock signal SYNC. The signal input terminal of the first D flip-flop is connected to a signal that is constantly at a high level. The output terminal of the previous D flip-flop is coupled to the signal input terminal of the next D flip-flop. The output terminal of the mth D flip-flop is coupled to the input terminal of the second inverter;

[0112] The output terminal of the second inverter outputs the frequency synchronization disable signal.

[0113] When m = 4, the schematic diagram of the external clock detection circuit is as Figure 5 shown, including four D flip-flops and a second inverter, that is, including a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop and a second inverter;

[0114] The clock control terminal of the first D flip-flop inputs an external clock signal SYNC, the signal input terminal of the first D flip-flop accesses a signal that is constantly at a high level (ONE), and the Q output terminal of the first D flip-flop is coupled to the signal input terminal of the second D flip-flop;

[0115] The clock control terminal of the second D flip-flop inputs an external clock signal SYNC, and the Q output terminal of the second D flip-flop is coupled to the signal input terminal of the third D flip-flop;

[0116] The clock control terminal of the third D flip-flop inputs an external clock signal SYNC, and the Q output terminal of the third D flip-flop is coupled to the signal input terminal of the fourth D flip-flop;

[0117] The clock control terminal of the fourth D flip-flop inputs an external clock signal SYNC, and the Q output terminal of the fourth D flip-flop is coupled to the input terminal of the second inverter; By using four D flip-flops to detect whether the input external clock signal SYNC contains four consecutive pulses, if it contains, the frequency synchronization requirement is met, if not, the frequency synchronization requirement is not met, avoiding interference from rough, noisy and other irrelevant signals;

[0118] The output terminal of the second inverter outputs a frequency synchronization disable signal SYNC_ONB.

[0119] Figure 4 In, the unity-gain negative feedback circuit includes a fourth current source I4, a third resistor R3, a voltage-controlled current source gm and a fourth switch S4;

[0120] The fourth current source I4 is respectively coupled to the inverting input terminal of the first comparator CMP1, the first terminal of the third resistor R3, the inverting input terminal of the voltage-controlled current source gm and the first terminal of the fourth switch S4;

[0121] The non-inverting input terminal of the voltage-controlled current source gm is respectively coupled to the second current source I2 and the first terminal of the third capacitor C3, and the output terminal of the voltage-controlled current source gm is coupled to the second terminal of the fourth switch S4;

[0122] The frequency synchronization enable signal SYNC_ON output by the first inverter controls the fourth switch S4 to be turned off or on;

[0123] The second terminal of the third resistor R3 is grounded.

[0124] Next, the working principle of the switching frequency synchronization circuit provided by the embodiments of the present disclosure will be described.

[0125] The present disclosure generates a triangular wave voltage SYNC_RAMP by controlling the end signal CLK of the lower transistor conduction time TON and the external clock signal SYNC, and feeds back the triangular wave voltage SYNC_RAMP to the reference voltage TON_REF of the lower transistor conduction time generation circuit, so as to adjust the length of the lower transistor conduction time TON and the end signal CLK of the lower transistor conduction time in the next cycle TON The generated time. After debugging for several cycles, the switching frequency of the DC-DC converter is synchronized with the frequency of the external clock signal.

[0126] When synchronizing the frequency of the external clock signal, first, the external clock detection circuit determines whether the external clock signal SYNC meets the requirements of the synchronization frequency; when the frequency synchronization requirement is not met, the frequency synchronization disable signal SYNC_ONB is at a high level, the frequency synchronization enable signal SYNC_ON is at a low level, the third switch S3 is closed, the fourth switch S4 is opened, the reset terminal R of the second RS flip-flop RS2 is at a high level, the Q terminal outputs a low level, and the second switch S2 is opened. The magnitude relationship between the second current source I2 and the fourth current source I4 is set as current I4 = I2, and the resistance value relationship between the second resistor R2 and the third resistor R3 is set as R2 = R3 = R, so that the initial value of the triangular wave voltage SYNC_RAMP is approximately equal to the reference voltage TON_REF, reducing the change range of the triangular wave voltage SYNC_RAMP before and after the switching frequency synchronization, enabling the reference voltage TON_REF to quickly follow the change of the triangular wave voltage SYNC_RAMP after the switching frequency synchronization; after meeting the frequency synchronization requirement, the frequency synchronization enable signal SYNC_ON is at a high level, and the conduction time generation circuit starts to synchronize with the external clock signal SYNC.

[0127] When the external clock detection circuit for synchronization is enabled, the frequency synchronization disable signal SYNC_ONB is at a low level, the frequency synchronization enable signal SYNC_ON is at a high level, the fourth switch S4 is closed, the third switch S3 is opened, the third resistor R3, the fourth current source I4, and the voltage-controlled current source gm in the switching frequency synchronization circuit form a unity-gain negative feedback circuit, enabling the reference voltage TON_REF of the lower transistor conduction time generation circuit to change with the change of the triangular wave voltage SYNC_RAMP, thereby adjusting the length of the lower transistor conduction time TON in each cycle and the end signal CLK of the lower transistor conduction time in the next cycle TON The generated time. After debugging for several cycles, the switching frequency of the DC-DC converter is synchronized with the frequency of the external clock signal SYNC.

[0128] The working waveform diagram of the switching frequency synchronization circuit provided by the present disclosure is as Figure 6As shown, SYNC is an external clock signal; SYNC_ON is a frequency synchronization enable signal; CLK TON is the end signal of the lower transistor conduction time; IL is the inductor current; TON_REF is the reference voltage; TON_RAMP is the ramp voltage of the conduction time generation circuit. The process of frequency synchronization is as follows: After the chip internally receives the rising edges of the external clock signal SYNC being valid 4 consecutive times, at the 5th rising edge of the external clock signal SYNC, the frequency synchronization enable signal SYNC_ON goes high, the fourth switch S4 closes, and the third switch S3 opens. At this time, the external clock signal SYNC is at a high level, and the Q output terminal of the second RS flip-flop RS2 outputs a high level, and the second switch S2 closes. The current magnitude relationship between the third current source I3 and the second current source I2 is designed as I3 = k * I2 (k > 1, for convenience of description, k = 2 in the working waveform diagram). The third capacitor C3 discharges, and the triangular wave voltage SYNC_RAMP drops. Under the control of the unity-gain negative feedback circuit, SYNC_RAMP ≈ TON_REF, and the reference voltage TON_REF also slowly drops, with a drop slope of (k - 1) * I2 / C3. After the ramp voltage TON_RAMP is greater than the reference voltage TON_REF, the first comparator CMP1 issues the end signal CLK of the lower transistor conduction time TON , the upper transistor conducts, the lower transistor turns off, and the inductor current I IND starts to decrease and enters the next cycle; at the same time, the end signal CLK of the lower transistor conduction time TON signal makes the Q output terminal of the second RS flip-flop RS2 output a low level, the second switch S2 opens, and the second current source I2 charges the third capacitor C3 with a slope of I2 / C3.

[0129] The rise of the reference voltage TON_REF is synchronized with the rising edge of the end signal CLK of the lower transistor conduction time TON , and the drop of the reference voltage TON_REF is synchronized with the rising edge of the external clock signal SYNC. Limited by the frequency synchronization ability, the change range of the reference voltage TON_REF is 0 to 2 * TON_REF0, where TON_REF0 is the reference voltage of the conduction time generation circuit when frequency synchronization does not occur. If the frequency of the end signal CLK of the lower transistor conduction time TON is higher than the frequency of the external clock signal SYNC, then compared with when frequency synchronization does not occur, the reference voltage TON_REF is on the high side during frequency synchronization, thereby increasing the conduction time TON and reducing the frequency of the end signal CLK of the lower transistor conduction time TON ; if the frequency of the end signal CLK of the lower transistor conduction time TON is lower than the frequency of the external clock signal SYNC, then compared with when frequency synchronization does not occur, the reference voltage TON_REF is on the low side during frequency synchronization, thereby reducing the conduction time TON and increasing the frequency of the end signal CLK of the lower transistor conduction timeTON The frequency. By converting the change in frequency between the external clock signal SYNC and the end signal CLK of the lower transistor conduction time into a change in the reference voltage TON_REF, the length of the conduction time TON and the generation time of the next end signal CLK of the lower transistor conduction time are adjusted. After several cycles of debugging, the switching frequency of the DC-DC converter is synchronized with the frequency of the external clock signal. TON The switching frequency synchronization circuit provided by the present disclosure can also adjust the phase difference between the rising edge of the end signal CLK of the lower transistor conduction time and the rising edge of the external clock signal SYNC in each cycle after frequency synchronization by controlling the rising and falling slopes of the triangular wave voltage SYNC_RAMP. As shown in the working waveform diagram in TON When I3 = 2 * I2, the phase difference between the end moment of the lower transistor conduction and the rising edge of the external clock signal is 180°.

[0130] The present disclosure also provides a chip, which includes a DC-DC converter according to the embodiments of the present disclosure. TON From the above description, it can be seen that the present disclosure achieves the following technical effects: Figure 6 When I3 = 2 * I2, the phase difference between the end moment of the lower transistor conduction and the rising edge of the external clock signal is 180°.

[0131] The present disclosure generates a triangular wave voltage SYNC_RAMP by controlling the end signal CLK of the lower transistor conduction time and the external clock signal SYNC, and feeds back the triangular wave voltage SYNC_RAMP to the reference voltage TON_REF of the lower transistor conduction time generation circuit, thereby adjusting the length of the lower transistor conduction time TON and the generation time of the end signal CLK of the lower transistor conduction time in the next cycle. After several cycles of feedback adjustment, the switching frequency of the DC-DC converter is synchronized with the frequency of the external clock signal SYNC.

[0132] From the above description, it can be seen that the present disclosure achieves the following technical effects:

[0133] The present disclosure generates a triangular wave voltage SYNC_RAMP by controlling the end signal CLK of the lower transistor conduction time and the external clock signal SYNC, and feeds back the triangular wave voltage SYNC_RAMP to the reference voltage TON_REF of the lower transistor conduction time generation circuit, thereby adjusting the length of the lower transistor conduction time TON and the generation time of the end signal CLK of the lower transistor conduction time in the next cycle. After several cycles of feedback adjustment, the switching frequency of the DC-DC converter is synchronized with the frequency of the external clock signal SYNC. TON The present disclosure generates a triangular wave voltage SYNC_RAMP by controlling the end signal CLK of the lower transistor conduction time and the external clock signal SYNC, and feeds back the triangular wave voltage SYNC_RAMP to the reference voltage TON_REF of the lower transistor conduction time generation circuit, thereby adjusting the length of the lower transistor conduction time TON and the generation time of the end signal CLK of the lower transistor conduction time in the next cycle. After several cycles of feedback adjustment, the switching frequency of the DC-DC converter is synchronized with the frequency of the external clock signal SYNC. TON The present disclosure generates a triangular wave voltage SYNC_RAMP by controlling the end signal CLK of the lower transistor conduction time and the external clock signal SYNC, and feeds back the triangular wave voltage SYNC_RAMP to the reference voltage TON_REF of the lower transistor conduction time generation circuit, thereby adjusting the length of the lower transistor conduction time TON and the generation time of the end signal CLK of the lower transistor conduction time in the next cycle. After several cycles of feedback adjustment, the switching frequency of the DC-DC converter is synchronized with the frequency of the external clock signal SYNC.

[0134] The present disclosure can also adjust the phase shift between the end signal CLK of the lower transistor conduction time of the DC-DC converter and the rising edge of the external clock signal SYNC in each cycle after switching frequency synchronization by controlling the rising and falling slopes of the triangular wave voltage SYNC_RAMP. TON The present disclosure can also adjust the phase shift between the end signal CLK of the lower transistor conduction time of the DC-DC converter and the rising edge of the external clock signal SYNC in each cycle after switching frequency synchronization by controlling the rising and falling slopes of the triangular wave voltage SYNC_RAMP.

[0135] Moreover, the present disclosure does not require the use of a PLL circuit, reducing the difficulty of switching frequency synchronization, with a simple circuit structure, saving chip area and system cost. At the same time, the phase shift is controllable after switching frequency synchronization, and the switching frequency synchronization speed is fast, solving the problems of complex circuit structure and large implementation difficulty in switching frequency synchronization in the related art.

[0136] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur in a different order than that noted in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0137] Unless the context clearly dictates otherwise herein, the singular forms of words used in this specification and the appended claims also include the plural, and vice versa. Thus, when reference is made to the singular, the corresponding plural is generally included. Similarly, the terms "comprising" and "including" are to be construed as inclusive rather than exclusive. Likewise, the term "or" should be interpreted as inclusive, unless expressly prohibited by the context of this disclosure. Where the term "exemplary" is used herein, particularly when it is placed after a list of terms, the "exemplary" is merely illustrative and explanatory and should not be considered exclusive or extensive.

[0138] Further aspects and scope become apparent from the description provided herein. It should be understood that the various aspects of the present disclosure may be implemented alone or in combination with one or more other aspects. It should also be understood that the description herein and the specific embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0139] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A DC-DC converter, characterized in that: It includes a pulse width modulation signal generator, a lower tube conduction time generating circuit, an external frequency generating circuit, a unit gain negative feedback circuit, a first comparator, a control circuit, an upper tube, an inductor and a lower tube; The pulse width modulation signal generator is configured to output PWM signals to the lower tube conduction time generating circuit and the control circuit respectively according to the inductor current sampling voltage and the output voltage of the DC-DC converter; The lower tube conduction time generating circuit is configured to output a ramp voltage to the non-inverting input terminal of the first comparator according to the PWM signal and the lower tube conduction time end signal output by the first comparator; The external frequency generating circuit is configured to detect whether the input external clock signal meets the frequency synchronization requirement, generate a frequency synchronization disable signal, invert the frequency synchronization disable signal and output a frequency synchronization enable signal to the unit gain negative feedback circuit, and output a triangular wave voltage to the unit gain negative feedback circuit according to the external clock signal, the frequency synchronization disable signal and the lower tube conduction time end signal output by the first comparator; The unit gain negative feedback circuit is configured to output a reference voltage to the inverting input terminal of the first comparator according to the triangular wave voltage output by the external frequency generating circuit when the frequency synchronization enable signal is at a high level; The non-inverting input terminal of the first comparator is connected to the ramp voltage, and the inverting input terminal is connected to the reference voltage. The first comparator is configured to output a lower tube conduction time end signal to the control circuit, the lower tube conduction time generating circuit and the external frequency generating circuit respectively; The control circuit is configured to output a high-side drive signal to the upper tube and a low-side drive signal to the lower tube according to the PWM signal and the lower tube conduction time end signal, so as to control the switches of the upper tube and the lower tube; The control electrode of the upper tube is connected to the high-side driving signal, the first electrode is respectively coupled to the first end of the inductor and the first electrode of the lower tube, the second end of the inductor is connected to the input voltage, and the inductor current sampling voltage is obtained by sampling from the second electrode of the upper tube; The control electrode of the lower tube is connected to the low-side driving signal, and the second electrode is grounded.

2. The DC-DC converter according to claim 1, characterized in that: The pulse width modulation signal generator includes an output circuit, an error amplification circuit and a second comparator; The output circuit is configured to generate an output voltage and a feedback voltage of the DC-DC converter, and output the feedback voltage to the error amplifier circuit; The error amplifier circuit is configured to amplify the error between the feedback voltage and the reference voltage, and output a comparison voltage to the non-inverting input terminal of the second comparator; The inverting input terminal of the second comparator is connected to the inductor current sampling voltage, and the second comparator is configured to output PWM signals to the lower tube conduction time generating circuit and the control circuit through the output terminal.

3. The DC-DC converter according to claim 2, characterized in that: The output circuit includes a first feedback resistor, a second feedback resistor, an output capacitor and a load; The first end of the first feedback resistor is respectively coupled to the second electrode of the upper tube, the first end of the output capacitor and the first end of the load, the second end of the first feedback resistor is coupled to the first end of the second feedback resistor, and the second end of the second feedback resistor is grounded; A second terminal of the output capacitor and a second terminal of the load are grounded respectively.

4. The DC-DC converter according to claim 2, characterized in that: The error amplification circuit includes an error amplifier, a first resistor and a first capacitor; The non-inverting input terminal of the error amplifier is connected to the reference voltage, the inverting input terminal of the error amplifier is connected to the feedback voltage, the output terminal of the error amplifier is respectively coupled to the non-inverting input terminal of the second comparator and the first end of the first resistor, and the error amplifier is configured to output the comparison voltage to the non-inverting input terminal of the second comparator; A second end of the first resistor is coupled to a first end of the first capacitor, and a second end of the first capacitor is grounded.

5. The DC-DC converter according to claim 1, characterized in that: The lower tube conduction time generating circuit comprises a first RS trigger, a first switch, a first current source and a second capacitor; The reset terminal of the first RS trigger is connected to the PWM signal, and the set terminal of the first RS trigger is connected to the lower tube conduction time end signal output by the first comparator. The first RS trigger is configured to control the first switch to be opened or closed according to the PWM signal and the lower tube conduction time end signal. When the PWM signal is at a high level, the first switch is controlled to be opened, and when the lower tube conduction time end signal is at a high level, the first switch is controlled to be closed; The first current source is respectively coupled to the non-inverting input terminal of the first comparator, the first terminal of the first switch and the first terminal of the second capacitor, and the first current source is configured to output the ramp voltage to the non-inverting input terminal of the first comparator and charge the second capacitor when the first switch is in an off state; The second terminal of the second capacitor is respectively coupled to the second terminal of the first switch and the ground terminal.

6. The DC-DC converter according to claim 1, characterized in that: The external frequency generating circuit includes an external clock detection circuit, an OR gate, a first inverter, a second RS trigger, a second current source, a third current source, a second switch, a third switch, a second resistor and a third capacitor; The external clock detection circuit is configured to detect whether the input external clock signal contains m consecutive pulses to determine whether the external clock signal meets the frequency synchronization requirement, and output a frequency synchronization disable signal to the first input terminal of the OR gate and the input terminal of the first inverter respectively according to the detection result, and use the frequency synchronization disable signal to control the third switch to be opened or closed, wherein m≥2; The output terminal of the first inverter outputs a frequency synchronization enable signal to the unit gain negative feedback circuit; The second input terminal of the OR gate is connected to the lower tube conduction time end signal output by the first comparator, and the output terminal of the OR gate is coupled to the reset terminal of the second RS trigger; The set terminal of the second RS flip-flop is connected to the external clock signal, and the second RS flip-flop is configured to control the second switch to be opened or closed. When the second RS flip-flop outputs a low level, the second switch is opened, and when the second RS flip-flop outputs a high level, the second switch is closed; The second current source is respectively coupled to the first end of the second switch, the first end of the third switch, the first end of the third capacitor and the unit gain negative feedback circuit, and the second current source is configured to charge the third capacitor; The second end of the third switch is coupled to the first end of the second resistor; A first end of the third current source is coupled to the second end of the second switch, a second end of the third current source is respectively coupled to the second end of the second resistor, the second end of the third capacitor and the ground, and the third current source is configured to discharge the third capacitor when the second switch is in a closed state, wherein a discharge current of the third current source to the third capacitor is greater than a charging current of the second current source to the third capacitor.

7. The DC-DC converter according to claim 6, characterized in that: When it is detected that the input external clock signal does not contain m consecutive pulses, the external clock signal does not meet the frequency synchronization requirement, the frequency synchronization disable signal is at a high level, and the third switch is closed; When it is detected that the input external clock signal contains m consecutive pulses, the external clock signal meets the frequency synchronization requirement, the frequency synchronization disable signal is at a low level, and the third switch is disconnected.

8. The DC-DC converter according to claim 6, characterized in that: The external clock detection circuit includes m D flip-flops and a second inverter; The m D flip-flops are configured to detect whether the input external clock signal contains m consecutive pulses; Among the m D flip-flops, the clock control terminal of each D flip-flop inputs the external clock signal, the signal input terminal of the first D flip-flop receives a signal at a constant high level, the output terminal of the previous D flip-flop is coupled to the signal input terminal of the next D flip-flop, and the output terminal of the mth D flip-flop is coupled to the input terminal of the second inverter; The output terminal of the second inverter outputs the frequency synchronization disable signal.

9. The DC-DC converter according to claim 6, characterized in that: The unit gain negative feedback circuit includes a fourth current source, a third resistor, a voltage-controlled current source and a fourth switch; The fourth current source is respectively coupled to the inverting input terminal of the first comparator, the first terminal of the third resistor, the inverting input terminal of the voltage-controlled current source and the first terminal of the fourth switch; The non-inverting input terminal of the voltage-controlled current source is coupled to the second current source and the first terminal of the third capacitor respectively, and the output terminal of the voltage-controlled current source is coupled to the second terminal of the fourth switch; The frequency synchronization enable signal output by the first inverter controls the fourth switch to be opened or closed; A second end of the third resistor is grounded.

10. A chip, characterized in that: A DC-DC converter comprising any one of claims 1 to 9.

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