DCDC device and control method

Abstract

The embodiment of the invention discloses a DCDC device and a control method, relates to the technical field of power systems, and is used for solving the problem that an existing device is difficult to meet efficient scenes. The device comprises a main loop topological structure and a control hardware architecture electrically connected with the main loop topological structure, wherein the main loop topological structure comprises a high-voltage side assembly, a low-voltage side assembly, a power switch module and an inductor assembly; the main loop topological structure is used for determining the connection mode of the components based on the switching time sequences of the power switch modules corresponding to different modes so as to realize bidirectional energy transmission of time sequence control between the high-voltage side and the low-voltage side in different modes through six-phase interleaving parallel connection; wherein the mode comprises a BUCK mode and a BOOST mode; and the control hardware architecture is used for receiving the real-time operation state fed back by the main loop topological structure so as to generate a control signal based on the real-time operation state, and feeding back the control signal to the power switch module of the main loop topological structure to form closed-loop control.

Description

Technical Field

[0001] This specification relates to the technical field of power systems, and particularly to a DC-DC device and a control method. Background Art

[0002] With the development of the economy and society, and the continuous development of manufacturing technologies, the current demand for electric energy is increasing. However, with the increasing depletion of traditional energy sources such as coal and oil, finding sustainable new energy sources is a major issue in the current power industry. In fields such as industrial manufacturing, new energy vehicles, and energy storage systems, the demand for efficient and stable electric energy conversion devices is particularly urgent. These application scenarios often require bidirectional energy transfer. For example, in new energy vehicles, when the battery is charging, energy flows from the power grid to the battery, and when the vehicle is driving and the battery discharges to drive the motor, energy flows from the battery to the motor. In this context, the DC-DC converter (DC-DC Converter, abbreviated as DCDC), a power electronic device that can convert direct current into direct current of different voltage levels, has become a key device for realizing efficient electric energy conversion and bidirectional energy transfer, playing an indispensable role in many fields.

[0003] Current traditional bidirectional DCDC devices, such as non-isolated bidirectional DCDC, isolated bidirectional DCDC, and cascaded bidirectional DCDC, all have the ability of bidirectional energy transfer. However, the current non-isolated bidirectional DCDC has a limited voltage regulation range and is only applicable to systems with a narrow voltage regulation range and no special requirements for the input-output electrical relationship, and cannot meet the demand for wide voltage regulation in most industrial and new energy fields. The isolated bidirectional DCDC has many switching devices, resulting in large losses during the energy transfer process, and its structure is complex, increasing the equipment cost and maintenance difficulty, which is not conducive to large-scale application. The cascaded bidirectional DCDC can achieve step-down and step-up on both sides respectively, but the number of switching devices doubles, and the system losses increase significantly, making it difficult to operate efficiently, and also restricting its application in scenarios with higher efficiency requirements. Summary of the Invention

[0004] To solve the above technical problems, one or more embodiments of this specification provide a DC-DC device and a control method.

[0005] One or more embodiments of this specification adopt the following technical solutions:

[0006] One or more embodiments of this specification provide a DC-DC device, the device includes:

[0007] A main circuit topology structure and a control hardware architecture electrically connected to the main circuit topology structure, the main circuit topology structure includes a high-voltage side component, a low-voltage side component, a power switch module, and an inductor component;

[0008] The main circuit topology is used to determine the connection modes of the high-voltage side components, low-voltage side components, power switch modules, and inductance components based on the switching timings of the power switch modules corresponding to different modes, so as to achieve bidirectional energy transfer with timing control between the high-voltage side and the low-voltage side in different modes through six-phase interleaved parallel connection; wherein, the modes include the BUCK mode and the BOOST mode.

[0009] The control hardware architecture is used to receive the real-time operating state fed back by the main circuit topology, generate a control signal based on the real-time operating state, and feed the control signal back to the power switch modules of the main circuit topology to form a closed-loop control.

[0010] Optionally, in one or more embodiments of this specification, the high-voltage side components include: a high-voltage side buffer component, a fuse, a plurality of filter capacitors, and a voltage-sharing resistor, which are used for energy storage filtering and voltage equalization of the high-voltage bus.

[0011] The low-voltage side components include: a low-voltage side filter capacitor, a voltage-sharing resistor, and a buffer component, which are used for energy storage filtering and voltage equalization of the low-voltage bus.

[0012] The power switch module is an IGBT module, which is used to achieve bidirectional energy conversion through phase-shifted 60° timing control in different modes.

[0013] The inductance component includes: six-phase independent inductors, and each phase inductor cooperates with the corresponding IGBT module, which is used to achieve smooth current output and ripple cancellation of the main circuit topology.

[0014] Optionally, in one or more embodiments of this specification, the control hardware architecture includes: a main control board, a sub-control board, a detection board, and a drive board; wherein,

[0015] The detection board is used to collect the real-time operating state of the main circuit topology in real time through sensors, and convert the real-time operating state into a digital signal and transmit it to the sub-control board.

[0016] The sub-control board is used to summarize the data of each component in the control hardware architecture for preliminary filtering and calibration, and upload the processed data to the main control board based on optical fibers.

[0017] The main control board is used to analyze the processed data based on DSP and FPGA to obtain the global control signal of the DCDC device.

[0018] The driving board is used to convert the global control signal output by the main control board into a high-precision driving level, control the switching actions of the power switch module, so as to control the power switch module to achieve six-phase interleaved conduction through a timing control with a 60° phase stagger, and form a closed-loop control.

[0019] Optionally, in one or more embodiments of the present specification, the control hardware architecture further includes: a power supply board and a human-machine interface;

[0020] Among them, the power supply board is used to provide multiple isolated power supplies to ensure the power supply requirements of each component in the DCDC device, and through power distribution technology, dynamically adjust the load to the other five phases in case of a single-phase fault to ensure the continuous operation of the DCDC device;

[0021] The human-machine interface is used to display the real-time operating status of the main circuit topology for timely fault alarm.

[0022] Optionally, in one or more embodiments of the present specification, through six-phase interleaved parallel connection, bidirectional energy transfer of timing control between the high-voltage side and the low-voltage side in different modes is achieved, specifically including:

[0023] If it is determined that the mode is the BUCK mode, based on the six-way PWM driving signals of the control hardware architecture, the phase of each phase driving signal of the power switch module on the high-voltage side is controlled to be staggered by 60° in sequence to form a first periodic conduction sequence;

[0024] Connect the high-voltage side energy to the high-voltage side filter capacitor through the buffer component and the fuse for energy storage and filtering;

[0025] Based on the first periodic conduction sequence, transfer the energy stored and filtered on the high-voltage side to the low-voltage side through the corresponding inductor, and absorb the remaining ripple through the series connection of the low-voltage side electrolytic capacitors and stabilize the output voltage, and equalize the series capacitor voltages through the parallel connection of the voltage equalizing resistors;

[0026] If it is determined that the mode is the BOOST mode, based on the six-way PWM driving signals of the control hardware architecture, the phase of each phase driving signal of the power switch module on the low-voltage side is controlled to be staggered by 60° in sequence to form a second periodic conduction sequence;

[0027] Transfer the low-voltage side energy in the reverse direction through the inductor, so as to feedback the low-voltage side energy to the high-voltage side in sequence based on the second periodic conduction sequence, and absorb the high-voltage bus ripple through the series connection of the high-voltage side electrolytic capacitors and stabilize the voltage, and parallelly connect the voltage equalizing resistors to each capacitor to equalize the series capacitor voltage division.

[0028] One or more embodiments of the present specification provide a control method for a DCDC device, which is applied to any of the above-mentioned DCDC devices, and the method includes:

[0029] The real-time operating state of the main circuit topology is collected in real time by a detection board sensor, so as to convert the real-time operating state into a digital signal and transmit it to the sub-control board;

[0030] The data of each component in the control hardware architecture is summarized by the sub-control board for preliminary filtering and calibration, so as to upload the processed data to the main control board based on an optical fiber;

[0031] Through the main control board, the processed data is analyzed based on DSP and FPGA to obtain the global control signal of the DCDC device;

[0032] The global control signal output by the main control board is converted into a high-precision drive level by a driver to control the switching action of the power switch module, so as to control the power switch module to achieve six-phase interleaved conduction through a timing control with a 60° phase stagger, forming a closed-loop control.

[0033] Optionally, in one or more embodiments of this specification, analyzing the processed data based on DSP and FPGA to obtain the global control signal of the DCDC device specifically includes:

[0034] Determine the mode corresponding to the DCDC device to determine the six-phase independent inductors corresponding to each mode and the IGBT modules corresponding to each phase inductor; wherein, the modes include: BUCK mode and BOOST mode;

[0035] Execute a preset double-loop PI control strategy and determine the allocated power of each phase IGBT module;

[0036] Optimize the allocated power of each phase IGBT module based on a preset genetic algorithm to obtain the global control signal of the DCDC device.

[0037] Optionally, in one or more embodiments of this specification, determining the allocated power of each phase IGBT module based on a preset double-loop PI control strategy specifically includes:

[0038] Determine the total current reference value according to the load demand power and the target voltage corresponding to each mode, so as to perform current sharing for each phase current based on the total current reference value to obtain the current reference value for each phase;

[0039] Calculate the voltage deviation output by the voltage outer loop, so that the PI controller adjusts and generates the current inner loop reference value according to the voltage deviation, and receives the current inner loop reference value in the current inner loop, so as to determine the current deviation according to the current inner loop reference value and the actual current value, so that the PI controller quickly adjusts the duty cycle based on the current deviation to complete the double-loop PI control;

[0040] Determine the total power required for each current mode, and divide the required total power evenly to obtain the allocated power for each phase, so as to determine the current allocation for each phase based on the allocated power for each phase and the given voltage corresponding to each mode.

[0041] Optionally, in one or more embodiments of this specification, optimize the allocated power of each-phase IGBT module based on a preset genetic algorithm to obtain the global control signal of the DCDC device, specifically including:

[0042] Determine the objective function corresponding to minimizing power loss and current imbalance; wherein, the objective function is: wherein, R i is the equivalent resistance of the i-th phase, is the average current of the power unit, and w is the current balance factor;

[0043] Initialize the population parameters of the allocated power to randomly generate initial individuals; wherein, the population parameters include: population size, maximum number of iterations;

[0044] Calculate the fitness value of the initial individual based on the objective function, obtain the current individual according to the fitness value to allocate the selection probability, iterate the genetic operation to obtain the optimal solution, and generate the global control signal corresponding to the optimal solution.

[0045] Optionally, in one or more embodiments of this specification, obtain the current individual according to the fitness value to allocate the selection probability, and iterate the genetic operation to obtain the optimal solution, specifically including:

[0046] Allocate the selection probability to each individual based on the fitness value, and screen the current individual based on the allocated selection probability corresponding to each individual;

[0047] Perform simulated binary crossover on the current individual to generate the current candidate solution;

[0048] Perform Gaussian mutation on the selected individuals in the current candidate set based on a preset mutation formula to obtain the current population, and evaluate each individual in the current population based on the objective function, so as to copy the individual with the best fitness in the previous generation to the next generation;

[0049] Iterate the current population. If it is determined that the fitness value meets the preset target value, stop the iteration to obtain the optimal solution.

[0050] The above at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0051] In the main circuit topology, bidirectional energy transfer between the high-voltage side and the low-voltage side is achieved through six-phase interleaved parallel connection and specific switching timings of power switch modules in different modes. Moreover, the six-phase interleaved parallel topology causes the phase currents to be staggered from each other. After superposition, part of the current ripple is effectively cancelled, and at the same time, the voltage harmonics are also reduced. Also, the interleaved parallel connection method reduces the current stress of each phase power switch module, reduces energy loss, and improves the energy conversion efficiency. The control hardware architecture receives the real-time operating status feedback from the main circuit, forms a closed-loop control, can dynamically adjust the output in a timely manner, and maintains the stability of voltage and current, providing reliable power supply for equipment with high requirements for power supply stability. Description of the Drawings

[0052] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in this specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. In the drawings:

[0053] Figure 1 It is a schematic diagram of the overall control of a DCDC device provided by an embodiment of this specification;

[0054] Figure 2 It is a topology diagram of the main circuit topology of a DCDC device provided by an embodiment of this specification;

[0055] Figure 3 It is a schematic diagram of the control method flow of a DCDC device provided by an embodiment of this specification;

[0056] Figure 4 It is a schematic diagram of the current sharing control of a DCDC device provided by an embodiment of this specification. Detailed Embodiments

[0057] Embodiments of this specification provide a DCDC device and a control method.

[0058] To enable those skilled in the art to better understand the technical solutions in this specification, the following will clearly and completely describe the technical solutions in the embodiments of this specification in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only some embodiments of this specification, rather than all embodiments. Based on the embodiments of this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this specification.

[0059] Such as Figure 1As shown, the embodiment of the present specification provides a schematic diagram of the overall control of a DCDC device. Combining Figure 1 with Figure 2 the topology diagram of the main circuit topology of the DCDC device shown, in one or more embodiments of the present specification, a DCDC device includes:

[0060] The main circuit topology and the control hardware architecture electrically connected to the main circuit topology. The main circuit topology includes a high-voltage side component, a low-voltage side component, a power switch module, and an inductor component. The main circuit topology is used to determine the connection modes of the high-voltage side component, the low-voltage side component, the power switch module, and the inductor component based on the switching timings of the power switch modules corresponding to different modes. Then, through six-phase interleaved parallel connection, bidirectional energy transfer with timing control between the high-voltage side and the low-voltage side in different modes is achieved; wherein, the modes include the BUCK mode and the BOOST mode. For example, in the BUCK mode, energy is transferred from the high-voltage side to the low-voltage side. At this time, as Figure 1 shown, the switching timings of the power switch modules VT1, VT3, VT5, VT7, VT9, VT11 need to be phase-shifted by 60 degrees to reduce current stress and ripple. In the BOOST mode, the energy transfer direction is opposite, and the low-voltage side feeds back energy to the high-voltage side, and phase-shifted control is also required. At this time, as Figure 1 shown, the switching timings of the power switch modules VT2, VT4, VT6, VT8, VT10, VT12 also need to be phase-shifted by 60 degrees. The design of six-phase interleaved parallel connection in this device helps to improve the efficiency and reliability of the system, and at the same time reduces the demand for filter capacitors. Specifically, after the six-phase currents are superimposed, the high-frequency harmonics cancel each other out, reducing the output ripple, and each phase only bears 1 / 6 of the total current, reducing device losses and temperature rise. In addition, when a single-phase fault occurs, the remaining five phases can still maintain system operation through power reallocation, reducing the risk of the DCDC device shutting down.

[0061] The control hardware architecture in the DCDC device is used to receive the real-time operating state feedback by the main circuit topology, generate a control signal based on the real-time operating state, and feedback the control signal to the power switch module of the main circuit topology to form a closed-loop control. This closed-loop control mechanism can ensure that the DCDC device operates stably and efficiently under different working conditions.

[0062] Specifically, in one or more embodiments of the present specification, as Figure 2As shown, the high-voltage side components include: a high-voltage side buffer component, a fuse, multiple filter capacitors and voltage equalizing resistors, which are used for energy storage filtering and voltage equalization of the high-voltage bus. The low-voltage side components include: low-voltage side filter capacitors, voltage equalizing resistors and buffer components, which are used for energy storage filtering and voltage equalization of the low-voltage bus. The power switch module is an IGBT module, which is used to achieve bidirectional energy conversion through phase-shifted 60° timing control in different modes, and the switching devices are not limited to this, and there are also those based on MOSFET and IGBT single-tube parallel connection. The inductor component includes: six-phase independent inductors, and each phase inductor cooperates with the corresponding IGBT module to achieve smooth output of the current in the main circuit topology and ripple cancellation. It can be understood that in this method, through high-voltage side energy storage filtering, six-phase interleaved parallel IGBT control and inductor ripple cancellation, efficient and low-ripple bidirectional energy transmission is achieved.

[0063] Specifically, in one or more embodiments of this specification, as Figure 1 shown, the control hardware architecture includes: a main control board, a sub-control board, a detection board, and a drive board; among them,

[0064] The detection board is used to collect the real-time operating state of the main circuit topology in real time through sensors, so as to convert the real-time operating state into a digital signal and transmit it to the sub-control board. Specifically, in the detection board, there are involved a high-voltage side voltage detection circuit, an IGBT module temperature detection circuit, an IGBT drive circuit, a current detection circuit, and a unit over-current protection circuit, which are connected to the sub-control board through a cable to transmit voltage signals, temperature signals, current signals, and fault signals to the sub-control board. The sub-control board is used to aggregate the data of each component in the control hardware architecture for preliminary filtering and calibration, and upload the processed data to the main control board based on optical fiber. In addition, it should also be noted that the sub-control board will also receive the command signals sent by the main control board, process them and then send them to the detection board, and the detection board will send the signals to the drive board through a cable. The main control board is used to analyze the processed data based on DSP and FPGA to obtain the global control signal of the DCDC device. That is, the main control board is a control system based on DSP TMS320F28335+FPGA EG4X20BG2565, which receives various signals of the drive board and user-set data, and sends out drive signals, relay control signals, etc. after processing. The drive board is used to convert the global control signal output by the main control board into a high-precision drive level to control the switching action of the power switch module, so as to control the power switch module to achieve six-phase interleaved conduction through phase-shifted 60° timing control, forming a closed-loop control.

[0065] During this process, the detection board uses a variety of sensors to collect the operating status of the main circuit topology in real time and converts analog signals into digital signals for transmission to the sub-control board. Through the high-voltage side voltage detection circuit, IGBT module temperature detection circuit, current detection circuit, etc., key parameters such as voltage, temperature, and current can be accurately obtained. This solves the problem that traditional devices cannot grasp the system operating conditions in real time and accurately, provides a data basis for subsequent precise control, ensures that the device can be adjusted in a timely manner under different working conditions, improves the stability of the output voltage and current, and reduces the ripple. The sub-control board aggregates the data of each component, performs preliminary filtering and calibration, and then uploads it to the main control board through optical fibers. This hierarchical processing method reduces the data processing burden on the main control board and improves the data processing efficiency. The sub-control board can also receive instructions from the main control board and forward them, realizing the efficient transmission and interaction of control signals, solving the problems of chaotic data processing and poor transmission, and ensuring the coordinated operation of the entire control hardware architecture. The main control board constructs a control system based on DSP TMS320F28335 and FPGA EG4X20BG2565, with powerful data processing and computing capabilities. It comprehensively analyzes the drive board signals and user-set data to generate global control signals. This can not only achieve precise control of the DCDC device but also adjust the control strategy in a timely manner according to the system operating conditions, solving the problem of inter-phase current sharing. The drive board converts the global control signal output by the main control board into a high-precision drive level to precisely control the switching actions of the power switch module. Six-phase interleaved conduction is achieved through a timing control with a 60° phase stagger, giving full play to the advantages of the six-phase interleaved parallel topology and realizing efficient bidirectional energy transfer.

[0066] Furthermore, in one or more embodiments of this specification, as Figure 1 shown, the control hardware architecture further includes: a power supply board and a human-machine interface; among them, the power supply board is used to provide multiple isolated power supplies to ensure the power supply requirements of each component in the DCDC device, and through power distribution technology, dynamically adjusts the load to the other five phases in the event of a single-phase fault to ensure the continuous operation of the DCDC device, as Figure 1 described in the scenario where the power supply board converts the bus voltage into multiple power outputs, where the 48V power supply is for relay control, fan, and external sensor power supply, and ±15V and 5V are for the detection board, main control board power supply, and multiple drive power supplies. This multiple isolated power supply method can effectively reduce the power interference between components, ensure that each component can work under a stable voltage, and improve the stability and reliability of the entire device operation. And in the event of a single-phase fault, it can dynamically adjust the load to the other five phases, avoiding the entire device from stopping running due to a fault in a certain phase. It should also be noted that the form of the board is not limited to Figure 1 the form shown. The power supply board can be combined with the drive board into one board, and the drive board can be in the form of a differential drive board and a gate-level board; the drive board can also be combined with the main control board to form a drive-control board.

[0067] The human - machine interface is used to display the real - time operating status of the main - circuit topology, enabling the operator to intuitively understand the working conditions of the device, including key parameters such as voltage, current, power, etc. Through the display of real - time data, the operator can timely detect abnormal conditions during the operation of the device, so as to give a fault alarm in time.

[0068] Specifically, in one or more embodiments of this specification, through six - phase interleaved parallel connection, bidirectional energy transfer with timing control between the high - voltage side and the low - voltage side in different modes is achieved, specifically including:

[0069] If the determined mode is the BUCK mode, then as Figure 2 shown, based on the six - way PWM drive signals of the control hardware architecture, the phase of each phase drive signal of the power - switch module on the high - voltage side is controlled to be staggered by 60° in sequence, forming a first periodic conduction sequence. Then, the high - voltage - side energy is connected to the high - voltage - side filter capacitor through the buffer component and fuse for energy storage and filtering. Then, according to the first periodic conduction sequence, the energy of the high - voltage side after energy - storage filtering is transmitted to the low - voltage side through the corresponding inductor, and the remaining ripple is absorbed by the series connection of low - voltage - side electrolytic capacitors and the output voltage is stabilized, and the series - capacitor voltage is balanced by the parallel voltage - equalizing resistors. That is, in the BUCK mode, the input buffer component is based on the first periodic conduction sequence and conducts in sequence through VT1, VT3, VT5, VT7, VT9, VT11 with a 60° phase shift, passes through the inductors L1, L2, L3, L4, L5, L6, and outputs smooth voltage and current. At this time, the electrolytic capacitor CL is connected in series with the low - voltage - side bus for energy storage and filtering, and each electrolytic capacitor is connected in parallel with a voltage - equalizing resistor RL.

[0070] If the determined mode is the BOOST mode, then based on the six - way PWM drive signals of the control hardware architecture, the phase of each phase drive signal of the power - switch module on the low - voltage side is controlled to be staggered by 60° in sequence, forming a second periodic conduction sequence. Then, the low - voltage - side energy is reversely transferred through the inductor, so that the low - voltage - side energy is fed back to the high - voltage side in sequence based on the second periodic conduction sequence, and the high - voltage - side bus ripple is absorbed by the series connection of high - voltage - side electrolytic capacitors and the voltage is stabilized, and the voltage - equalizing resistors are connected in parallel to each capacitor to balance the series - capacitor voltage division. That is, in the BOOST mode, the input buffer component passes through the inductors L1, L2, L3, L4, L5, L6, and then based on the second periodic conduction sequence, conducts in sequence through VT2, VT4, VT6, VT8, VT10, VT12 with a 60° phase shift and outputs smooth voltage and current. The electrolytic capacitors CH1, CH2, and CH3 are connected in series with the high - voltage - side bus for energy storage and filtering. At this time, each electrolytic capacitor is connected in parallel with a voltage - equalizing resistor R, which is used to balance the voltage division of the series - connected electrolytic capacitors.

[0071] In this process, the six-phase interleaved parallel design enables the driving signals of each phase of the power switch module to be staggered by 60° in sequence in the BUCK mode and the BOOST mode. This means that at the same moment, not all power switches conduct or turn off simultaneously, but work alternately. Compared with a single-phase or a circuit with fewer phases, the current stress borne by each phase of the power switch is significantly reduced. In addition, under the interleaved parallel structure, the currents of each phase are staggered in time, and after superimposition, a part of the current ripple can be effectively cancelled out. In the BUCK mode, when the energy on the high-voltage side is transmitted to the low-voltage side through the inductor, the electrolytic capacitors on the low-voltage side are connected in series to absorb the remaining ripple and stabilize the output voltage; in the BOOST mode, the electrolytic capacitors on the high-voltage side are connected in series to absorb the ripple of the high-voltage bus. At the same time, the setting of the voltage-sharing resistors further optimizes the working state of the capacitors, effectively suppressing both the output voltage and current ripples. And in the BUCK mode and the BOOST mode, the entire energy transmission process goes through energy storage filtering, voltage sharing and other links, ensuring efficient energy conversion and stable output. The electrolytic capacitors and inductors on the high-voltage side and the low-voltage side work together to effectively store and release energy, reducing energy loss. The use of the voltage-sharing resistors ensures the balance of capacitor voltage division, avoids damage caused by uneven capacitor voltages, further improves the efficiency and stability of energy conversion, and reduces the energy consumption of the system.

[0072] As Figure 3 shown, the embodiment of this specification provides a schematic flow chart of a control method for a DCDC device. It can be Figure 3 seen that the embodiment of this specification provides a control method for a DCDC device, which is applied to any of the above-mentioned DCDC devices. The method specifically includes the following steps:

[0073] S301: Real-time collect the real-time operating state of the main circuit topology through the detection board sensor, so as to convert the real-time operating state into a digital signal and transmit it to the sub-control board.

[0074] First, the real-time operating state of the main circuit topology is real-time collected through the detection board sensor. In this process, through the high-voltage side voltage detection circuit, IGBT module temperature detection circuit, current detection circuit, etc., data such as voltage, temperature, and current of the real-time operating state can be accurately obtained. Thus, the real-time operating state is converted into a digital signal and transmitted to the sub-control board. In this process, the detection board real-time collects the operating state of the main circuit, enabling the system to timely understand its own working conditions, which solves the problem that traditional devices cannot real-time and accurately master the system operating conditions, providing a data basis for subsequent precise control.

[0075] S302: Aggregate the data of each component in the control hardware architecture through the sub-control board for preliminary filtering and calibration, and upload the processed data to the main control board based on the optical fiber.

[0076] As the intermediate hub in the control hardware architecture, the slave control board is responsible for collecting data from various components such as the detection board and the human-machine interface. After the detection board collects the real-time operation status data of the main circuit topology, it transmits the data to the slave control board. The user operation data of the human-machine interface, etc. will also be aggregated to the slave control board. Therefore, in the embodiments of this specification, the slave control board will aggregate the data of each component in the control hardware architecture for preliminary filtering to remove the noise and interference signals in the data. Then, in order to correct the data to ensure data accuracy, the data will also be calibrated. For example, the voltage and current data collected by the sensor will be calibrated to make it closer to the true value. After the preliminary processed data, the slave control board uploads it to the master control board through optical fiber. In this process, based on the slave control board for preliminary filtering and calibration, it is equivalent to preprocessing the data, avoiding the large amount of data that the master control board needs to process when the data of each component is directly transmitted to the master control board, and improving the operation efficiency of the entire DCDC device. In addition, using optical fiber to transmit data avoids the influence of electromagnetic interference on data transmission.

[0077] S303: Through the master control board, analyze the processed data based on DSP and FPGA to obtain the global control signal of the DCDC device.

[0078] Based on the above step S302, in the embodiments of this specification, the processed data will be analyzed according to DSP and FPGA to obtain the global control signal of the DCDC device. In the embodiments of this specification, by integrating DSP and FPGA on the master control board, the number of external components is reduced, and the integration degree of the system is improved. This not only reduces the complexity and cost of the system, but also reduces the signal interference and failure risk caused by component connection, and improves the stability and reliability of the entire control system.

[0079] Specifically, in one or more embodiments of this specification, analyzing the processed data based on DSP and FPGA to obtain the global control signal of the DCDC device specifically includes:

[0080] First, determine the mode corresponding to the DCDC device to determine the six-phase independent inductors corresponding to each mode and the IGBT modules corresponding to each phase inductor; where the modes include: BUCK mode and BOOST mode. Then, execute the preset double-loop PI control strategy and determine the allocated power of each phase IGBT module. Optimize the allocated power of each phase IGBT module according to the preset genetic algorithm to obtain the global control signal of the DCDC device. That is, in the control of the DCDC device, it is first necessary to clarify what working mode the current device is in, that is, the BUCK mode or the BOOST mode. In different modes, the energy flow direction and voltage conversion method of the DCDC device are different. After determining the mode, find the six-phase independent inductors corresponding to each mode and the IGBT modules corresponding to each phase inductor. The double-loop PI control strategy can use the voltage outer loop to quickly reach a stable output voltage and use the current inner loop to accelerate the system response speed. Then use the power distribution technology to achieve the current and power balance of each phase. Read the sampled voltage and current values through the detection board and the low-voltage side current Hall and low-voltage side voltage Hall, calculate the voltage deviation, calculate the current deviation, calculate the power deviation, and find the optimal P i Make the inter-phase current and power balanced. In this process, by determining the allocated power of each phase IGBT module and using the genetic algorithm for optimization, the problem of unbalanced inter-phase current and power in the six-phase interleaved parallel DCDC device can be effectively solved. And automatically adjust the control strategy and power distribution scheme according to different working modes, so that the DCDC device has stronger adaptability. Whether in the buck or boost working scenario, it can ensure the stable operation and high-efficiency work of the device, meeting the diverse needs of different application scenarios.

[0081] Furthermore, in one or more embodiments of this specification, based on the preset double-loop PI control strategy, determining the allocated power of each phase IGBT module specifically includes:

[0082] According to the load demand power and the target voltage corresponding to each mode, determine the total current reference value, and perform current sharing distribution on each phase current based on the total current reference value to obtain the current reference value of each phase. Calculate the voltage deviation output by the voltage outer loop so that the PI controller adjusts and generates the current inner loop reference value according to the voltage deviation, and receive the current inner loop reference value in the current inner loop to determine the current deviation according to the current inner loop reference value and the actual current value, so that the PI controller quickly adjusts the duty cycle based on the current deviation to complete the double-loop PI control. Then determine the total power required for each current mode, and divide the required total power equally to obtain the allocated power of each phase, so as to determine the current distribution of each phase based on the allocated power of each phase and the given voltage corresponding to each mode. That is, in this process, the current inner loop will be used to accelerate the system response speed, the voltage outer loop will be used to reach a stable output, and the power distribution will be used to balance the current and power of each phase. The PI control formula is In the BUCK mode, optimizing power distribution and current control can ensure the stable operation of the system. As Figure 4 shown, the allocated power Pi for each phase is expressed as: P load is the total power required for 6 phases; the current distribution for each phase satisfies: where, V L is the given voltage on the low-voltage side, I i is the output current of the i-th phase, and I total is the total system current. In this process, by evenly distributing the current reference value and optimizing the power distribution, the balance of the current and power of each phase is achieved. This greatly reduces the working stress of the IGBT module of each phase, reduces problems such as overheating and damage caused by excessive power or current imbalance in a certain phase, extends the service life of the IGBT module, and improves the stability and reliability of the entire system. Adding power and current distribution under the traditional PI control of the current inner loop and voltage outer loop can better achieve the current balance of each phase.

[0083] Specifically, in one or more embodiments of this specification, the allocated power of the IGBT module of each phase is optimized based on a preset genetic algorithm to obtain the global control signal of the DCDC device, which specifically includes the following:

[0084] First, determine the objective function corresponding to minimizing power loss and current imbalance. Among them, the objective function is: where, R i is the equivalent resistance of the i-th phase, is the average current of the power unit, and w is the current balance factor. That is, based on the genetic algorithm, the goal of minimizing power loss and current imbalance is to find the optimal P i to make f minimum. To achieve this goal, the population parameters of the allocated power will be initialized to randomly generate M initial individuals; among them, the population parameters include: population size M, maximum number of iterations T;

[0085] Then, calculate the fitness value of the initial individual based on the objective function, obtain the current individual according to the fitness value to allocate the selection probability, and iterate the genetic operation to obtain the optimal solution, and generate the global control signal corresponding to the optimal solution. Further, in one or more embodiments of this specification, obtaining the current individual according to the fitness value to allocate the selection probability and iterating the genetic operation to obtain the optimal solution specifically includes:

[0086] Step 1: Allocate the selection probability to each individual based on the fitness value, and screen the current individual based on the allocated selection probability corresponding to each individual. That is where P i (0) is the power allocation value of the individual at the initial time, and P minis the minimum output power for each phase, P max is the maximum output power for each phase, rand(0,1) represents a random number between 0 and 1, which is used to generate random power distribution values and calculate fitness

[0087] Step 2: Perform simulated binary crossover on the current individual to generate the current candidate solution;

[0088] Step 3: Perform Gaussian mutation on the selected individuals in the current candidate set based on the preset mutation formula to obtain the current population;

[0089] Step 4: Evaluate each individual in the current population based on the objective function;

[0090] Step 5: Copy the individual with the optimal fitness in the previous generation to the next generation according to the evaluation results.

[0091] By iterating the above steps 1 - 5 until the fitness f(X) satisfies Stop the iteration to obtain the optimal solution. Where t is the current iteration number, T is the preset maximum iteration number, ∈ is the set convergence threshold, and k is the set stable algebra.

[0092] S304: Convert the global control signal output by the main control board into a high-precision drive level through a driver, and control the switching action of the power switch module, so as to control the power switch module to achieve six-phase interleaved conduction through a timing control with a 60° phase stagger, forming a closed-loop control.

[0093] After obtaining the global control signal based on the above step S303, convert the global control signal output by the main control board into a high-precision drive level through a drive board, and precisely control the switching action of the power switch module. Achieve six-phase interleaved conduction through a timing control with a 60° phase stagger, give full play to the advantages of the six-phase interleaved parallel topology structure, and realize efficient bidirectional energy transfer. The six-phase interleaved conduction combined with the closed-loop control enables the system to operate stably under different load conditions and working environments. And the six-phase interleaved conduction method with a 60° phase stagger makes the phase currents stagger from each other in time, and after superimposition, it can effectively cancel a part of the current ripple. At the output end of the DCDC device, this interleaved conduction combined with the filter circuit can significantly reduce the ripple coefficients of the output voltage and current. In addition, the driver converts the control signal of the main control board into a high-precision drive level, which can quickly respond to the instructions of the main control board and precisely control the switching action of the power switch module.

[0094] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the embodiments of the apparatus, device, and non-volatile computer storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the corresponding descriptions in the method embodiments.

[0095] The specific embodiments of this specification are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0096] The above description is only for one or more embodiments of this specification and is not intended to limit this specification. For those skilled in the art, various modifications and changes can be made to one or more embodiments of this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included within the scope of the claims of this specification.

Claims

1. A DCDC device, characterized in that: The device comprises: a main circuit topology structure and a control hardware architecture electrically connected to the main circuit topology structure, wherein the main circuit topology structure comprises a high-voltage side component, a low-voltage side component, a power switch module and an inductor component; The main loop topology is used to determine the connection mode of the high-voltage side component, the low-voltage side component, the power switch module and the inductor component based on the switching timing of the power switch module corresponding to different modes, so as to realize the timing-controlled bidirectional energy transmission between the high-voltage side and the low-voltage side in different modes through six-phase staggered parallel connection; wherein the modes include BUCK mode and BOOST mode; The control hardware architecture is used to receive the real-time operating status fed back by the main loop topology structure, to generate a control signal based on the real-time operating status, and to feed back the control signal to the power switch module of the main loop topology structure to form a closed-loop control.

2. A DCDC device according to claim 1, characterized in that: The high-voltage side components include: a high-voltage side buffer component, a fuse, a plurality of filter capacitors and a voltage-equalizing resistor, which are used for energy storage filtering and voltage balancing of the high-voltage bus; The low-voltage side components include: low-voltage side filter capacitors, voltage-equalizing resistors and buffer components, which are used for energy storage filtering and voltage balancing of the low-voltage bus; The power switch module is an IGBT module, which is used to realize bidirectional energy conversion by timing control with a phase shift of 60° in different modes; The inductor assembly includes: six-phase independent inductors, and each phase inductor is matched with a corresponding IGBT module to achieve current smoothing output and ripple cancellation of the main loop topology structure.

3. A DCDC device according to claim 1, characterized in that: The control hardware architecture includes: a main control board, a sub-control board, a detection board, and a driver board; wherein, The detection board is used to collect the real-time operating status of the main circuit topology structure through sensors in real time, so as to convert the real-time operating status into a digital signal and transmit it to the sub-control board; The sub-control board is used to aggregate the data of each component in the control hardware architecture for preliminary filtering and calibration, so as to upload the processed data to the main control board based on optical fiber; The main control board is used to analyze the processed data based on DSP and FPGA to obtain the global control signal of the DCDC device; The driving board is used to convert the global control signal output by the main control board into a high-precision driving level to control the switching action of the power switch module, so as to control the power switch module to achieve six-phase staggered conduction through timing control with a phase stagger of 60° to form a closed-loop control.

4. A DCDC device according to claim 3, characterized in that: The control hardware architecture also includes: a power board and a human-machine interface; The power board is used to provide multi-channel isolated power supply to ensure the power supply requirements of each component in the DCDC device, and dynamically adjust the load to the other five phases through power distribution technology when a single-phase fault occurs, so as to ensure the continuous operation of the DCDC device; The human-machine interface is used to display the real-time operating status of the main circuit topology structure so as to provide timely fault alarm.

5. A DCDC device according to claim 2, characterized in that: Through six-phase interleaved parallel connection, bidirectional energy transmission with timing control between the high-voltage side and the low-voltage side in different modes is realized, including: If it is determined that the mode is the BUCK mode, based on the six PWM drive signals of the control hardware architecture, the phases of each phase drive signal of the power switch module on the high-voltage side are controlled to be staggered by 60° in sequence to form a first periodic conduction sequence; The high-voltage side energy is connected to the high-voltage side filter capacitor through the buffer component and fuse for energy storage and filtering; Based on the first periodic conduction sequence, the high-voltage side energy after energy storage filtering is transmitted to the low-voltage side through the corresponding inductor, and the remaining ripple is absorbed and the output voltage is stabilized through the low-voltage side electrolytic capacitor in series, and the series capacitor voltage is balanced through the parallel voltage-equalizing resistor; If it is determined that the mode is the BOOST mode, based on the six PWM drive signals of the control hardware architecture, the phases of each phase drive signal of the power switch module on the low-voltage side are controlled to be staggered by 60° in sequence to form a second periodic conduction sequence; The energy on the low-voltage side is transferred in reverse through the inductor, so as to feed back the energy on the low-voltage side to the high-voltage side in sequence based on the second periodic conduction sequence, and the high-voltage bus ripple is absorbed and the voltage is stabilized through the high-voltage side electrolytic capacitor in series, and the voltage is balanced by connecting the equalizing resistor in parallel to each capacitor.

6. A control method for a DCDC device, applied to the DCDC device according to any one of claims 1 to 5, characterized in that: The method comprises: The real-time operating status of the main circuit topology structure is collected in real time by the detection board sensor, so as to convert the real-time operating status into a digital signal and transmit it to the sub-control board; Aggregating the data of each component in the control hardware architecture through the sub-control board for preliminary filtering and calibration, so as to upload the processed data to the main control board based on optical fiber; Through the main control board, the processed data is analyzed based on DSP and FPGA to obtain the global control signal of the DCDC device; The global control signal output by the main control board is converted into a high-precision driving level through a driver to control the switching action of the power switch module, so as to control the power switch module through a timing control with a phase stagger of 60° to achieve six-phase staggered conduction and form a closed-loop control.

7. A control method for a DCDC device according to claim 6, characterized in that: The processed data is analyzed based on DSP and FPGA to obtain the global control signal of the DCDC device, specifically including: Determine the mode corresponding to the DCDC device to determine the six-phase independent inductors corresponding to each mode, and the IGBT modules corresponding to each phase inductor; wherein the modes include: BUCK mode and BOOST mode; Execute the preset dual-loop PI control strategy and determine the allocated power of each phase IGBT module; The distributed power of each phase IGBT module is optimized based on a preset genetic algorithm to obtain a global control signal of the DCDC device.

8. A control method for a DCDC device according to claim 7, characterized in that: Based on the preset dual-loop PI control strategy, the power distribution of each phase IGBT module is determined, including: Determine a total current reference value according to the load demand power and the target voltage corresponding to each mode, and distribute the current of each phase based on the total current reference value to obtain various current reference values; The voltage deviation of the output is calculated in the voltage outer loop, so that the PI controller generates a current inner loop reference value according to the voltage deviation adjustment, and receives the current inner loop reference value in the current inner loop, so as to determine the current deviation according to the current inner loop reference value and the actual current value, so that the PI controller quickly adjusts the duty cycle based on the current deviation to complete the dual-loop PI control; The total power required by each current mode is determined to evenly divide the required total power to obtain the distributed power of each phase, so as to determine the current distribution of each phase based on the distributed power of each phase and the given voltage corresponding to each mode.

9. The control method of a DCDC device according to claim 7, characterized in that: The distributed power of each phase IGBT module is optimized based on a preset genetic algorithm to obtain a global control signal of the DCDC device, specifically including: Determine the objective function corresponding to minimizing power loss and current imbalance; wherein the objective function is: Among them, R i is the equivalent resistance of the i-th phase, is the average current of the power unit, w is the current balancing factor; Initializing the population parameters of the power allocation to randomly generate initial individuals; wherein the population parameters include: population size and maximum number of iterations; The fitness value of the initial individual is calculated based on the objective function, the current individual is obtained by allocating the selection probability according to the fitness value, the optimal solution is obtained by iterative genetic operation, and a global control signal corresponding to the optimal solution is generated.

10. A control method for a DCDC device according to claim 9, characterized in that: According to the fitness value, the selection probability is allocated to obtain the current individual, and the optimal solution is obtained by iterative genetic operation, which specifically includes: Allocating a selection probability to each individual based on the fitness value, so as to screen the current individual based on the corresponding allocated selection probability of each individual; Performing a simulated binary crossover on the current individual to generate a current candidate solution; Performing Gaussian mutation on the selected individuals of the current candidate set based on a preset mutation formula to obtain a current population, and evaluating each individual of the current population based on the objective function so as to copy the individual with the best fitness in the previous generation to the next generation; The current population is iterated, and if it is determined that the fitness value meets the preset target value, the iteration is stopped to obtain the optimal solution.

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