Three-level power unit and three-level power module

Abstract

The invention provides a three-level power unit and a three-level power module. The three-level power unit comprises a substrate; a first power terminal; a second power terminal; and a third power terminal; the first power terminal, the second power terminal and the third power terminal are all arranged on the first side edge of the substrate, and the current flow direction of the first power terminal is set to be a bidirectional path; wherein the first power terminal, the second power terminal and the third power terminal are arranged in a layered mode in the direction perpendicular to the substrate, and the projection area of the first power terminal at least covers the projection area path of at least one of the second power terminal and the third power terminal. According to the invention, the structure and size of the additional DC terminal are optimized, so that the new power unit and module can be adapted to the three-level topology.

Description

Technical Field

[0001] The present invention relates to the field of power devices, and particularly to a three-level power unit and a three-level power module. Background Art

[0002] One of the main shortcomings of current electric vehicles is the relatively short driving range. How to effectively improve the driving range has become a key issue in the industry. As the power conversion device of an electric vehicle, the main drive inverter acts as a connecting bridge between the DC battery and the AC motor, and its electrical characteristics and efficiency have a decisive impact on the driving range of the whole vehicle. At present, two-level inverter topologies are widely used in the main drive inverters of electric vehicles. This topology structure and control are relatively simple, and the number of power devices used is small, so it is favored by most automobile manufacturers. However, this topology operates in a hard-switching mode, resulting in relatively large switching losses. In addition, since the output voltage has only two levels (i.e., VDC / 2 and -VDC / 2), the harmonic components of the output voltage and current are relatively high, increasing the harmonic losses such as core loss in the permanent magnet synchronous motor, thereby reducing the overall efficiency and limiting the improvement of the driving range.

[0003] In contrast, the three-level topology has significant advantages. Its output voltage introduces a 0 level on the basis of the original two-level topology, making the output waveform closer to a sine wave, effectively reducing the output harmonic components, reducing the losses generated by harmonics in the motor, and thus improving the driving range of the whole vehicle. However, the current power modules only support two-level topologies. Since the three-level topology requires the additional introduction of new power terminals, the traditional packaging design is no longer applicable.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a three-level power unit and a three-level power module, which are used to solve the problem that the existing two-level power modules in the prior art are difficult to adapt to the three-level topology.

[0006] To achieve the above object and other related objects, the present invention provides a three-level power unit, including: a substrate;

[0007] A first power terminal;

[0008] A second power terminal; and

[0009] A third power terminal;

[0010] The first power terminal, the second power terminal, and the third power terminal are all disposed on the first side of the substrate, and the current flow direction of the first power terminal is set as a bidirectional path;

[0011] Wherein, the first power terminal, the second power terminal, and the third power terminal are arranged in layers in a direction perpendicular to the substrate, and the projected area of the first power terminal covers at least the projected area path of at least one of the second power terminal and the third power terminal.

[0012] Optionally, the first power terminal, the second power terminal, and the third power terminal are all arranged in parallel, and both opposite surfaces of the first power terminal and the second power terminal are set as rectangles, and both opposite surfaces of the first power terminal and the third power terminal are set as rectangles.

[0013] Optionally, the second power terminal and the third power terminal are both disposed on one side of the first power terminal, and the distance between the second power terminal and the first power terminal is equal to the distance between the third power terminal and the first power terminal.

[0014] Optionally, the surface area of the first surface of the first power terminal satisfies: S1≥S2+S3; where S1 is the surface area of the first surface of the first power terminal; the first surface of the first power terminal is the opposite surface of the first power terminal close to the second power terminal and the third power terminal; S2 is the surface area of the first surface of the second power terminal; the first surface of the second power terminal is the opposite surface of the second power terminal and the first power terminal; S3 is the surface area of the first surface of the third power terminal; the first surface of the third power terminal is the opposite surface of the third power terminal and the first power terminal.

[0015] Optionally, the three-level power unit further includes a first power component, a second power component, a third power component, a fourth power component, and a fourth power terminal; the first power component, the second power component, the third power component, and the fourth power component are all disposed on the upper surface of the substrate, and the fourth power terminal is disposed on the second side of the substrate; the first power component and the second power component are sequentially connected in series to form a first series structure; the third power component and the fourth power component are sequentially connected in series to form a second series structure; the first end of the first series structure is connected to the first power terminal, and the second end is connected to the fourth power terminal; the second end of the first series structure is further connected to the connection node between the third power component and the fourth power component; the first end of the second series structure is connected to the second power terminal, and the second end is connected to the third power terminal.

[0016] Optionally, the three-level power unit further includes a fifth power component, a sixth power component, a seventh power component, an eighth power component, and a fifth power terminal; the fifth power component, the sixth power component, the seventh power component, and the eighth power component are all disposed on the upper surface of the substrate, and the fifth power terminal is disposed on the second side of the substrate; the fifth power component, the sixth power component, the seventh power component, and the eighth power component are connected in series in sequence to form a third series structure; a first end of the third series structure is connected to the second power terminal, and a second end is connected to the third power terminal; a connection node between the fifth power component and the sixth power component is connected to the first power terminal; a connection node between the seventh power component and the eighth power component is connected to the first power terminal; a connection node between the sixth power component and the seventh power component is connected to the fifth power terminal.

[0017] Optionally, the three-level power unit further includes a ninth power component, a tenth power component, an eleventh power component, a twelfth power component, a thirteenth power component, a fourteenth power component, and a sixth power terminal; the ninth power component, the tenth power component, the eleventh power component, the twelfth power component, the thirteenth power component, and the fourteenth power component are all disposed on the upper surface of the substrate, and the sixth power terminal is disposed on the second side of the substrate; the ninth power component and the tenth power component are connected in series in sequence to form a fourth series structure; the eleventh power component, the twelfth power component, the thirteenth power component, and the fourteenth power component are connected in series in sequence to form a fifth series structure; a first end of the fourth series structure is connected to a connection node between the eleventh power component and the twelfth power component, and a second end is connected to a connection node between the thirteenth power component and the fourteenth power component; a first end of the fifth series structure is connected to the second power terminal, and a second end is connected to the third power terminal; a connection node between the ninth power component and the tenth power component is connected to the first power terminal; a connection node between the twelfth power component and the thirteenth power component is connected to the sixth power terminal.

[0018] Optionally, a third power component area, a first power component area, a second power component area, and a fourth power component area are arranged in sequence along the first side direction of the substrate; the first power component is disposed in the first power component area, and the first power component includes X first power chips connected in parallel; the second power component is disposed in the second power component area, and the second power component includes X second power chips connected in parallel; the third power component is disposed in the third power component area, and the third power component includes Y third power chips connected in parallel; the fourth power component is disposed in the fourth power component area, and the fourth power component includes Y fourth power chips connected in parallel.

[0019] Optionally, the three-level power unit layout structure further includes a control area; the control area is disposed on the substrate and on a side close to the fourth power terminal; the control area is sequentially provided with a first control terminal, a second control terminal, a third control terminal, a fourth control terminal, a fifth control terminal, a sixth control terminal, a seventh control terminal, an eighth control terminal, and a ninth control terminal along the first side direction of the substrate; the first control terminal, the second control terminal, and the third control terminal are respectively connected to the first control end, the second control end, and the third control end of the third power component; the fourth control terminal and the fifth control terminal are respectively connected to the first control end and the second control end of the first power component; the sixth control terminal is connected to the first control end of the second power component; the seventh control terminal, the eighth control terminal, and the ninth control terminal are respectively connected to the first control end, the second control end, and the third control end of the fourth power component.

[0020] Optionally, the third control ends of the fourth power component are all electrically connected to the ninth control terminal through a sub-substrate.

[0021] To achieve the above object and other related objects, the present invention provides a three-level power module, including M of the above-mentioned three-level power units; M is an integer greater than or equal to 1;

[0022] Each of the three-level power units is arranged in sequence along a first direction, the first direction is the same as the first side direction of the substrate, and the first side of the substrate is disposed opposite to the second side of the substrate.

[0023] As described above, the three-level power unit and the three-level power module of the present invention have the following beneficial effects:

[0024] The present invention optimizes the structure and size of the additionally added DC terminals, ensuring that the new power units and modules can be adapted to the three-level topology under the same volume and size, achieving a compact design with a high power density and greatly simplifying the structural design of the main drive inverter. Meanwhile, the commutation path of the layout structure set by the present invention is further optimized, and the parasitic inductance of the switching commutation path is specifically reduced in cooperation with the magnetic field cancellation principle. Under the same module size, a lower loop parasitic inductance than that of the two-level power module is achieved, having good application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It shows a circuit schematic diagram of an existing two-level power topology.

[0026] Figure 2 It shows a circuit schematic diagram of a three-level power unit according to an embodiment of the present invention.

[0027] Figure 3 It shows an overall external view schematic diagram of a three-level power module according to an embodiment of the present invention.

[0028] Figure 4 It shows an arrangement schematic diagram of the first power terminal to the third power terminal according to an embodiment of the present invention.

[0029] Figure 5 It shows according to an embodiment of the present invention Figure 4 side view schematic diagram of each power terminal.

[0030] Figure 6 It shows a magnetic field cancellation schematic diagram of a current direction between the third power terminal and the first power terminal according to an embodiment of the present invention.

[0031] Figure 7 It shows a magnetic field cancellation schematic diagram of another current direction between the third power terminal and the first power terminal according to an embodiment of the present invention.

[0032] Figure 8 It shows an arrangement position schematic diagram of a three-level power unit according to an embodiment of the present invention.

[0033] Figure 9 It shows a schematic diagram of the outer frame of the package of a three-level power module according to an embodiment of the present invention.

[0034] Figure 10 It shows a top view of the structure of a three-level power module according to an embodiment of the present invention.

[0035] Figure 11 It shows a circuit schematic diagram of a three-level power unit according to another embodiment of the present invention.

[0036] Figure 12 It shows a circuit schematic diagram of a three-level power unit according to another embodiment of the present invention.

[0037] Description of component labels

[0038] 1 Three-level power unit module

[0039] 11 Three-level power unit

[0040] 11’ Three-level power unit

[0041] 11” Three-level power unit

[0042] 110 Substrate

[0043] 110a First power component area

[0044] 110b Second power component area

[0045] 110c Third power component area

[0046] 110d Fourth power component area

[0047] 110e Control area

[0048] 1101 Temperature detector

[0049] 1102 Sub-substrate

[0050] 111 First power terminal

[0051] 112 Second power terminal

[0052] 113 Third power terminal

[0053] 114 First power component

[0054] 114’ Fifth power component

[0055] 114” Ninth power component

[0056] 115 Second power component

[0057] 115’ Fifth power component

[0058] 115” Tenth power component

[0059] 116 Third power component

[0060] 116’ Seventh power component

[0061] 116” Eleventh power component

[0062] 117 Fourth power component

[0063] 117’ eighth power component

[0064] 117” twelfth power component

[0065] 118 fourth power terminal

[0066] 118” thirteenth power component

[0067] 119” fourteenth power component Detailed implementation manners

[0068] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0069] Please refer to Figures 1 to 12 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0070] Figure 1 A circuit schematic diagram of a two-level power topology is provided, including an upper half transistor T1 and a lower half transistor T2. Among them, the upper half transistor T1 and the lower half transistor T2 are connected in series to form a series structure. The first end of this series structure serves as the first DC-side power P terminal, and the second end of this series structure serves as the second DC-side power N terminal. The connection node between the upper half transistor T1 and the lower half transistor T2 serves as the AC-side power AC terminal.

[0071] However, this two-level power topology operates in a hard-switching mode, with relatively large switching losses. And since the output voltage of the AC-side power AC terminal has only two levels, namely VDC / 2 and -VDC / 2, therefore, the harmonic components of the output voltage and current are relatively large, increasing the core loss caused by harmonics in the permanent magnet synchronous motor, etc., reducing the overall efficiency, and thus limiting the cruising range.

[0072] To improve the above situation, as Figure 2 shown, a three-level power topology is proposed. It adds two horizontal power transistors and thus introduces a third DC-side power O terminal. Through such a setting, the upper and lower half transistors ( Figure 2The switching voltage of the third power component 116 and the fourth power component 117) is reduced by half, reducing their switching losses. At the same time, a 0 level is introduced, making the waveform output at the AC side AC terminal closer to a sine wave, effectively reducing the output harmonic components, reducing the losses generated by the motor due to harmonics, and improving the vehicle's cruising range.

[0073] However, for the main drive application of electric vehicles, the traditional two-level HPD package only supports the two-level topology and is no longer applicable to the three-level power topology with an additional power O terminal introduced. Based on this, the embodiment of the present application provides a new three-level power unit to provide a power module and a packaging structure applicable to the three-level power topology.

[0074] Embodiment 1

[0075] As Figure 3 shown, the embodiment of the present application provides a three-level power unit 11, including: a substrate 110, a first power terminal 111, a second power terminal 112, and a third power terminal 113.

[0076] As Figure 3 shown, the first power terminal 111, the second power terminal 112, and the third power terminal 113 are all arranged on the first side of the substrate 110. The current flow direction of the first power terminal 111 is set to be bidirectional, so that the switching transient commutation current of the first power terminal 111 is output through the substrate 110 to the second power terminal 112 or the third power terminal 113 respectively, and different current paths with different flow directions are formed. It should be noted that the current of the inverter circuit can be divided into a transient commutation current path during the switching of the switching state and a load current path in the stable conduction state. Among them, the transient commutation current path refers to the current path formed during the process of the current transferring from one branch to another during the switching of the switching state (as Figure 7 shown), and the first power terminal 111 set in this embodiment is output to the second power terminal 112 and the third power terminal 113 respectively to form current paths respectively.

[0077] In this embodiment, when the direction of the commutation current (during the switching transient commutation state) of the first power terminal 111 is positive (as Figure 3 and Figure 4 shown by the positive current direction I+ of the left solid line), the corresponding second power terminal 112 on the left is the negative current direction (shown by the dotted line), and at the same time, there is no current in the third power terminal 113; when the direction of the commutation current of the first power terminal 111 is negative (as Figure 3 and Figure 4As shown by the solid line on the right side, the negative direction of the current is I-), corresponding to the positive direction of the current for the third power terminal 113 (shown by the dotted line). At the same time, there is no current in the second power terminal 112. It should be noted that the direction of the current is only an example in this embodiment, and the actually set direction is not limited to the above description. As long as it is ensured that the first power terminal 111 can respectively form different current paths with the second power terminal 112 and the third power terminal 113, it falls within the protection scope of this embodiment.

[0078] As Figure 3 shown, the first power terminal 111, the second power terminal 112, and the third power terminal 113 are arranged in layers in a direction perpendicular to the substrate 110. Moreover, the projected area of the first power terminal 111 covers at least the projected area of at least one of the second power terminal 112 and the third power terminal 113 to cancel out the magnetic field of the current path.

[0079] Specifically, in this embodiment, the first power terminal 111, the second power terminal 112, and the third power terminal 113 are all arranged in parallel. Moreover, two opposite surfaces of the first power terminal 111 and the second power terminal 112 are set as rectangles (that is, Figure 5 the first surface S1’ of the first power terminal 111 and the first surface S2’ of the second power terminal 112 in Figure 5 are both set as rectangles), and two opposite surfaces of the first power terminal 111 and the third power terminal 113 are set as rectangles ((that is, Figure 5 the first surface S1’ of the first power terminal 111 and the first surface S3’ of the third power terminal 113 are oppositely arranged). By setting the opposite surfaces as rectangles, the magnetic field uniformity of the power terminals is ensured as much as possible. In this embodiment, it is necessary to ensure that the projected part of the opposite surfaces is as complete as possible (for example, to avoid situations such as punching that damage the opposite surfaces) to ensure the effect of magnetic field cancellation. It should be noted that the magnetic field cancellation effect is the best when the three power terminals are parallel to each other, and it is also convenient for process manufacturing. In actual manufacturing, there may be a parallelism deviation during the process manufacturing. However, no matter how much the deviation is, as long as there is an overlap in the projection direction, it can be ensured that the first power terminal 111 of the three terminals covers at least one of the other two terminals (the second power terminal 112 and the third power terminal 113), so as to achieve the purpose of optimizing the magnetic field of the current path and reducing the parasitic inductance.

[0080] As an example, both the second power terminal 112 and the third power terminal 113 are disposed on one side of the first power terminal 111, and the distance between the second power terminal 112 and the first power terminal 111 is equal to the distance between the third power terminal 113 and the first power terminal 111. In this embodiment, the second power terminal 112 and the third power terminal 113 are arranged side by side and are both disposed below the first power terminal 111 to improve the integration degree; at the same time, such an arrangement can ensure the magnetic field cancellation effect. In another embodiment, the second power terminal 112 and the third power terminal 113 may not be arranged side by side. In fact, as long as it is ensured that the first power terminal 111 and the other two power terminals are stratified, it is within the protection scope of this embodiment.

[0081] In this embodiment, as Figure 5 shown, the surface area of the first surface of the first power terminal satisfies: S1≥S2+S3; where, S1 is the surface area of the first surface of the first power terminal; the first surface of the first power terminal is the opposite surface of the first power terminal close to the second power terminal and the third power terminal; S2 is the surface area of the first surface of the second power terminal; the first surface of the second power terminal is the opposite surface of the second power terminal and the first power terminal; S3 is the surface area of the first surface of the third power terminal; the first surface of the third power terminal is the opposite surface of the third power terminal and the first power terminal. As Figure 5 shown, when the first power terminal 111 completely covers the second power terminal 112 and the third power terminal 113, the magnetic field cancellation effect is the best at this time.

[0082] The first power terminal 111 is denoted as the O terminal, the second power terminal 112 is denoted as the N terminal, and the third power terminal 113 is denoted as the P terminal, and the Figure 6 and Figure 7 current magnetic field diagrams of the first power terminal and the third power terminal provided are used to illustrate the principle:

[0083] As Figure 6 shown, in this embodiment, when the current direction is set to the negative current direction I- (that is, the current flows out from the P terminal to the O terminal), the current direction of the O terminal flows in, and the current direction of the P terminal flows out. The current directions of the two terminals are opposite, and the magnetic field directions of the two terminals follow the right-hand screw relationship of Ampere's rule. The magnetic field direction of the O terminal (the tangent in the horizontal direction is to the right) is opposite to the magnetic field direction of the P terminal (the tangent in the horizontal direction is to the left). At this time, the magnetic field between the first power terminal and the third power terminal is cancelled. And in another embodiment, as Figure 7As shown, when the set current direction is the positive current direction I- (i.e., current flows from the O terminal to the P terminal), the current direction at the O terminal flows out, and the current direction at the P terminal flows in. The current directions at the two terminals are opposite. The magnetic field direction at the O terminal (the tangent in the horizontal direction is to the left) is opposite to the magnetic field direction at the P terminal (the tangent in the horizontal direction is to the right). Obviously, the inflow and outflow directions at the O terminal are opposite to those at the P terminal, which is opposite to the previous situation to ensure that the magnetic field directions at the O terminal and the P terminal are opposite, realizing magnetic field cancellation between the first power terminal and the third power terminal. In fact, no matter what direction the current is set, as long as it can be ensured that the upper and lower projections of the current flow paths formed by the first power terminal 111 and the third power terminal 113 with opposite current flows have an overlapping part, the corresponding magnetic fields can be cancelled.

[0084] Similarly, for the case where the first power terminal 111 and the second power terminal 112 form a path, as long as the upper and lower projections have an overlapping part, the corresponding magnetic fields can be cancelled. In this embodiment, the current directions of the second power terminal 112 and the third power terminal 113 can be set arbitrarily, as long as it is ensured that the currents of the two respectively form paths with opposite flows to the first power terminal 111.

[0085] It should be noted that generally, the widths of the power terminals are all set to the same width for ease of process manufacturing, installation, and detection. At the same time, since the power module has a relatively standard size to be compatible with various scenarios, if an additional O terminal is directly introduced without restricting the arrangement position and size, it may reduce the widths of all power terminals, thereby reducing the current-carrying capacity of each power terminal. Therefore, the three-level power unit provided in this embodiment can further reduce the magnetic fields generated respectively when the current conducts through each path without sacrificing the width of the terminals, reduce the parasitic inductance of the loop, and is beneficial to reducing switching losses, parasitic oscillations, and the turn-off voltage spikes of the devices. Through the optimization of the DC terminals, in the same volume size, this embodiment can be adapted to the three-level power topology, realizing a compact design, having a high power density, and simplifying the structural design of the main drive inverter as a whole to the greatest extent.

[0086] Specifically, as a first example, as Figure 2 and Figure 3 shown, the three-level power unit 11 further includes a first power component 114, a second power component 115, a third power component 116, a fourth power component 117, and a fourth power terminal 118 (i.e., the AC side AC terminal).

[0087] Among them, the first power component 114, the second power component 115, the third power component 116, and the fourth power component 117 are all disposed on the upper surface of the substrate 110, and the fourth power terminal 118 is disposed on the second side of the substrate 110. The first power component 114 and the second power component 115 are connected in series in sequence to form a first series structure; the third power component 116 and the fourth power component 117 are connected in series in sequence to form a second series structure; the first end of the first series structure is connected to the first power terminal 111 (i.e., Figure 2 the medium power O terminal), and the second end is connected to the fourth power terminal (i.e., the AC terminal in the figure); the second end of the first series structure is also connected to the connection node between the third power component 116 and the fourth power component 117; the first end of the second series structure is connected to the second power terminal 112 (i.e., Figure 2 the medium N terminal), and the second end is connected to the third power terminal 113 (i.e., Figure 2 the medium P terminal). By the first power terminal 111, the second power terminal 112, and the third power terminal 113 provided in this embodiment, the magnetic field cancellation of the first path (O-N) and / or the second path (P-O) can be achieved.

[0088] As Figure 8 shown, the three-level power unit of this embodiment further includes a third power component area 110c, a first power component area 110a, a second power component area 110b, and a fourth power component area 110d, which are used to implement the three-level power unit as shown in Figure 2 and Figure 3 shown, that is: when the three-level power unit 11 includes the first power component 114, the second power component 115, the third power component 116, the fourth power component 117, and the fourth power terminal 118, the three-level power unit includes:

[0089] The third power component area 110c, the first power component area 110a, the second power component area 110b, and the fourth power component area 110d are disposed on the substrate 110 and arranged in sequence along the first side direction of the substrate 110 (as Figure 12 arranged from left to right in the figure); the first power component 114 is disposed in the first power component area 110a, and the first power component 114 includes X first power chips connected in parallel; the second power component 115 is disposed in the second power component area 110b, and the second power component 115 includes X second power chips connected in parallel; the third power component 116 is disposed in the third power component area 110c, and the third power component 116 includes Y third power chips connected in parallel; the fourth power component 117 is disposed in the fourth power component area 110d, and the fourth power component 117 includes Y fourth power chips connected in parallel.

[0090] Each power component area is provided with a plurality of power chips arranged along the direction of the first side edge perpendicular to the substrate 110 (such as Figure 12 arranged from top to bottom therein); among them, the first power component area 110a and the second power component area 110b are both provided with X power chips; the third power component area 110c and the fourth power component area 110d are both provided with Y power chips; both X and Y are integers greater than or equal to 1. In this embodiment, X is set to 4 and Y is set to 5, and the actual quantity is not limited to this embodiment. In this embodiment, the X power chips are all 1.2 kV SiC MOSFET chips; the Y power chips are all 750 V SiC MOSFET chips.

[0091] Furthermore, each chip connected in parallel in the first power component area 110a and each chip connected in parallel in the second power component area 110b are connected in series to obtain a first series structure; the first end of the first series structure is connected to the first power terminal 111 (O terminal), and the second end is connected to the fourth power terminal (AC terminal). Each chip connected in parallel in the third power component area 110c and each chip connected in parallel in the fourth power component area 110d are connected in series to obtain a second series structure; the first end of the second series structure is connected to the second power terminal (N terminal), and the second end is connected to the fourth power terminal (P terminal).

[0092] Furthermore, the three-level power unit layout structure further includes a control area 110e; the control area 110e is arranged on the substrate 110 and on the side close to the fourth power terminal (AC terminal); along the direction of the first side edge of the substrate 110, the control area 110e is successively arranged with a first control terminal (D1), a second control terminal (G1), a third control terminal (S1), a fourth control terminal (G3), a fifth control terminal (S3), a sixth control terminal (G4), a seventh control terminal (D2), an eighth control terminal (S2), and a ninth control terminal (G2).

[0093] As Figure 2 and Figure 8 shown, among them, the first control terminal (D1), the second control terminal (G1), and the third control terminal (S1) are respectively connected to the first control end, the second control end, and the third control end of the third power component 116. The fourth control terminal (G3) and the fifth control terminal (S3) are respectively connected to the first control end and the second control end of the first power component 114; the sixth control terminal (G4) is connected to the first control end of the second power component 115; the seventh control terminal (D2), the eighth control terminal (S2), and the ninth control terminal (G2) are respectively connected to the first control end, the second control end, and the third control end of the fourth power component 117.

[0094] It should be noted that, in order to ensure electrical isolation, Figure 8There is a high-voltage signal terminal below the left side of the control area 110e, and it needs to maintain a certain physical distance from other low-voltage signal terminals. In this embodiment, there is a certain spacing between the control terminals on the left and right sides of the control area 110e, rather than being closely arranged.

[0095] In this embodiment, the third control ends of the fourth power components 117 are all electrically connected to the ninth control terminal (G2) through the sub-substrate 1102. In this embodiment, through such a layout setting, the commutation path can be further optimized, minimizing the commutation path, improving the integration while ensuring the magnetic field cancellation effect between the first power terminal 111 and the other two power terminals respectively. In this embodiment, the gates of the fourth power components 117 are electrically connected through a sub-DBC board welded on the mother DBC (Direct Bonded Copper, direct copper clad ceramic substrate).

[0096] Furthermore, in this embodiment, two temperature detectors 1101 are also provided on the substrate 110. In this embodiment, it includes two NTC (negative temperature coefficient) thermistors for temperature detection.

[0097] It should be noted that in the three-level power unit of this embodiment, the first side and the second side of the substrate 110 can be set to be opposite to each other or adjacent to each other, and this embodiment is not limiting. In addition, multiple control terminals of the corresponding power components (mainly the power tubes included therein) are directly arranged on the substrate 110 and electrically led out subsequently. In fact, the actual position structure of the multiple control terminals is not limited to the several illustrations in this embodiment, and in some examples, they can also be arranged on the side of the substrate 110 by means of leading out.

[0098] As Figure 9 and Figure 10 shown, this embodiment also provides a three-level power module 1, including: M three-level power units 11; M is an integer greater than or equal to 1.

[0099] As Figure 10 shown, each three-level power unit 11 is arranged in sequence along the first direction; the first direction is the same as the direction of the first side of the substrate 110; the first side of the substrate 110 is opposite to the second side of the substrate 110, that is, the AC side terminal and the DC side terminal are opposite to each other.

[0100] Specifically, in this embodiment, the three-level power module 1 further includes a DC bus bar (not shown in the figure); the first power terminal 111, the second power terminal 112, and the third power terminal 113 are all connected to the DC bus bar by laser welding. The electrical lead-out is carried out by laser welding, avoiding punching holes in the first power terminal 111, the second power terminal 112, and the third power terminal 113 (that is: avoiding connecting to the bus capacitor by screwing). Therefore, the three-level power module 1 of this embodiment can avoid the problem that the connection by screwing may become loose during long-term operation, reducing the connection reliability, further avoiding the loss of the three-level power module 1 and the risk of causing local hot spots. At the same time, the laser welding method adopted in this embodiment can also further improve the assembly efficiency.

[0101] In this embodiment, M is set to 3, that is, there are 3 three-level power units 11 arranged side by side, and their respective AC side terminals (AC1 to AC3) are respectively connected to the three phases (U phase, V phase, and W phase) of the three-phase alternating current. The phase differences of the alternating current of these three phases are 120 degrees and are used to connect three-phase loads, such as three-phase motors.

[0102] The three-level power module 1 of this embodiment is further improved on the basis of the HPD package, solving the problem that the HPD package has only a two-level topology and cannot be applied to the three-level topology. Through a compact internal layout and optimized chip design, it can achieve a higher power output within a smaller package size.

[0103] It should be further noted that comparing the three-level power unit provided in this embodiment with Figure 1 the two-level HPD package gives the following table:

[0104] Loop Inductance under 10MHz Detection Condition Figure 1 P-N path in 14.43 Nanohenry Figure 2 P-O path in 10.50 Nanohenry Figure 2 O-N path in 12.56 Nanohenry

[0105] It can be seen from this table that through the structure of this embodiment, the equivalent inductance can be significantly reduced. Among them, the P-O path is reduced by 27.2%, and the O-N path is reduced by 13.0%.

[0106] Therefore, by covering and overlapping the first power terminal, the second power terminal, and the third power terminal in a designed manner, the problem that the terminal width is reduced due to the increase of one terminal under the standard size, ultimately affecting the current-carrying capacity, etc. is avoided. In addition, the parasitic inductance of the switching commutation path is specifically reduced by the magnetic field cancellation principle. Under the same module size, a lower loop parasitic inductance than the two-level power module is achieved, having a good application prospect.

[0107] Embodiment 2

[0108] This embodiment provides another three-level power unit 11', which is basically the same as the first embodiment, except that the connection relationship of the power components in the three-level power unit of this embodiment is different.

[0109] Specifically, as Figure 11 shown, the three-level power unit 11' further includes a fifth power component 114', a sixth power component 115', a seventh power component 116', an eighth power component 116', and a fifth power terminal (AC terminal in the figure).

[0110] Among them, the fifth power component 114', the sixth power component 115', the seventh power component 116', and the eighth power component 117' are all arranged on the upper surface of the substrate; the fifth power terminal is arranged on the second side of the substrate; the fifth power component 114', the sixth power component 115', the seventh power component 116', and the eighth power component 117' are connected in series in sequence to form a third series structure; the first end of the third series structure is connected to the second power terminal (N terminal), and the second end is connected to the third power terminal (P terminal); the connection node between the fifth power component 114' and the sixth power component 115' is connected to the first power terminal (O terminal); the connection node between the seventh power component 116' and the eighth power component 116' is connected to the first power terminal (O terminal); the connection node between the sixth power component 115' and the seventh power component 116' is connected to the fifth power terminal (AC terminal). In this embodiment, the three-level power unit 11 further includes two diodes. The first diode D1 is arranged between the first power terminal 111 and the seventh power component 116', and the second diode D2 is arranged between the first power O terminal and the eighth power component 117'.

[0111] It should be noted that the power components in this embodiment are set as power chips based on the basic configuration of IGBT chips. However, the actual type of power components is not limited to this embodiment. Each power component may include an IGBT chip with a diode or a MOSFET chip with a diode (the diode and the power transistor are integrated into one chip), or may also be set as an independently arranged IGBT chip, MOSFET chip, and diode chip (the diode and the power transistor are respectively independent as different chips).

[0112] Embodiment Three

[0113] This embodiment provides yet another three-level power unit 11", which is basically the same as the first and second embodiments, except that the connection relationship of the power components in the three-level power unit 11" of this embodiment is different.

[0114] Specifically, as Figure 12As shown, the three-level power unit 11" further includes a ninth power component 114", a tenth power component 115", an eleventh power component 116", a twelfth power component 117", a thirteenth power component 118", a fourteenth power component 119", and a sixth power terminal (AC terminal in the figure).

[0115] Among them, the ninth power component 114", the tenth power component 115", the eleventh power component 116", the twelfth power component 117", the thirteenth power component 118", and the fourteenth power component 119" are all arranged on the upper surface of the substrate; the sixth power terminal is arranged on the second side of the substrate; the ninth power component 114" and the tenth power component 115" are connected in series in turn to form a fourth series structure; the eleventh power component 116", the twelfth power component 117", the thirteenth power component 118", and the fourteenth power component 119' are connected in series in turn to form a fifth series structure; the first end of the fourth series structure is connected to the connection node between the eleventh power component 116" and the twelfth power component 117", and the second end is connected to the connection node between the thirteenth power component 118" and the fourteenth power component 119"; the first end of the fifth series structure is connected to the second power terminal (N terminal), and the second end is connected to the third power terminal (P terminal); the connection node between the ninth power component and the tenth power component is connected to the first power terminal (O terminal); the connection node between the twelfth power component and the thirteenth power component is connected to the sixth power terminal (AC terminal).

[0116] It should be noted that the power components in this embodiment are set as power chips with an IGBT-based configuration, but the actual type is not limited to this embodiment. The specific principles and settings have been described in the previous text and will not be elaborated here one by one.

[0117] The present invention optimizes the structure and size of the additional DC terminals, ensuring that the new power unit and module can be adapted to the three-level topology. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0118] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A three-level power unit, comprising: substrate; a first power terminal; A second power terminal; as well as A third power terminal; The first power terminal, the second power terminal and the third power terminal are all arranged on a first side of the substrate, and the current flow direction of the first power terminal is arranged as a bidirectional path; The first power terminal, the second power terminal and the third power terminal are arranged in layers in a direction perpendicular to the substrate, and the projection area of ​​the first power terminal at least covers the projection area path of at least one of the second power terminal and the third power terminal.

2. The three-level power unit according to claim 1, characterized in that: The first power terminal is arranged in parallel with the second power terminal and the third power terminal, and two opposite surfaces of the first power terminal and the second power terminal are arranged in a rectangular shape, and two opposite surfaces of the first power terminal and the third power terminal are arranged in a rectangular shape.

3. The three-level power unit according to claim 2, characterized in that: The second power terminal and the third power terminal are both arranged at one side of the first power terminal, and the distance between the second power terminal and the first power terminal is equal to the distance between the third power terminal and the first power terminal.

4. The three-level power unit according to claim 3, characterized in that: The surface area of ​​the first surface of the first power terminal satisfies: S1≥S2+S3; Wherein, S1 is the surface area of ​​the first surface of the first power terminal; the first surface of the first power terminal is the opposite surface of the first power terminal close to the second power terminal and the third power terminal; S2 is the surface area of ​​the first surface of the second power terminal; the first surface of the second power terminal is the opposite surface of the second power terminal and the first power terminal; S3 is the surface area of ​​the first surface of the third power terminal; the first surface of the third power terminal is the opposite surface of the third power terminal and the first power terminal.

5. The three-level power unit according to claim 1, characterized in that: The three-level power unit further includes a first power component, a second power component, a third power component, a fourth power component and a fourth power terminal; The first power component, the second power component, the third power component, and the fourth power component are all disposed on the upper surface of the substrate, and the fourth power terminal is disposed on the second side of the substrate; The first power component and the second power component are connected in series in sequence to form a first series structure; the third power component and the fourth power component are connected in series in sequence to form a second series structure; the first end of the first series structure is connected to the first power terminal, and the second end is connected to the fourth power terminal; the second end of the first series structure is also connected to the connection node between the third power component and the fourth power component; the first end of the second series structure is connected to the second power terminal, and the second end is connected to the third power terminal.

6. The three-level power unit according to claim 1, characterized in that: The three-level power unit further includes a fifth power component, a sixth power component, a seventh power component, an eighth power component and a fifth power terminal; The fifth power component, the sixth power component, the seventh power component, and the eighth power component are all disposed on the upper surface of the substrate, and the fifth power terminal is disposed on the second side of the substrate; The fifth power component, the sixth power component, the seventh power component, and the eighth power component are connected in series in sequence to form a third series structure; the first end of the third series structure is connected to the second power terminal, and the second end is connected to the third power terminal; the connection node between the fifth power component and the sixth power component is connected to the first power terminal; the connection node between the seventh power component and the eighth power component is connected to the first power terminal; and the connection node between the sixth power component and the seventh power component is connected to the fifth power terminal.

7. The three-level power unit according to claim 1, characterized in that: The three-level power unit further includes a ninth power component, a tenth power component, an eleventh power component, a twelfth power component, a thirteenth power component, a fourteenth power component and a sixth power terminal; The ninth power component, the tenth power component, the eleventh power component, the twelfth power component, the thirteenth power component, and the fourteenth power component are all disposed on the upper surface of the substrate, and the sixth power terminal is disposed on the second side of the substrate; The ninth power component and the tenth power component are connected in series in sequence to form a fourth series structure; the eleventh power component, the twelfth power component, the thirteenth power component, and the fourteenth power component are connected in series in sequence to form a fifth series structure; the first end of the fourth series structure is connected to the connection node between the eleventh power component and the twelfth power component, and the second end is connected to the connection node between the thirteenth power component and the fourteenth power component; the first end of the fifth series structure is connected to the second power terminal, and the second end is connected to the third power terminal; the connection node between the ninth power component and the tenth power component is connected to the first power terminal; the connection node between the twelfth power component and the thirteenth power component is connected to the sixth power terminal.

8. The three-level power unit according to claim 5, characterized in that: A third power component area, a first power component area, a second power component area and a fourth power component area are arranged in sequence along the first side direction of the substrate; the first power component is arranged in the first power component area, and the first power component includes X first power chips connected in parallel; the second power component is arranged in the second power component area, and the second power component includes X second power chips connected in parallel; the third power component is arranged in the third power component area, and the third power component includes Y third power chips connected in parallel; the fourth power component is arranged in the fourth power component area, and the fourth power component includes Y fourth power chips connected in parallel.

9. The three-level power unit according to claim 8, characterized in that: The three-level power unit layout structure also includes a control area; the control area is arranged on the substrate and on a side close to the fourth power terminal; the control area is sequentially arranged with a first control terminal, a second control terminal, a third control terminal, a fourth control terminal, a fifth control terminal, a sixth control terminal, a seventh control terminal, an eighth control terminal and a ninth control terminal along the first side direction of the substrate; The first control terminal, the second control terminal, and the third control terminal are respectively connected to the first control end, the second control end, and the third control end of the third power component; The fourth control terminal and the fifth control terminal are respectively connected to the first control end and the second control end of the first power component; The sixth control terminal is connected to the first control terminal of the second power component; The seventh control terminal, the eighth control terminal, and the ninth control terminal are respectively connected to the first control end, the second control end, and the third control end of the fourth power component.

10. The three-level power unit according to claim 9, characterized in that: The third control terminals of the fourth power components are electrically connected to the ninth control terminal through the sub-base.

11. A three-level power module, characterized in that: The three-level power module comprises M three-level power units according to any one of claims 1 to 10, where M is an integer greater than or equal to 1; The three-level power units are arranged in sequence along a first direction, the first direction is the same as a direction of a first side of the substrate, and the first side of the substrate is arranged opposite to the second side of the substrate.

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