Anti-radiation frequency multiplier applied to satellite-borne wireless communication system

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an anti-radiation frequency multiplier applied to a satellite-borne wireless communication system. The circuit structure comprises an anti-radiation frequency multiplier core circuit, a power detection circuit, an analog-to-digital converter and a control module. An input signal is input into the anti-radiation frequency multiplier core circuit, and a generated signal is output to the power detection circuit; the power detection circuit processes the received signal, outputs a processing result to the analog-to-digital converter, receives an instruction of the control module circuit and outputs a final signal; the analog-to-digital converter converts a processing result output by the power detection circuit into a digital signal and outputs the digital signal to the control module; and the control module performs judgment according to the input digital signal, generates a control signal for controlling the working mode of the anti-radiation frequency multiplier core circuit, and generates a control signal for controlling the power detection circuit and the analog-to-digital converter. Wherein the core circuit architecture of the anti-radiation frequency multiplier is a frequency multiplier which has backup and can be reorganized, and the actually working frequency multiplier branch is switched through a switch. By utilizing the structure, the probability of circuit failure caused by space irradiation can be obviously reduced, and the anti-irradiation performance and the stability of a satellite-borne wireless communication system are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a frequency multiplier. Background Art

[0002] A frequency multiplier is an electronic device that can multiply the frequency of an input signal by using the characteristics of non-linear elements or frequency control circuits. Frequency multipliers are widely used in fields such as wireless communication, radar, and measuring instruments. For example, in a wireless communication system, a frequency multiplier is used to double the frequency of an input signal to expand the frequency range of the communication system; in a radar system, a frequency multiplier is used to expand the detection range and resolution; in a measuring instrument, a frequency multiplier is used to improve the measurement accuracy.

[0003] Currently, the mainstream architectures of frequency multipliers can be divided into passive frequency multipliers and active frequency multipliers. Among them, the Gilbert double-balanced frequency multiplier is a high-performance active frequency multiplier. The Gilbert double-balanced frequency multiplier has good linearity, and there is little signal leakage between it and each port. The structure of the Gilbert double-balanced frequency multiplier provides good isolation performance, especially the isolation performance from the local oscillator port to the intermediate frequency port is improved compared with that of a single-balanced frequency multiplier.

[0004] With the progress of technology and the continuous expansion of the communication application field, more requirements are put forward for frequency multiplier circuits. In the aerospace field, the working environment of spaceborne chips is the space with strong radiation. The circuit modules in the chips are affected by radiation, having a higher failure probability and a shorter expected life. Therefore, in order to improve the performance of spaceborne chips, it is necessary to effectively utilize chip anti-radiation technology to improve the system stability and reliability. Summary of the Invention

[0005] The purpose of the present invention is to propose an anti-radiation frequency multiplier applied to spaceborne communication chips.

[0006] The frequency multiplier circuit structure proposed by the present invention includes: an anti-radiation frequency multiplier core circuit, a power detection circuit, an analog-to-digital converter, and a control module. An input signal is input to the anti-radiation frequency multiplier core circuit, and a signal is generated and output to the power detection circuit; the power detection circuit processes the signal it receives, outputs the processing result to the analog-to-digital converter, and receives the instruction of the control module circuit to output the final signal; the analog-to-digital converter converts the processing result output by the power detection circuit into a digital signal and outputs it to the control module; the control module makes a judgment according to the input digital signal, generates a control signal for controlling the working mode of the anti-radiation frequency multiplier core circuit, and generates control signals for controlling the power detection circuit and the analog-to-digital converter.

[0007] In the present invention, the core circuit of the anti-radiation frequency doubler is composed of two resistors, two capacitors, eight transistors, and four single-pole double-throw numerically controlled switches; under the control of the numerically controlled switches, these eight transistors and the reference current source can generate a total of four frequency doubler combinations. These four groups of frequency doublers are backup to each other and are controlled by the numerically controlled switches. Only one frequency doubler combination is used during actual normal operation; the numerically controlled switches switch the actually working frequency doubler combination according to the signals from the control module in the system, thereby greatly improving the anti-radiation performance and stability of the system. Description of the Drawings

[0008] Figure 1 It is a schematic structural diagram of the anti-radiation frequency doubler of the present invention.

[0009] Figure 2 It is a schematic diagram of the core circuit of the anti-radiation frequency doubler. Detailed Embodiment

[0010] The present invention will be described in more detail with reference to the accompanying drawings. In each of the drawings, like elements are denoted by like reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0011] Many specific details of the present invention, such as the structure, materials, dimensions, processing techniques, and technologies of the device, are described below in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0012] Figure 1 It shows a schematic structural diagram of the spaceborne anti-radiation frequency doubler of the present invention.

[0013] As Figure 1 shown, the spaceborne anti-radiation frequency doubler 100 in the present invention includes an anti-radiation frequency doubler core circuit 101, a power detection circuit 102, a control module 103, and an analog-to-digital converter 104. The external input signals Input+ and Input- serve as the input signals of the anti-radiation frequency doubler core circuit 101, and the output signals Output+ and Output- of the anti-radiation frequency doubler core circuit 101 are transmitted to the power detection circuit 102. The power detection circuit 102 outputs Output0+ and Output0- as the output signals of the entire frequency doubler circuit. The power detection circuit 102 outputs pdout to the analog-to-digital converter 104, the analog-to-digital converter 104 outputs adout to the control module 103, and the control module 103 outputs Ctrl<1:4> to the anti-radiation current mirror core circuit 101, outputs Ctrl5 to the power detection circuit 102, and outputs Ctrl6 to the analog-to-digital converter 104.

[0014] Figure 2Schematic diagram of the core circuit of the anti-radiation frequency doubler in the present invention is shown.

[0015] Such as Figure 2As shown, the core circuit of the radiation-resistant frequency doubler includes a total of four numerically controlled switches S1 - S4, two capacitors C1 - C2, two resistors R1 - R2, and eight transistors M0 - M7; under the control of the numerically controlled switches, the circuit has four working modes, and the circuit acts as a frequency doubler in each mode; when the core circuit of the radiation-resistant frequency doubler receives a control signal and enters the first working mode, switch S1 is connected to the fixed terminal 1.1, switch S2 is connected to the fixed terminal 2.1, switch S3 is connected to the fixed terminal 3.1, and switch S4 is connected to the fixed terminal 4.1. At this time, only M0, M1, M2, M3, M4, and M6 among the eight transistors actually work; when the core circuit of the radiation-resistant frequency doubler receives a control signal and enters the second working mode, switch S1 is connected to the fixed terminal 1.1, switch S2 is connected to the fixed terminal 2.1, switch S3 is connected to the fixed terminal 3.2, and switch S4 is connected to the fixed terminal 4.2. At this time, only M0, M1, M2, M3, M4, and M7 among the eight transistors actually work; when the core circuit of the radiation-resistant frequency doubler receives a control signal and enters the third working mode, switch S1 is connected to the fixed terminal 1.2, switch S2 is connected to the fixed terminal 2.2, switch S3 is connected to the fixed terminal 3.1, and switch S4 is connected to the fixed terminal 4.1. At this time, only M0, M1, M2, M3, M5, and M6 among the eight transistors actually work; when the core circuit of the radiation-resistant frequency doubler receives a control signal and enters the fourth working mode, switch S1 is connected to the fixed terminal 1.2, switch S2 is connected to the fixed terminal 2.2, switch S3 is connected to the fixed terminal 3.2, and switch S4 is connected to the fixed terminal 4.2. At this time, only M0, M1, M2, M3, M5, and M7 among the eight transistors actually work.In this circuit, one end of resistor R1 is connected to bias voltage VB, and the other end is connected to capacitor C1 and the gates of transistors M0 and M3; one end of resistor R2 is connected to bias voltage VB, and the other end is connected to capacitor C2 and the gates of transistors M1 and M2; one end of capacitor C1 is connected to resistor R1 and the gates of transistors M0 and M3, and the other end is connected to the movable end of switch S2 and external input terminal Input+; one end of capacitor C2 is connected to resistor R2 and the gates of transistors M1 and M2, and the other end is connected to the movable end of switch S3 and external input terminal Input-; the gate of transistor M0 is connected to resistor R1, capacitor C1 and the gate of transistor M3, the drain of M0 is connected to output terminal Output+ and the drain of transistor M2, and the source of M0 is connected to the movable end of switch S1 and the source of transistor M1; the gate of transistor M1 is connected to resistor R2, capacitor C2 and the gate of transistor M2, the drain of M1 is connected to output terminal Output- and the drain of transistor M3, and the source of M1 is connected to the movable end of switch S1 and the source of transistor M0; the gate of transistor M2 is connected to resistor R2, capacitor C2 and the gate of transistor M1, the drain of M2 is connected to output terminal Output+ and the drain of transistor M0, and the source of M2 is connected to the movable end of switch S4 and the source of transistor M3; the gate of transistor M3 is connected to resistor R1, capacitor C1 and the gate of transistor M0, the drain of M3 is connected to output terminal Output- and the drain of transistor M1, and the source of M3 is connected to the movable end of switch S4 and the source of transistor M2; the gate of transistor M4 is connected to the fixed end 2.1 of switch S2, the drain is connected to the fixed end 1.1 of switch S1, and the source is grounded; the gate of transistor M5 is connected to the fixed end 2.2 of switch S2, the drain is connected to the fixed end 1.2 of switch S1, and the source is grounded; the gate of transistor M6 is connected to the fixed end 3.1 of switch S3, the drain is connected to the fixed end 4.1 of switch S4, and the source is grounded; the gate of transistor M7 is connected to the fixed end 3.2 of switch S3, the drain is connected to the fixed end 4.2 of switch S4, and the source is grounded; signal input terminal Input+ is connected to capacitor C1 and the movable end of switch S2; signal input terminal Input- is connected to capacitor C2 and the movable end of switch S3; signal output terminal Output+ is connected to the drains of transistors M0 and M2; signal output terminal Output- is connected to the drains of transistors M1 and M3. The core of this circuit structure is that the control signal can change the states of switches S1 - S4, thereby changing the working mode of the circuit. The circuit has four working modes and all of them function as frequency multipliers. Each working mode actually only uses six out of the eight transistors, and the other two transistors can be used as backups. When space radiation causes some of the working transistors to fail, the control signal can change the switch states, thereby changing the working mode of the circuit, enabling the normal transistors to be connected to the working circuit, thus greatly improving the stability and reliability of the system.

Claims

1. A frequency multiplier applied to a satellite communication chip, the circuit structure of which comprises: The core circuit of the radiation-resistant frequency multiplier, the power detection circuit, the analog-to-digital converter and the control module. The input signal is input to the core circuit of the radiation-resistant frequency multiplier, and the generated signal is output to the power detection circuit; the power detection circuit processes the received signal, outputs the processing result to the analog-to-digital converter, and receives the instruction of the control module circuit to output the final signal; The analog-to-digital converter converts the processing result output by the power detection circuit into a digital signal and outputs it to the control module; the control module makes a judgment based on the input digital signal, generates a control signal for controlling the working mode of the core circuit of the radiation-resistant frequency multiplier, and generates a control signal for controlling the power detection circuit and the analog-to-digital converter.

2. The frequency multiplier for satellite communication chip according to claim 1, characterized in that: The core circuit of the radiation-resistant frequency multiplier consists of two resistors, two capacitors, eight transistors and four single-pole double-throw digital switches; under the control of the digital switches, these eight transistors and the reference current source can generate a total of four frequency multiplier combinations. These four sets of frequency multipliers are backed up for each other and are controlled by the digital switches. In actual normal operation, only one frequency multiplier combination is used; the digital switches switch the actual working frequency multiplier combination according to the signal of the control module in the system, thereby greatly improving the radiation resistance and stability of the system.

3. The frequency multiplier for satellite communication chip according to claim 2, characterized in that: The core circuit of the radiation-resistant frequency multiplier includes four digital switches S1-S4, two capacitors C1-C2, two resistors R1-R2 and eight transistors M0-M7; under the control of the digital switches, the circuit has four working modes, and the circuit acts as a frequency multiplier in each mode; when the core circuit of the radiation-resistant frequency multiplier receives a control signal and enters the first working mode, switch S1 is connected to the fixed terminal 1.1, switch S2 is connected to the fixed terminal 2.1, switch S3 is connected to the fixed terminal 3.1, and switch S4 is connected to the fixed terminal 4.

1. At this time, only M0, M1, M2, M3, M4, and M6 of the eight transistors actually work; when the core circuit of the radiation-resistant frequency multiplier receives a control signal and enters the second working mode, switch S1 is connected to the fixed terminal 1.1, switch S2 is connected to the fixed terminal 2.1, switch S3 is connected to the fixed terminal 3.2, and switch S4 is connected to the fixed terminal 4.

2. At this time, only M0, M1, M2, M3, M4, and M7 of the eight transistors actually work; when the core circuit of the radiation-resistant frequency multiplier receives a control signal to enter the third working mode, switch S1 is connected to the fixed terminal 1.2, switch S2 is connected to the fixed terminal 2.2, switch S3 is connected to the fixed terminal 3.1, and switch S4 is connected to the fixed terminal 4.

1. At this time, only M0, M1, M2, M3, M5, and M6 of the eight transistors actually work; when the core circuit of the radiation-resistant frequency multiplier receives a control signal to enter the fourth working mode, switch S1 is connected to the fixed terminal 1.2, switch S2 is connected to the fixed terminal 2.2, switch S3 is connected to the fixed terminal 3.2, and switch S4 is connected to the fixed terminal 4.

2. At this time, only M0, M1, M2, M3, M5, and M7 of the eight transistors actually work. In the circuit, one end of the resistor R1 is connected to the bias voltage VB, and the other end is connected to the capacitor C1 and the gates of the transistors M0 and M3; one end of the resistor R2 is connected to the bias voltage VB, and the other end is connected to the capacitor C2 and the gates of the transistors M1 and M2; one end of the capacitor C1 is connected to the resistor R1 and the gates of the transistors M0 and M3, and the other end is connected to the moving end of the switch S2 and the external input terminal Input+; one end of the capacitor C2 is connected to the resistor R2 and the gates of the transistors M1 and M2, and the other end is connected to the moving end of the switch S3 and the external input terminal Input-; The gate of transistor M0 is connected to resistor R1, capacitor C1 and the gate of transistor M3, the drain of M0 is connected to the output terminal Output+ and the drain of transistor M2, and the source of M0 is connected to the active end of switch S1 and the source of transistor M1; The gate of transistor M1 is connected to resistor R2, capacitor C2 and the gate of transistor M2, the drain of M1 is connected to the output terminal Output- and the drain of transistor M3, and the source of M1 is connected to the active terminal of switch S1 and the source of transistor M0; The gate of transistor M2 is connected to resistor R2, capacitor C2 and the gate of transistor M1, the drain of M2 is connected to the output terminal Output+ and the drain of transistor M0, and the source of M2 is connected to the active terminal of switch S4 and the source of transistor M3; The gate of transistor M3 is connected to resistor R1, capacitor C1 and the gate of transistor M0, the drain of M3 is connected to the output terminal Output- and the drain of transistor M1, and the source of M3 is connected to the active terminal of switch S4 and the source of transistor M2; The gate of transistor M4 is connected to the fixed terminal 2.1 of switch S2, the drain is connected to the fixed terminal 1.1 of switch S1, and the source is grounded; the gate of transistor M5 is connected to the fixed terminal 2.2 of switch S2, the drain is connected to the fixed terminal 1.2 of switch S1, and the source is grounded; the gate of transistor M6 is connected to the fixed terminal 3.1 of switch S3, the drain is connected to the fixed terminal 4.1 of switch S4, and the source is grounded; the gate of transistor M7 is connected to the fixed terminal 3.2 of switch S3, the drain is connected to the fixed terminal 4.2 of switch S4, and the source is grounded; the signal input terminal Input+ is connected to the capacitor C1 and the moving terminal of switch S2; the signal input terminal Input- is connected to the capacitor C2 and the moving terminal of switch S3; the signal output terminal Output+ is connected to the drains of transistors M0 and M2; the signal output terminal Output- is connected to the drains of transistors M1 and M3. The core of this circuit structure is that the control signal can change the state of switches S1-S4 and thus change the working mode of the circuit. The circuit has four working modes and all act as frequency multipliers. Each working mode actually uses only six of the eight transistors, and the other two transistors can be used as backups. When space radiation causes some working transistors to fail, the control signal can change the switch state and thus change the working mode of the circuit, allowing normal transistors to be connected to the working circuit, thereby greatly improving the stability and reliability of the system.

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