Multi-channel small signal amplifier for microcomputer type variable capacitor array

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a multi-channel small signal amplifier for a microcomputer type variable capacitor array. The amplifier comprises a microcomputer type variable capacitor array, a front signal switch array, a rear signal switch array, a synchronous clock control module and a signal amplifier, an initial small signal is generated by an acoustic signal received by the variable capacitor array and is input to the pre-switch array, and the synchronous clock control module selects an array element signal channel of the pre-switch array; a single small signal output by the front switch array is amplified by the signal amplifier and then is output to the rear switch array, and array elements of the rear switch array are selected by the synchronous clock control module. And a control signal of the synchronous clock control module synchronously selects the front switch array and the rear switch array. According to the invention, multi-channel accurate output control of the microcomputer type variable capacitor array under the condition of a small number of amplifiers can be realized, the cost of utilizing other microcontrollers is saved, the circuit power consumption is low, the occupied volume is small, and the structure is simple, reliable and durable.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a multi-channel small-signal amplifier. Background Art

[0002] The multi-channel small-signal amplifier applied to a microcomputer-based variable capacitor array is composed of system components. Its principle is to amplify small signals of multiple channels for subsequent acquisition, analysis, and processing. As a key link in the signal processing chain, the performance of the multi-channel small-signal amplifier directly affects the performance indicators of the entire system. With the rapid development of electronic technology, multi-channel signal processing systems have been widely used in fields such as communication, medical treatment, and industrial control. In these systems, higher requirements are put forward for the consistency of gain and bandwidth, the quality of amplified signals, and the cost of multi-channel amplifiers. Traditional multi-channel small-signal amplifiers usually adopt the following several schemes: building a multi-channel amplifier with discrete components, integrating a multi-channel operational amplifier, and a multi-channel amplifier based on switched-capacitor technology.

[0003] Among the above several multi-channel amplifiers, the integrated multi-channel operational amplifier has the advantages of small volume, high integration, and good inter-channel consistency. The multi-channel amplifier based on switched-capacitor technology uses the switching frequency of a clock-controlled switch to ensure the correct sampling and transmission of signals. Multiple switched-capacitor circuits can work in parallel, and each channel independently completes signal sampling, holding, and amplification.

[0004] In a sensor system composed of a microcomputer-based variable capacitor array, the more the number of array elements of the sensor acquisition signal array, the higher the required transmission power and the greater the energy consumption; the receiving circuit is also in this system, and it is also very important to eliminate the crosstalk problem between amplified signals of multiple channels. Therefore, a multi-channel small-signal amplifier with lower power consumption, higher integration, and smaller crosstalk is expected. Summary of the Invention

[0005] The object of the present invention is to provide a multi-channel small-signal amplifier with high integration, low power consumption, and low crosstalk applied to a microcomputer-based variable capacitor array.

[0006] The multi-channel small-signal amplifier for a microcomputer-based variable capacitor array proposed by the present invention has a circuit structure including: a microcomputer-based variable capacitor array, a front-end signal switch array, a signal amplifier, a synchronous clock control module, and a rear-end signal switch array; an initial small signal is generated by the variable capacitor array receiving an acoustic signal, and the multi-channel small signals generated by the variable capacitor array are input to the front-end switch array, and the synchronous clock control module selects the element signal channels of the front-end switch array; the single small signal output by the front-end switch array is amplified by the signal amplifier and then output to the rear-end switch array, and the rear-end switch array also has its elements selected by the synchronous clock control module; the control signals of the synchronous clock control module synchronously select the front-end switch array and the rear-end switch array; that is, the two switch array modules are kept synchronous.

[0007] In the present invention, the synchronous clock control module includes a synchronous clock single-pulse generation module, a clock generation module, and a switch selector; the synchronous clock single-pulse generation module and the clock generation module each have an independent enable signal input terminal and are connected to each other. The synchronous clock single-pulse generation module has an independent clock input terminal. The switch selector has an independent synchronous clock single-pulse signal input terminal and an independent clock signal input terminal; the synchronous clock single-pulse generation module has an independent output terminal, which is connected to the input terminal of the synchronous clock single-pulse signal of the switch selector; the clock generation module has an independent output terminal, which is connected to the clock signal input terminal of the switch selector and the clock input terminal of the synchronous clock single-pulse generation module; the output terminal of the switch selector has N independent switch array control signal output ports, which are respectively connected to the N independent element switch enable terminals of the front-end and rear-end switch arrays.

[0008] In the present invention, the synchronous clock single-pulse generation module in the synchronous clock control module includes: two transistors M1, M2, two inverters C1, C2, and two D flip-flops D1, D2; the enable signal is connected to the gates of transistors M1 and M2. The drain of transistor M1 is connected to the power supply VDD, and the drain of transistor M2 is grounded. Transistor M1 and transistor M2 are connected and connected to the data input terminal of D flip-flop D1; the data output terminal of D flip-flop D1 is connected to the data input of D flip-flop D2, and the data output terminal of D flip-flop D2 is connected to the output terminal of the synchronous clock single-pulse signal module; the clock signal is connected to the input terminal of inverter C1, and the output terminal of inverter C1 is connected to the chip select enable terminal of D flip-flop D1 and the input terminal of inverter C2; the output terminal of inverter C2 is connected to the chip select enable terminal of D flip-flop D2.

[0009] In the present invention, the switch selector in the synchronous clock control module includes N D flip-flops triggered by the rising edge of the clock and one transistor M3. The source of the transistor M3 is connected to its gate and is connected to the input terminal of the synchronous clock single-pulse signal. The drain of the transistor M3 is connected to the data input terminal of the first flip-flop among the N D flip-flops triggered by the rising edge of the clock. The data output terminal of the X-th flip-flop among the N D flip-flops triggered by the rising edge of the clock is connected to the data input terminal of the next (i.e., the (X + 1)-th) flip-flop (X = 1, 2,...), and the data output terminal of the N-th flip-flop is connected to the data input terminal of the first flip-flop. The N data input terminals of the N D flip-flops triggered by the rising edge of the clock are respectively connected to N independent switch control signal output ports, and the clock signal input terminal is connected to the clock input terminals of the N D flip-flops triggered by the rising edge of the clock.

[0010] In the multi-channel small-signal amplifier designed by the present invention, due to the triggering of the switch selector by the single pulse generated by the synchronous clock single-pulse generation module after triggering, the jointly constituted synchronous clock control module can independently control the switch array elements. Only one signal is amplified by the signal amplifier in each clock cycle, thereby realizing the design of a signal multi-channel amplification circuit with low power consumption, high integration, low cost, and low crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural diagram of the low-power, high-integration, low-crosstalk, and low-cost multi-channel small-signal amplifier of the present invention.

[0012] Figure 2 It is a structural diagram of the synchronous clock control module in the present invention.

[0013] Figure 3 It is a circuit diagram of the synchronous clock single-pulse generation module in the synchronous clock control module.

[0014] Figure 4 It is a circuit diagram of the switch selector in the synchronous clock control module. DETAILED DESCRIPTION OF THE INVENTION

[0015] The present invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, the same elements are denoted by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0016] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques, and technologies of the devices, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0017] Figure 1Shows the structural schematic diagram of the low-power, high-integration, low-crosstalk, low-cost multi-channel small-signal amplifier of the present invention.

[0018] As Figure 1 shown, the low-power, high-integration, low-crosstalk, low-cost multi-channel small-signal amplifier 100 in the present invention includes a microcomputer-type variable capacitor array 101, a front-end switch array 102, a signal amplifier 103, a rear-end switch array 104, and a synchronous clock control module 105. The small-signal multi-channels generated by the microcomputer-type variable capacitor array 101 are input to the front-end switch array 102, and the synchronous clock control module 105 selects the element signal channels of the front-end switch array 102; the single small-signal output by the front-end switch array 102 is input to the signal amplifier 103, and the signal amplified by the signal amplifier 103 is output to the rear-end switch array 104. The rear-end switch array 104 also has its elements selected by the synchronous clock control module 105; the control signal of the synchronous clock control module 105 synchronously selects the front-end switch array 102 and the rear-end switch array 104.

[0019] Figure 2 Shows the schematic diagram of the synchronous clock control module of the present invention.

[0020] As Figure 2 shown, the synchronous clock control module 200 includes a synchronous clock single-pulse generation module 201, a clock generation module 202, and a switch controller 203. The synchronous clock single-pulse generation module 201 and the clock generation module 202 each have an independent enable signal input terminal and are connected to each other. The synchronous clock single-pulse generation module 201 has an independent clock input terminal. The switch selector 203 has an independent synchronous clock single-pulse signal input terminal and an independent clock signal input terminal; the synchronous clock single-pulse generation module 201 has an independent output terminal, which is connected to the input terminal of the synchronous clock single-pulse signal of the switch selector 203; the clock generation module 202 has an independent output terminal, which is connected to the clock signal input terminal of the switch selector 203 and the clock input terminal of the synchronous clock single-pulse generation module 201; the output terminal of the switch selector 203 has N independent array switch control signal output ports, which are respectively connected to the N independent element switch enable terminals of the front-end switch array 102 and the rear-end switch array 104.

[0021] Figure 3 Is the circuit schematic diagram of the synchronous clock single-pulse generation module in the synchronous clock control module.

[0022] As Figure 3As shown, the synchronous clock single-pulse generation module 201 includes two transistors M1 (PMOS transistor) and M2 (NMOS transistor), two inverters C1 and C2, and two D flip-flops D1 and D2. The enable signal is connected to the gates of transistors M1 (PMOS transistor) and M2 (NMOS transistor). The drain of transistor M1 (PMOS transistor) is connected to the power supply VDD, the drain of transistor M2 (NMOS transistor) is grounded, and transistors M1 (PMOS transistor) and M2 (NMOS transistor) are connected and also connected to the data input terminal of D1 flip-flop. The data output terminal of D1 flip-flop is connected to the data input of D2 flip-flop, and the data output terminal of D2 flip-flop is connected to the output terminal of the synchronous clock single-pulse signal module 201. The clock signal is connected to the input terminal of inverter C1, and the output terminal of inverter C1 is connected to the chip select enable terminal of flip-flop D1 and the input terminal of inverter C2. The output terminal of inverter C2 is connected to the chip select enable terminal of flip-flop D2.

[0023] Figure 4 It is a circuit schematic diagram of the switch selector in the synchronous clock control module.

[0024] As Figure 4 shown, the switch selector 203 includes N D flip-flops triggered by the rising edge of the clock and one transistor M3 (PMOS transistor). The source of transistor M3 (PMOS transistor) is connected to its gate and also connected to the input terminal of the synchronous clock single-pulse signal. The drain of transistor M3 (PMOS transistor) is connected to the data input terminal of the first flip-flop among the N D flip-flops triggered by the rising edge of the clock. The data output terminal of the Xth flip-flop among the N D flip-flops triggered by the rising edge of the clock is connected to the data input terminal of the (X + 1)th flip-flop, where the data output terminal of the Nth flip-flop is connected to the data input terminal of the first flip-flop. The N data input terminals of the N D flip-flops triggered by the rising edge of the clock are respectively connected to N independent switch array control signal output ports, and the clock signal input terminal is connected to the clock input terminals of the N D flip-flops triggered by the rising edge of the clock.

[0025] In this article, the term "including", "containing" or any other variant thereof is intended to cover non-exclusive inclusion, so that a series of elements (such as processes, methods, articles or devices) included not only include those elements, but also other elements not explicitly listed. Without further limitations, an element defined by the statement "including one..." does not exclude the existence of another identical element outside the included element.

[0026] In the present invention, the embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. According to the above description, many changes can be made. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A multi-channel small signal amplifier for a microcomputer-based variable capacitor array, characterized in that: The circuit structure includes: a microcomputer-type variable capacitor array, a front switch array, a signal amplifier, a synchronous clock control module and a rear switch array; the initial small signal is generated by the acoustic signal received by the variable capacitor array, the multi-channel small signal generated by the variable capacitor array is input to the front switch array, and the synchronous clock control module selects the array element signal channel of the front switch array; the single small signal output by the front switch array is amplified by the signal amplifier and then output to the rear switch array, and the array element of the rear switch array is also selected by the synchronous clock control module; the control signal of the synchronous clock control module synchronously selects the front switch array and the rear switch array.

2. The multi-channel small signal amplifier according to claim 1, characterized in that: The synchronous clock control module includes a synchronous clock single pulse generation module, a clock generation module and a switch controller; the synchronous clock single pulse generation module and the clock generation module each have an independent enable signal input terminal and the two are connected, the synchronous clock single pulse generation module has an independent clock input terminal, and the switch selector has an independent synchronous clock single pulse signal input terminal and an independent clock signal input terminal; the synchronous clock single pulse generation module has an independent output terminal, which is connected to the synchronous clock single pulse signal input terminal of the switch selector; the clock generation module has an independent output terminal, which is connected to the clock signal input terminal of the switch selector and the clock input terminal of the synchronous clock single pulse generation module; the switch selector output terminal has N independent switch array control signal output ports, which are respectively connected to N independent array element switch enable terminals of the front and rear switch arrays.

3. The multi-channel small signal amplifier according to claim 2, characterized in that: The synchronous clock single pulse generation module in the synchronous clock control module includes two transistors M1 and M2, two inverters C1 and C2 and two D flip-flops D1 and D2; the enable signal is connected to the gates of transistors M1 and M2, the drain of transistor M1 is connected to the power supply VDD, the drain of transistor M2 is grounded, transistors M1 and M2 are connected and connected to the data input end of the D flip-flop D1; the data output end of the D flip-flop D1 is connected to the data input of the D flip-flop D2, and the data output end of the D flip-flop D2 is connected to the output end of the synchronous clock single pulse signal module; the clock signal is connected to the input end of the inverter C1, the output end of the inverter C1 is connected to the chip select enable end of the D flip-flop D1 and the input end of the inverter C2; the output end of the inverter C2 is connected to the chip select enable end of the D flip-flop D2.

4. The multi-channel small signal amplifier according to claim 3, characterized in that: The switch selector in the synchronous clock control module includes N D flip-flops triggered by the rising edge of the clock and a transistor M3; The source of the transistor M3 is connected to the gate of the transistor M3 and to the input terminal of the synchronous clock single pulse signal, and the drain of the transistor M3 is connected to the data input terminal of the first trigger among the N clock rising edge triggered D triggers; the data output terminal of the Xth trigger among the N clock rising edge triggered D triggers is connected to the data input terminal of the X+1th trigger, wherein the data output terminal of the Nth trigger is connected to the data input terminal of the first trigger; the N data input terminals of the N clock rising edge triggered D triggers are respectively connected to the N independent switch control signal output ports, and the clock signal input terminal is connected to the clock input terminal of the N clock rising edge triggered D triggers.

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