Self-return-to-zero amplification circuit and analog front-end detection circuit

Abstract

The invention relates to a self-return-to-zero amplification circuit and an analog front-end detection circuit. The self-return-to-zero amplification circuit comprises a main amplification circuit, a first compensation amplification circuit and a second compensation amplification circuit, the main amplification circuit is used for generating an initial amplification voltage signal; the first compensation amplification circuit and the second compensation amplification circuit are used for alternately generating a first compensation signal and a second compensation signal. According to the self-return-to-zero amplification circuit, the two compensation amplification circuits are adopted to alternately generate the first compensation signal and the second compensation signal, so that one of the compensation amplification circuits generates the second compensation signal to compensate the offset voltage of the main amplification circuit; the offset voltage of one compensation amplification circuit is compensated by the first compensation signal generated by the other compensation amplification circuit, and the offset voltage of the compensation amplification circuit is prevented from being compensated to the main amplifier, so that the compensation precision of the offset voltage of the main amplifier is improved, the signal noise is reduced, and the detection precision is improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and particularly to a self-zeroing amplification circuit and an analog front-end detection circuit. Background Art

[0002] With the rapid development of integrated circuits and the rise of the Internet of Things, magnetic sensors are widely used in various fields. A magnetic sensor can convert a weak magnetic signal into an electrical signal, thereby indirectly detecting physical quantity information related to a magnetic field.

[0003] Magnetic sensors have characteristics such as high sensitivity and a wide dynamic range. However, the induction signal of a magnetic sensor is a weak voltage signal. Therefore, an amplifier is required to amplify the weak voltage signal to obtain an amplified voltage signal for detecting the weak voltage signal. However, during the process of amplifying the weak voltage signal, affected by the zero offset of the weak voltage signal itself and the offset voltage of the amplifier itself, the amplified voltage signal output by the amplifier has an offset voltage, resulting in a high noise and low precision of the signal. In addition, the amplification range of some existing amplification circuits is narrow and the circuit structure is complex, resulting in a high cost. Summary of the Invention

[0004] The present invention provides a self-zeroing amplification circuit and an analog front-end detection circuit to solve at least one of the above technical problems.

[0005] The technical solution of the present invention for solving the above technical problems is as follows: A self-zeroing amplification circuit includes:

[0006] A first differential input terminal for inputting a first differential voltage signal;

[0007] A second differential input terminal for inputting a second differential voltage signal;

[0008] A main amplification circuit, connected to the first differential input terminal and the second differential input terminal, for amplifying the difference between the first differential voltage signal and the second differential voltage signal to generate an initial amplified voltage signal; the main amplification circuit includes a main amplifier, and the main amplifier outputs the initial amplified voltage signal;

[0009] A first compensation amplification circuit, the first compensation amplification circuit includes a first compensation input terminal, a second compensation input terminal and a first compensation output terminal; the first compensation input terminal is connected to the non-inverting input terminal of the main amplifier, the second compensation input terminal is connected to the inverting input terminal of the main amplifier, and the first compensation output terminal is connected to the output terminal of the main amplifier;

[0010] A second compensation amplifier circuit, the second compensation amplifier circuit including a third compensation input terminal, a fourth compensation input terminal, and a second compensation output terminal; the third compensation input terminal is connected to the non-inverting input terminal of the main amplifier, the fourth compensation input terminal is connected to the inverting input terminal of the main amplifier, and the second compensation output terminal is connected to the first compensation output terminal;

[0011] The first compensation amplifier circuit and the second compensation amplifier circuit are used to alternately generate a first compensation signal and a second compensation signal, and the first compensation signal compensates for the offset voltage of the second compensation signal, and the second compensation signal compensated by the first compensation signal compensates for the offset voltage of the initial amplified voltage signal to generate a zero self - reset amplified voltage signal.

[0012] The beneficial effects of the present invention are as follows: A zero self - reset amplifier circuit of the present invention compensates for the offset voltage of the main amplifier by setting a second compensation signal generated by a compensation amplifier circuit. At the same time, in order to avoid the offset voltage of the compensation amplifier circuit itself being compensated to the main amplifier and causing a compensation error, it is also necessary to compensate for the offset voltage of the compensation amplifier circuit itself. Therefore, the present invention uses two compensation amplifier circuits to alternately generate a first compensation signal and a second compensation signal, so that before one of the compensation amplifier circuits generates a second compensation signal to compensate for the offset voltage of the main amplifier circuit, the other compensation amplifier circuit generates a first compensation signal to compensate for its own offset voltage, avoiding the offset voltage of the compensation amplifier circuit itself being compensated to the main amplifier, thereby improving the compensation accuracy of the offset voltage of the main amplifier, further reducing the signal noise, and improving the detection accuracy.

[0013] On the basis of the above - mentioned technical solution, the present invention can be further improved as follows.

[0014] Further, the first compensation amplifier circuit further includes a first switch circuit and a first auxiliary amplifier, the first switch circuit is connected to the first compensation input terminal and the second compensation input terminal and receives non - overlapping first clock signal and second clock signal, and the first auxiliary amplifier is connected to the first switch circuit and the first compensation output terminal;

[0015] The first switch circuit is used to control the conduction or disconnection between the first auxiliary amplifier and the main amplifier according to the first clock signal, and to control the disconnection or short - circuit between the positive and negative input terminals of the first auxiliary amplifier according to the second clock signal;

[0016] When the first clock signal controls the conduction between the first auxiliary amplifier and the main amplifier, the first auxiliary amplifier is used to generate the second compensation signal; and when the second clock signal controls the short - circuit between the positive and negative input terminals of the first auxiliary amplifier, the first auxiliary amplifier is used to generate the first compensation signal.

[0017] Further, the first switching circuit includes:

[0018] A first switch group, connected to the first clock signal. The first switch group includes a first switch and a second switch. The first switch is connected in series between the first compensation input terminal and the positive-phase input terminal of the first auxiliary amplifier, and the second switch is connected in series between the second compensation input terminal and the negative-phase input terminal of the first auxiliary amplifier. The first switch group is used to control the conduction or disconnection between the main amplifier and the first auxiliary amplifier according to the first clock signal;

[0019] A third switch, connected to the second clock signal and connected in series between the positive-phase and negative-phase input terminals of the first auxiliary amplifier, and is used to control the disconnection or short-circuit between the positive-phase and negative-phase input terminals of the first auxiliary amplifier according to the second clock signal.

[0020] Further, the second compensation amplification circuit further includes a second switching circuit and a second auxiliary amplifier. The second switching circuit is connected to the third compensation input terminal and the fourth compensation input terminal and is connected to non-overlapping first clock signal and second clock signal. The second auxiliary amplifier is connected to the second switching circuit and the second compensation output terminal;

[0021] The second switching circuit is used to control the disconnection or conduction between the second auxiliary amplifier and the main amplifier according to the second clock signal, and to control the short-circuit or disconnection between the positive-phase and negative-phase input terminals of the second auxiliary amplifier according to the first clock signal;

[0022] When the second clock signal controls the conduction between the second auxiliary amplifier and the main amplifier, the second auxiliary amplifier is used to generate the second compensation signal; and when the first clock signal controls the short-circuit between the positive-phase and negative-phase input terminals of the second auxiliary amplifier, the second auxiliary amplifier generates the first compensation signal.

[0023] Further, the second switching circuit includes:

[0024] A second switch group, connected to the second clock signal. The second switch group includes a fourth switch and a fifth switch. The fourth switch is connected in series between the third compensation input terminal and the positive-phase input terminal of the second auxiliary amplifier, and the fifth switch is connected in series between the fourth compensation input terminal and the negative-phase input terminal of the second auxiliary amplifier. The second switch group is used to control the disconnection or conduction between the main amplifier and the second auxiliary amplifier according to the second clock signal;

[0025] The sixth switch is connected to the first clock signal and is serially connected between the positive and negative input terminals of the second auxiliary amplifier, and is used to control the short - circuit or disconnection between the positive and negative input terminals of the second auxiliary amplifier according to the first clock signal.

[0026] Furthermore, it further includes:

[0027] The first subtractor circuit is connected to the first compensation output terminal and the second compensation output terminal, and is used to perform a subtraction operation on the second compensation signal and the first compensation signal, so that the first compensation signal compensates for the offset voltage of the second compensation signal, and then generates a third compensation signal.

[0028] Furthermore, it further includes:

[0029] The second subtractor circuit is connected to the main amplifier and the first subtractor circuit, and is used to perform a subtraction operation on the initial amplified voltage signal and the third compensation signal, so that the third compensation signal compensates for the offset voltage of the initial amplified voltage signal, and then generates a self - zeroing amplified voltage signal.

[0030] Furthermore, the first compensation amplifier circuit further includes a first RC filter and a second RC filter. Among them, the first RC filter is connected between the positive input terminal of the main amplifier and the first compensation input terminal; the second RC filter is connected between the negative input terminal of the main amplifier and the second compensation input terminal.

[0031] Based on the above self - zeroing amplifier circuit, the present invention further provides an analog front - end detection circuit; this analog front - end detection circuit includes:

[0032] A first differential input terminal group for accessing a first differential voltage signal group and a second differential input terminal group for accessing a second differential voltage signal group;

[0033] The first primary amplifier circuit is connected to the first differential input terminal group and is used to amplify the difference between the first differential voltage signal group to obtain a first primary amplified signal;

[0034] The second primary amplifier circuit is connected to the second differential input terminal group and is used to amplify the difference between the second differential voltage signal group to obtain a second primary amplified signal;

[0035] The logic operation circuit is connected to the first primary amplifier circuit and the second primary amplifier circuit, and is used to perform an addition or subtraction operation on the first primary amplified signal and the second primary amplified signal to obtain a logic operation signal;

[0036] A second-stage amplifier circuit, connected to the logic operation circuit, for amplifying the logic operation signal to obtain a first differential voltage signal and a second differential voltage signal; and

[0037] The self-zeroing amplifier circuit as described above, connected to the second-stage amplifier circuit, for performing signal amplification processing based on offset voltage compensation on the first differential voltage signal and the second differential voltage signal to generate a self-zeroing amplified voltage signal.

[0038] The beneficial effects of the present invention are as follows: An analog front-end detection circuit provided by the present invention can achieve a wider amplification range by adopting a three-stage amplification architecture of a first-stage amplifier circuit, a second-stage amplifier circuit, and a self-zeroing amplifier circuit; at the same time, the three-stage amplification architecture of the analog front-end detection circuit of the present invention is such that after the signal is amplified by the first-stage amplifier circuit, it is combined through logic operation and then subjected to two subsequent cascaded amplifications. Compared with a completely independent three-stage amplification architecture, the three-stage amplification architecture of the analog front-end detection circuit of the present invention is simpler, and thus the cost is also lower. On the basis of the above technical solutions, the present invention can be further improved as follows.

[0039] Further, it further includes a correction circuit, and the correction circuit is connected to the logic operation circuit for providing a correction signal to compensate for the zero offset of the first differential voltage signal group and the second differential voltage signal group in the logic operation circuit through the correction signal. Description of the Drawings

[0040] Figure 1 It is a structural block diagram of a self-zeroing amplifier circuit of the present invention;

[0041] Figure 2 It is a schematic diagram of a self-zeroing amplifier circuit of the present invention;

[0042] Figure 3 It is a waveform diagram of a first clock signal and a second clock signal;

[0043] Figure 4 It is another schematic diagram of a self-zeroing amplifier circuit of the present invention;

[0044] Figure 5 It is a structural block diagram of an analog front-end detection circuit of the present invention;

[0045] Figure 6 It is another structural block diagram of an analog front-end detection circuit of the present invention. Detailed Embodiments

[0046] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0047] AsFigure 1 As shown in Figure 1 , a self-zeroing amplifier circuit 100 includes:

[0048] A first differential input terminal 1 for inputting a first differential voltage signal VIP;

[0049] A second differential input terminal 2 for inputting a second differential voltage signal VIN;

[0050] A main amplifier circuit 3, connected to the first differential input terminal 1 and the second differential input terminal 2, for amplifying the difference between the first differential voltage signal VIP and the second differential voltage signal VIN to generate an initial amplified voltage signal VOUT'; the main amplifier circuit 3 includes a main amplifier A1, and the main amplifier A1 outputs the initial amplified voltage signal VOUT';

[0051] A first compensation amplifier circuit 4, the first compensation amplifier circuit 4 includes a first compensation input terminal 41, a second compensation input terminal 42 and a first compensation output terminal 43; the first compensation input terminal 41 is connected to the non-inverting input terminal of the main amplifier A1, the second compensation input terminal 42 is connected to the inverting input terminal of the main amplifier A1, and the first compensation output terminal 43 is connected to the output terminal of the main amplifier A1;

[0052] A second compensation amplifier circuit 5, the second compensation amplifier circuit 5 includes a third compensation input terminal 51, a fourth compensation input terminal 52 and a second compensation output terminal 53; the third compensation input terminal 51 is connected to the non-inverting input terminal of the main amplifier A1, the fourth compensation input terminal 52 is connected to the inverting input terminal of the main amplifier A1, and the second compensation output terminal 53 is connected to the first compensation output terminal 43;

[0053] The first compensation amplifier circuit 4 and the second compensation amplifier circuit 5 are used to alternately generate a first compensation signal S1 and a second compensation signal S2, and the first compensation signal S1 compensates for the offset voltage of the second compensation signal S2, and the second compensation signal S2 compensated by the first compensation signal S1 compensates for the offset voltage of the initial amplified voltage signal VOUT' to generate a self-zeroing amplified voltage signal VOUT.

[0054] In this embodiment, due to the offset voltage existing in the main amplifier A1 itself, the initial amplified voltage signal VOUT′ output has noise, resulting in low detection result accuracy. Therefore, the present invention provides a self-zeroing amplifier circuit 100, which compensates for the offset voltage of the main amplifier A1 by setting a compensation signal generated by a compensation amplifier circuit. At the same time, in order to avoid compensating the offset voltage of the compensation amplifier circuit itself to the main amplifier A1 and causing a compensation error, it is also necessary to compensate for the offset voltage of the compensation amplifier circuit itself. Therefore, the present invention uses two compensation amplifier circuits to alternately generate a first compensation signal S1 and a second compensation signal S2, so that before one of the compensation amplifier circuits generates the second compensation signal S2 to compensate for the offset voltage of the main amplifier circuit 31, the offset voltage of itself is compensated by the first compensation signal S1 generated by the other compensation amplifier circuit, avoiding the offset voltage of the compensation amplifier circuit itself from being compensated to the main amplifier A1, thereby improving the compensation accuracy of the offset voltage of the main amplifier A1, reducing signal noise, and improving detection accuracy.

[0055] In some embodiments, as Figure 2 shown, the main amplifier circuit 3 further includes:

[0056] A proportional amplification resistor R0, connected between the first differential input terminal 1 and the positive-phase input terminal of the main amplifier A1, for performing proportional amplification adjustment on the first differential voltage signal VIP to obtain a proportional adjustment signal V1;

[0057] A feedback resistor RF, one end connected between the second differential input terminal 2 and the inverting input terminal of the main amplifier A1, and the other end connected to the output terminal of the main amplifier A1, for feeding back the self-zeroing voltage amplified signal VOUT to obtain a feedback signal V2.

[0058] In the main amplifier circuit 3, the main amplifier A1 is used to amplify the proportional adjustment signal V1 and the net voltage signal V3 composed of the feedback signal V2 and the second differential voltage signal VIN, and output the initial amplified voltage signal VOUT′. Additionally, the main amplifier A1 can specifically adopt a transconductance amplifier.

[0059] The main amplifier circuit 3 composed of the proportional amplification resistor R0, the feedback resistor RF, and the main amplifier A1 is the most basic amplifier circuit; the proportional amplification resistor R0 and the feedback resistor RF determine the closed-loop amplification factor of the main amplifier A1; and by introducing the feedback resistor RF, the amplitude of the output voltage and current of the main amplifier A1 can be adjusted, thereby achieving an amplification or limiting effect, reducing the gain fluctuation of the circuit, improving the stability of the gain, and enhancing the stability and reliability of the circuit, ensuring that the circuit can operate normally under different environments and conditions.

[0060] In some embodiments, such as Figure 2 shown, the first compensation amplification circuit 4 further includes a first switching circuit 44 and a first auxiliary amplifier A2. The first switching circuit 44 is connected to the first compensation input terminal 41 and the second compensation input terminal 42 and receives non-overlapping first clock signal φ1 and second clock signal φ2. The first auxiliary amplifier A2 is connected to the first switching circuit 44 and the first compensation output terminal 43;

[0061] The first switching circuit 44 is configured to control the conduction or disconnection between the first auxiliary amplifier A2 and the main amplifier A1 according to the first clock signal φ1, and control the disconnection or short-circuit between the positive and negative input terminals of the first auxiliary amplifier A2 according to the second clock signal φ2;

[0062] When the first clock signal φ1 controls the conduction between the first auxiliary amplifier A2 and the main amplifier A1, the first auxiliary amplifier A2 is configured to generate the second compensation signal S2; and when the second clock signal φ2 controls the short-circuit between the positive and negative input terminals of the first auxiliary amplifier A2, the first auxiliary amplifier A2 is configured to generate the first compensation signal S1.

[0063] In the first compensation amplification circuit 4, the first auxiliary amplifier A2 can adopt a transconductance amplifier. By controlling the first auxiliary amplifier A2 to alternately operate in two working states through the first switching circuit 44, the first auxiliary amplifier A2 is cleverly made to alternately generate the first compensation signal S1 and the second compensation signal S2. When the first auxiliary amplifier A2 is conducting with the main amplifier A1, the first auxiliary amplifier A2 generates the second compensation signal S2 according to the proportional adjustment signal V1 and the net voltage signal V3. When the positive and negative input terminals of the first auxiliary amplifier A2 are short-circuited, the voltage difference between the positive and negative input terminals of the first auxiliary amplifier A2 changes; therefore, even if no signal is applied to the positive and negative input terminals of the first auxiliary amplifier A2, a signal will be output at its output terminal, and this signal is the first compensation signal S1.

[0064] Using the first switching circuit 44 to control the first auxiliary amplifier A2 to alternately generate the first compensation signal S1 and the second compensation signal S2 is ingeniously designed and has a simple circuit structure.

[0065] In some embodiments, such as Figure 2 shown, the first switching circuit 44 includes:

[0066] The first switch group is connected to the first clock signal φ1. The first switch group includes a first switch K1 and a second switch K2. The first switch K1 is connected in series between the first compensation input terminal 41 and the non-inverting input terminal of the first auxiliary amplifier A2. The second switch K2 is connected in series between the second compensation input terminal 42 and the inverting input terminal of the first auxiliary amplifier A2. The first switch group is used to control the conduction or disconnection between the main amplifier A1 and the first auxiliary amplifier A2 according to the first clock signal φ1.

[0067] The third switch K3 is connected to the second clock signal φ2 and is connected in series between the non-inverting and inverting input terminals of the first auxiliary amplifier A2, and is used to control the disconnection or short-circuit between the non-inverting and inverting input terminals of the first auxiliary amplifier A2 according to the second clock signal φ2.

[0068] In the first switch circuit 44, the first clock signal φ1 and the second clock signal φ2 are non-overlapping clock signals, which are used to control the opening or closing of the switch. The so-called non-overlapping clock signals are two clock signals that are not both high level or low level at the same time. In this embodiment, a high level is used to control the switch to close, and a low level is used to control the switch to open. Therefore, the first clock signal φ1 and the second clock signal φ2 selected in this embodiment are two clock signals that are not both high level at the same time, and their waveforms are as Figure 3 shown. When the first clock signal φ1 is at a high level, the first switch K1 and the second switch K2 are controlled to close. When the first clock signal φ1 is at a low level, the first switch K1 and the second switch K2 are controlled to open. When the second clock signal φ2 is at a high level, the third switch K3 is controlled to close. When the second clock signal φ2 is at a low level, the third switch K3 is controlled to open. Since the first clock signal φ1 and the second clock signal φ2 are not both high level at the same time, the first switch group and the third switch K3 will not close at the same time. Therefore, the first auxiliary amplifier A2 alternately operates in two states to alternately generate a first compensation signal S1 and a second compensation signal S2. Specifically, when the first switch group is closed and the third switch K3 is turned off, the first auxiliary amplifier A2 generates a first compensation signal S1; or when the first switch group is open and the third switch K3 is closed, the first auxiliary amplifier A2 generates a second compensation signal S2.

[0069] In this embodiment, the first switch group composed of the first switch K1 and the second switch K2 and the third switch K3 constitute the first switch circuit. The circuit structure is simple, the control process is relatively simple, and the cost is low.

[0070] In some embodiments, such as Figure 2As shown, the second compensation amplifier circuit 5 further includes a second switching circuit 54 and a second auxiliary amplifier A3. The second switching circuit 54 is connected to the third compensation input terminal 51 and the fourth compensation input terminal 52 and receives non-overlapping first clock signal φ1 and second clock signal φ2. The second auxiliary amplifier A3 is connected to the second switching circuit 54 and the second compensation output terminal 53;

[0071] The second switching circuit 54 is configured to control the disconnection or conduction between the second auxiliary amplifier A3 and the main amplifier A1 according to the second clock signal φ2, and to control the short-circuiting or disconnection between the positive and negative input terminals of the second auxiliary amplifier A3 according to the first clock signal φ1;

[0072] When the second clock signal φ2 controls the conduction between the second auxiliary amplifier A3 and the main amplifier A1, the second auxiliary amplifier A3 is configured to generate the second compensation signal S2; and when the first clock signal φ1 controls the short-circuiting between the positive and negative input terminals of the second auxiliary amplifier A3, the second auxiliary amplifier A3 generates the first compensation signal S1.

[0073] In the second compensation amplifier circuit 5, the second auxiliary amplifier A3 can adopt a transconductance amplifier. The second switching circuit 54 is used to control the second auxiliary amplifier A3 to alternately operate in two working states, so as to cleverly make the second auxiliary amplifier A3 alternately generate the first compensation signal S1 and the second compensation signal S2. When the second auxiliary amplifier A3 is conducting with the main amplifier A1, the second auxiliary amplifier A3 generates the second compensation signal S2 according to the proportional adjustment signal V1 and the net voltage signal V3. When the positive and negative input terminals of the second auxiliary amplifier A3 are short-circuited, the voltage difference between the positive and negative input terminals of the second auxiliary amplifier A3 changes; therefore, even if no signal is applied to the positive and negative input terminals of the second auxiliary amplifier A3, a signal will be output at its output terminal, and this signal is the first compensation signal S1.

[0074] Using the second switching circuit 54 to control the second auxiliary amplifier A3 to alternately generate the first compensation signal S1 and the second compensation signal S2, the circuit structure is simple.

[0075] In some embodiments, as Figure 2 shown, the second switching circuit 54 includes:

[0076] The second switch group is connected to the second clock signal φ2. The second switch group includes a fourth switch K4 and a fifth switch K5. The fourth switch K4 is connected in series between the third compensation input terminal 51 and the non-inverting input terminal of the second auxiliary amplifier A3. The fifth switch K5 is connected in series between the fourth compensation input terminal 52 and the inverting input terminal of the second auxiliary amplifier A3. The second switch group is used to control the disconnection or conduction between the main amplifier A1 and the second auxiliary amplifier A3 according to the second clock signal φ2;

[0077] A sixth switch K6 is connected to the first clock signal φ1 and is connected in series between the non-inverting and inverting input terminals of the second auxiliary amplifier A3, and is used to control the short-circuit or disconnection between the non-inverting and inverting input terminals of the second auxiliary amplifier A3 according to the first clock signal φ1.

[0078] In this embodiment, similar to the above first switch circuit 44, in the second switch circuit 54, the first clock signal φ1 and the second clock signal φ2 are also non-overlapping clock signals, which are used to control the disconnection or closing of the switches. In this embodiment, when the second clock signal φ2 is at a high level, the fourth switch K4 and the fifth switch K5 are controlled to close. When the second clock signal φ2 is at a low level, the fourth switch K4 and the fifth switch K5 are controlled to disconnect; when the first clock signal φ1 is at a high level, the sixth switch K6 is controlled to close. When the first clock signal φ1 is at a low level, the sixth switch K6 is controlled to disconnect. Since the first clock signal φ1 and the second clock signal φ2 are not simultaneously at a high level, the second switch group and the sixth switch K6 will not close simultaneously; therefore, the second auxiliary amplifier A3 alternately operates in two states to alternately generate a first compensation signal S1 and a second compensation signal S2. Specifically, when the second switch group is closed and the sixth switch K6 is turned off, the second auxiliary amplifier A3 generates a first compensation signal S1; or, when the second switch group is disconnected and the sixth switch K6 is closed, the second auxiliary amplifier A3 generates a second compensation signal S2.

[0079] The first switch circuit formed by the first switch K1, the second switch K2, and the third switch K3 has a simple circuit structure, a relatively simple control process, and low cost.

[0080] Combining the first switch circuit 44 and the second switch circuit 54, it can be seen that the switch state of the first switch group is the same as that of the sixth switch K6, and the switch state of the second switch group is the same as that of the third switch K3. Therefore, when the first switch group is closed, the sixth switch K6 is also closed, and at the same time, the second switch group and the third switch K3 are open. At this time, the first auxiliary amplifier A2 generates the second compensation signal S2, and the second auxiliary amplifier A3 generates the first compensation signal S1. In this way, the second auxiliary amplifier A3 compensates for the offset voltage of the first auxiliary amplifier A2 by generating the first compensation signal S1, and then the compensated first auxiliary amplifier A2 compensates for the main amplifier A1 through the second compensation signal S2; when the first switch group is open, the sixth switch K6 is also open, and at the same time, the second switch group and the third switch K3 are closed. At this time, the first auxiliary amplifier A2 generates the first compensation signal S1, and the second auxiliary amplifier A3 generates the second compensation signal S2. In this way, the first auxiliary amplifier A2 compensates for the offset voltage of the second auxiliary amplifier A3 by generating the first compensation signal S1, and then the compensated second auxiliary amplifier A3 compensates for the main amplifier A1 through the second compensation signal S2.

[0081] The present invention utilizes the first switch circuit 44 and the second switch circuit 54 to cleverly realize the first auxiliary amplifier A2 and the second auxiliary amplifier A3 to alternately generate the first compensation signal S1 and the second compensation signal S2 under the control of non-overlapping clocks, thereby realizing the compensation of the offset voltage of the initial amplified voltage signal output by the main amplifier A1, effectively reducing signal noise, and improving detection accuracy.

[0082] In some embodiments, as Figure 4 shown, the auto-zeroing amplifier circuit 100 of the present invention further includes:

[0083] A first subtractor circuit 6, connected to the first compensation output terminal 41 and the second compensation output terminal 51, for performing a subtraction operation on the second compensation signal S2 and the first compensation signal S1, so that the first compensation signal S1 compensates for the offset voltage of the second compensation signal S2, and then generates a third compensation signal S3.

[0084] Specifically, the first subtractor circuit 6 subtracts the second compensation signal S2 from the first compensation signal S1 to enable the first compensation signal S1 to compensate for the offset voltage of the second compensation signal S2. The third compensation signal S3 generated by the first subtraction circuit is the second compensation signal S2 compensated by the first compensation signal S1. The first compensation signal S1 compensates for the offset voltage of the second compensation signal S2 to avoid the offset voltage of the compensation amplifier itself of the second compensation signal S2 being compensated into the initial amplified voltage signal VOUT′ when the second compensation signal S2 compensates the initial amplified voltage signal VOUT′, thereby improving the compensation accuracy of the offset voltage of the initial amplified voltage signal VOUT′.

[0085] In some embodiments, as Figure 4 shown, the auto-zeroing amplifier circuit 100 of the present invention further includes:

[0086] A second subtractor circuit 7, connected to the main amplifier A1 and the first subtractor circuit 6, for subtracting the initial amplified voltage signal VOUT′ and the third compensation signal S3 to enable the third compensation signal S3 to compensate for the offset voltage of the initial amplified voltage signal VOUT′, thereby generating an auto-zeroing amplified voltage signal VOUT.

[0087] Specifically, the second subtractor circuit 7 subtracts the initial amplified voltage signal VOUT′ and the third compensation signal S3 to achieve compensation of the initial amplified voltage signal VOUT′ by the second compensation signal S2 compensated by the first compensation signal S1, and finally generates an auto-zeroing amplified voltage signal VOUT. This auto-zeroing amplified voltage signal VOUT has substantially no offset voltage, so its signal noise is extremely low.

[0088] In some embodiments, as Figure 4 shown, the first compensation amplifier circuit 4 further includes a first RC filter 45 and a second RC filter 46. Among them, the first RC filter 45 is connected between the non-inverting input terminal of the main amplifier A1 and the first compensation input terminal 41; the second RC filter 46 is connected between the inverting input terminal of the main amplifier A1 and the second compensation input terminal 42.

[0089] In this application, the main amplifier is a high-frequency signal path with a relatively high bandwidth, and the first auxiliary amplifier and the second auxiliary amplifier are low-frequency signal paths with a relatively low bandwidth. The first RC filter 45 and the second RC filter 46 are used to filter the proportional adjustment signal V1 and the net voltage signal V3 transmitted to the first compensation amplification circuit 4 to filter out high-frequency signals. Additionally, the second compensation amplification circuit 5 can also be connected to the first RC filter 45 and the second RC filter 46; specifically, the third compensation input terminal 51 is connected to the non-inverting input terminal of the main amplifier A1 through the first RC filter 45, and the fourth compensation input terminal 52 is connected to the inverting input terminal of the main amplifier A1 through the second RC filter 46. When the second compensation amplification circuit 5 is used to generate the second compensation signal S2, the first RC filter 45 and the second RC filter 46 are used to filter the proportional adjustment signal V1 and the net voltage signal V3 transmitted to the second compensation amplification circuit 5 to filter out high-frequency signals.

[0090] A self-zeroing amplification circuit 100 provided by the present invention alternately generates a first compensation signal and a second compensation signal through a low-frequency signal path. When compensating for the offset voltage of the high-frequency signal path, it also avoids compensating its own offset voltage to the main amplifier, thereby improving the compensation accuracy of the offset voltage of the high-frequency signal path and further reducing the noise of the high-frequency signal path.

[0091] Based on the above self-zeroing amplification circuit 100, the present invention further provides an analog front-end detection circuit.

[0092] As Figure 5 shown, an analog front-end detection circuit of the present invention includes:

[0093] A first differential input terminal group 200 for accessing a first differential voltage signal group (Hsin+, Hsin-) and a second differential input terminal group 300 for accessing a second differential voltage signal group (Hcos+, Hcos-);

[0094] A first primary amplification circuit 400, connected to the first differential input terminal group 200, for amplifying the difference between the first differential voltage signal group (Hsin+, Hsin-) to obtain a first primary amplification signal Osin;

[0095] A second primary amplification circuit 500, connected to the second differential input terminal group 300, for amplifying the difference between the second differential voltage signal group (Hcos+, Hcos-) to obtain a second primary amplification signal Ocos;

[0096] A logic operation circuit 600, connected to the first stage amplification circuit 400 and the second stage amplification circuit 500, is configured to perform addition or subtraction operation processing on the first stage amplified signal Osin and the second stage amplified signal Ocos to obtain a logic operation signal Osc;

[0097] A second stage amplification circuit 700, connected to the logic operation circuit 600, is configured to perform amplification processing on the logic operation signal Osc to obtain a first differential voltage signal VIP and a second differential voltage signal VIN; and

[0098] The auto-zeroing amplification circuit 100 as described above is connected to the second stage amplification circuit 700, and is configured to perform signal amplification processing based on offset voltage compensation on the first differential voltage signal VIP and the second differential voltage signal VIN to generate an auto-zeroing amplified voltage signal VOUT.

[0099] Specifically, the first differential voltage signal group (Hsin+, Hsin-) and the second differential voltage signal group (Hcos+, Hcos-) can be two groups of differential Hall induction signals output by a Hall sensor; wherein, Hsin+ and Hsin- represent the X-axis differential Hall induction signals, and Hcos+ and Hcos- represent the differential Hall induction signals orthogonal to the Y-axis.

[0100] Both the first stage amplification circuit 400 and the second stage amplification circuit 500 can adopt a transconductance amplification circuit. The first differential voltage signal group (Hsin+, Hsin-) is amplified by the first stage amplification circuit 400 and then outputs the first stage amplified signal Osin; the second differential voltage signal group (Hcos+, Hcos-) is amplified by the second stage amplification circuit 500 and then outputs the second stage amplified signal Ocos.

[0101] The logic operation circuit 600 can adopt an adder circuit or a subtractor circuit; the logic operation circuit 600 performs addition or subtraction processing on the first stage amplified signal Osin and the second stage amplified signal Ocos to obtain a logic operation signal Osc.

[0102] The second stage amplification circuit 700 can also adopt a transconductance amplification circuit, and the second stage amplification circuit 700 performs amplification processing on the logic operation signal Osc and then outputs the first differential voltage signal VIP and the second differential voltage signal VIN.

[0103] Finally, the auto-zeroing amplification circuit 100 of the present invention as described above is used to perform signal amplification processing based on offset voltage compensation on the first differential voltage signal VIP and the second differential voltage signal VIN to generate an auto-zeroing amplified voltage signal VOUT.

[0104] The analog front-end detection circuit of the present invention adopts the above self-zeroing amplifier circuit 100, which can reduce circuit noise; in addition, a three-stage amplification architecture including a first-stage amplifier circuit, a second-stage amplifier circuit, and a self-zeroing amplifier circuit can achieve a wider amplification range; at the same time, the three-stage amplification architecture of the analog front-end detection circuit of the present invention is such that the signal is amplified by the first-stage amplifier circuit, then combined through logical operation, and then amplified in two subsequent cascaded stages. Compared with a completely independent three-stage amplification architecture, the three-stage amplification architecture of the analog front-end detection circuit of the present invention is simpler, and thus the cost is also lower.

[0105] In some embodiments, as Figure 6 shown, the analog front-end detection circuit of the present invention further includes a calibration circuit 800, and the calibration circuit 800 is connected to the logic operation circuit 600 for providing a calibration signal DAC to compensate for the zero offset of the first differential voltage signal group (Hsin+, Hsin-) and the second differential voltage signal group (Hcos+, Hcos-) in the logic operation circuit 600 through the correction signal DAC.

[0106] Specifically, the calibration circuit 800 can adopt a current-mode digital-to-analog converter. The function of the current-mode digital-to-analog converter is to generate a calibration signal DAC according to the change in the magnitude of the current based on the input digital value; for example, assuming that the measured signal offset is 5 mV and the feedback resistor RF in the self-zeroing amplifier circuit 100 = 100 K, then the calibration signal DAC that the current-mode digital-to-analog converter needs to provide is -5 mV / 100 K = 500 nA. This calibration signal DAC is subtracted from the logic operation signal Osc to compensate for the zero offset of the first differential voltage signal group (Hsin+, Hsin-) and the second differential voltage signal group (Hcos+, Hcos-), so as to make the noise of the self-zeroing amplified voltage signal VOUT lower.

[0107] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A self-zeroing amplifier circuit, characterized in that: include: A first differential input terminal for inputting a first differential voltage signal; A second differential input terminal for inputting a second differential voltage signal; a main amplifier circuit, connected to the first differential input terminal and the second differential input terminal, and configured to amplify the difference between the first differential voltage signal and the second differential voltage signal to generate an initial amplified voltage signal; the main amplifier circuit comprises a main amplifier, and the main amplifier outputs the initial amplified voltage signal; A first compensation amplifier circuit, the first compensation amplifier circuit comprising a first compensation input terminal, a second compensation input terminal and a first compensation output terminal; the first compensation input terminal is connected to the non-inverting input terminal of the main amplifier, the second compensation input terminal is connected to the inverting input terminal of the main amplifier, and the first compensation output terminal is connected to the output terminal of the main amplifier; a second compensation amplifier circuit, wherein the second compensation amplifier circuit comprises a third compensation input terminal, a fourth compensation input terminal and a second compensation output terminal; the third compensation input terminal is connected to the non-inverting input terminal of the main amplifier, the fourth compensation input terminal is connected to the inverting input terminal of the main amplifier, and the second compensation output terminal is connected to the first compensation output terminal; The first compensation amplifier circuit and the second compensation amplifier circuit are used to alternately generate a first compensation signal and a second compensation signal, and the first compensation signal compensates for the offset voltage of the second compensation signal, and the second compensation signal compensated by the first compensation signal compensates for the offset voltage of the initial amplified voltage signal to generate a self-zeroing amplified voltage signal.

2. The self-reset-to-zero amplifier circuit according to claim 1, characterized in that: The first compensation amplifier circuit further includes a first switch circuit and a first auxiliary amplifier, wherein the first switch circuit is connected to the first compensation input terminal and the second compensation input terminal and receives a non-overlapping first clock signal and a second clock signal, and the first auxiliary amplifier is connected to the first switch circuit and the first compensation output terminal; The first switch circuit is used to control the connection or disconnection between the first auxiliary amplifier and the main amplifier according to the first clock signal, and to control the disconnection or short-circuit between the positive and negative input terminals of the first auxiliary amplifier according to the second clock signal; When the first clock signal controls the first auxiliary amplifier and the main amplifier to be turned on, the first auxiliary amplifier is used to generate the second compensation signal; and when the second clock signal controls the positive and negative input terminals of the first auxiliary amplifier to be short-circuited, the first auxiliary amplifier is used to generate the first compensation signal.

3. The self-reset-to-zero amplifier circuit according to claim 2, characterized in that: The first switch circuit comprises: a first switch group, connected to the first clock signal, the first switch group comprising a first switch and a second switch, the first switch being connected in series between the first compensation input terminal and the non-inverting input terminal of the first auxiliary amplifier, the second switch being connected in series between the second compensation input terminal and the inverting input terminal of the first auxiliary amplifier, the first switch group being used to control the connection or disconnection between the main amplifier and the first auxiliary amplifier according to the first clock signal; The third switch is connected to the second clock signal and in series between the positive and negative input terminals of the first auxiliary amplifier, and is used to control the positive and negative input terminals of the first auxiliary amplifier to be disconnected or short-circuited according to the second clock signal.

4. The self-reset-to-zero amplifier circuit according to claim 1, characterized in that: The second compensation amplifier circuit further includes a second switch circuit and a second auxiliary amplifier, the second switch circuit is connected to the third compensation input terminal and the fourth compensation input terminal and receives the non-overlapping first clock signal and the second clock signal, and the second auxiliary amplifier is connected to the second switch circuit and the second compensation output terminal; The second switch circuit is used for controlling the second auxiliary amplifier to be disconnected or connected with the main amplifier according to the second clock signal, and controlling the positive and negative input terminals of the second auxiliary amplifier to be short-circuited or disconnected according to the first clock signal; When the second clock signal controls the second auxiliary amplifier and the main amplifier to be turned on, the second auxiliary amplifier is used to generate the second compensation signal; and when the first clock signal controls the positive and negative input terminals of the second auxiliary amplifier to be short-circuited, the second auxiliary amplifier generates the first compensation signal.

5. The self-reset-to-zero amplifier circuit according to claim 4, characterized in that: The second switch circuit comprises: a second switch group, connected to the second clock signal, the second switch group comprising a fourth switch and a fifth switch, the fourth switch being connected in series between the third compensation input terminal and the non-inverting input terminal of the second auxiliary amplifier, the fifth switch being connected in series between the fourth compensation input terminal and the inverting input terminal of the second auxiliary amplifier, the second switch group being used for controlling the main amplifier and the second auxiliary amplifier to be disconnected or connected according to the second clock signal; The sixth switch is connected to the first clock signal and in series between the positive and negative input terminals of the second auxiliary amplifier, and is used to control the positive and negative input terminals of the second auxiliary amplifier to be short-circuited or disconnected according to the first clock signal.

6. The self-reset-to-zero amplifier circuit according to claim 1, characterized in that: Also includes: A first subtractor circuit is connected to the first compensation output terminal and the second compensation output terminal, and is used to perform a subtraction operation on the second compensation signal and the first compensation signal so that the first compensation signal compensates for the offset voltage of the second compensation signal, thereby generating a third compensation signal.

7. The self-reset-to-zero amplifier circuit according to claim 6, characterized in that: Also includes: A second subtractor circuit is connected to the main amplifier and the first subtractor circuit, and is used to perform a subtraction operation on the initial amplified voltage signal and the third compensation signal, so that the third compensation signal compensates for the offset voltage of the initial amplified voltage signal, thereby generating a self-zeroing amplified voltage signal.

8. The self-reset-to-zero amplifier circuit according to claim 2, characterized in that: The first compensation amplifier circuit also includes a first RC filter and a second RC filter, wherein the first RC filter is connected between the non-inverting input terminal of the main amplifier and the first compensation input terminal; the second RC filter is connected between the inverting input terminal of the main amplifier and the second compensation input terminal.

9. An analog front-end detection circuit, characterized in that: include: A first differential input terminal group for receiving a first differential voltage signal group and a second differential input terminal group for receiving a second differential voltage signal group; A first first-stage amplifier circuit, connected to the first differential input terminal group, and used for amplifying the difference between the first differential voltage signal groups to obtain a first first-stage amplified signal; a second first-stage amplifying circuit, connected to the second differential input terminal group, and used for amplifying the difference between the second differential voltage signal groups to obtain a second first-stage amplified signal; a logic operation circuit connected to the first first-stage amplifying circuit and the second first-stage amplifying circuit, and configured to perform addition or subtraction operations on the first first-stage amplified signal and the second first-stage amplified signal to obtain a logic operation signal; a second-stage amplifier circuit connected to the logic operation circuit, and configured to amplify the logic operation signal to obtain a first differential voltage signal and a second differential voltage signal; and The self-zero amplifier circuit according to any one of claims 1 to 8 is connected to the second-stage amplifier circuit, and is used to perform signal amplification processing based on offset voltage compensation on the first differential voltage signal and the second differential voltage signal to generate a self-zero amplified voltage signal.

10. The analog front-end detection circuit according to claim 9, characterized in that: It also includes a correction circuit, which is connected to the logic operation circuit and is used to provide a correction signal to compensate the zero offset of the first differential voltage signal group and the second differential voltage signal group in the logic operation circuit through the correction signal.

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