Input stage circuit, control method, differential amplifier, chip and electronic equipment

Abstract

The invention discloses an input stage circuit, a control method, a differential amplifier, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The input stage circuit comprises a current applying module and an input differential pair module which are connected with each other; the current applying module is used for applying target current corresponding to the current control signal to the input differential pair module based on the current control signal, the current control signal is determined based on the differential input signal, and the target current is used for enabling transconductance of the input differential pair module for processing the differential input signal to be maintained within a constant range; and the input differential pair module is used for processing the differential input signal based on the target current. The input stage circuit can realize constant transconductance in the whole common-mode input voltage range, and is relatively high in stability.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of integrated circuit technologies, and particularly to an input stage circuit, a control method, a differential amplifier, a chip, and an electronic device. Background Art

[0002] With the development of integrated circuits, differential amplifiers are increasingly widely used. A differential amplifier includes an input stage circuit and a load circuit. Among them, the input stage circuit can process the differential input signal input to the differential amplifier, amplify the data information transmitted by the differential input signal, and suppress interference signals.

[0003] In related technologies, the input stage circuit includes a tail current source, an input differential pair module, and a current mirror. Based on the traditional input stage circuit including only a tail current source and an input differential pair module, a current mirror is added. Among them, the amplitude of the current mirrored by the current mirror is controlled by the common-mode input voltage range. The current mirror can provide a mirrored current to compensate the tail current source when the common-mode input voltage corresponding to the differential input signal is in the low voltage range and the high voltage range within the common-mode input voltage range, so as to offset the problem that the transconductance corresponding to the intermediate voltage range within the common-mode input voltage range of the traditional input stage circuit is greater than the transconductance corresponding to the two end voltage ranges.

[0004] This type of input stage circuit adjusts the transconductance in units of voltage ranges within the common-mode input voltage range. The adjustment granularity of the transconductance is relatively coarse, and the constancy of the transconductance is poor. In addition, the mirrored current provided by the current mirror is prone to deviation under the influence of various factors (such as temperature, process, voltage, etc.), resulting in poor stability of the input stage circuit. Summary of the Invention

[0005] Embodiments of the present application provide an input stage circuit, a control method, a differential amplifier, a chip, and an electronic device, which can be used to maintain the transconductance of the input stage circuit within a constant range and ensure the stability of the input stage circuit. The technical solutions are as follows:

[0006] On the one hand, embodiments of the present application provide an input stage circuit, and the input stage circuit includes a current application module and an input differential pair module connected to each other;

[0007] The current application module is configured to apply a target current corresponding to the current control signal to the input differential pair module based on the current control signal. The current control signal is determined based on the differential input signal, and the target current is used to maintain the transconductance of the input differential pair module for processing the differential input signal within a constant range;

[0008] The input differential pair module is configured to process the differential input signal based on the target current.

[0009] In a possible implementation, the input stage circuit further includes a logic module, and the logic module is connected to the current application module;

[0010] The logic module is configured to receive a common-mode input setting code provided by a sending device, and based on the common-mode input setting code, determine the current control signal. The sending device is a device that sends the differential input signal, and the common-mode input setting code is used to indicate the voltage range in which the common-mode input voltage corresponding to the differential input signal is located.

[0011] In a possible implementation, the logic module is configured to correct the common-mode input setting code based on the process parameters of the input stage circuit to obtain a corrected common-mode input setting code; and based on the corrected common-mode input setting code, determine the current control signal.

[0012] In a possible implementation, the current application module includes a first current application unit and a second current application unit, the input differential pair module includes a P-type differential pair unit and an N-type differential pair unit, the first current application unit is connected to the P-type differential pair unit, and the second current application unit is connected to the N-type differential pair unit; the current control signal includes a first current control sub-signal and a second current control sub-signal, and the target current includes a first current corresponding to the first current control sub-signal and a second current corresponding to the second current control sub-signal;

[0013] The first current application unit is configured to apply the first current to the P-type differential pair unit based on the first current control sub-signal;

[0014] The second current application unit is configured to apply the second current to the N-type differential pair unit based on the second current control sub-signal;

[0015] The P-type differential pair unit is configured to process the differential input signal based on the first current;

[0016] The N-type differential pair unit is configured to process the differential input signal based on the second current;

[0017] Wherein, the sum of the transconductances of the P-type differential pair unit for processing the differential input signal and the N-type differential pair unit for processing the differential input signal is maintained within the constant range.

[0018] In a possible implementation manner, the first current application unit includes a plurality of first constant current sources, and the first current control sub-signal is used to indicate the state of the connection path between each first constant current source and the P-type differential pair unit; the first current is the sum of the currents provided by the first constant current sources whose connection paths indicated by the first current control sub-signal are in a connected state;

[0019] The second current application unit includes a plurality of second constant current sources, and the second current control sub-signal is used to indicate the state of the connection path between each second constant current source and the N-type differential pair unit; the second current is the sum of the currents provided by the second constant current sources whose connection paths indicated by the second current control sub-signal are in a connected state.

[0020] In a possible implementation manner, the first current application unit includes a first adjustable current source, and the first current control sub-signal is used to indicate the adjustment method of the first adjustable current source; the first current is the current provided by the first adjustable current source after being adjusted according to the adjustment method indicated by the first current control sub-signal;

[0021] The second current application unit includes a second adjustable current source, and the second current control sub-signal is used to indicate the adjustment method of the second adjustable current source; the second current is the current provided by the second adjustable current source after being adjusted according to the adjustment method indicated by the second current control sub-signal.

[0022] In a possible implementation manner, the P-type differential pair unit includes a first P-type transistor and a second P-type transistor. The gates of the first P-type transistor and the second P-type transistor are respectively connected to the first input terminal and the second input terminal of the input stage circuit. The first P-type transistor and the second P-type transistor share a source electrode, and the first current application unit is connected to the shared source electrode of the first P-type transistor and the second P-type transistor;

[0023] The N-type differential pair unit includes a first N-type transistor and a second N-type transistor. The gates of the first N-type transistor and the second N-type transistor are respectively connected to the first input terminal and the second input terminal. The first N-type transistor and the second N-type transistor share a source electrode, and the second current application unit is connected to the shared source electrode of the first N-type transistor and the second N-type transistor.

[0024] On the other hand, an embodiment of the present application further provides a control method for an input stage circuit. The input stage circuit includes a current application module and an input differential pair module connected to each other; the method includes:

[0025] Based on the current control signal, the current application module applies a target current corresponding to the current control signal to the input differential pair module. The current control signal is determined based on the differential input signal, and the target current is used to maintain the transconductance for the input differential pair module to process the differential input signal within a constant range;

[0026] The input differential pair module processes the differential input signal based on the target current.

[0027] In a possible implementation, the input stage circuit further includes a logic module, and the logic module is connected to the current application module; the method further includes:

[0028] The logic module receives a common-mode input setting code provided by a sending device, and based on the common-mode input setting code, determines the current control signal. The sending device is the device that sends the differential input signal, and the common-mode input setting code is used to indicate the voltage range where the common-mode input voltage corresponding to the differential input signal is located.

[0029] In a possible implementation, the determining the current control signal based on the common-mode input setting code includes:

[0030] Based on the process parameters of the input stage circuit, correct the common-mode input setting code to obtain a corrected common-mode input setting code; based on the corrected common-mode input setting code, determine the current control signal.

[0031] In a possible implementation, the current application module includes a first current application unit and a second current application unit, the input differential pair module includes a P-type differential pair unit and an N-type differential pair unit, the first current application unit is connected to the P-type differential pair unit, and the second current application unit is connected to the N-type differential pair unit; the current control signal includes a first current control sub-signal and a second current control sub-signal, and the target current includes a first current corresponding to the first current control sub-signal and a second current corresponding to the second current control sub-signal;

[0032] The applying, by the current application module based on the current control signal, the target current corresponding to the current control signal to the input differential pair module includes:

[0033] The first current application unit applies the first current to the P-type differential pair unit based on the first current control sub-signal; the second current application unit applies the second current to the N-type differential pair unit based on the second current control sub-signal;

[0034] The processing of the differential input signal based on the target current by the input differential pair module includes:

[0035] processing the differential input signal by the P-type differential pair cell based on the first current; processing the differential input signal by the N-type differential pair cell based on the second current;

[0036] wherein, the sum of the transconductances of the P-type differential pair cell for processing the differential input signal and the N-type differential pair cell for processing the differential input signal is maintained within the constant range.

[0037] In a possible implementation manner, the first current application unit includes a plurality of first constant current sources, and the first current control sub-signal is used to indicate the state of the connection path between each first constant current source and the P-type differential pair cell; the first current is the sum of the currents provided by the first constant current sources whose connection paths indicated by the first current control sub-signal are in the connected state;

[0038] The second current application unit includes a plurality of second constant current sources, and the second current control sub-signal is used to indicate the state of the connection path between each second constant current source and the N-type differential pair cell; the second current is the sum of the currents provided by the second constant current sources whose connection paths indicated by the second current control sub-signal are in the connected state.

[0039] In a possible implementation manner, the first current application unit includes a first adjustable current source, the first current control sub-signal is used to indicate the adjustment manner of the first adjustable current source, and the first current is the current provided by the first adjustable current source after being adjusted according to the adjustment manner indicated by the first current control sub-signal;

[0040] The second current application unit includes a second adjustable current source, the second current control sub-signal is used to indicate the adjustment manner of the second adjustable current source, and the second current is the current provided by the second adjustable current source after being adjusted according to the adjustment manner indicated by the second current control sub-signal.

[0041] In a possible implementation manner, the P-type differential pair cell includes a first P-type transistor and a second P-type transistor. The gates of the first P-type transistor and the second P-type transistor are respectively connected to the first input terminal and the second input terminal of the input stage circuit. The first P-type transistor and the second P-type transistor share a source electrode, and the first current application unit is connected to the shared source electrode of the first P-type transistor and the second P-type transistor;

[0042] The N-type differential pair unit includes a first N-type transistor and a second N-type transistor. The gates of the first N-type transistor and the second N-type transistor are respectively connected to the first input terminal and the second input terminal. The first N-type transistor and the second N-type transistor share a source electrode, and the second current application unit is connected to the source electrode shared by the first N-type transistor and the second N-type transistor.

[0043] On the other hand, an embodiment of the present application further provides a differential amplifier, and the differential amplifier includes the input stage circuit described in any one of the above.

[0044] On the other hand, an embodiment of the present application further provides a chip, and the chip includes the above differential amplifier.

[0045] On the other hand, an embodiment of the present application further provides an electronic device, and the electronic device includes the above chip.

[0046] The technical solution provided by the embodiment of the present application at least brings the following beneficial effects:

[0047] In the technical solution provided by the embodiment of the present application, when the input differential pair module needs to process a differential input signal, the current application module applies a target current to the input differential pair module so that the transconductance of the input differential module for processing the differential input signal is maintained within a constant range. The target current corresponds to a current control signal, and the current control signal is determined based on the differential input signal. The method of adjusting the transconductance according to the target current is a method of adjusting the transconductance in units of the differential input signal, and the adjustment granularity of the transconductance is relatively fine. Based on this, regardless of the common-mode input voltage corresponding to the differential input signal, after being processed by the input stage circuit, the transconductance can be maintained within a constant range, so as to achieve a constant transconductance within the entire common-mode input voltage range.

[0048] In addition, the applied current is directly controlled by the current control signal, and the process of controlling the current application is relatively accurate, which is beneficial to ensuring the stability of the input stage circuit. Description of the Drawings

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0050] Figure 1 is a schematic structural diagram of an input stage circuit in the related art;

[0051] Figure 2It is a graph showing the variation of the transconductance of the input stage circuit in the related art within the entire common-mode input voltage range;

[0052] Figure 3 It is a schematic structural diagram of an input stage circuit provided by an embodiment of the present application;

[0053] Figure 4 It is a schematic structural diagram of another input stage circuit provided by an embodiment of the present application;

[0054] Figure 5 It is a schematic structural diagram of another input stage circuit provided by an embodiment of the present application;

[0055] Figure 6 It is a schematic structural diagram of another input stage circuit provided by an embodiment of the present application;

[0056] Figure 7 It is a schematic structural diagram of another input stage circuit provided by an embodiment of the present application;

[0057] Figure 8 It is a schematic structural diagram of another input stage circuit provided by an embodiment of the present application;

[0058] Figure 9 It is a graph showing the variation of the transconductance of an input stage circuit provided by an embodiment of the present application within the entire common-mode input voltage range;

[0059] Figure 10 It is a flowchart of a control method for an input stage circuit provided by an embodiment of the present application;

[0060] Figure 11 It is a schematic structural diagram of a differential amplifier provided by an embodiment of the present application;

[0061] Figure 12 It is a schematic structural diagram of another differential amplifier provided by an embodiment of the present application;

[0062] Figure 13 It is a schematic structural diagram of a chip provided by an embodiment of the present application;

[0063] Figure 14 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0064] Figure 15 It is a flowchart of the operation of a receiver provided by an embodiment of the present application.

[0065] The reference numerals in the figure are respectively represented as:

[0066] 1 - Current application module; 2 - Input differential pair module; 3 - Logic module; 11 - First current application unit; 12 - Second current application unit; 21 - P-type differential pair unit; 22 - N-type differential pair unit; 111 - First constant current source; 121 - Second constant current source; 112 - First adjustable current source; 122 - Second adjustable current source. Detailed implementation manners

[0067] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe in detail the implementation manners of the present application with reference to the accompanying drawings.

[0068] To support various types of application products, more and more display interface protocols cover a wide range of common-mode input voltages. This requires a receiver that supports a wide range of common-mode input voltage ranges to meet these protocols. To achieve information transmission between chips, the cooperation between the transmitter (TX) and receiver (RX) in the display interface is required. The TX end transmits differential input signals through the signal line channel, and the RX end needs to accurately receive and process the differential input signals. The RX includes an analog front-end (AFE) and a clock data recovery (CDR) circuit.

[0069] The analog front-end is responsible for the initial stage of processing analog signals. Analog signals are continuously varying physical quantities, such as sound, images, temperature, etc. The main task of the analog front-end is to amplify, filter, convert, etc. these analog signals so that subsequent digital circuits or processors can accurately receive and process these signals. The analog front-end usually includes key components such as signal amplifiers, filters, analog-to-digital converters, etc., and they work together to ensure the integrity and accuracy of the signals. Clock recovery refers to recovering the clock signal from the input signal according to the reference clock. In a serial communication system, to ensure the accuracy of data, a clock data recovery circuit needs to be designed so that the clock signal can be recovered to the same state as the original clock signal, thereby providing support for subsequent digital modules.

[0070] To expand the application scenarios of various types of RX and broaden the common-mode input voltage range of the received differential input signals, an analog front-end with the ability of a wide common-mode input voltage range is required to support these protocols. The signal amplifier in the analog front-end can include a multi-stage amplifier, and the analog front-end can support a wide range of common-mode input voltages through the first-stage amplifier in the multi-stage amplifier. The first-stage amplifier refers to the amplifier located at the front end of the analog front-end and used to receive the signal sent by the TX. For the case where the signal sent by the TX is a differential input signal, the form of the first-stage amplifier is a differential amplifier.

[0071] A differential input signal refers to a signal input in the form of a differential signal. A differential input signal includes two signals with equal amplitudes and opposite phases. Among them, the amplitudes of the two signals in the differential input signal refer to the amplitudes by which the voltages of the two signals deviate from the common-mode input voltage, and the phases of the two signals in the differential input signal refer to the directions in which the voltages of the two signals deviate from the common-mode input voltage. The common-mode input voltage refers to the average voltage between the voltages of the two signals in the differential input signal. That is to say, among the two signals of the differential input signal, the voltage of one signal is higher than the common-mode input voltage, and the voltage of the other signal is lower than the common-mode input voltage, but the amplitudes by which the voltages of the two signals deviate from the common-mode input voltage are the same. The differential input signal transmits information through the differential-mode input voltage, which refers to the voltage difference between the voltages of the two signals in the differential input signal. For example, if the voltages of the two signals in the differential input signal are 3V (volts) and 7V respectively, the corresponding common-mode input voltage of the differential input signal is 5V, and the corresponding differential-mode input voltage of the differential input signal is 4V.

[0072] Achieving a constant transconductance for a wide range of common-mode input voltages plays an important role in circuit design and signal processing and is crucial for achieving high-performance and accurate signal amplification and processing.

[0073] A differential amplifier includes an input-stage circuit that can process the differential input signal input to the differential amplifier, amplify the information transmitted by the differential input signal (i.e., the differential-mode input voltage), and suppress interference signals. The input-stage circuit mostly adopts a Rail-To-Rail (R2R) structure to support the processing of differential input signals with a wide common-mode input voltage range. The Rail-To-Rail common-mode input voltage range refers to the entire range in which the common-mode input voltage ranges from the maximum voltage (VDD) of the power supply line to its minimum voltage (GND or the minimum negative voltage, VEE). An input-stage circuit with a common-mode input voltage range that almost covers the GND-to-VDD or VEE-to-VDD range is called a Rail-To-Rail input-stage circuit.

[0074] A traditional Rail-To-Rail input-stage circuit includes a tail current source and an input differential pair module. The input differential pair module includes two types of complementary parallel input pair transistors (P-type input pair transistors and N-type input pair transistors). The tail current source is an important part that provides a constant current for the input differential pair module to stabilize the operation of the input differential pair module, improve the stability and anti-interference ability of the circuit. The basic principle of the tail current source is to generate a constant current through a reference current source and then flow it to the input differential pair module, so that the input differential pair module is always in a suitable operating state. The tail current source includes a P-type tail current source for providing a constant current for the P-type input pair transistors and an N-type tail current source for providing a constant current for the N-type input pair transistors.

[0075] The P-type input pair transistor includes two P-type transistors sharing a common source (which can be referred to as a common source). The common source of the two P-type transistors is connected to a P-type tail current source. The gates of the two P-type transistors are respectively used to input two signals in the differential input signal. In this structure, if the P-type input pair transistor works (at least one of the P-type transistors in the P-type input pair transistor is turned on), then the voltage difference between the drain voltages of the two P-type transistors is positively correlated with the differential input voltage corresponding to the differential input signal. By reasonably designing circuit parameters (such as the size of the P transistor, the size of the load resistor connected to the drain of the P-type transistor, etc.), the voltage difference between the drain voltages of the two P-type transistors can be made greater than the differential input voltage corresponding to the differential input signal, thereby realizing the amplification of the differential input voltage corresponding to the differential input signal. In addition, in this structure, the transconductance of the P-type input pair transistor for processing the differential input signal is positively correlated with the current input to the common source of the P-type input pair transistor.

[0076] Similarly, the N-type input pair transistor includes two N-type transistors sharing a common source (which can be referred to as a common source). The common source of the two N-type transistors is connected to an N-type tail current source. The gates of the two N-type transistors are respectively used to input two signals in the differential input signal. In this structure, if the N-type input pair transistor works (at least one of the N-type transistors in the N-type input pair transistor is turned on), then the voltage difference between the drain voltages of the two N-type transistors is positively correlated with the differential input voltage corresponding to the differential input signal. By reasonably designing circuit parameters (such as the size of the N transistor, the size of the load resistor connected to the drain of the N-type transistor, etc.), the voltage difference between the drain voltages of the two N-type transistors can be made greater than the differential input voltage corresponding to the differential input signal, thereby realizing the amplification of the differential input voltage corresponding to the differential input signal. In addition, in this structure, the transconductance of the N-type input pair transistor for processing the differential input signal is positively correlated with the current input to the common source of the N-type input pair transistor.

[0077] Since the operating ranges of the two types of input pair transistors are different, the transconductance of the traditional input stage circuit is not constant within the entire common-mode input voltage range, showing a situation where the transconductance in the middle interval is greater than that in the two end intervals. Transconductance refers to the rate of change of the output current with respect to the input voltage, and transconductance can be represented by the symbol gm.

[0078] Specifically, when the common-mode input voltage corresponding to the differential input signal is low (e.g., close to the minimum voltage of the power supply line), only the P-type input pair transistors are turned on and the N-type input pair transistors are turned off. At this time, the transconductance of the input stage circuit is equivalent to the transconductance gmp of the P-type input pair transistors. When the common-mode input voltage corresponding to the differential input signal is high (e.g., close to the maximum voltage of the power supply line), only the N-type input pair transistors are turned on and the P-type input pair transistors are turned off. At this time, the transconductance of the input stage circuit is equivalent to the transconductance gmn of the N-type input pair transistors. When the common-mode input voltage corresponding to the differential input signal is medium (e.g., near the average voltage between the maximum voltage and the minimum voltage of the power supply line), both the N-type input pair transistors and the P-type input pair transistors are turned on. At this time, the transconductance of the input stage circuit is equivalent to the sum of the transconductance of the N-type input pair transistors and the transconductance of the P-type input pair transistors. Therefore, the transconductance of the traditional input stage circuit is not constant within the entire common-mode input voltage range, showing that the transconductance in the middle interval is greater than that in the two end intervals.

[0079] For ease of understanding, the following takes the statement in the above text "when the common-mode input voltage corresponding to the differential input signal is low, only the P-type input pair transistors are turned on and the N-type input pair transistors are turned off" as an example for further explanation. Since the differential input signal needs to be amplified by a differential amplifier for its differential-mode input voltage, it is generally considered that the differential-mode input voltage corresponding to the differential input signal is small. According to the definitions of the common-mode input voltage and the differential-mode input voltage in the previous text, if the differential-mode input voltage corresponding to the differential input signal is small, it means that the amplitudes of the two signals in the differential input signal deviate from the common-mode input voltage by a small amount, that is, it can be considered that the voltages of the two signals in the differential input signal are close to the common-mode input voltage. Therefore, when the common-mode input voltage is low, the voltages of the two signals in the differential input signal are also low. The low voltage can turn on the P-type input pair transistors but cannot turn on the N-type input pair transistors (this is because the threshold voltage of the P-type transistor is low and the threshold voltage of the N-type transistor is high). Therefore, when the common-mode input voltage corresponding to the differential input signal is low, only the P-type input pair transistors are turned on and the N-type input pair transistors are turned off. It should be noted that the turning on of the P-type input pair transistors can refer to the turning on of one P-type transistor in the P-type input pair transistors or the turning on of both P-type transistors in the P-type input pair transistors. The embodiments of the present application do not limit this. The turning off of the N-type input pair transistors means that both N-type transistors in the N-type input pair transistors are turned off.

[0080] In the related art, the input stage circuit includes a tail current source, an input differential pair module, and a current mirror. That is, on the basis of the traditional input stage circuit including only a tail current source and an input differential pair module, a current mirror is added. Such an input stage circuit is an analog feedback type R2R input stage circuit. Such an input stage circuit divides the common-mode input voltage range into three intervals: a low voltage interval, a medium voltage interval, and a high voltage interval, and uses an external adjustment signal feedback to compensate the current in different common-mode input voltage intervals to achieve a constant transconductance in different intervals. For example, in the low voltage interval and the high voltage interval, a P-type current mirror and an N-type current mirror are respectively used to specifically compensate the P-type tail current source and the N-type tail current source, and no compensation is performed in the medium voltage interval, so as to offset the problem that the transconductance in the middle interval is greater than the transconductance in the two end intervals.

[0081] That is to say, when the common-mode input voltage corresponding to the differential input signal is in the low voltage interval and the high voltage interval within the common-mode input voltage range, the current mirror can provide a mirror current to compensate the tail current source, so as to offset the problem that the transconductance corresponding to the middle voltage interval within the common-mode input voltage range in the traditional input stage circuit is greater than the transconductance corresponding to the two end voltage intervals.

[0082] The division methods of the low voltage interval, the medium voltage interval, and the high voltage interval can be set according to experience, or can be adjusted according to the characteristic parameters of the P-type input pair transistor and the N-type input pair transistor. For example, taking the entire common-mode input voltage range as 0V to VDD, the low voltage interval can be 0V to 0.3VDD, the medium voltage interval can be 0.3VDD to 0.7VDD, and the high voltage interval can be 0.7VDD to VDD.

[0083] The current mirror in the input stage circuit in the related art can be a 1:3 type current mirror. In this case, the input stage circuit in the related art can be as Figure 1 shown. In Figure 1 the shown input stage circuit, the input differential pair module includes a P-type input pair transistor and an N-type input pair transistor. The P-type input pair transistor includes transistor MP0 and transistor MP1, and the N-type input pair transistor includes transistor MN0 and MN1. The tail current source includes a P-type tail current source IREF2 and an N-type tail current source IREF1.

[0084] The P-type tail current source IREF2 is connected to the common source of two transistors (transistor MP0 and transistor MP1) in the P-type input pair transistors, and the N-type tail current source IREF1 is connected to the common source of two transistors (transistor MN0 and transistor MN1) in the N-type input pair transistors. The gates of transistor MP0 and transistor MN0 are connected to the first input terminal VIN of the input stage circuit, and the gates of transistor MP1 and transistor MN1 are connected to the second input terminal VIP of the input stage circuit. In some embodiments, the first input terminal VIN may also be referred to as the in-phase input terminal, and the second input terminal VIP may also be referred to as the anti-phase input terminal.

[0085] In Figure 1 the input stage circuit shown, the current mirror includes a P-type current mirror and an N-type current mirror. The P-type current mirror includes transistor MP2 and transistor MP3, and the N-type current mirror includes transistor MN2 and MN3. The input stage circuit further includes transistor MN4 and transistor MP4, wherein the gate of transistor MN4 is connected to the external adjustment signal VBN, and the gate of transistor MP4 is connected to the external adjustment signal VBP.

[0086] Figure 1 The working principle of the input stage circuit shown is as follows: when the common-mode input voltage corresponding to the differential input signal is in the low voltage range, the external adjustment signal VBN controls transistor MN4 to conduct, and the external adjustment signal VBP controls transistor MP4 to cut off. The current provided by the N-type tail current source IREF1 passes through a 1:3 P-type current mirror, and the 1:3 P-type current mirror compensates the mirror current obtained according to the current provided by the N-type tail current source IREF1 on the P-type input pair transistors, increasing the transconductance of the input stage circuit in the low voltage range. When the common-mode input voltage corresponding to the differential input signal is in the high voltage range, the external adjustment signal VBN controls transistor MN4 to cut off, and the external adjustment signal VBP controls transistor MP4 to conduct. The current provided by the P-type tail current source IREF2 passes through a 1:3 N-type current mirror, and the 1:3 N-type current mirror compensates the mirror current obtained according to the current provided by the P-type tail current source IREF2 on the N-type input pair transistors, increasing the transconductance of the input stage circuit in the high voltage range. When the common-mode input voltage corresponding to the differential input signal is in the medium voltage range, the external adjustment signal VBN controls transistor MN4 to cut off, and the external adjustment signal VBP controls transistor MP4 to cut off, without performing additional current compensation on the input pair transistors.

[0087] The above input stage circuit divides the common-mode input voltage range into three voltage ranges for transconductance adjustment, but the granularity of this transconductance adjustment is relatively coarse, and it cannot ensure that the transconductance remains constant throughout the common-mode input voltage range. For example, the change curve of the transconductance of the input stage circuit in the related art within the entire common-mode input voltage range is as Figure 2 shown, Figure 2The variation curve in [it] has two relatively large bulges, which also means that the input-stage circuit in the related art has a relatively large transconductance variation in the transition intervals of the three voltage ranges, resulting in an unconstant transconductance within the entire common-mode input voltage range, and thus causing a discontinuous signal amplification ability within the entire common-mode input voltage range. In addition, the complementary differential structure is prone to reducing the common-mode rejection ratio, and the input-stage offset voltage is discontinuous. All of these will cause the quality of the signal eye diagram to change during the actual signal transmission process. It is very difficult for this structure to optimize the performance of the differential amplifier with the change of the common-mode input voltage.

[0088] Continuing with the input-stage circuit in the related art as Figure 1 shown as an example for illustration, the condition for the establishment of the 1:3 current mirror requires the transistors in the current mirror to operate in the saturation region, which severely depends on the current-voltage relationship. When the common-mode input voltage range biases towards both ends, affected by the gate-source voltage of the input pair transistors, the space of the drain voltages VDN and VDP of the transistors MN3 and MP3 is squeezed, which will force the transistors MN3 and MP3 to enter the linear region, thus causing a serious deviation in the mirror current provided by the 1:3 current mirror. Therefore, to ensure the stability of the mirror current provided by the 1:3 current mirror, the common-mode input voltage range can only be limited within a narrow space. For example, when the common-mode input voltage is very small, the gate voltages of the transistors MN0 and MN1 are very small, so that the common-source voltages of all the transistors MN0 and MN1 are also very small. Since the drain of the transistor MN3 is connected to the common source of the transistors MN0 and MN1, the voltage VDN of the drain of the transistor MN3 is also very small. When the voltage VDN of the drain of the transistor MN3 is very small, it will cause the transistor MN3 to enter the linear region.

[0089] In addition, the requirements for the external adjustment signals VBN and VBP are of high precision. Under the multiple variations of the power supply voltage, temperature, and process, it is difficult to fully meet the design requirements of the circuit, which will lead to a reduction in the accuracy of the mirror current provided by the 1:3 current mirror, affect the performance of the input-stage circuit, and reduce the stability of the input-stage circuit.

[0090] The embodiment of the present application provides an input-stage circuit, which can achieve a constant transconductance within the entire common-mode input voltage range and has relatively high stability. Refer to Figure 3 , this input-stage circuit includes a current application module 1 and an input differential pair module 2 that are connected to each other. Among them, the current application module 1 is used to apply a target current corresponding to the current control signal to the input differential pair module 2 based on the current control signal. The current control signal is determined based on the differential input signal, and the target current is used to keep the transconductance of the input differential pair module 2 for processing the differential input signal within a constant range; the input differential pair module 2 is used to process the differential input signal based on the target current.

[0091] Based onFigure 3 For the input stage circuit shown, when the input differential pair module 2 needs to process the differential input signal, the current application module 1 applies a target current to the input differential pair module 2, so that the transconductance of the input differential module 2 for processing the differential input signal is maintained within a constant range. The target current corresponds to the current control signal, and the current control signal is determined based on the differential input signal. The method of adjusting the transconductance according to the target current is a method of adjusting the transconductance in units of the differential input signal, and the adjustment granularity of the transconductance is relatively fine. Based on this, regardless of the common-mode input voltage corresponding to the differential input signal, after being processed by the input stage circuit, the transconductance can be maintained within a constant range, so as to achieve a constant transconductance within the entire common-mode input voltage range.

[0092] In addition, directly controlling the applied current through the current control signal makes the process of controlling the current application more accurate, which is beneficial to ensuring the stability of the input stage circuit.

[0093] The current control signal is a signal used to control the current application module 1 to apply current to the input differential pair module 2. In the embodiments of the present application, the current control signal is determined based on the differential input signal, and the current applied by the current control signal to control the current application module 1 to the input differential pair module 2 is the target current corresponding to the current control signal. The target current can make the transconductance of the input stage circuit for processing the differential input signal be maintained within a constant range.

[0094] In an exemplary embodiment, that the transconductance is maintained within a constant range may mean that the difference between the actual transconductance and the constant transconductance is less than the difference threshold. The actual transconductance refers to the transconductance of the input differential pair module 2 for processing the differential input signal; the constant transconductance is a fixed transconductance, which can be set according to experience or flexibly adjusted according to the application scenario. The embodiments of the present application do not limit this. The embodiments of the present application do not limit the method for determining the difference between the actual transconductance and the constant transconductance. Exemplarily, the difference between the actual transconductance and the constant transconductance may refer to the absolute difference between the actual transconductance and the constant transconductance. For example, the absolute difference may refer to the absolute value of the difference between the actual transconductance and the constant transconductance. Exemplarily, the difference between the actual transconductance and the constant transconductance may also refer to the relative difference between the actual transconductance and the constant transconductance. For example, the relative difference may refer to the ratio of the absolute difference to the constant transconductance, and the absolute difference refers to the absolute value of the difference between the actual transconductance and the constant transconductance.

[0095] The difference threshold can be set according to experience or flexibly adjusted according to the application scenario. The embodiments of the present application do not limit this. The difference threshold is generally a relatively small value. For example, for the case where the difference between the actual transconductance and the constant transconductance refers to the absolute difference between the actual transconductance and the constant transconductance, the difference threshold can be 0.01, 0.05, etc.; for the case where the difference between the actual transconductance and the constant transconductance refers to the relative difference between the actual transconductance and the constant transconductance, the difference threshold can be 1%, 0.1%, etc.

[0096] In a possible implementation manner, the current control signal may be determined by the sending device of the differential input signal and sent to the input stage circuit, for example, sent to the current application module 1, or sent to the module connected to the current application module 1 in the input stage circuit, so that the current application module 1 can directly obtain the current control signal, or obtain the current control signal through interaction with other modules. Based on this, the current control signal is determined by the sending device of the differential input signal, and the determination logic of the current control signal is executed by the sending device of the differential input signal, which helps to save the computing resources of the input stage circuit.

[0097] In a possible implementation manner, refer to Figure 4 , the input stage circuit further includes a logic module 3, and the logic module 3 is connected to the current application module 1. The logic module 3 is used to obtain the current control signal, and the current application module 1 obtains the current control signal through interaction with the logic module 3.

[0098] In an exemplary embodiment, for the case where the current control signal is determined by the sending device, the logic circuit 3 may be used to receive the current control signal sent by the sending device. The sending device is the device that sends the differential input signal.

[0099] In an exemplary embodiment, the current control signal may also be determined by the logic module 3. In this case, the logic module 3 is used to receive the common-mode input setting code provided by the sending device, and based on the common-mode input setting code, determine the current control signal. The sending device is the device that sends the differential input signal, and the common-mode input setting code is used to indicate the voltage range where the common-mode input voltage corresponding to the differential input signal is located. In this case, the sending device only needs to provide the common-mode input setting code for indicating the voltage range where the common-mode input voltage corresponding to the differential input signal is located, and does not need to execute the determination logic of the current control signal, which helps to save the computing resources of the sending device. In addition, the current control signal is determined by considering the voltage range where the common-mode input voltage corresponding to the differential input signal is located, which helps to ensure the matching degree between the current control signal and the voltage range where the common-mode input voltage corresponding to the differential input signal is located, thereby ensuring the accuracy of applying the target current, and further improving the accuracy of transconductance adjustment.

[0100] The embodiments of the present application do not limit the representation form of the common-mode input setting code, as long as it can indicate the voltage range where the common-mode input voltage corresponding to the differential input signal is located. Exemplarily, the common-mode input setting code may be represented by a binary number, and different binary numbers correspond to different voltage ranges. For example, the common-mode input setting code may be represented by a 4-bit binary number, and such a common-mode input setting code may be represented as G<3:0>, where 3:0 is used to represent the value of each bit from the 3rd bit to the 0th bit.

[0101] The embodiments of the present application do not limit the representation form of the current control signal, as long as the target current to be applied to the input differential pair module 2 can be determined according to the current control signal. Exemplarily, the current control signal can be represented by a binary number, and different binary numbers correspond to different target currents. For example, the current control signal can be represented by a 16-bit binary number, and such a current control signal can be expressed as <15:0>, where 15:0 is used to represent the value of each bit from the 15th bit to the 0th bit.

[0102] Exemplarily, the sending device of the differential input signal can store the correspondence between the setting code and the voltage range. After the sending device of the differential input signal determines the differential input signal to be processed by the input stage circuit, it further determines the common-mode input voltage corresponding to the differential input signal, and then determines the setting code corresponding to the voltage range in which the common-mode input voltage corresponding to the differential input signal is located according to the correspondence between the setting code and the voltage range, and uses this setting code as the common-mode input setting code. The correspondence between the setting code and the voltage range can be preset by those skilled in the art. The embodiments of the present application do not limit the representation form of the correspondence between the setting code and the voltage range. Exemplarily, the correspondence between the setting code and the voltage range can be represented by a table or by a function.

[0103] In an exemplary embodiment, the logic module 3 can directly determine the current control signal based on the common-mode input setting code. The embodiments of the present application do not limit the manner of directly determining the current control signal based on the common-mode input setting code.

[0104] Exemplarily, the correspondence between the setting code and the control signal is stored in the logic module 3, and the logic module 3 can determine the control signal corresponding to the common-mode input setting code according to the correspondence, and use the determined control signal as the current control signal. The correspondence between the setting code and the control signal can be preset by those skilled in the art. The embodiments of the present application do not limit the representation form of the correspondence between the setting code and the control signal. Exemplarily, the correspondence between the setting code and the control signal can be represented by a table or by a function.

[0105] Exemplarily, to ensure that after the current application module 1 applies the target current corresponding to the current control signal determined based on the differential input signal to the input differential pair module 2, the transconductance after the input differential pair module 2 processes the differential input signal based on the target current remains within a constant range, the setting principle of the correspondence between the setting code and the control signal is: after the current application module 1 applies the corresponding current to the input differential pair module 2 according to the control signal corresponding to a certain setting code, the transconductance after the input differential pair module 2 processes the differential input signal with the common-mode input voltage within the voltage range corresponding to this setting code remains within a constant range.

[0106] Exemplarily, the common-mode input setting code may include multiple sub-codes. The logic module 3 may determine the sub-control signals corresponding to each sub-code respectively, and then combine the sub-control signals corresponding to each sub-code to obtain a current control signal. In some embodiments, the correspondence between the sub-codes and the sub-control signals is stored in the logic module 3, and the sub-control signals corresponding to each sub-code can be determined based on this correspondence. The correspondence between the sub-codes and the sub-control signals can be preset by those skilled in the art. The present application embodiment does not limit the representation form of the correspondence between the sub-codes and the sub-control signals. Exemplarily, the correspondence between the sub-codes and the sub-control signals can be represented by a table or by a function.

[0107] Exemplarily, to ensure that after the current application module 1 applies the target current corresponding to the current control signal determined based on the differential input signal to the input differential pair module 2, the transconductance after the input differential pair module 2 processes the differential input signal based on the target current remains within a constant range, the setting principle of the correspondence between the sub-codes and the sub-control signals is: after the current application module 1 applies a corresponding current to the input differential pair module 2 according to the control signal obtained by combining the sub-control signals corresponding to each sub-code in a certain setting code, the transconductance after the input differential pair module 2 processes the differential input signal with the common-mode input voltage within the voltage range corresponding to this setting code remains within a constant range.

[0108] In a possible implementation manner, the logic module 3 is configured to correct the common-mode input setting code based on the process parameters of the input stage circuit to obtain a corrected common-mode input setting code; and determine a current control signal based on the corrected common-mode input setting code. That is to say, after the logic module 3 obtains the common-mode input setting code, it does not directly determine the current control signal based on the common-mode input setting code, but first corrects the common-mode input setting code based on the process parameters of the input stage circuit, and then determines the current control signal based on the corrected common-mode input setting code. Based on this, the matching degree between the current control signal and the process parameters of the input stage circuit is relatively high, which is beneficial to reducing the deviation caused by the process parameters of the input stage.

[0109] The process parameters of the input stage circuit refer to a series of key indicators used to control the manufacturing process and finished product performance of the input stage circuit. In an exemplary embodiment, the process parameters of the input stage circuit may include, but are not limited to, wire width, transistor size, lithography accuracy, doping concentration, etc. Exemplarily, the logic module 3 stores the correspondence between process parameters - original setting codes - revised setting codes. The logic module 3 can determine the revised setting code corresponding to the process parameters of the input stage circuit and the common-mode input setting code according to this correspondence, and use this revised setting code as the revised common-mode input setting code. Exemplarily, the voltage ranges indicated by different common-mode input setting codes may be the same or different. The voltage range indicated by the revised common-mode input setting code is the same as or has a small difference from the voltage range indicated by the common-mode input setting code before revision, so as to ensure the matching of the finally determined current control signal and the differential input signal.

[0110] In an exemplary embodiment, the logic module 3 can determine the control signal corresponding to the revised common-mode input setting code based on the correspondence between the setting code and the control signal, and use this control signal as the current control signal. In an exemplary embodiment, the logic module 3 can determine the sub-control signal corresponding to each sub-code in the revised common-mode input setting code based on the correspondence between the sub-code and the sub-control signal, and then combine the sub-control signals corresponding to each sub-code to obtain the current control signal.

[0111] According to the above content, the relationship between the current control signal and the differential input signal is: the current control signal is determined based on the common-mode input setting code used to indicate the voltage range where the common-mode input voltage corresponding to the differential input signal is located. For example, directly find the current control signal corresponding to the common-mode input setting code according to the correspondence between the setting code and the control signal or the correspondence between the sub-code and the sub-control signal. For another example, first revise the common-mode input setting code according to the process parameters, and then find the current control signal corresponding to the revised common-mode input setting code according to the correspondence between the setting code and the control signal or the correspondence between the sub-code and the sub-control signal. In either case, after applying the target current corresponding to the current control signal to the input differential pair module 2 based on the current control signal, the transconductance of the input differential pair module 2 for processing the differential input signal can be maintained within a constant range.

[0112] After obtaining the current control signal, the current application module 1 applies the target current corresponding to the current control signal to the input differential pair module 2 based on the current control signal, so that the input differential pair module 2 processes the differential input signal based on the target current to obtain a transconductance maintained within a constant range.

[0113] The implementation manner in which the current application module 1 applies a target current to the input differential pair module 2 based on a current control signal and the input differential pair module 2 processes the differential input signal based on the target current is related to the specific structures of the current application module 1 and the input differential pair module 2.

[0114] In a possible implementation manner, referring to Figure 5 , the current application module 1 includes a first current application unit 11 and a second current application unit 12, the input differential pair module 2 includes a P-type differential pair unit 21 and an N-type differential pair unit 22, the first current application unit 11 is connected to the P-type differential pair unit 21, and the second current application unit 12 is connected to the N-type differential pair unit 22; the current control signal includes a first current control sub-signal and a second current control sub-signal, and the target current includes a first current corresponding to the first current control sub-signal and a second current corresponding to the second current control sub-signal. Exemplarily, the P-type differential pair unit 21 and the N-type differential pair unit 22 are connected in parallel.

[0115] The first current application unit 11 is configured to apply a first current to the P-type differential pair unit 21 based on the first current control sub-signal; the second current application unit 12 is configured to apply a second current to the N-type differential pair unit 22 based on the second current control sub-signal; the P-type differential pair unit 21 is configured to process the differential input signal based on the first current; the N-type differential pair unit 22 is configured to process the differential input signal based on the second current; wherein, the sum of the transconductances of the P-type differential pair unit 21 processing the differential input signal and the N-type differential pair unit 22 processing the differential input signal is maintained within a constant range.

[0116] Based on the input stage circuit with such a structure, by respectively controlling the currents applied to the two types of differential pair units through the two sub-signals of the first current control sub-signal and the second current control sub-signal, it is beneficial to improve the convenience and accuracy of the control process of the applied current.

[0117] The P-type differential pair unit 21 and the N-type differential pair unit 22 are two different types of differential pair units. Exemplarily, the P-type differential pair unit 21 is composed of P-type input pair transistors, and the N-type differential pair unit 22 is composed of N-type input pair transistors. The first current application unit 11 is a unit for applying current to the P-type differential pair unit 21, and the second current application unit 12 is a unit for applying current to the N-type differential pair unit 22.

[0118] Since the transconductance of the P-type differential pair unit 21 for processing the differential input signal is positively correlated with the current applied by the first current application unit 11 to the P-type differential pair unit 21, and the transconductance of the N-type differential pair unit 22 for processing the differential input signal is positively correlated with the current applied by the second current application unit 12 to the N-type differential pair unit 22, therefore, by reasonably designing the current applied by the first current application unit 11 to the P-type differential pair unit 21 and the current applied by the second current application unit 12 to the N-type differential pair unit 22, it is possible to maintain the sum of the transconductances of the P-type differential pair unit 21 for processing the differential input signal and the N-type differential pair unit 22 for processing the differential input signal within a constant range.

[0119] The embodiments of the present application do not limit the representation forms of the first current control sub-signal and the second current control sub-signal. Exemplarily, both the first current control sub-signal and the second current control sub-signal can be represented by binary numbers. For example, both the first current control sub-signal and the second current control sub-signal can be represented by 16-bit binary numbers. In this case, the current control signal includes two 16-bit binary numbers. In some embodiments, the first current control sub-signal can be represented as P<15:0>, and the second current control sub-signal can be represented as N<15:0>.

[0120] When the target current includes the first current and the second current, the transconductance of the input differential pair module 2 for processing the differential input signal refers to the sum of the transconductances of the P-type differential pair unit 21 for processing the differential input signal and the N-type differential pair unit 22 for processing the differential input signal. Since the target current is used to maintain the transconductance of the input differential pair module 2 for processing the differential input signal within a constant range, therefore, the first current and the second current are used to maintain the sum of the transconductances of the P-type differential pair unit 21 for processing the differential input signal and the N-type differential pair unit 22 for processing the differential input signal within a constant range. Based on this, after the P-type differential pair unit 21 processes the differential input signal based on the first current and the N-type differential pair unit 22 processes the differential input signal based on the second current, the sum of the transconductances of the P-type differential pair unit 21 for processing the differential input signal and the N-type differential pair unit 22 for processing the differential input signal is maintained within a constant range.

[0121] Taking the structure of the input stage circuit as Figure 5Taking the structure shown as an example, an exemplary description is given of the relationship between the current control signal and the differential input signal. When the voltage range in which the common-mode input voltage corresponding to the differential input signal is located is a lower voltage range, the common-mode input setting code G<3:0> is a 4-bit binary number corresponding to the lower voltage range, for example, 0000. Since when the voltage range in which the common-mode input voltage is located is a lower voltage range, the P-type differential pair unit 21 plays a main role and the N-type differential pair unit 22 plays a secondary role or does not play a role, in order to ensure that after applying the first current based on the first current control sub-signal and applying the second current based on the second current control sub-signal, the sum of the transconductances of the P-type differential pair unit 21 processing the differential input signal and the N-type differential pair unit 22 processing the differential input signal is maintained within a constant range, the first current control sub-signal P<15:0> can be a 16-bit binary number corresponding to a larger current, for example, 1111111111111111; the second current control sub-signal N<15:0> can be a 16-bit binary number corresponding to a smaller current, for example, 0000000000000000.

[0122] When the voltage range in which the common-mode input voltage corresponding to the differential input signal is located is a higher voltage range, the common-mode input setting code G<3:0> is a 4-bit binary number corresponding to the higher voltage range, for example, 1111. Since when the voltage range in which the common-mode input voltage is located is a higher voltage range, the N-type differential pair unit 22 plays a main role and the P-type differential pair unit 21 plays a secondary role or does not play a role, in order to ensure that after applying the first current based on the first current control sub-signal and applying the second current based on the second current control sub-signal, the sum of the transconductances of the P-type differential pair unit 21 processing the differential input signal and the N-type differential pair unit 22 processing the differential input signal is maintained within a constant range, the first current control sub-signal P<15:0> can be a 16-bit binary number corresponding to a smaller current, for example, 0000000000000000; the second current control sub-signal N<15:0> can be a 16-bit binary number corresponding to a larger current, for example, 1111111111111111.

[0123] In the exemplary embodiment, the specific situation of the first current applied by the first current application unit 11 to the P-type differential pair unit 21 based on the first current control sub-signal is related to the specific structure of the first current application unit 11, and the specific situation of the second current applied by the second current application unit 12 to the N-type differential pair unit 22 based on the second current control sub-signal is related to the specific structure of the second current application unit 12. Next, in combination with the specific structures of the first current application unit 11 and the second current application unit 12, the specific situations of the first current and the second current are introduced.

[0124] In a possible implementation, refer to Figure 6 , the first current application unit 11 includes a plurality of first constant current sources 111. In this case, the plurality of first constant current sources 111 are all connected to the P-type differential pair unit 21. There is a switch on the connection path between any one of the first constant current sources 111 and the P-type differential pair unit 21. The switch is used to control the state of the connection path between any one of the first constant current sources 111 and the P-type differential pair unit 21. When the switch is closed, the state of the connection path between any one of the first constant current sources 111 and the P-type differential pair unit 21 is the connected state; when the switch is open, the state of the connection path between any one of the first constant current sources 111 and the P-type differential pair unit 21 is the disconnected state.

[0125] For the case where the first current application unit 11 includes a plurality of first constant current sources 111, the first current control sub-signal is used to indicate the state of the connection path between each of the first constant current sources 111 and the P-type differential pair unit 21; the first current is the sum of the currents provided by the first constant current sources 111 whose connection paths indicated by the first current control sub-signal are in the connected state.

[0126] Exemplarily, for the case where the first current application unit 11 includes a plurality of first constant current sources 111, the first current control sub-signal can be represented by a binary number of Q bits, where Q is the number of the first constant current sources 111, and Q is an integer greater than 1. The value of each bit in the binary number of Q bits is used to indicate the state of the connection path between one of the first constant current sources 111 and the P-type differential pair unit 21.

[0127] Exemplarily, if the first current control sub-signal indicates that the state of the connection path between a certain first constant current source 111 and the P-type differential pair unit 21 is the connected state, the first current application unit 11 can control the switch in the connection path between the first constant current source 111 and the P-type differential pair unit 21 to be closed to ensure that the connection path between the first constant current source 111 and the P-type differential pair unit 21 is in the connected state; if the first current control sub-signal indicates that the state of the connection path between a certain first constant current source 111 and the P-type differential pair unit 21 is the disconnected state, the first current application unit 11 can control the switch in the connection path between the first constant current source 111 and the P-type differential pair unit 21 to be open to ensure that the connection path between the first constant current source 111 and the P-type differential pair unit 21 is in the disconnected state.

[0128] The first current is the sum of the currents provided by the first constant current sources 111 whose connection paths indicated by the first current control sub-signal are in the connected state. Exemplarily, the process of the first current application unit 11 applying the first current to the P-type differential pair unit 21 based on the first current control sub-signal can be as follows: The first current application unit 11 controls the states of the connection paths between the respective first constant current sources 111 and the P-type differential pair unit 21 based on the first current control sub-signal, and applies the first current to the P-type differential pair unit 21 through the first constant current sources 111 whose connection paths are in the connected state.

[0129] In a possible implementation manner, continue to refer to Figure 6 , the second current application unit 12 includes a plurality of second constant current sources 121. In this case, the plurality of second constant current sources 121 are all connected to the N-type differential pair unit 22, and there is a switch on the connection path between any second constant current source 121 and the N-type differential pair unit 22. The switch is used to control the state of the connection path between any second constant current source 121 and the N-type differential pair unit 22. When the switch is closed, the state of the connection path between any second constant current source 121 and the N-type differential pair unit 22 is the connected state; when the switch is open, the state of the connection path between any second constant current source 121 and the N-type differential pair unit 22 is the disconnected state.

[0130] For the case where the second current application unit 12 includes a plurality of second constant current sources 121, the second current control sub-signal is used to indicate the states of the connection paths between the respective second constant current sources 121 and the N-type differential pair unit 22; the second current is the sum of the currents provided by the second constant current sources 121 whose connection paths indicated by the second current control sub-signal are in the connected state.

[0131] Exemplarily, for the case where the second current application unit 12 includes a plurality of second constant current sources 121, the second current control sub-signal can be represented by an M-bit binary number, where M is the number of second constant current sources 121, and M is an integer greater than 1. The value of each bit in the M-bit binary number is used to indicate the state of the connection path between a second constant current source 121 and the N-type differential pair unit 22. Exemplarily, the value of M can be the same as the value of Q or different from the value of Q.

[0132] Exemplarily, if the second current control sub-signal indicates that the connection path between a certain second constant current source 121 and the N-type differential pair unit 22 is in a connected state, the second current application unit 12 can control the switch in the connection path between the second constant current source 121 and the N-type differential pair unit 22 to close, so as to ensure that the connection path between the second constant current source 121 and the N-type differential pair unit 22 is in a connected state; if the second current control sub-signal indicates that the connection path between a certain second constant current source 121 and the N-type differential pair unit 22 is in a disconnected state, the second current application unit 12 can control the switch in the connection path between the second constant current source 121 and the N-type differential pair unit 22 to open, so as to ensure that the connection path between the second constant current source 121 and the N-type differential pair unit 22 is in a disconnected state.

[0133] The second current is the sum of the currents provided by the second constant current sources 121 whose connection paths indicated by the second current control sub-signal are in a connected state. Exemplarily, the process of the second current application unit 12 applying the second current to the N-type differential pair unit 22 based on the second current control sub-signal can be as follows: controlling the states of the connection paths between the respective second constant current sources 121 and the N-type differential pair unit 22 based on the second current control sub-signal, and applying the second current to the N-type differential pair unit 22 through the second constant current sources 121 whose connection paths are in a connected state.

[0134] For example, assume that the number of the first constant current sources 111 and the second constant current sources 121 is both 4, the first current control sub-signal is a 4-bit binary number 1110, and the second current control sub-signal is a 4-bit binary number 1011. Among them, 0 in the binary number is used to indicate that the connection path between the constant current source and the corresponding differential pair unit is in a disconnected state, and 1 in the binary number is used to indicate that the connection path between the constant current source and the corresponding differential pair unit is in a connected state. The value of the i-th bit in the 4-bit binary number is used to indicate the state of the connection path between the i-th constant current source among the 4 constant current sources (4 first constant current sources 111 or 4 second constant current sources 121) and the corresponding differential pair unit.

[0135] In the above case, the first current control sub-signal 1110 is used to indicate that the connection paths of the first constant current source 111 of the first, the second constant current source 111 of the second, and the third constant current source 111 of the third with the P-type differential pair unit 21 are in the connected state, and the connection path of the fourth constant current source 111 with the P-type differential pair unit 21 is in the disconnected state. Therefore, the first current is the sum of the currents provided by the first constant current source 111 of the first, the second constant current source 111 of the second, and the third constant current source 111 of the third. The second current control sub-signal 1011 is used to indicate that the connection paths of the first constant current source 121 of the first, the third constant current source 121 of the third, and the fourth constant current source 121 of the fourth with the N-type differential pair unit 22 are in the connected state, and the connection path of the second constant current source 121 with the N-type differential pair unit 22 is in the disconnected state. Therefore, the second current is the sum of the currents provided by the first constant current source 121 of the first, the third constant current source 121 of the third, and the fourth constant current source 121 of the fourth.

[0136] In a possible implementation, referring to Figure 7 , the first current application unit 11 includes a first adjustable current source 112. In this case, the first adjustable current source 112 is connected to the P-type differential pair unit 21. The first current control sub-signal is used to indicate the adjustment method of the first adjustable current source 112, and the first current is the current provided by the first adjustable current source 112 after being adjusted according to the adjustment method indicated by the first current control sub-signal. The adjustment method indicated by the first current control sub-signal is used to restrict the current that the first adjustable current source 112 can provide. In this case, the process of the first current application unit 11 applying the first current to the P-type differential pair unit 21 based on the first current control sub-signal can be: the first current application unit 11 adjusts the first adjustable current source 112 according to the adjustment method indicated by the first current control sub-signal, and applies the first current to the P-type differential pair unit 21 through the adjusted first adjustable current source 112.

[0137] Continue to refer to Figure 7, the second current application unit 12 includes a second adjustable current source 122. In this case, the second adjustable current source 122 is connected to the N-type differential pair unit 22. The second current control sub-signal is used to indicate the adjustment mode of the second adjustable current source 122, and the second current is the current provided by the second adjustable current source 122 after being adjusted according to the adjustment mode indicated by the second current control sub-signal. The adjustment mode indicated by the second current control sub-signal is used to restrict the current that the second adjustable current source 122 can provide. In this case, the process of the second current application unit 12 applying the second current to the N-type differential pair unit 22 based on the second current control sub-signal can be: the second current application unit 12 adjusts the second adjustable current source 122 according to the adjustment mode indicated by the second current control sub-signal, and applies the second current to the N-type differential pair unit 22 through the adjusted second adjustable current source 122.

[0138] The first adjustable current source 121 and the second adjustable current source 122 can be any current-adjustable current source, and the embodiments of the present application do not limit this.

[0139] In an exemplary embodiment, the P-type differential pair unit 21 processes the differential input signal based on the first current, which means that the P-type differential pair unit 21 obtains the differential output signal corresponding to the differential input signal under the action of the first current. The N-type differential pair unit 22 processes the differential input signal based on the second current, which means that the N-type differential pair unit 22 obtains the differential output signal corresponding to the differential input signal under the action of the second current.

[0140] In a possible implementation manner, the P-type differential pair unit 21 includes a first P-type transistor and a second P-type transistor. The gates of the first P-type transistor and the second P-type transistor are respectively connected to the first input terminal and the second input terminal of the input stage circuit. The first P-type transistor and the second P-type transistor share a source electrode, and the first current application unit 11 is connected to the shared source electrode of the first P-type transistor and the second P-type transistor; the N-type differential pair unit 22 includes a first N-type transistor and a second N-type transistor. The gates of the first N-type transistor and the second N-type transistor are respectively connected to the first input terminal and the second input terminal. The first N-type transistor and the second N-type transistor share a source electrode, and the second current application unit 12 is connected to the shared source electrode of the first N-type transistor and the second N-type transistor.

[0141] The first P-type transistor and the second P-type transistor are two P-type transistors; the first N-type transistor and the second N-type transistor are two N-type transistors. The first input terminal and the second input terminal are two different input terminals of the input stage circuit. In some embodiments, the first input terminal can also be referred to as the in-phase input terminal, and the second input terminal can also be referred to as the anti-phase input terminal. The differential input signal can be input to the input stage circuit through the first input terminal and the second input terminal for processing.

[0142] The first current application unit 11 is connected to the source shared by the first P-type transistor and the second P-type transistor, so that the first current application unit 11 can apply a first current to the source shared by the first P-type transistor and the second P-type transistor to apply the first current to the P-type differential pair unit 21, improving the convenience of applying the first current.

[0143] The second current application unit 12 is connected to the source shared by the first N-type transistor and the second N-type transistor, so that the second current application unit 12 can apply a second current to the source shared by the first N-type transistor and the second N-type transistor to apply the second current to the N-type differential pair unit 22, improving the convenience of applying the second current.

[0144] In an exemplary embodiment, the drain of the first P-type transistor is connected to the first output terminal of the input stage circuit, the drain of the second P-type transistor is connected to the second output terminal of the input stage circuit, the drain of the first N-type transistor is connected to the third output terminal of the input stage circuit, and the drain of the second N-type transistor is connected to the fourth output terminal of the input stage circuit. The first output terminal, the second output terminal, the third output terminal, and the fourth output terminal are the four output terminals of the input stage circuit. Exemplarily, the signals output from the first output terminal and the second output terminal are differential output signals obtained by the P-type differential pair unit 21 processing the differential input signal based on the first current, and the signals output from the third output terminal and the fourth output terminal are differential output signals obtained by the N-type differential pair unit 22 processing the differential input signal based on the second current.

[0145] The differential output signals output from the first output terminal and the second output terminal and the differential output signals output from the third output terminal and the fourth output terminal have complementary characteristics. When the common-mode input voltage corresponding to the differential input signal is small, the first P-type transistor and the second P-type transistor play a major role, and the differential output signals output from the first output terminal and the second output terminal have a strong amplification effect. The first N-type transistor and the second N-type transistor play a minor role or do not play a role, and the differential output signals output from the third output terminal and the fourth output terminal have a weak amplification effect, or no amplification effect. When the common-mode input voltage corresponding to the differential input signal is large, the first N-type transistor and the second N-type transistor play a major role, and the differential output signals output from the third output terminal and the fourth output terminal have a strong amplification effect. The first P-type transistor and the second P-type transistor play a minor role or do not play a role, and the differential output signals output from the first output terminal and the second output terminal have a weak amplification effect, or no amplification effect.

[0146] The amplification effect of the differential output signal refers to the multiple by which the differential output voltage corresponding to the differential output signal is amplified compared to the differential input voltage corresponding to the differential input signal. Among them, the differential output voltage refers to the voltage difference between the voltages of the two signals in the differential output signal. Through the two pairs of complementary differential output signals output, the input stage circuit can achieve the amplification of the differential input voltage corresponding to the differential input signal throughout the entire range of the common-mode input voltage from the maximum voltage of the power supply line to its minimum voltage.

[0147] It should be noted that regardless of the magnitude of the common-mode input voltage corresponding to the differential input signal, signals will be output at the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal. However, when the transistor connected to a certain output terminal does not function (that is, the voltage applied to the gate is less than the threshold voltage), the signal output from this output terminal is meaningless. For example, the voltage corresponding to the signal output from this output terminal is always 0V.

[0148] In an exemplary embodiment, the input stage circuit refers to the front-stage structure of the differential amplifier. The differential amplifier further includes a load module. The four output terminals of the input stage circuit need to be connected to the load module to jointly form a complete differential amplifier structure. The load module can be composed of elements such as resistors.

[0149] Exemplarily, after the four output terminals of the input stage circuit are connected to the load module, the load module can convert the signals output from the first output terminal and the third output terminal to obtain a first target signal; convert the signals output from the second output terminal and the fourth output terminal to obtain a second target signal. The first target signal and the second target signal are the differential signals finally output by the differential amplifier, and the voltage difference between the voltages of the first target signal and the second target signal is the final result obtained by amplifying the differential input voltage corresponding to the differential input signal by the differential amplifier. The voltage difference between the voltages of the first target signal and the second target signal can reflect the superposition effect of the differential output voltage corresponding to the differential output signals output from the first output terminal and the second output terminal and the differential output voltage corresponding to the differential output signals output from the third output terminal and the fourth output terminal. The manner in which the load module converts to obtain the first target signal and the second target signal is related to the structure of the load module, and the embodiments of the present application do not limit this. The subsequent applications of the first target signal and the second target signal are related to the application scenario in which the differential amplifier is located, and the embodiments of the present application do not limit this.

[0150] In the embodiment of the present application, when the input differential pair module needs to process a differential input signal, the current application module applies a target current to the input differential pair module so that the transconductance of the input differential module for processing the differential input signal is maintained within a constant range. The target current corresponds to a current control signal, and the current control signal is determined based on the differential input signal. The method of adjusting the transconductance according to the target current is a method of adjusting the transconductance in units of the differential input signal, and the adjustment granularity of the transconductance is relatively fine. Based on this, regardless of the common-mode input voltage corresponding to the differential input signal, after being processed by the input stage circuit, the transconductance can be maintained within a constant range, so that a constant transconductance is achieved within the entire common-mode input voltage range.

[0151] In addition, by directly controlling the applied current through the current control signal, the process of controlling the current application is relatively accurate, which is beneficial to ensuring the stability of the input stage circuit.

[0152] The common-mode input setting code may include multiple digits. Based on this, the input stage circuit provided in the embodiment of the present application can be considered a digital feedback type rail-to-rail input stage circuit. The circuit structure of this type of input stage circuit is simple. Before the input stage circuit officially receives the differential input signal each time, the sending device of the differential input signal sends multiple digits of the common-mode input setting code. According to the different voltage ranges of the common-mode input voltage, different setting codes are sent, which can actively adjust the common-mode input voltage reception range of the input stage circuit. Using the multi-digit digital adjustable mode, the adjustment interval is more refined, and the problem of excessive transconductance mutation can be solved. There is no need to add a current mirror as a tail current source for compensation inside, and the circuit performance will not be affected by the common-mode input voltage squeezing the drain voltage of the transistors in the current mirror, and the supported common-mode input voltage range is wider. In addition, the input stage circuit can actively adjust the common-mode input setting code according to the process parameters inside, so as to correct the deviation influence from the manufacturing process of the input stage circuit and improve the robustness of the system (such as, display interface system) where the input stage circuit is located.

[0153] Next, the specific structure and function of the input stage circuit will be further introduced in combination with specific examples.

[0154] Exemplarily, the structure of the input stage circuit can be as Figure 8As shown in the figure. The input stage circuit includes a first current application unit 11, a second current application unit 12, a transistor MP5, a transistor MP6, a transistor MN5, a transistor MN6, an input terminal VIN, an input terminal VIP, an output terminal VPP, an output terminal VPN, an output terminal VNN, and an output terminal VNP. The gate of the transistor MP5 is connected to the input terminal VIN, and the drain of the transistor MP5 is connected to the output terminal VPN; the gate of the transistor MP6 is connected to the input terminal VIP, and the drain of the transistor MP6 is connected to the output terminal VPP; the common source of the transistor MP5 and the transistor MP6 is connected to the first current application unit 11. The gate of the transistor MN5 is connected to the input terminal VIN, and the drain of the transistor MN5 is connected to the output terminal VNN; the gate of the transistor MN6 is connected to the input terminal VIP, and the drain of the transistor MN6 is connected to the output terminal VNP; the common source of the transistor MN5 and the transistor MN6 is connected to the second current application unit 12.

[0155] Among them, the transistor MP5 corresponds to the first P-type transistor in the above embodiment, the transistor MP6 corresponds to the second P-type transistor in the above embodiment, the transistor MN5 corresponds to the first N-type transistor in the above embodiment, and the transistor MN6 corresponds to the second N-type transistor in the above embodiment.

[0156] The first current application unit 11 includes 16 first constant current sources 111 (respectively denoted as IP0, IP1,..., IP14, IP15), and the second current application unit 12 includes 16 second constant current sources 121 (respectively denoted as IN0, IN1,..., IN14, IN15).

[0157] The first current application unit 11 controls the state of the connection path between the 16 first constant current sources 111 and the common source of the transistor MP5 and the transistor MP6 based on a first current control sub-signal, and applies a first current to the transistor MP5 and the transistor MP6 through the first constant current sources 111 in the connection state of the connection path. Under the action of the first current, the transistor MP5 and the transistor MP6 obtain differential output signals corresponding to the differential input signals input by the input terminal VIN and the input terminal VIP, and output the differential output signals through the output terminal VPN and the output terminal VPP respectively.

[0158] The second current application unit 12 controls the state of the connection path of the 16 second constant current sources 121 to the source shared by the transistor MN5 and the transistor MN6 based on the second current control sub-signal, and applies a second current to the transistor MN5 and the transistor MN6 through the second constant current source 121 in the connected state of the connection path. Under the action of the second current, the transistors MN5 and MN6 obtain a differential output signal corresponding to the differential input signal input by the input terminal VIN and the input terminal VIP, and output the differential output signal through the output terminal VNN and the output terminal VNP respectively.

[0159] Based on Figure 8 the input stage circuit shown in, it is possible to adjust the transconductance within the entire common-mode input voltage range by adjusting the number of constant current sources that provide current in different intervals.

[0160] Exemplarily, the change curve graph of the transconductance of the input stage circuit provided by the embodiment of the present application within the entire common-mode input voltage range is as Figure 9 shown. By comparing with the Figure 2 shown change curve, it can be seen that the transconductance of the input stage circuit provided by the embodiment of the present application is more constant within the entire common-mode input voltage range. The input stage circuit provided by the embodiment of the present application can refine the entire common-mode input voltage range, thereby adjusting the transconductance of different intervals and broadening the overall effective common-mode input interval range.

[0161] The embodiment of the present application also provides a control method for an input stage circuit. The control method for the input stage circuit is used to control the input stage circuit introduced in the above embodiment. The input stage circuit includes a current application module and an input differential pair module connected to each other. Refer to Figure 10 and the control method for the input stage circuit includes the following steps 1001 and 1002.

[0162] Step 1001: Through the current application module, based on the current control signal, apply the target current corresponding to the current control signal to the input differential pair module. The current control signal is determined based on the differential input signal, and the target current is used to maintain the transconductance of the input differential pair module for processing the differential input signal within a constant range.

[0163] In a possible implementation manner, the input stage circuit further includes a logic module, and the logic module is connected to the current application module; the method further includes:

[0164] Receive the common-mode input setting code provided by the sending device through the logic module, and determine the current control signal based on the common-mode input setting code. The sending device is the device that sends the differential input signal, and the common-mode input setting code is used to indicate the voltage range where the common-mode input voltage corresponding to the differential input signal is located.

[0165] In a possible implementation manner, determining a current control signal based on a common-mode input setting code includes:

[0166] Correcting the common-mode input setting code based on the process parameters of the input stage circuit to obtain a corrected common-mode input setting code; determining a current control signal based on the corrected common-mode input setting code.

[0167] Step 1002: Processing the differential input signal based on a target current through an input differential pair module.

[0168] In a possible implementation manner, the current application module includes a first current application unit and a second current application unit, the input differential pair module includes a P-type differential pair unit and an N-type differential pair unit, the first current application unit is connected to the P-type differential pair unit, and the second current application unit is connected to the N-type differential pair unit; the current control signal includes a first current control sub-signal and a second current control sub-signal, and the target current includes a first current corresponding to the first current control sub-signal and a second current corresponding to the second current control sub-signal.

[0169] Applying a target current to the input differential pair module based on the current control signal through the current application module includes: applying a first current to the P-type differential pair unit by the first current application unit based on the first current control sub-signal; applying a second current to the N-type differential pair unit by the second current application unit based on the second current control sub-signal.

[0170] Processing the differential input signal based on the target current through the input differential pair module includes: processing the differential input signal by the P-type differential pair unit based on the first current; processing the differential input signal by the N-type differential pair unit based on the second current; wherein, the sum of the transconductances of the P-type differential pair unit for processing the differential input signal and the N-type differential pair unit for processing the differential input signal is maintained within a constant range.

[0171] In a possible implementation manner, the first current application unit includes a plurality of first constant current sources, and the first current control sub-signal is used to indicate the state of the connection path between each first constant current source and the P-type differential pair unit; the first current is the sum of the currents provided by the first constant current sources in the connection state indicated by the first current control sub-signal; the second current application unit includes a plurality of second constant current sources, and the second current control sub-signal is used to indicate the state of the connection path between each second constant current source and the N-type differential pair unit; the second current is the sum of the currents provided by the second constant current sources in the connection state indicated by the second current control sub-signal.

[0172] In a possible implementation manner, the first current application unit includes a first adjustable current source. The first current control sub-signal is used to indicate the adjustment manner of the first adjustable current source, and the first current is the current provided by the first adjustable current source after being adjusted according to the adjustment manner indicated by the first current control sub-signal.

[0173] The second current application unit includes a second adjustable current source. The second current control sub-signal is used to indicate the adjustment manner of the second adjustable current source, and the second current is the current provided by the second adjustable current source after being adjusted according to the adjustment manner indicated by the second current control sub-signal.

[0174] In a possible implementation manner, the P-type differential pair unit includes a first P-type transistor and a second P-type transistor. The gates of the first P-type transistor and the second P-type transistor are respectively connected to the first input terminal and the second input terminal of the input stage circuit. The first P-type transistor and the second P-type transistor share a source electrode, and the first current application unit is connected to the shared source electrode of the first P-type transistor and the second P-type transistor. The N-type differential pair unit includes a first N-type transistor and a second N-type transistor. The gates of the first N-type transistor and the second N-type transistor are respectively connected to the first input terminal and the second input terminal. The first N-type transistor and the second N-type transistor share a source electrode, and the second current application unit is connected to the shared source electrode of the first N-type transistor and the second N-type transistor.

[0175] The description of the embodiments of the above control method of the input stage circuit has beneficial effects similar to those of the embodiments of the above input stage circuit. For the technical details not disclosed in the embodiments of the control method of the input stage circuit, please refer to the description of the embodiments of the input stage circuit of this application for understanding.

[0176] See Figure 11 , in an embodiment, a differential amplifier is further provided, and the differential amplifier includes the input stage circuit in any of the above possible implementation manners.

[0177] In an exemplary embodiment, see Figure 12 , the differential amplifier includes an input stage circuit and a load module. The input stage circuit includes a logic module, a current application module, and an input differential pair module. The current application module includes a P-type current application unit and an N-type current application unit. The input differential pair module includes a P-type differential pair unit and an N-type differential pair unit. Exemplarily, the P-type current application unit corresponds to the first current application unit 11 in the above embodiment, and the N-type current application unit corresponds to the second current application unit 12 in the above embodiment.

[0178] The logic module determines the first current control sub-signal P<15:0> and the second current control sub-signal N<15:0> according to the common-mode input setting code G<3:0> provided by the transmitting device of the differential input signal. There is a corresponding relationship between G<3:0> and P<15:0>, N<15:0>, and the specific corresponding relationship can be determined by the designer according to design experience and application environment. The first current control sub-signal P<15:0> acts on the P-type current application unit, and the second current control sub-signal N<15:0> acts on the N-type current application unit. The first current control sub-signal P<15:0> and the second current control sub-signal N<15:0> divide the common-mode input voltage range into several intervals, and adjust the currents applied by the P-type current application unit and the N-type current application unit in different control intervals to achieve a constant transconductance within the entire common-mode input voltage range.

[0179] The P-type current application unit applies a first current IBP to the P-type differential pair unit based on the first current control sub-signal P<15:0>, and the N-type current application unit applies a second current IBN to the N-type differential pair unit based on the second current control sub-signal N<15:0>. Under the action of the first current IBP, the P-type differential pair unit obtains the differential output signal corresponding to the differential input signal input at the input terminal VIN and the input terminal VIP, and transmits the differential output signal to the load module through the output terminals VPN and VPP respectively. Under the action of the second current IBN, the N-type differential pair unit obtains the differential output signal corresponding to the differential input signal input at the input terminal VIN and the input terminal VIP, and transmits the differential output signal to the load module through the output terminals VNN and VNP respectively. The load module obtains the output result of the differential amplifier based on the signals output from the output terminals VPN, VPP, VNN, and VNP, and outputs the output result of the differential amplifier through the output terminals VON and VOP. Exemplarily, the signal output from the output terminal VOP is the signal obtained by the load module after converting the signals output from the output terminals VNP and VPP; the signal output from the output terminal VON is the signal obtained by the load module after converting the signals output from the output terminals VNN and VPN.

[0180] In some embodiments, the logic module can actively correct the common-mode input setting code under the drive of the internal clock CLK to improve the transconductance deviation caused by process effects. Exemplarily, the internal clock CLK can be obtained through the CDR circuit. In some embodiments, the CDR can determine the accuracy of the differential input signal received by the differential amplifier and send a SET_EN signal back to the logic module of the input stage circuit. The input stage circuit can process the differential input signal after receiving the SET_EN.

[0181] See Figure 13, in one embodiment, a chip is further provided, and the chip includes the above differential amplifier. Optionally, the chip may be a display driver chip.

[0182] See Figure 14 , in one embodiment, an electronic device is further provided, and the electronic device includes the above chip.

[0183] In an exemplary embodiment, the electronic device may refer to a receiver in a display interface system. See Figure 15 , the working process of the receiver may include four steps:

[0184] The first step: The receiver is powered on and the working state is reset;

[0185] The second step: The training mode is enabled, and during this process, the CDR achieves locking;

[0186] The third step: Receive the common-mode input setting code from the receiver, update the setting of the common-mode input voltage range, and correct the common-mode input setting code;

[0187] The fourth step: Receive the differential input signal transmitted by the transmitter, and control the current applied during the process of processing the differential input signal according to the corrected common-mode input setting code to achieve a constant transconductance. If there is a problem of CDR unlocking, then return to the training mode again and continue the process of the second step.

[0188] It should be noted that the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of relevant countries and regions.

[0189] It should be understood that "a plurality of" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0190] The terms "first", "second", etc. in this application are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the application described here can be implemented in an order other than those illustrated or described here. The embodiments described in the above exemplary embodiments do not represent all embodiments consistent with this application. On the contrary, they are only examples of devices and methods consistent with some aspects of this application.

[0191] The above are only exemplary embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included within the protection scope of the present application.

Claims

1. An input stage circuit, characterized in that: The input stage circuit includes a current applying module and an input differential pair module connected to each other; The current applying module is used to apply a target current corresponding to the current control signal to the input differential pair module based on the current control signal, wherein the current control signal is determined based on the differential input signal, and the target current is used to maintain the transconductance of the input differential pair module processing the differential input signal within a constant range; The input differential pair module is used to process the differential input signal based on the target current.

2. The circuit according to claim 1, characterized in that The input stage circuit further comprises a logic module, wherein the logic module is connected to the current applying module; The logic module is used to receive a common-mode input setting code provided by a sending device, and determine the current control signal based on the common-mode input setting code. The sending device is a device that sends the differential input signal, and the common-mode input setting code is used to indicate the voltage range of the common-mode input voltage corresponding to the differential input signal.

3. The circuit according to claim 2, characterized in that The logic module is used to correct the common-mode input setting code based on the process parameters of the input stage circuit to obtain a corrected common-mode input setting code; The current control signal is determined based on the modified common-mode input setting code.

4. The circuit according to any one of claims 1 to 3, characterized in that: The current applying module includes a first current applying unit and a second current applying unit, the input differential pair module includes a P-type differential pair unit and an N-type differential pair unit, the first current applying unit is connected to the P-type differential pair unit, and the second current applying unit is connected to the N-type differential pair unit; the current control signal includes a first current control sub-signal and a second current control sub-signal, and the target current includes a first current corresponding to the first current control sub-signal and a second current corresponding to the second current control sub-signal; The first current applying unit is used to apply the first current to the P-type differential pair unit based on the first current control sub-signal; The second current applying unit is used to apply the second current to the N-type differential pair unit based on the second current control sub-signal; The P-type differential pair unit is used to process the differential input signal based on the first current; The N-type differential pair unit is used to process the differential input signal based on the second current; The sum of the transconductance of the P-type differential pair unit processing the differential input signal and the sum of the transconductance of the N-type differential pair unit processing the differential input signal is maintained within the constant range.

5. The circuit according to claim 4, characterized in that The first current applying unit includes a plurality of first constant current sources, the first current control sub-signal is used to indicate the state of the connection path between each first constant current source and the P-type differential pair unit; the first current is the sum of the currents provided by the first constant current sources in the connection state of which the connection path indicated by the first current control sub-signal is in the connection state; The second current applying unit includes a plurality of second constant current sources, and the second current control sub-signal is used to indicate the state of the connection path between each second constant current source and the N-type differential pair unit; The second current is the sum of currents provided by the second constant current sources when the connection path indicated by the second current control sub-signal is in a connection state.

6. The circuit according to claim 4, characterized in that The first current applying unit includes a first adjustable current source, the first current control sub-signal is used to indicate an adjustment mode of the first adjustable current source, and the first current is a current provided by the first adjustable current source after being adjusted according to the adjustment mode indicated by the first current control sub-signal; The second current applying unit includes a second adjustable current source, the second current control sub-signal is used to indicate an adjustment mode of the second adjustable current source, and the second current is the current provided by the second adjustable current source after being adjusted according to the adjustment mode indicated by the second current control sub-signal.

7. The circuit according to claim 4, characterized in that The P-type differential pair unit includes a first P-type transistor and a second P-type transistor, the gate of the first P-type transistor and the gate of the second P-type transistor are respectively connected to the first input terminal and the second input terminal of the input stage circuit, the first P-type transistor and the second P-type transistor share a source, and the first current applying unit is connected to the source shared by the first P-type transistor and the second P-type transistor; The N-type differential pair unit includes a first N-type transistor and a second N-type transistor, the gate of the first N-type transistor and the gate of the second N-type transistor are respectively connected to the first input terminal and the second input terminal, the first N-type transistor and the second N-type transistor share a source, and the second current applying unit is connected to the source shared by the first N-type transistor and the second N-type transistor.

8. A control method for an input stage circuit, characterized in that: The input stage circuit comprises a current applying module and an input differential pair module connected to each other; the method comprises: Applying a target current corresponding to the current control signal to the input differential pair module through the current applying module based on the current control signal, wherein the current control signal is determined based on the differential input signal, and the target current is used to maintain the transconductance of the input differential pair module in processing the differential input signal within a constant range; The differential input signal is processed based on the target current by the input differential pair module.

9. The method according to claim 8, characterized in that The input stage circuit further includes a logic module, and the logic module is connected to the current applying module; the method further includes: The common-mode input setting code provided by the sending device is received through the logic module, and the current control signal is determined based on the common-mode input setting code. The sending device is a device that sends the differential input signal, and the common-mode input setting code is used to indicate the voltage range of the common-mode input voltage corresponding to the differential input signal.

10. The method according to claim 9, characterized in that The determining the current control signal based on the common mode input setting code comprises: The common-mode input setting code is modified based on the process parameters of the input stage circuit to obtain a modified common-mode input setting code; and the current control signal is determined based on the modified common-mode input setting code.

11. The method according to any one of claims 8 to 10, characterized in that: The current applying module includes a first current applying unit and a second current applying unit, the input differential pair module includes a P-type differential pair unit and an N-type differential pair unit, the first current applying unit is connected to the P-type differential pair unit, and the second current applying unit is connected to the N-type differential pair unit; the current control signal includes a first current control sub-signal and a second current control sub-signal, and the target current includes a first current corresponding to the first current control sub-signal and a second current corresponding to the second current control sub-signal; The step of applying a target current corresponding to the current control signal to the input differential pair module through the current applying module based on the current control signal includes: Applying the first current to the P-type differential pair unit based on the first current control sub-signal through the first current applying unit; applying the second current to the N-type differential pair unit based on the second current control sub-signal through the second current applying unit; The processing of the differential input signal based on the target current by the input differential pair module includes: Processing the differential input signal based on the first current through the P-type differential pair unit; processing the differential input signal based on the second current through the N-type differential pair unit; The sum of the transconductance of the P-type differential pair unit processing the differential input signal and the sum of the transconductance of the N-type differential pair unit processing the differential input signal is maintained within the constant range.

12. The method according to claim 11, characterized in that The first current applying unit includes a plurality of first constant current sources, the first current control sub-signal is used to indicate the state of the connection path between each first constant current source and the P-type differential pair unit; the first current is the sum of the currents provided by the first constant current sources in the connection state of which the connection path indicated by the first current control sub-signal is in the connection state; The second current applying unit includes a plurality of second constant current sources, and the second current control sub-signal is used to indicate the state of the connection path between each second constant current source and the N-type differential pair unit; The second current is the sum of currents provided by the second constant current sources when the connection path indicated by the second current control sub-signal is in a connection state.

13. The method according to claim 11, characterized in that The first current applying unit includes a first adjustable current source, the first current control sub-signal is used to indicate an adjustment mode of the first adjustable current source, and the first current is a current provided by the first adjustable current source after being adjusted according to the adjustment mode indicated by the first current control sub-signal; The second current applying unit includes a second adjustable current source, the second current control sub-signal is used to indicate an adjustment mode of the second adjustable current source, and the second current is the current provided by the second adjustable current source after being adjusted according to the adjustment mode indicated by the second current control sub-signal.

14. The method according to claim 11, characterized in that The P-type differential pair unit includes a first P-type transistor and a second P-type transistor, the gate of the first P-type transistor and the gate of the second P-type transistor are respectively connected to the first input terminal and the second input terminal of the input stage circuit, the first P-type transistor and the second P-type transistor share a source, and the first current applying unit is connected to the source shared by the first P-type transistor and the second P-type transistor; The N-type differential pair unit includes a first N-type transistor and a second N-type transistor, the gate of the first N-type transistor and the gate of the second N-type transistor are respectively connected to the first input terminal and the second input terminal, the first N-type transistor and the second N-type transistor share a source, and the second current applying unit is connected to the source shared by the first N-type transistor and the second N-type transistor.

15. A differential amplifier, characterized in that: The differential amplifier comprises the input stage circuit according to any one of claims 1 to 7.

16. A chip, characterized in that: The chip includes the differential amplifier as claimed in claim 15 .

17. An electronic device, characterized in that: The electronic device comprises the chip as claimed in claim 16.

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